Chip, digital isolator and chip manufacturing method

Abstract

Embodiments of the present application provide a chip, a digital isolator, and a chip manufacturing method. In one embodiment, the chip includes: a substrate and an isolation device disposed on the substrate; the isolation device includes a first conductive structure, a second conductive structure, and an isolation layer located between the first conductive structure and the second conductive structure; the first conductive structure is disposed on a first surface of the substrate; the second conductive structure is for disposing bonding leads; wherein, an insulating layer edge is disposed extending in a direction from the first surface towards a second surface of the substrate, and the insulating layer edge completely or partially wraps a conductive region between the first surface and the second surface, and an outer surface of the chip is for filling a packaging material to form a package body. This helps to improve the problem of relatively weak withstand voltage performance of isolator products in the prior art.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a chip, a digital isolator, and a chip manufacturing method. Background Art

[0002] In traditional isolation systems, optical couplers are usually used to achieve isolation. However, in recent years, due to requirements in terms of data rate, power consumption, ease of use, etc., digital isolators with advantages such as high data rate, low power consumption, and long service life are used in many application fields to replace optical couplers.

[0003] Currently, digital isolators mainly rely on isolation devices manufactured on the chip surface to achieve high-voltage isolation. With the improvement of the manufacturing ability of isolation devices, the breakdown voltage tolerance of isolation devices on the chip is getting higher and higher. For example, they can withstand high voltages of 5 - 10 KV.

[0004] However, in some scenarios, if only considering the insulating medium of the isolation device on the chip itself or only considering the breakdown voltage tolerance of the isolation device on the chip itself, the breakdown voltage problems brought by the specific connection method of the isolator product may be ignored. In this case, even if the breakdown voltage tolerance of the isolation device on the chip itself is improved, the isolation breakdown voltage performance of the entire isolator product in the circuit system cannot be enhanced. Summary of the Invention

[0005] The purpose of the present application is to provide a chip, a digital isolator, and a chip manufacturing method, which can improve the problem of weak breakdown voltage performance of existing isolator products.

[0006] In a first aspect, the present application provides a chip, which includes: a substrate and an isolation device disposed on the substrate;

[0007] The isolation device includes a first conductive structure, a second conductive structure, and an isolation layer located between the first conductive structure and the second conductive structure;

[0008] The first conductive structure is disposed on a first surface of the substrate;

[0009] The second conductive structure is for setting bonding leads;

[0010] Wherein, an insulating layer edge is extended and disposed in a direction from the first surface towards the second surface of the substrate. The insulating layer edge completely or partially wraps the conductive region between the first surface and the second surface, and the outer surface of the chip is used to fill encapsulation material to form an encapsulation body.

[0011] In the above chip structure, isolation devices are provided on the substrate of the chip. Since an insulating layer edge is provided on the substrate of the chip, and the insulating layer edge extends and wraps the substrate in the direction from the first surface of the substrate to the second surface of the substrate, therefore, in the case where there are bonding leads on the chip, the package formed by the insulating layer edge and filling can improve the package breakdown voltage performance of the entire chip, and can break through the product breakdown voltage bottleneck. Compared with the prior art in which only the breakdown voltage ability of the isolation devices on the chip itself is considered and the product breakdown voltage performance cannot be further improved, the above chip structure can improve the isolation breakdown voltage problem caused by the bonding leads provided on the chip. Even if bonding leads that are difficult to modify are provided on the chip, the isolation breakdown voltage performance can still be improved based on the above insulating layer edge structure.

[0012] In an alternative embodiment, the insulating layer edge is a structure formed at the edge region of the first surface after cutting the specified position, by opening a first trench at a specified position on the wafer and disposing a first dielectric layer in the first trench during the chip manufacturing process.

[0013] Through the above embodiment, in the case where it is difficult to further improve the breakdown voltage performance of the individual chips obtained after cutting in the prior art, chips with insulating layer edges can be obtained by specific processing and cutting of the wafer. Based on this embodiment, chips with stronger isolation breakdown voltage ability can be obtained.

[0014] In an alternative embodiment, the breakdown voltage relationship between the insulating layer edge and the package satisfies a first expression:

[0015] The first expression includes: 0.5×tox×Eox < ht×Et < 2×tox×Eox;

[0016] Wherein, ht represents the depth of the first trench, tox represents the thickness of the first dielectric layer disposed in the first trench, Eox represents the breakdown voltage ability per unit thickness of the first dielectric layer, and the first dielectric layer becomes the insulating layer edge after the chip manufacturing process is completed, and Et represents the breakdown voltage ability per unit thickness of the package filled on the outer surface of the insulating layer edge.

[0017] Through the above implementation, the breakdown path between the substrate and the bonding leads can be extended, and the isolation breakdown voltage performance of the chip can be improved.

[0018] In an alternative embodiment, the breakdown voltage relationship between the insulating layer edge and the package satisfies a second expression;

[0019] The second expression includes: ht×Et < tox×Eox.

[0020] Through the above implementation method, the entire depth of the first trench can be fully utilized, which can extend the breakdown path between the substrate and the bonding lead, thereby optimizing the isolation breakdown voltage capability of the chip.

[0021] In an alternative embodiment, the specified position is the saw street of the wafer, and the width of the first trench in a first direction perpendicular to the saw street is greater than the width of the cutting tool for cutting the saw street.

[0022] Through the above implementation method, the above limitations on the first trench are beneficial to ensuring that after the wafer is cut, the insulating layer edge can be exposed on the side cutting surface of the chip, and the exposed insulating layer edge has a covering and isolating effect on a specific area of the substrate.

[0023] In an alternative embodiment, the width of the first trench in a second direction parallel to the saw street satisfies a third expression;

[0024] The third expression includes:

[0025]

[0026] Wherein, AB represents the width of the first trench in the second direction parallel to the saw street, W1′W2 represents the depth of the first trench, and W2W3 represents the shortest distance between the edge of the first trench on the first surface and the bonding lead.

[0027] Through the above implementation method, some special positions on the insulating layer edge (such as both ends of the line segment AB) can be avoided from becoming breakdown weak points, and it is easy to implement.

[0028] In a second aspect, the present application provides a digital isolator, including the chip described in the first aspect above. Thereby, the isolation breakdown voltage capability of the digital isolator can be improved.

[0029] In a third aspect, the present application provides a method for manufacturing a chip, the method including:

[0030] Etching a first trench on the saw street of the wafer to be processed;

[0031] Forming a first dielectric layer in the first trench;

[0032] For a wafer to be cut that includes the first dielectric layer and isolation devices, a cutting tool is used to cut the saw lane corresponding to the first trench, so as to cut a chip with an insulating layer edge from the wafer to be cut. The chip includes: a substrate and the isolation devices disposed on the substrate. The isolation devices include: a first conductive structure, a second conductive structure, and an isolation layer located between the first conductive structure and the second conductive structure. The first conductive structure is disposed on a first surface of the substrate. The insulating layer edge is formed by the first dielectric layer extending from the first surface toward the second surface of the substrate. The insulating layer edge completely or partially wraps the conductive region between the first surface and the second surface;

[0033] For the obtained chip, bonding leads are disposed on the second conductive structure;

[0034] A second dielectric layer is filled on the outer surface of the chip as the package of the chip.

[0035] In the above method, by first forming a first trench and forming a first dielectric layer in the first trench before cutting the wafer, and performing wafer cutting and processing based on this, an implementation method for obtaining the chip structure of the foregoing first aspect is provided. When the chip obtained based on this is applied to a circuit system, the isolation breakdown voltage performance of the circuit system or isolator product having the above chip structure can be improved. In the case where there are bonding leads on the chip, the package breakdown voltage performance of the entire chip can be improved through the insulating layer edge and package of the chip, and the product breakdown voltage bottleneck can be broken.

[0036] In an alternative embodiment, the etching to form the first trench on the saw lane of the wafer to be processed includes:

[0037] After completing part of the post-process of the chip on the wafer to be processed, a first trench is etched on the saw lane of the wafer to be processed. The wafer to be processed includes the substrates of each chip and the isolation devices of each chip;

[0038] The forming of the first dielectric layer in the first trench includes:

[0039] A first dielectric layer is formed in the first trench by a deposition process to obtain the wafer to be cut.

[0040] Through the above implementation, an implementation for obtaining the chip structure of the foregoing first aspect can be achieved when the front process is completed.

[0041] In an alternative embodiment, the etching to form the first trench on the saw lane of the wafer to be processed after completing part of the post-process of the chip on the wafer to be processed includes:

[0042] After more than 70% of the total number of lithography processes in the back-end process of the chip are completed, the first trench is formed on the scribe lane by performing insulating layer etching and deep silicon etching.

[0043] Through the above implementation method, it is beneficial to reduce the impact on the lithography result.

[0044] In an alternative embodiment, etching and forming the first trench on the scribe lane of the wafer to be processed includes: in the front-end process of chip manufacturing, etching and forming the first trench on the scribe lane of the wafer to be processed;

[0045] Forming the first dielectric layer in the first trench includes: forming the first dielectric layer in the first trench by an oxidation process or a deposition process, and obtaining a substrate covered by the first dielectric layer as the structure to be processed;

[0046] Before cutting the scribe lane corresponding to the first trench with a tool, the method further includes: forming the isolation devices of each chip on the structure to be processed to obtain the wafer to be cut.

[0047] Through the above implementation method, a method for setting the first trench and the first dielectric layer in the front-end (front-end process) of chip processing is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a schematic diagram of a partial structure related to the isolation device on the chip of an isolator product in the prior art.

[0050] Figure 2 It is a schematic cross-sectional structure diagram of a chip in the prior art.

[0051] Figure 3 It is a schematic diagram of a wafer cutting principle in the prior art.

[0052] Figure 4 It is a schematic cross-sectional structure diagram of a chip provided by an embodiment of the present application.

[0053] Figure 5 It is a partial top view of a wafer provided by an embodiment of the present application.

[0054] Figure 6 Schematic diagram of the first trench distribution of a wafer provided by an embodiment of the present application.

[0055] Figure 7 Schematic diagram of the size of a first trench provided by an embodiment of the present application.

[0056] Figure 8 Flow chart of a chip manufacturing method provided by an embodiment of the present application.

[0057] Figure 9 Schematic diagram of a wafer to be processed provided by an embodiment of the present application.

[0058] Figure 10 Based on Figure 9 Schematic diagram of the wafer to be processed obtained after setting the first opening according to the shown structure.

[0059] Figure 11 Based on Figure 10 Schematic diagram of the trench processing result obtained after opening the first trench according to the shown structure.

[0060] Figure 12 Based on Figure 11 Schematic diagram of the processing result obtained after forming the first dielectric layer according to the shown structure.

[0061] Figure 13 Based on Figure 12 Schematic diagram of the wafer to be cut obtained according to the shown structure.

[0062] Figure 14 Schematic diagram of the trench processing result obtained after opening the first trench in another wafer to be processed provided by an embodiment of the present application.

[0063] Figure 15 Based on Figure 14 Schematic diagram of the processing result obtained after forming the first dielectric layer according to the structure.

[0064] Figure 16 Based on Figure 15 Schematic diagram of the wafer to be cut obtained according to the shown structure.

[0065] Reference numerals: 10 - first conductive structure; 20 - second conductive structure; 30 - substrate; 40 - bonding lead; 50 - isolation layer; 60 - blue film; 101 - insulating dielectric layer; 102 - metal layer; 200 - cutting tool; 201 - first trench; 202 - first dielectric layer; 301 - cutting area; 302 - center line. Detailed implementation manners

[0066] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0067] As described in the background art, for a chip that needs to achieve an isolation function, isolation devices that can play an isolation role are integrated on the chip. Usually, if you want to improve the withstand voltage isolation performance of the chip, you will start from the isolation device and improve the insulation performance of the isolation device itself through some processing methods. For example, if a capacitor is used as an isolation device on a chip, the withstand voltage capacity of the capacitor itself can be improved by changing the distance between the two electrodes of the capacitor and replacing the dielectric material between the two electrodes of the capacitor.

[0068] However, the inventors have found through research that the method of changing the insulation performance of the isolation device itself can only improve the performance of the chip in some cases. The inventors have found that if only the withstand voltage isolation performance of the isolation device itself is continuously improved, the withstand voltage isolation ability of the entire chip will soon reach a withstand voltage bottleneck. If only the withstand voltage capacity of the isolation device itself on the chip is considered, but the withstand voltage problems brought by the specific connection method of the isolator product are not concerned, and the restriction of the withstand voltage capacity caused by the packaging structure of the chip product on the specific connection structure of the isolator is not concerned, there will be a situation where even if the withstand voltage capacity of the isolation device itself on the chip is enhanced, the isolation withstand voltage ability of the entire chip cannot be further improved.

[0069] For example, after bonding wires that provide a connection function are provided on the chip, the withstand voltage problems brought by the bonding wires connected to the isolation device may be difficult to improve only by replacing the isolation device on the chip. In this case, the chip packaging technology has gradually become the main bottleneck of product withstand voltage.

[0070] Next, the factors of existing chips that affect the isolation withstand voltage performance of the product will be introduced.

[0071] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a partial structure related to the isolation device on a chip of an isolator product.

[0072] Figure 1 In the shown structure, the substrate 30 has conductivity, and integrated circuits are fabricated on the surface of the substrate 30, usually including but not limited to circuit modules such as amplifiers, comparators, drivers, etc. On the first surface of the substrate 30 (corresponding to Figure 1An isolation device is also fabricated on the surface (referred to as "Q" in [])). The isolation device mainly includes three parts: a first conductive structure 10, a second conductive structure 20, and an isolation layer 50 located between the first conductive structure 10 and the second conductive structure 20. One or more bonding wires 40 are led out and arranged on the second conductive structure 20.

[0073] For the isolation device, an insulating medium is provided as the isolation layer 50 between its two conductive structures to achieve the isolation withstand voltage function. The distance between the two conductive structures is d1. The material of the isolation layer 50 is usually silicon dioxide, and most of them have a withstand voltage capacity of 400 - 800 V / μm. For example, 10 μm of silicon dioxide can achieve a withstand voltage capacity of 4000 - 8000 V between the first conductive structure 10 and the second conductive structure 20. For the convenience of subsequent description, the case of a withstand voltage capacity of 400 V / μm will be taken as an example for introduction. If the withstand voltage capacity per unit thickness of the isolation layer 50 is 400 V / μm as an example, then the 10 μm isolation layer 50 can achieve a 4000 V withstand voltage. In the prior art, usually the first conductive structure 10, the second conductive structure 20, and the isolation layer 50 of the isolation device are improved to enhance the overall isolation withstand voltage performance of the chip by improving the withstand voltage performance of the isolation device itself.

[0074] The inventor found through research that when the chip is put into use after the bonding wire 40 is arranged on the second conductive structure 20, the voltage of the bonding wire 40 is almost the same as the voltage of the second conductive structure 20, and the voltage of the substrate 30 is very close to the voltage of the first conductive structure 10 (not exceeding the power supply voltage of the chip, generally a few volts). Although the distance d2 from the bonding wire 40 to the edge of the chip is greater than the thickness d1 of the isolation layer 50, for the path part corresponding to d2, its main withstand voltage capacity is provided by the packaging structure formed by the epoxy molding compound filled on the outer surface of the chip. The withstand voltage capacity of the epoxy molding compound is much lower than that of the silicon dioxide at the isolation layer 50 of the isolation device. If d2 = 200 μm and the withstand voltage capacity per unit thickness of the epoxy molding compound is 18 V / μm as an example, then the withstand voltage capacity corresponding to d2 (between the bonding wire 40 and the substrate 30) is only 3600 V < 4000 V (4000 V is the withstand voltage capacity corresponding to the aforementioned d1). That is, the withstand voltage value between the bonding wire 40 and the substrate 30 is lower than the withstand voltage value between the first conductive structure 10 and the second conductive structure 20. Then the corresponding circuit system of the entire chip will be broken down on the path corresponding to d2. At this time, no matter how the thickness of the isolation layer 50 or the manufacturing process of the isolation device is improved, the withstand voltage situation between the bonding wire 40 and the substrate 30 (the position corresponding to d2) cannot be changed. In other words, the withstand voltage capacity of the entire circuit system is limited by this distance d2.

[0075] Those skilled in the art know that the radian and height of the bonding wire 40 are restricted by many factors such as the manufacturing process and the plastic encapsulation hydrodynamics, and cannot be adjusted arbitrarily. Therefore, the inventor believes that simply increasing the breakdown voltage at the isolation device d2 on the chip has limited help for the breakdown voltage of the entire chip system. When the breakdown voltage at d2 is high enough, the bottleneck of the system's breakdown voltage lies between the bonding wire 40 and the substrate 30.

[0076] Figure 2 Yes Figure 1 is a schematic cross-sectional structure diagram corresponding to the shown structure. Compared with Figure 1 , more chip details are shown in Figure 2 .

[0077] In Figure 2 , the aforementioned isolation device (including the first conductive structure 10, the second conductive structure 20, and the isolation layer 50) is disposed on the first surface of the substrate 30 of the chip. On the first surface of the substrate 30 in the chip, there is also other metal layer 102 covered by the insulating dielectric layer 101. The periphery of the chip is filled with epoxy plastic encapsulant by plastic encapsulation, and the structure formed by the plastic encapsulation filling is denoted as the plastic encapsulation body or the package body.

[0078] However, the position W1 on the side of the substrate 30 (the side position below the lower surface of the insulating dielectric layer 101) is not covered. Therefore, the shortest path from W1 to the bonding wire 40 is: the path corresponding to the shortest distance of the path from W1 through the upper surface W2 of the insulating dielectric layer 101 to the position W3 on the bonding wire 40 (i.e., W1-W2-W3). In the prior art, the distance from W1 through W2 to W3 is close to Figure 1 d2 in

[0079] . Usually, the distance between W1 and W2 is very small, generally on the order of 10um, while the distance between W2 and W3 is relatively large, usually on the order of 100 - 300um. Therefore, in the prior art, the main breakdown voltage is borne by the plastic encapsulation material filled between W2 and W3.

[0080] Currently, as Figure 3 shown, a group of chips without bonding wires 40 are all fabricated on the surface of a complete wafer and arranged repeatedly (i.e., there are many repeated chip particles on one wafer). If independent chips are needed, the wafer needs to be diced.

[0081] In one example, when dicing a wafer, the wafer is adhered to a blue film 60, and then the wafer is diced by a cutting blade rotating at high speed (denoted as tool 200) to separate the individual chips on the wafer. Among them, in order to avoid damaging the effective circuit modules of each chip during the dicing process, a dedicated dicing channel E-F (also called a scribe lane) is reserved between the chips, and the width range of the dicing channel is approximately 40-200 um. When the tool 200 cuts the wafer between E-F, the substrates 30 of the two separated chips are exposed from the side of the cutting position, thus forming Figure 2 the cutting surfaces corresponding to W0 and W1 in

[0082] In view of this, the inventor has proposed the following embodiments through research for improvement. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0083] Embodiment 1

[0084] This embodiment provides a chip. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a chip provided by an embodiment of the present application.

[0085] As shown in Figure 4 , the chip provided by the embodiment of the present application includes: a substrate 30 and isolation devices disposed on the substrate 30. This chip can be called an isolator chip.

[0086] The substrate 30 can be a silicon substrate 30 and has conductivity. In addition to the isolation devices, other circuit modules (such as amplifiers, comparators, drivers, etc.) can also be integrally provided on the substrate 30 of the chip. These circuit modules can independently or cooperate with the isolation devices to implement the chip functions, and the present application does not limit other circuit modules in the chip except the isolation devices.

[0087] Among them, the isolation device includes a first conductive structure 10, a second conductive structure 20, and an isolation layer 50 located between the first conductive structure 10 and the second conductive structure 20.

[0088] The material of the isolation layer 50 can be silicon dioxide, which is used to provide isolation withstand voltage ability for the isolation device. Optionally, the thickness of the isolation layer 50 is greater than or equal to 5 microns. In one example, the unit thickness withstand voltage ability of the isolation layer 50 can be between 400-800 V / um.

[0089] The first conductive structure 10 of the isolation device is disposed on the first surface of the substrate 30 (the position of the first surface can be regarded as being the same asFigure 1 is the same as the "Q" in

[0090] The bonding wire 40 is to be arranged on the second conductive structure 20. One or more bonding wires 40 can be arranged on the second conductive structure 20, and the chip can be connected to other external circuits based on the bonding wires 40.

[0091] Optionally, the isolation device can be a device manufactured based on the principles of capacitance, transformer, or giant magnetoresistance resistor network. In one example, the isolation device operates based on the capacitance isolation principle, and the first conductive structure 10 and the second conductive structure 20 are respectively the lower plate and the upper plate of the capacitor. The upper plate and the lower plate usually adopt rectangular structures with similar shapes and sizes, and the lower plate is connected to some integrated circuits on the first surface of the substrate 30. In another example, the isolation device operates based on the transformer isolation principle, and the first conductive structure 10 and the second conductive structure 20 are respectively the bottom-layer spiral coil and the top-layer spiral coil of the transformer, and the bottom-layer spiral coil is connected to some integrated circuits on the first surface of the substrate 30. In yet another example, the isolation device operates based on the giant magnetoresistance isolation principle, and the first conductive structure 10 and the second conductive structure 20 are respectively the giant magnetoresistance bridge and the spiral coil of the giant magnetoresistance resistor network, and the giant magnetoresistance bridge is connected to some integrated circuits on the first surface of the substrate 30. The specific isolation device and the technology for manufacturing the isolation device should not be construed as a limitation to this application.

[0092] In the embodiment of this application, an insulating layer edge is extended and arranged in the direction from the first surface towards the second surface of the substrate 30, and the insulating layer edge wraps all or part of the conductive region between the first surface and the second surface. The outer surface of the chip can be filled with a packaging material (the packaging material here can be the same as the plastic packaging material filled in the prior art) to form a package. The first surface and the second surface can be regarded as the top surface and the bottom surface of the substrate 30 respectively.

[0093] For the chip structure that already has the above-mentioned insulating layer edge, after the bonding wires 40 are arranged, a plastic packaging material can be used for filling to generate the package on the outer surface of the chip. That is, the material of the package can be epoxy molding compound. The voltage withstand capacity per unit thickness of the package is lower than that of the isolation layer 50 and lower than that of the insulating layer edge.

[0094] In the embodiment of this application, the insulating layer edge is a structure formed at the edge region of the first surface after cutting the specified position during the chip processing by opening a first trench 201 at the specified position on the wafer and arranging a first dielectric layer 202 in the first trench 201. The first dielectric layer 202 can be silicon dioxide (i.e., can be the same as the material of the isolation layer 50).

[0095] In the case where it is difficult to further improve the breakdown voltage performance of the individual chips obtained after cutting in the prior art (the reasons have been introduced in the foregoing description and will not be elaborated here), by performing a specific treatment on the wafer (setting the first trench 201 at a specified position and then cutting the wafer after setting the first dielectric layer 202 in the first trench 201), chips with an insulating layer edge can be obtained, and chips with stronger isolation breakdown voltage capabilities can be obtained.

[0096] Taking the depth of the opened first trench 201 as 100 um, the breakdown voltage capability per unit thickness of the first dielectric layer 202 set in the first trench 201 as 450 V / um, and the breakdown voltage capability per unit thickness of the encapsulation material filled for the chip as 18 V / um as an example, as long as the insulating layer (the first dielectric layer 202) formed in the first trench 201 reaches 4.5 um, then the breakdown voltage capability between the P2 point (see Figure 4 ) inside the substrate 30 in the top region of the first trench 201 and the P1 point outside the substrate 30 is 1800 V. The distance between the W1' point at the bottom of the first trench 201 and the W2 point at the top of the first trench 201 is 100 um, and the W2 point can also be regarded as the point on the upper surface of the insulating dielectric layer 101 closest to the bottom W1' of the first trench 201. Therefore, the breakdown voltage value between W1' and W2 increases to 1800 V. Adding the 3600 V breakdown voltage between W2 and W3 (W3 is the point on the bonding lead 40 closest to W2), the total breakdown voltage capability of the path from W1' through W2 to W3 is increased to 5400 V (i.e., 1800 V + 3600 V).

[0097] Taking the 4000 V of the isolation device corresponding to d1 described above as a reference, it can be proved that through the chip structure provided by the embodiments of the present application, the isolation breakdown voltage capability of the chip can be effectively improved. If the processing method of the prior art will result in the isolation breakdown voltage capability being limited to 3600 V (not reaching the 4000 V of the isolation device), and based on the principle of the embodiments of the present application, the total breakdown voltage capability between the substrate 30 and the bonding lead 40 can be improved. For example, in the above example, the total breakdown voltage capability of the path from W1' through W2 to W3 reaches 5400 V, which has exceeded the breakdown voltage value of 4000 V between the first conductive structure 10 and the second conductive structure 20 of the isolation device. Therefore, the isolation breakdown voltage capability of the entire circuit system is improved, making the 4000 V isolation breakdown voltage capability of the isolation device of the chip effective, and the chip as a whole can support an isolation breakdown voltage capability of 4000 V (greater than 3600 V).

[0098] It should be noted that the numerical values in this example are only examples taken for comparison with the prior art. In actual applications, first trenches 201 with other depths and first dielectric layers 202 with other breakdown voltage capabilities per unit thickness can be used to form the insulating layer edge.

[0099] In the embodiments of the present application, in order to extend the breakdown path between the substrate 30 and the bonding wire 40, and to improve the overall breakdown voltage withstand capacity of the path of W1'-W2-W3, the edge wrapping of the insulating layer and the package body can be set to satisfy the breakdown voltage relationship of the first expression.

[0100] The first expression may include: 0.5×tox×Eox < ht×Et < 2×tox×Eox.

[0101] Wherein, ht represents the depth of the first trench 201, tox represents the thickness of the first dielectric layer 202 provided in the first trench 201, Eox represents the breakdown voltage withstand capacity per unit thickness of the first dielectric layer 202, and the first dielectric layer 202 becomes the edge wrapping of the insulating layer after the chip processing is completed, and Et represents the breakdown voltage withstand capacity per unit thickness of the package body filled on the outer surface of the edge wrapping of the insulating layer.

[0102] The Et can also be understood in another meaning: Et represents the breakdown voltage withstand capacity per unit thickness of the filled second dielectric layer, and the second dielectric layer is the plastic encapsulation material filled in the area corresponding to the first trench 201 (referring to the outer wall area of the edge wrapping of the insulating layer) and the outer surface space of the entire chip, and the second dielectric layer becomes the above-mentioned package body after the chip processing is completed (referring to after the chip encapsulation is completed).

[0103] Optionally, by reasonably setting the first dielectric layer 202, the overall breakdown voltage withstand capacity of the first dielectric layer 202 formed at the first trench 201 (including the breakdown voltage withstand capacity between points P1 and P2) can be made closer to the breakdown voltage withstand capacity corresponding to the thickness of the first trench 201, that is, the isolation breakdown voltage withstand capacity at the distance between P1 and P2 is improved as much as possible.

[0104] If the first dielectric layer 202 is relatively thick, then the breakdown path from the substrate 30 to the bonding wire 40 is from W1' at the bottom of the first trench 201 to W2 at the top of the chip and then to W3 of the bonding wire 40. If the first dielectric layer 202 is relatively thin, then the breakdown path is from a certain depth position Wx of the first trench 201 to W2 at the top of the chip and then to W3 of the bonding wire 40 (see Figure 4 ). However, no matter which of these two cases, the breakdown path is longer than that in the prior art ( Figure 2 W1-W2-W3 in), so the isolation breakdown voltage withstand capacity of the chip can be improved.

[0105] Optionally, in order to make full use of the entire depth ht of the first trench 201, so that in the case of opening the first trench 201 with a depth of ht, a chip with better isolation breakdown voltage withstand performance can be obtained with a breakdown path as long as possible, the edge wrapping of the insulating layer (the first dielectric layer 202) and the package body (the second dielectric layer) can be set to satisfy the breakdown voltage relationship of the second expression.

[0106] The second expression may include: ht×Et < tox×Eox.

[0107] This can extend the breakdown path between the substrate 30 and the bonding wire 40, so that the isolation breakdown voltage capability of the chip is optimized.

[0108] For the above chip structure provided by the embodiments of the present application, since an isolation device is provided on the substrate 30 of the chip, and an insulating layer edge wrapping is provided on the substrate 30 of the chip, and the insulating layer edge wrapping extends and wraps the substrate 30 in the direction from the first surface of the substrate 30 towards the second surface of the substrate 30. Therefore, in the case where there is a bonding wire 40 on the chip, the package formed by the insulating layer edge wrapping and filling can improve the package breakdown voltage performance of the entire chip, and can break through the product breakdown voltage bottleneck. Compared with the processing method that only considers the breakdown voltage capability of the isolation device itself on the chip and cannot further improve the product breakdown voltage performance, the above chip structure can improve the isolation breakdown voltage problem caused by the setting of the bonding wire 40 on the chip. Even if the difficult-to-modify bonding wire 40 is provided on the chip, the isolation breakdown voltage performance can be improved based on the above insulating layer edge wrapping structure. In some application scenarios, the bonding wire 40 and the package can be regarded as part of the chip provided by this embodiment.

[0109] Next, the position of the first trench 201 will be introduced, which can be regarded as an optimization of the position of the first trench 201.

[0110] Those skilled in the art should know that generally, forming a trench with a relatively large depth on a chip will bring relatively large stress, and if the stress is not well controlled, it is easy to cause the wafer or the chip to break. In addition, from the perspective of monitoring the manufacturing quality of the chip, it may be necessary to place some PCM structures (process control monitor) in the scribe lanes of the wafer for real-time monitoring of the product quality during the processing. Therefore, in the embodiments of the present application, considering these two aspects, the position of the first trench 201 is optimized.

[0111] Please refer to Figure 5 , Figure 5 which is a partial top view of a wafer. For the sake of simplicity of description, only the boundaries of four chips and the second conductive structure 20 in the isolation devices of these four chips are shown. In Figure 5 , the dotted line corresponding to each chip represents the wire bonding direction of the subsequent bonding wire 40 after cutting, and it is not a physical structure on the chip. Figure 5 A scribe region 301 is provided between the four chips in Figure 5 The "301" region in Figure 3 may include the "E-F" region in

[0112] Based on the above introduction of the insulating layer edge wrapping, the designated position for opening the first trench 201 is the scribe line of the wafer. As Figure 6 shown, the range of the first trench 201 must cover the center line 302 of the scribe line to ensure that the insulating layer edge wrapping can be exposed when the cutting is completed. Among them, Figure 6 A, B, C, and D in

[0113] are respectively the four corner points on the first trench 201.

[0114] Optionally, the width of the first trench 201 in the first direction perpendicular to the scribe line (AD = BC) is greater than the width of the tool 200, and the tool 200 is used to cut the scribe line. In this way, after the wafer is cut, the insulating layer edge wrapping can be exposed on the side cutting surface of the chip (that is, the side of the chip is still covered by the first dielectric layer 202), and the exposed insulating layer edge wrapping has a covering and isolation effect on a specific area of the substrate 30 (this specific area refers to part or all of the conductive area in the cutting surface of the substrate 30 in the direction from the first surface of the substrate 30 to the second surface).

[0115] Among them, the width of the first trench 201 in the second direction parallel to the scribe line (AB = CD) should be large enough, and the width of the first trench 201 in the second direction parallel to the scribe line can be determined based on Figure 7 the schematic diagram shown. The second direction is perpendicular to the first direction.

[0116] If when opening the first trench 201, it is ensured that the distance of the path W3 - W4 (see Figure 7 ) is not less than the distance of the path W1’ - W2 - W3, then new breakdown weak points can be avoided from being formed at positions such as W4 and W5 other than W2 after the first dielectric layer 202 is formed in the first trench 201. Among them, W4 and W5 respectively correspond to Figure 6 the A and B positions in

[0117] To avoid positions such as W4 and W5 other than W2 from becoming new breakdown weak points, the first trench 201 can be set according to the following requirements: Based on this, it can be obtained that:

[0118] That is, W2W4 represents half of the width of the first groove 201 in the second direction parallel to the scribe line. In specific implementation, for the consideration of design accuracy, the width of the first groove 201 in the second direction parallel to the scribe line (AB = CD = 2·W2W4, which can be denoted as the second width) can be relaxed, for example, it can be set to meet the requirements of the third expression.

[0119] The third expression may include:

[0120]

[0121] Wherein, AB represents the width of the first groove 201 in the second direction parallel to the scribe line, W1′W2 represents the depth of the first groove 201, and W2W3 represents the shortest distance between the edge of the first groove 201 on the first surface and the bonding wire 40.

[0122] Through the above implementation, some special positions on the insulation layer edge (such as both ends of the line segment AB) can be avoided from becoming breakdown weaknesses, and it is easy to implement.

[0123] Embodiment 2

[0124] This embodiment provides a digital isolator (not shown in the figure). The digital isolator includes the chip provided in the first embodiment. Other integrated circuit modules may also be included in the digital isolator. For the specific details of the chip with isolation devices in the digital isolator, please refer to the content about the chip provided in the first embodiment (for example, the content about the insulation layer edge, package, isolation devices, etc. can be referred to the content related to Figure 4 the shown structure), which will not be elaborated in this embodiment.

[0125] Since the digital isolator has the chip with an insulation layer edge provided in the first embodiment, the isolation breakdown voltage capability of the digital isolator can be improved.

[0126] Embodiment 3

[0127] This embodiment provides a wafer. The wafer referred to in this embodiment is the wafer to be cut. For the wafer provided in this embodiment, the content about the wafer introduced in the first embodiment can be referred to (for example, it can be referred to Figure 6 and the structure related to Figure 6 ).

[0128] The wafer provided in this embodiment includes: a plurality of chips, a scribe line is arranged between the plurality of chips, and a first groove 201 is formed on the scribe line. A first dielectric layer 202 is arranged in the first groove 201.

[0129] Any one of the multiple chips includes: a substrate 30 and an isolation device disposed on the substrate 30. The isolation device includes a first conductive structure 10, a second conductive structure 20, and an isolation layer 50 located between the first conductive structure 10 and the second conductive structure 20.

[0130] The substrate 30 has conductivity and can be a silicon substrate 30. The isolation layer 50 has good isolation breakdown voltage performance, and the material can be silicon dioxide. The thickness of the isolation layer 50 can be greater than or equal to 5 micrometers.

[0131] The first conductive structure 10 is disposed on the first surface of the substrate 30. The bonding lead 40 is to be disposed on the second conductive structure 20.

[0132] Among them, the wafer provided in this embodiment can obtain chips with an insulating layer edge after being cut by a tool 200 along the dicing street. The insulating layer edge is formed by extending in the direction from the first surface towards the second surface of the substrate 30. The insulating layer edge completely or partially wraps the conductive region between the first surface and the second surface. The outer surface of the chip is used to fill a second dielectric layer as a package.

[0133] Regarding other details of the wafer or chip provided in this embodiment, reference can be made to the relevant description in Embodiment 1, and details will not be elaborated herein.

[0134] The wafer provided in this embodiment can obtain the chips provided in the foregoing Embodiment 1, which is beneficial to improving the isolation breakdown voltage performance of the chips from the perspective of package breakdown voltage.

[0135] Embodiment 4

[0136] This embodiment provides a method for manufacturing a wafer chip.

[0137] Please refer to Figure 8 , a method for manufacturing a chip provided in this embodiment includes steps S41 - S45.

[0138] S41: Etch a first trench 201 on the dicing street of the wafer to be processed.

[0139] S42: Form a first dielectric layer 202 in the first trench 201.

[0140] Among them, regarding the content of the first trench 201, reference can be made to the relevant description in Embodiment 1. For example, for the position optimization of the first trench 201, the breakdown voltage setting requirements of the first dielectric layer 202, etc., reference can be made to the content related to the first expression, the second expression, and the third expression in Embodiment 1.

[0141] S43: For the wafer to be cut that includes the first dielectric layer 202 and isolation devices, use the cutting tool 200 to cut the cutting lane corresponding to the first trench 201, so as to cut a chip with an insulating layer edge from the wafer to be cut.

[0142] Among them, the chip obtained by cutting through S43 includes: a substrate 30 and isolation devices disposed on the substrate 30. The isolation devices include: a first conductive structure 10, a second conductive structure 20, and an isolation layer 50 located between the first conductive structure 10 and the second conductive structure 20. The first conductive structure 10 is disposed on the first surface of the substrate 30. The insulating layer edge is formed by the first dielectric layer 202 extending from the first surface towards the second surface of the substrate 30, and the insulating layer edge wraps all or part of the conductive region between the first surface and the second surface.

[0143] S44: For the cut chip, dispose a bonding lead 40 on the second conductive structure 20.

[0144] S45: Fill the outer surface of the chip with a second dielectric layer as the package of the chip.

[0145] In the methods of S41 - S45 above, by first opening the first trench 201 and forming the first dielectric layer 202 in the first trench 201 before cutting the wafer, and then performing wafer cutting and processing based on this, a process implementation method that can obtain the chip structure provided in the foregoing Embodiment 1 is provided. When the chip obtained based on this method is applied to a circuit system, the chip with an insulating layer edge and a package can effectively improve the isolation breakdown voltage of the entire circuit system or isolator product. When there is a bonding lead 40 on the chip, the package breakdown voltage performance of the entire chip can be improved through the insulating layer edge and the package of the chip, and the product breakdown voltage bottleneck can be broken. For the content related to the structure of the chip in this method, reference can be made to the relevant description in Embodiment 1 above.

[0146] Next, two implementation manners will be provided to introduce the chip manufacturing method provided in this embodiment. The difference between these two implementation manners lies in: the timing of setting the first trench 201 and the first dielectric layer 202 is different. The first implementation manner is to set the first trench 201 and the first dielectric layer 202 in the back-end process, while the second implementation manner is to set the first trench 201 and the first dielectric layer 202 in the front-end process of chip manufacturing (referring to the front process).

[0147] Among them, the full English name of the back-end process is back-end of layout, abbreviated as BEOL, and the full English name of the front-end process is front-end of layout, abbreviated as FEOL. The division between the front-end process and the back-end process is demarcated by the contact (interconnection) process. The process before interconnection is usually called the front-end process, and vice versa (usually including copper interconnection) is called the back-end process.

[0148] Since in the field of chip manufacturing, the conventional processes of the front-end process and the back-end process are common knowledge to those skilled in the art, this application does not introduce specific process details. In the method provided in this embodiment, as long as a wafer to be cut that meets the requirements can be obtained before performing the wafer dicing step, and then a chip structure including an insulating layer edge wrap and a package can be obtained through the steps of S43-S45.

[0149] In the first implementation manner, the execution timing of S41 is selected in the back-end process flow of the chip.

[0150] That is, S41 may include: S411.

[0151] S411: After completing part of the back-end process of the chip on the wafer to be processed, etch a first trench 201 on the dicing lane of the wafer to be processed. The wafer to be processed includes the substrate 30 of each chip and the isolation devices of each chip.

[0152] Among them, after completing more than 70% of the total number of photolithography times of the back-end process of the chip, the first trench 201 can be formed on the dicing lane by performing insulating layer etching and deep silicon etching. Figure 9 Shows the processing state of the wafer to be processed before executing S411. In Figure 9 Among them, the area between E and F is regarded as the dicing lane of the wafer to be processed. This wafer to be processed includes the substrate 30 shared by adjacent chip components (with isolation devices). In Figure 9 In the state schematic diagram shown, only the last dielectric layer remains to be deposited in the back-end process of the chip at this time, and all other necessary processes have been completed. Among them, this last dielectric layer can be the aforementioned insulating dielectric layer 101, which needs to be formed before plastic packaging.

[0153] The reason for starting to etch the first trench 201 only after completing more than 70% of the total number of photolithography times of the back-end process is that the subsequent process will increase the unevenness of the chip surface, which is more suitable for being carried out when the line width is larger in the later stage. Based on this, selecting the timing of etching the first trench 201 and then executing the above method can reduce the impact on the photolithography result.

[0154] Based on S411, after etching and forming the first trench 201, based on Figure 9 The structure shown, inFigure 9 A first opening is provided on the surface of the chip shown. Among them, by means of spin-coating photoresist and exposure and development, the position of the first opening is within the range of the dicing street (the dicing street is located between adjacent chips on the wafer, and the area in the dicing street where no actual functional circuits are fabricated), and the processing result as shown in Figure 10 is obtained. Then, an etching machine (such as an oxide etching machine and a deep reactive ion etching machine) can be used to etch and form the first trench 201, and the trench processing result as shown in Figure 11 can be obtained.

[0155] In the case where the first trench 201 is formed by the implementation method of S411, the above S42 may include: S421.

[0156] S421: Form a first dielectric layer 202 in the first trench 201 by a deposition process to obtain the wafer to be diced.

[0157] Exemplarily, based on Figure 11 the obtained trench processing result, deposition can be carried out on this basis. The first dielectric layer 202 (and the aforementioned insulating dielectric layer 101 can also be deposited) can be deposited and formed, so that there is a first dielectric layer 202 with better voltage resistance in the first trench 201, and the deposition result is as shown in Figure 12 shown. Among them, after the first dielectric layer 202 is formed, a second opening can be opened in the first dielectric layer 202 formed at some positions, so that the welding position of the second conductive structure 20 in the isolation device is exposed, and the processing result as shown in Figure 13 can be obtained. That is, the partial position here refers to the position where the second conductive structure 20 is located. Opening the second opening is beneficial to the setting of the bonding wire 40. Figure 13 The structure of can be used as the wafer to be diced.

[0158] Optionally, according to the design requirements of the chip structure, the timing of opening the second opening can be before dicing or after dicing, as long as it can provide a wire bonding space for the setting of the bonding wire 40.

[0159] After performing the aforementioned methods of S41 - S45 based on the first embodiment, completing wafer dicing, setting the bonding wire 40, and completing packaging, the chip structure as shown in Figure 4 can be obtained ( Figure 4 the package body is not marked in, but in the whole chip, except for the bonding wire 40 that needs to be exposed, the remaining areas can be regarded as being encapsulated by the plastic encapsulation material).

[0160] It can be understood that the content about the first trench 201 and the insulating layer edge (the first dielectric layer 202) in the first embodiment is still applicable in this embodiment, and the same parts can be referred to each other.

[0161] The second implementation mode selects the execution timing of S41 in the front-end process flow of the chip. This second implementation mode is similar to the aforementioned first implementation mode, except for the specific processes of forming the first trench 201 and the first dielectric layer 202. In this second implementation mode, it is allowed to complete the fabrication of the oxide trench at the front end (front-end process) of the chip manufacturing process, thereby forming the first trench 201.

[0162] That is, S41 may include: S412.

[0163] S412: In the front-end process of the chip manufacturing process, etch and form the first trench 201 on the scribe line of the wafer to be processed.

[0164] Exemplarily, considering that STI (shallow trench isolation process) or LOCOS (local oxidation of silicon process) will be used in the chip manufacturing process, for example, oxides with a thickness of several hundred nanometers to dozens of micrometers will be formed by oxidation. Therefore, before performing the polar STI or LOCOS process on the chip, a first trench 201 with an aspect ratio greater than 5:1 can be formed on the first surface of the substrate 30 by etching, and the trench processing result as shown in Figure 14 can be obtained (at this time, the processed isolation device has not been obtained on the substrate 30).

[0165] Based on S412, S42 in the above method may include: S422.

[0166] S422: Form the first dielectric layer 202 in the first trench 201 by an oxidation process or a deposition process to obtain the substrate 30 covered by the first dielectric layer 202 as the structure to be processed.

[0167] Exemplarily, based on the structure shown in Figure 14 , in the STI or LOCOS process flow, the first trench 201 can be filled with the first dielectric layer 202 (such as silicon oxide) by an oxidation process or a deposition process to obtain the structure to be processed as shown in Figure 15 (at this time, the processed isolation device has not been obtained on the substrate 30).

[0168] Then, on the basis of the structure to be processed, isolation devices for each chip can be formed to obtain the wafer to be diced, and the result as shown in Figure 16The wafer to be diced as shown. For example, surface planarization processing can be performed on the structure to be processed (in the case of the STI process, there is usually a subsequent planarization step by default), and then subsequent chip manufacturing processes are performed on the planarized structure to be processed to form circuit modules of each chip on the structure to be processed. For example, isolation devices of each chip are formed on the structure to be processed (and the aforementioned insulating dielectric layer 101 can also be formed on the isolation devices). Based on this, a wafer to be diced including the first dielectric layer 202 and isolation devices is obtained.

[0169] Similar to the first implementation manner, after processing in the second implementation manner, it is also possible to cut and obtain a bevel with an oxide around the first surface of the substrate 30 (i.e., the aforementioned insulating layer bevel), which plays a role in enhancing the isolation breakdown voltage capability.

[0170] In the embodiments provided in the present application, it should be understood that the described embodiments can be implemented in other ways. The embodiments described above are merely illustrative. For example, the wafer processing process can be implemented by other process technologies, and there can be other more abundant circuit function modules on the chip in addition to the isolation devices.

[0171] It should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", "horizontal", "vertical", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. Terms such as "horizontal" and "vertical" do not mean that the components are required to be absolutely horizontal or hanging, but can be slightly inclined.

[0172] In this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0173] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip, characterized in that, The chip includes: a substrate and isolation devices disposed on the substrate; The isolation devices include a first conductive structure, a second conductive structure, and an isolation layer located between the first conductive structure and the second conductive structure; The first conductive structure is disposed on a first surface of the substrate; Bonding leads are to be disposed on the second conductive structure; Wherein, an insulating layer edge is disposed extending in a direction from the first surface towards a second surface of the substrate, and the insulating layer edge wholly or partially wraps a conductive region between the first surface and the second surface, and an outer surface of the chip is for filling with a packaging material to form a package.

2. The chip according to claim 1, characterized in that The insulating layer edge is a structure formed at an edge region of the first surface after cutting the specified position on the wafer after opening a first trench at a specified position on the wafer and disposing a first dielectric layer in the first trench during the chip processing.

3. The chip according to claim 2, characterized in that, A voltage withstand relationship of a first expression is satisfied between the insulating layer edge and the package; The first expression includes: 0.5×tox×Eox < ht×Et < 2×tox×Eox; Wherein, ht represents a depth of the first trench, tox represents a thickness of the first dielectric layer disposed in the first trench, Eox represents a voltage withstand capacity per unit thickness of the first dielectric layer, and the first dielectric layer becomes the insulating layer edge after the chip processing is completed, and Et represents a voltage withstand capacity per unit thickness of the package filled on an outer surface of the insulating layer edge.

4. The chip according to claim 3, characterized in that, A voltage withstand relationship of a second expression is satisfied between the insulating layer edge and the package; The second expression includes: ht×Et < tox×Eox.

5. The chip according to claim 2, wherein, The specified position is a dicing lane of the wafer, and a width of the first trench in a first direction perpendicular to the dicing lane is greater than a width of a tool for cutting the dicing lane.

6. The chip according to claim 5, characterized in that, A width of the first trench in a second direction parallel to the dicing lane satisfies a third expression; The third expression includes: Wherein, AB represents the width of the first trench in the second direction parallel to the dicing lane, W1′W2 represents the depth of the first trench, and W2W3 represents the shortest distance between an edge of the first trench on the first surface and the bonding lead.

7. A digital isolator, characterized in that, Including the chip according to any one of claims 1-6.

8. A method for manufacturing a chip, characterized in that, The method includes: Etching to form a first trench on a dicing lane of a wafer to be processed; Forming a first dielectric layer in the first trench; For a wafer to be diced that includes the first dielectric layer and isolation devices, a cutting tool is used to cut the saw street corresponding to the first trench, so as to cut a chip with an insulating layer edge from the wafer to be diced. The chip includes: a substrate and the isolation devices disposed on the substrate. The isolation devices include: a first conductive structure, a second conductive structure, and an isolation layer located between the first conductive structure and the second conductive structure. The first conductive structure is disposed on a first surface of the substrate. The insulating layer edge is formed by the first dielectric layer extending from the first surface toward the second surface of the substrate. The insulating layer edge completely or partially wraps the conductive region between the first surface and the second surface. For the obtained chip, bonding leads are disposed on the second conductive structure. A second dielectric layer is filled on the outer surface of the chip as a package body of the chip.

9. The method according to claim 8, wherein The etching to form the first trench on the saw street of the wafer to be processed includes: After completing part of the post-process of the chip on the wafer to be processed, the first trench is etched on the saw street of the wafer to be processed. The wafer to be processed includes the substrates of the respective chips and the isolation devices of the respective chips. The forming of the first dielectric layer in the first trench includes: The first dielectric layer is formed in the first trench by a deposition process to obtain the wafer to be diced.

10. The method according to claim 9, wherein After completing part of the post-process of the chip on the wafer to be processed, the etching to form the first trench on the saw street of the wafer to be processed includes: After completing more than 70% of the total number of photolithography times of the post-process of the chip, the first trench is formed on the saw street by performing insulating layer etching and deep silicon etching.

11. According to the method described in claim 8, wherein The etching to form the first trench on the saw street of the wafer to be processed includes: In the front process of chip manufacturing, the first trench is etched on the saw street of the wafer to be processed. The forming of the first dielectric layer in the first trench includes: The first dielectric layer is formed in the first trench by an oxidation process or a deposition process to obtain a substrate covered by the first dielectric layer as a structure to be processed. Before using the cutting tool to cut the saw street corresponding to the first trench, the method further includes: The isolation devices of the respective chips are formed on the structure to be processed to obtain the wafer to be diced.

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