A method for restoring a PWM pass-through signal to its original signal

Abstract

The present invention discloses a method for restoring a PWM through-signal to an original signal, comprising a current limiting resistor, a NAND gate chip, a NOR gate chip, and a logic gate chip to form a sequential logic circuit with a memory function; the present invention realizes the processing of the PWM through-signal through a simple hardware circuit, and effectively improves the anti-interference performance of a power electronic device by restoring the through-signal interfered on a PWM transmission line to an original signal; through the solution proposed by the present invention, the PWM through-state caused by interference on the transmission line does not damage the power electronic device and does not reduce its working performance.

Description

Technical Field

[0001] The invention relates to a method for restoring a PWM through signal to an original signal, belonging to the technical field of power electronics. Background Art

[0002] In power electronic devices, the PWM drive link is the hub for realizing the control of the strong power system by the weak current system, and the working reliability of the PWM drive link is crucial for power electronic devices. For the voltage source bridge conversion circuit, the PWM drive signal of the same bridge arm is a complementary signal and has a dead zone. When the PWM drive signal of the same bridge arm is in a through state due to interference, it will cause the voltage source to short-circuit and damage the power electronic switch of the bridge arm. The traditional solution is to convert the PWM through-drive signal of the same bridge arm into a dead zone signal to protect the power electronic switch. In complex electromagnetic environments or extreme conditions, especially in high-power applications, converting the interfered PWM through-signal into a dead zone signal will affect the performance of the power supply. For example, the bridge topology power electronic device will cause high harmonic distortion rate of the input current and large output voltage ripple. Therefore, it is necessary to propose a method to restore the PWM through-signal to the original signal. Summary of the invention

[0003] In view of the above problems and technical requirements, the inventors have proposed a method for restoring a PWM direct-pass signal to an original signal. This method can protect a power electronic device from being damaged by PWM drive direct-pass, and at the same time, can restore the PWM drive direct-pass signal caused by interference to the original signal, thereby ensuring that the performance of the power electronic device is not affected.

[0004] The technical solution of the present invention is: a method for restoring a PWM direct-through signal to an original signal. When a direct-through signal appears in the PWM drive of the same bridge arm, a sequential logic circuit is formed by a NAND gate circuit and a NOR gate circuit to latch the level information of the circuit at the previous moment, and the direct-through PWM drive level signal is restored to the initial value, thereby protecting the working performance of the power electronic device from being affected.

[0005] The technical solution of the present invention is as follows:

[0006] The first input terminal and the second input terminal of the scheme are respectively connected to the PWM controller. The driving signal of the upper bridge arm of the PWM controller is input from the first input terminal, and the driving signal of the lower bridge arm of the PWM controller is input from the second input terminal.

[0007] The first input terminal is connected to the first terminal of the first NAND gate through a first current limiting resistor, and the first input terminal is connected to the first terminal of the first NOR gate through a first current limiting resistor.

[0008] The second input terminal is connected to the first terminal of the second NAND gate through a second current limiting resistor, and the second input terminal is connected to the second terminal of the first NOR gate through a second current limiting resistor.

[0009] The output end of the first NAND gate is connected to the second end of the second NAND gate, and the output end of the first NAND gate is connected to the first end of the second NOR gate.

[0010] The output end of the second NAND gate is connected to the second end of the first NAND gate, and the output end of the second NAND gate is connected to the first end of the third NOR gate.

[0011] The output end of the first NOR gate is connected to the second end of the second NOR gate, and the output end of the first NOR gate is connected to the second end of the third NOR gate.

[0012] The output end of the second NOR gate drives the upper bridge arm switch, and the output end of the third NOR gate drives the lower bridge arm switch.

[0013] The present invention adopts the above technical solution and has the following beneficial effects:

[0014] (1) In the current voltage source bridge topology, the PWM direct-through signal is converted into a dead zone signal through an anti-direct-through circuit. This engineering solution can only protect the power electronic device from being damaged by the PWM direct-through signal, but cannot restore the actual PWM drive signal, which affects the working performance of the power electronic device. By adopting the technical solution in the present invention and utilizing the memory function of the sequential logic circuit, the direct-through PWM drive signal can be restored to the initial drive signal, effectively improving the anti-interference performance of the power electronic device.

[0015] (2) According to the technical solution proposed by the present invention, the protection of PWM direct-through signals of different levels ("11" and "00") can be easily realized by using the NAND gate and the NOR gate, and the direct-through "11" or "00" level signal can be restored to the initial level signal by using the memory function of the timing logic circuit.

[0016] (3) The present invention adopts discrete NAND gates and NOR gate devices, which facilitates PCB layout and wiring, effectively reduces line impedance, and improves the anti-interference performance of the power electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the circuit principle of the present invention;

[0018] Figure 2 It is a schematic diagram of the processing of the PWM drive direct-through signal of the present invention;

[0019] Figure 3 is the circuit operation truth table of the present invention;

[0020] Figure 4 It is the circuit schematic diagram of the actual design;

[0021] Figure 5 The present invention is a schematic diagram of a circuit principle for restoring a PWM direct-pass signal to an original signal by using a NAND gate and a NOR gate in different application scenarios when the PWM driving level "00" is a direct-pass signal according to the technical solution proposed in this scheme. DETAILED DESCRIPTION

[0022] The technical solution of the invention is described in detail below in conjunction with the accompanying drawings. The examples given are only used to explain the invention but not to limit the scope of the invention.

[0023] The present invention proposes a method for restoring a PWM direct-through signal to an original signal, please refer to Figure 1 The circuit schematic diagram shown. The output signal PWM1 of the PWM controller is connected to the first input end of the first NAND gate U1 and the first input end of the first NOR gate U3 through the current limiting resistor R1; the output signal PWM2 of the PWM controller is connected to the second input end of the second NAND gate U2 and the second input end of the first NOR gate U3 through the current limiting resistor R2; the output end of the first NAND gate U1 is connected to the first input end of the second NAND gate U2 and the first input end of the second NOR gate U4; the output end of the second NAND gate U2 is connected to the second input end of the first NAND gate U1 and the second input end of the third NOR gate U5; the input end of the first NOR gate U3 is connected to the second input end of the second NOR gate U4 and the first input end of the third NOR gate U5; the output signal Drive_up of the second NOR gate U4 drives the upper tube of the bridge arm, and the output signal Drive_down of the third NOR gate U5 drives the lower tube of the bridge arm.

[0024] The present invention proposes a method for restoring a PWM direct-through signal to an original signal. According to the technical solution proposed by the present invention, the PWM drive signal of the same bridge arm is restored to an original signal through the direct-through signal. Figure 1 The output signal after the circuit schematic is shown is:

[0025] (1) When PWM1 is high and PWM2 is low, the upper and lower are complementary. According to the technical solution proposed by the present invention, the output signal Drive_up is high and Drive_down is low. After the gate circuit pulse shaping, the original logic level of the PWM signal is not changed;

[0026] (2) When PWM1 is low and PWM2 is high, the upper and lower are complementary. According to the technical solution proposed by the present invention, the output signal Drive_up is low and Drive_down is high. After the gate circuit pulse shaping, the original logic level of the PWM signal is not changed;

[0027] (3) When PWM1 is low and PWM2 is low, the dead zone is entered. According to the technical solution proposed by the present invention, the output signal Drive_up is low and Drive_down is low. After the gate circuit pulse shaping, the original logic level of the PWM signal is not changed, and the dead zone is not affected.

[0028] (4) When PWM1 is high and PWM2 is high, this state is not the normal state of the power electronic device. In the bridge topology without the soft switching technology solution, the interference between the upper and lower tubes of the bridge arm is difficult to eliminate. If the power electronic device is in a complex electromagnetic environment, the complementary level signal output by the PWM controller is easily interfered with, resulting in a direct-through condition. If the PWM controller outputs PWM1 as a high level and PWM2 as a low level, and the transmission line is interfered with, causing PWM2 to appear high, this will cause a direct-through condition in the same bridge arm. The current engineering solution converts this condition into a dead zone to protect the power electronic device. According to the technical solution proposed in the present invention, the PWM direct-through signal passes through Figure 1 After the circuit schematic diagram is shown, the output signals Drive_up and Drive_down can be restored to the state before the interference, please refer to Figure 2 The direct signal processing schematic is shown.

[0029] Combination Figure 2 As shown, at t0~t3, the PWM controller output signal PWM1 is high and PWM2 is low; t3~t4 is the dead time when PWM1 and PWM2 are low; under normal working conditions without interference, the logic levels of the signals at points A and B are the same as PWM1 and PWM2 respectively; at t1, the PWM signal transmission loop is disturbed, causing the signal at point B to suddenly change from a low level to a high level. Since the latch composed of the first NAND gate U1, the second NAND gate U2, the second NOR gate U4 and the third NOR gate U5 can memorize the level states of the signals Q and Q', the level states of Drive_up and Drive_down are respectively consistent with the level states of PWM1 and PWM2, and are not affected by the sudden change of the signal at point B from a low level to a high level due to the interference of the PWM transmission loop during the time period t1~t2. During the dead time t3~t4, PWM1 and PWM2 are both low levels. After passing through the first NOR gate U3, the output terminal level S is high, ensuring that the level states of Drive_up and Drive_down are both low levels during the dead time period. Similarly, when the PWM controller output signals PWM1 is low and PWM2 is high, when the signal at point A suddenly changes from a low level to a high level due to interference in the PWM signal transmission loop, Drive_up and Drive_down can maintain the level states of PWM1 and PWM2.

[0030] The circuit schematic diagram designed according to the technical solution of the present invention has a working truth table as shown in FIG. Figure 3 shown.

[0031] In order to more clearly explain the technical solution proposed by the present invention, please refer to Figure 4 . Figure 4 It is a circuit schematic diagram designed in an actual product. It should be pointed out that the circuit is only a method to implement the solution of the present invention. All equivalent technical changes made under the working principle and idea of ​​the present invention are deemed to be within the protection scope of the present invention.

[0032] According to the technical solution proposed by the present invention, those skilled in the art can obtain other drawings without creative work, such as Figure 5 In engineering design, when the through signal of the same bridge arm is at a low level and the dead zone signal is at a high level, according to the idea of ​​the present invention, it is easy to obtain Figure 5 .

Claims

1. A method for restoring a PWM through signal to an original signal, characterized in that: Contains current limiting resistors, NAND gate chips, and NOR gate chips; The first input terminal and the second input terminal of the method are respectively connected to the PWM controller, the driving signal of the PWM controller to the upper bridge arm is input from the first input terminal, and the driving signal of the PWM controller to the lower bridge arm is input from the second input terminal; The first input terminal is connected to the first terminal of the first NAND gate through the first current limiting resistor, and the first input terminal is connected to the first terminal of the first NOR gate through the first current limiting resistor; the second input terminal is connected to the first terminal of the second NAND gate through the second current limiting resistor, and the second input terminal is connected to the second terminal of the first NOR gate through the second current limiting resistor; the output terminal of the first NAND gate is connected to the second terminal of the second NAND gate, and the output terminal of the first NAND gate is connected to the first terminal of the second NOR gate; the output terminal of the second NAND gate is connected to the second terminal of the first NAND gate, and the output terminal of the second NAND gate is connected to the first terminal of the third NOR gate; the output terminal of the first NOR gate is connected to the second terminal of the second NOR gate, and the output terminal of the first NOR gate is connected to the second terminal of the third NOR gate; The output end of the second NOR gate drives the upper bridge arm switch, and the output end of the third NOR gate drives the lower bridge arm switch.

2. A method for restoring a PWM through signal to an original signal as claimed in claim 1, characterized in that: Logic gate chips form sequential logic circuits with memory functions.

Images