Full-mold semiconductor packaging for power devices and its manufacturing method

Abstract

This application discloses a method for fabricating a semiconductor device, which may include providing a semiconductor die including a front surface having a gate bonding pad and a source bonding pad, and a back surface opposite the front surface having a drain. A gate pillar may be formed above and coupled to the gate bonding pad. A source pillar may be formed above and coupled to the source bonding pad. A package may be formed above the semiconductor die. A via interconnect may extend between opposing first and second surfaces of the package. An RDL may be coupled to the gate pillar, the source pillar, and the via interconnect. After the semiconductor die is diced from its native wafer and after the package is formed above the semiconductor die, a pad bonding pad may be formed above the back surface of the semiconductor die and coupled to the drain.

Description

[0001] Cross-referencing of related patent applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 62 / 661,535, filed April 23, 2018, entitled “Fully Molded Semiconductor Package for Power Devices,” the disclosure of which is hereby incorporated by reference. Technical Field

[0003] This application relates generally to semiconductor devices, and more particularly to fully molded semiconductor packages, and even more particularly to fully molded semiconductor packages (FMSP-PD) for power devices. Background Technology

[0004] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices typically contain one type of electrical component, such as light-emitting diodes (LEDs), small-signal transistors, resistors, capacitors, inductors, and power metal-oxide-semiconductor field-effect transistors (MOSFETs). Integrated semiconductor devices generally contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

[0005] Semiconductor devices perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual projections for television displays. Semiconductor devices are found in entertainment, communications, power conversion, networking, computers, and consumer products. They are also used in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0006] Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of semiconductor materials allows their conductivity to be manipulated by applying an electric field or base current, or through doping processes. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

[0007] Semiconductor devices contain active and passive electrical structures. Active structures (including bipolar and field-effect transistors) control the flow of current. By changing the level of doping and the level of the electric field or base current applied, transistors promote or restrict the flow of current. Passive structures (including resistors, capacitors, and inductors) establish the voltage-current relationship necessary to perform a variety of electrical functions. Passive and active structures are electrically connected to form circuits, which enable semiconductor devices to perform high-speed calculations and other practical functions.

[0008] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication, each potentially involving hundreds of steps. Front-end fabrication involves forming multiple semiconductor dies on the surface of a semiconductor wafer. Each semiconductor die is generally identical and contains circuitry formed by electrically connecting active and passive components. Back-end fabrication involves dicing individual semiconductor dies from a finished wafer and packaging the die to provide structural support and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word and can refer to both a single semiconductor device and multiple semiconductor devices.

[0009] One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be manufactured more efficiently. Furthermore, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. Smaller semiconductor die sizes can be achieved by improving front-end processes, resulting in semiconductor dies with smaller, higher-density active and passive components. Back-end processes can produce semiconductor device packages with smaller footprints by improving electrical interconnects and packaging materials. Summary of the Invention

[0010] This disclosure relates to a fully molded semiconductor package, and more particularly to a fully molded semiconductor package (FMSP-PD) for power devices. Thus, in one aspect, a method of fabricating a semiconductor package may include providing a semiconductor die including a front surface having a gate bonding pad and a source bonding pad, and a back surface opposite the front surface having a drain. A gate pillar may be formed above and coupled to the gate bonding pad. A source pillar may be formed above and coupled to the source bonding pad. A package may be formed above the semiconductor die, and the package includes a first surface and a second surface opposite the first surface, the first surface being above the front surface of the semiconductor die. A through-hole interconnect (RDI) may extend between the first surface and the second surface of the package. An RDL may be coupled to the gate pillar, the source pillar, and the RDL. After the semiconductor die is diced from its native wafer and after the package is formed on top of the semiconductor die, land pads can be formed on the back surface of the semiconductor die and coupled to the drain.

[0011] The method of fabricating the semiconductor device may further include forming the package around the semiconductor die and contacting the side surface of the gate pillar and the side surface of the source pillar. The pad bonding joint may be formed having an area larger than the area of ​​the semiconductor die. The source pillar may be formed having an area greater than or equal to 50% of the area of ​​the semiconductor die. A barrier layer may be formed above the drain and extend beyond the occupied area of ​​the semiconductor die. The barrier layer may contact 80% or more of the back surface of the semiconductor die. The pad bonding joint may be formed above the barrier layer after the barrier layer is formed. The source pillar may be formed having an area greater than or equal to 50% of the area of ​​the semiconductor die. The gate pillar may be formed above the gate bonding joint and coupled to the gate bonding joint before the semiconductor die is diced from its native wafer. The source pillar can be formed above the source bonding pad and coupled to the source bonding pad before the semiconductor die is cut from its native wafer.

[0012] In another aspect, a method of fabricating a semiconductor package may include providing a semiconductor die including a front surface containing source bonding pads and a back surface opposite the front surface containing a drain. Source pillars may be formed above and coupled to the source bonding pads. A package may be formed above the semiconductor die, and the package includes a first surface and a second surface opposite the first surface, the first surface above the front surface of the semiconductor die. Through-hole interconnects may be formed extending between the first surface and the second surface of the package. After the semiconductor die is diced from its native wafer, bonding pads may be formed above the back surface of the semiconductor die and coupled to the drain, the bonding pads extending beyond the occupied area of ​​the semiconductor die.

[0013] The method of fabricating the semiconductor device may further include forming a pad bonding joint having an area larger than that of the semiconductor die. The package may be formed around the semiconductor die and contacting a side surface of the gate pillar and a side surface of the source pillar. The source pillar may be formed having an area greater than or equal to 50% of the area of ​​the semiconductor die. A barrier layer may be formed above the drain and extending beyond the occupied area of ​​the semiconductor die, the barrier layer contacting 80% or more of the back surface of the semiconductor die. The pad bonding joint may be formed above the barrier layer after the barrier layer is formed. The source pillar may be formed having an area greater than or equal to 50% of the area of ​​the semiconductor die. The gate pillar may be formed above the gate bonding joint and coupled to the gate bonding joint before the semiconductor die is diced from its native wafer. The source pillar can be formed above the source bonding pad and coupled to the source bonding pad before the semiconductor die is cut from its native wafer.

[0014] In another aspect, a method of fabricating a semiconductor package may include providing a semiconductor die including a front surface containing source bonding pads and a back surface opposite the front surface containing a drain. A package may be formed over the semiconductor die, and the package includes a first surface and a second surface opposite the first surface, the first surface being located above the front surface of the semiconductor die. Through-hole interconnects may be formed and extend between the first surface and the second surface of the package. After the package is formed over the semiconductor die, bonding pads may be formed above the back surface of the semiconductor die and coupled to the drain.

[0015] The semiconductor package may further include a pad bonding joint formed to extend beyond the occupied area of ​​the semiconductor die. A source pillar may be formed above and coupled to the source bonding joint. The package may be formed to surround the semiconductor die and contact the side surface of the source pillar. The source pillar may be formed to have an area greater than or equal to 50% of the area of ​​the semiconductor die. A barrier layer may be formed above the drain and extend beyond the occupied area of ​​the semiconductor die, the barrier layer contacting 80% or more of the back surface of the semiconductor die. The pad bonding joint may be formed above the barrier layer after the barrier layer is formed. A gate pillar may be formed above and coupled to the gate bonding joint before the semiconductor die is diced from its native wafer. A source pillar may be formed above and coupled to the source bonding joint before the semiconductor die is diced from its native wafer.

[0016] Those skilled in the art will clearly understand the foregoing and other aspects, features and advantages from the specific embodiments, drawings and claims. Attached Figure Description

[0017] Figures 1A to 1D The illustration depicts multiple semiconductor dies containing pillars for use in FMSP-PD;

[0018] Figures 2A to 2F A view illustrating the method for forming FMSP-PD;

[0019] Figure 3A and Figure 3B Various cross-sectional side views illustrating embodiments of FMSP-PD are shown. Detailed Implementation

[0020] Referring in the following description to the accompanying drawings, this disclosure includes one or more aspects or embodiments, wherein similar reference numerals represent the same or similar components. Those skilled in the art will understand that this description is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of this disclosure, which is defined by the appended claims and their effects supported by the following disclosure and figures.

[0021] In this description, numerous specific details, such as specific configurations, components, and procedures, are set forth to provide a full understanding of this disclosure. In other instances, specific details of well-known procedures and manufacturing techniques have not been described to avoid obscuring this disclosure. Furthermore, the various embodiments shown in the figures are illustrative and not necessarily to scale.

[0022] The terms “exemplary,” “example,” or any of their various forms, as used herein, are intended to be used as examples, cases, or illustrations. Any aspect or design described herein as “exemplary” or “example” is not necessarily to be considered preferred or superior to other aspects or designs. Furthermore, examples are provided for clarity and understanding purposes only and are not intended to limit or restrict the disclosed subject matter or any part thereof in any way. It will be understood that numerous additional or alternative examples of varying scope may be presented, but have been omitted for the sake of brevity.

[0023] As used herein, the terms “above,” “between,” and “above” refer to the relative position of a layer with respect to other layers. A layer deposited or disposed above or below another layer may be in direct contact with that other layer or may have one or more intermediate layers. A layer deposited or disposed between layers may be in direct contact with those layers or may have one or more intermediate layers.

[0024] Broadly speaking, semiconductor devices are manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming a plurality of dies on the surface of a semiconductor die. Each die on the wafer contains active and passive electrical components electrically connected to form functional circuitry. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, resistors, and transformers) establish the voltage and current relationships necessary to perform the circuitry's functions.

[0025] Passive and active components are formed on the surface of a semiconductor die through a series of process steps, including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material using techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device, transforming it into an insulator, a conductor, or dynamically changing its conductivity in response to an electric field or base current. Transistors contain regions configured with different types and degrees of doping as necessary to enable the transistor to facilitate or restrict current flow when an electric field or base current is applied.

[0026] Active and passive components are formed from layers of materials with different electrical properties. These layers can be formed using a variety of deposition techniques, the specific technique depending on the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. Generally, the layers are patterned to form active component portions, passive component portions, or electrical connections between components.

[0027] Photolithography can be used to pattern layers. Patterning is a fundamental operation for removing portions of the top layer from the surface of a semiconductor die. Photolithography, photomasks, oxide or metal removal, photographic and stencil printing, and microlithography can be used to remove portions of the semiconductor die. Optical lithography involves: forming a pattern in an intermediate reticle or a photomask; and transferring the pattern to the layer to be patterned, such as the surface layer of the semiconductor die. Optical lithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor die in a one-to-two process. The first step is to transfer the pattern of a magnifying mask or photomask onto a photoresist layer. Photoresist is a photosensitive material whose structure and properties change upon exposure. The process of changing the structure and properties of the photoresist occurs as negative-active or positive-active photoresist. The second step is to transfer the photoresist layer to the wafer surface. Transfer occurs when etching removes the portion of the top layer of the semiconductor die that is not covered by the photoresist. Alternatively, some types of materials are patterned by directly depositing the material onto areas or voids formed by photoresist or by previous deposition / etching processes using techniques such as electroless and electrolytic plating. The chemistry of the photoresist ensures that it remains substantially intact and resists removal by chemical etching solutions or plating chemicals while removing or adding portions of the top layer of the semiconductor die that are not covered by the photoresist. The processes for forming, exposing, and removing the photoresist can be modified depending on the specific photoresist used and the desired result, as well as the process for removing or adding portions of the semiconductor die.

[0028] Back-end manufacturing refers to the process of dicing or slicing finished wafers into individual semiconductor dies, followed by packaging the dies for structural support and environmental isolation. To dice semiconductor dies, the wafer is cut along non-functional areas known as saw streets or scribes. Laser dicing tools or saw blades are used. After dicing, the individual semiconductor dies are mounted to a package substrate, which includes pins or contact bonding pads for interconnection with other system components. Contact bonding pads formed on the semiconductor die are then connected to contact bonding pads within the package. Electrical connections can be created using solder bumps, column bumps, conductive paste, redistribution layers (RDLs), or wire bonding. Encapsulation material or other molding materials are deposited on top of the package to provide physical support and electrical isolation. The packaged assembly is then inserted into an electrical system, making the semiconductor device functional and accessible to other system components.

[0029] An electrical system can be a standalone system that uses semiconductor devices to perform one or more electrical functions. Alternatively, an electrical system can be a sub-component of a larger system. For example, an electrical system can be part of a mobile phone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication device. Alternatively, an electrical system can be a graphics adapter, network adapter, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, application-specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electronic components. Miniaturization and weight reduction are necessary for products seeking market acceptance. The distance between semiconductor devices must be reduced to achieve higher density.

[0030] By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-manufactured components into electronic devices and systems. Because these semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and streamlined production processes. The resulting devices are less prone to failure and less expensive to manufacture, thereby reducing costs for consumers.

[0031] Figure 1A A plan view of a semiconductor die 20 is shown, which has a substrate material 22 for structural support, such as, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. A plurality of semiconductor dies or components 24, separated by non-functional inter-die wafer regions or saw tracks 26 as described above, are formed on the wafer 20. The saw tracks 26 provide dicing areas to individually dice the semiconductor die 20 into individual semiconductor dies 24. The semiconductor dies 24 include power devices or other back-side contact devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), MOSFET semiconductor dies, insulated-gate bipolar transistors (IGBTs), and power diodes, collectively referred to herein as power devices (PDs).

[0032] Figure 1B Showing previously Figure 1AThe plan view shows a cross-sectional view of a portion of a semiconductor die 20. Each semiconductor die 24 has a back side or back surface 28 and an active surface 30 opposite to the back side. The active surface 30 contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die, and electrically interconnected according to the electrical design and function of the semiconductor die. For example, the circuitry may include one or more transistors, diodes, and other circuit components formed within the active surface 30 to implement analog or digital circuitry, such as DSPs, ASICs, memory, or other signal processing circuitry. The semiconductor die 24 may also contain integrated passive devices (IPDs) for performing radio frequency signal processing, such as inductors, capacitors, and resistors.

[0033] A conductive layer 32 is formed above the active surface 30 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 32 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 32 functions as contact bonding points or bonding pads electrically connected to circuitry on the active surface 30. The conductive layer 32 can be formed as contact bonding points arranged side-by-side at a first distance from the edge of the semiconductor die 24, such as… Figure 1B As shown. Alternatively, the conductive layer 32 may be formed as offset contact bonding points in multiple columns or arrays spanning the entire surface area of ​​the semiconductor die 24. Depending on the configuration and design of the semiconductor die, a complete array of contact bonding points may be formed across the entire surface of the semiconductor die 24 in a regular or irregular pattern.

[0034] The semiconductor die 24 may include a diode (PD), in which a portion of the conductive layer 32 is formed together with one or more gate bonding pads 33 and one or more source or emitter bonding pads 34 formed on the active surface of the semiconductor die 24. The semiconductor die 24 may also include a back side or back surface 28 opposite to the front side or active surface of the semiconductor die 24. The back side 28 of the semiconductor die 24 may include one or more drains 35 or sources.

[0035] Figure 1BAn optional insulating or passivation layer 36 is also shown, formed over the active surface 30 of the semiconductor die 24, which comprises portions of the native semiconductor dies 20 of a plurality of semiconductor dies 24. The insulating layer 36 may be conformally applied to the semiconductor die 24, and may have a bottom or first surface along the contour of the semiconductor die 24. The insulating layer 36 has a top or second flat surface 37 opposite the first surface. The insulating layer 36 may be an organic or inorganic layer and may contain one or more layers of low-curing-temperature dielectric photoresist, composite photoresist, composite laminate, solder resist, liquid molding compound, polymer layer, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), polyimide, or other materials having similar insulating and structural properties. The insulating layer 36 may be deposited using printing, spin coating, spraying, lamination, or other suitable processes. A portion of the insulating layer 36 can be removed by laser stripping, etching, or other suitable processes to expose the conductive layer 32 of the semiconductor die 24, including multiple gate bonding pads 33 and multiple source bonding pads 34, depending on the configuration and design of the semiconductor die. The insulating layer 36 can be patterned to form an opening 38 that extends fully through the insulating layer 36, and the insulating layer 36 can then be selectively cured.

[0036] Figure 1C The stud or conductive layer 40 can be formed using patterning and metal deposition processes (such as sputtering, electroplating, and electroless plating). The stud 40 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, including seed layers, barrier layers, and adhesive layers. The stud 40 can be electrically connected to contact bonding pads 32. More specifically, the stud or conductive layer 40 may include one or more of a gate stud 43 and a source stud 45. The thickness T of the conductive layer or stud 40 can be in the range of 20 to 100 micrometers (μm), 20 to 80 μm, 20 to 50 μm, greater than or equal to 20 micrometers (μm), and greater than or equal to 50 μm. Before the semiconductor die 20 undergoes dicing or singulation to separate individual semiconductor dies 24, pillars 43 and 45 can be formed on the native wafer, such as... Figure 1D As shown.

[0037] Gate pillar 43 may be formed above gate bond joint 33 to provide electrical interconnection and bias from the active surface of semiconductor die 24, and as mentioned above, in some cases, the gate pillar may be a Cu pillar or an electroplated Cu pillar. Some vertical power semiconductor devices or semiconductor dies 24 (such as power diodes) do not include gate bond joint 33, and therefore do not require the associated gate pillar 43.

[0038] Source pillar 45 may be formed above source bond pad 34 to provide electrical interconnection and bias from the active surface of semiconductor die 24, and as mentioned above, in some cases, the source pillar may be a Cu pillar or an electroplated Cu pillar. Source pillar 45 may include (or) a large-area interconnect to source bond pad 34 for low drain-source on resistance (Rdson / RDS(on)) or for low total resistance between drain 35 and source 34 in semiconductor die 24, such as for MOSFETs when turned on. Source pillar 45 may include a region that is thick, large, or both thick and large (relative to the total area or occupied area of ​​semiconductor die 24), and this region is connected to source bond pad 34 on die 24. Source pillar 45 may include a size or area greater than 50% of the die area or occupied area of ​​semiconductor die 24 (as seen in the xy plane). As noted above, the thickness T of the source pillar 45 is at least 20 micrometers (μm) and may be greater than or equal to 50 μm. In some cases, the source pillar 45 may have a size or area greater than 20 times the size, occupied area, or form factor of the gate pillar 43. In some cases, for example... Figure 3B As shown in the enlarged view, the insulating layer 36 may include multiple openings formed above a single source bonding pad 34 or multiple source bonding pads 34.

[0039] Figure 1C One embodiment is illustrated, in which a pillar 40 may first be formed by depositing and patterning a temporary insulating or passivation layer 42. The insulating layer 42 may be conformally applied to the semiconductor die 24, the insulating layer 36, or both, and the insulating layer 42 may have a first surface along the contour of the semiconductor die 24, the insulating layer 36, or both. The insulating layer 42 may have a second flat surface opposite the first surface. The insulating layer 42 may be an organic or inorganic layer and may contain one or more layers of low-curing-temperature dielectric photoresist, composite photoresist, composite laminate, solder resist, liquid molding compound, polymer, SiO2, Si3N4, SiON, Al2O3, polyimide, or other materials having similar insulating and structural properties. The insulating layer 42 may be deposited using printing, spin coating, spraying, lamination, or other suitable processes. The insulating layer 42 may be patterned to form openings that extend completely through the insulating layer 42 and through the insulating layer 36 (if present) to expose contact bonding pads 32, including gate bonding pads 33 and source bonding pads 34.

[0040] The insulating layer 36 can also be selectively cured, and this insulating layer can form part of the permanent structure of the final semiconductor package. Alternatively, the insulating layer 36 can be a temporary layer such as a photoresist layer, which is subsequently removed and does not form part of the final structure of the semiconductor die. The insulating layer 42 can be deposited over the insulating layer 36, or when the optional insulating layer 36 is omitted, the insulating layer 42 can be deposited over and in contact with the semiconductor die 24. A portion of the insulating layer 42 can be removed by laser, or when the insulating layer is a photoresist layer, a portion of the insulating layer can be exposed and removed by an etching and development process. Pillars 40 can then be formed in the removed portion of the insulating layer 42 and in the opening 38 (if present). The opening 38 and the opening in the insulating layer 42 can be formed at the same time or at different times. The entire pillar 40 can be formed at the same time, or portions of the conductive layer can be formed at different times. The insulating layer 42 can be removed after the pillar 40 is formed.

[0041] exist Figure 1C or Figure 1D In this process, the semiconductor wafer 20 may undergo optional polishing operations, using a polishing machine to planarize the surface of the back side 28 and reduce the thickness of the semiconductor wafer 20. Chemical etching or other suitable processes may also be used to remove and planarize the semiconductor wafer 20. The native wafer 20 may be thinned to a transitional thickness in the range of 400 to 600 μm or about 500 μm, where "about" means a percentage difference of less than or equal to 10%, 5%, 3%, or 1%.

[0042] Figure 1D A native semiconductor wafer 20 comprising a plurality of semiconductor dies 24 is shown. This native semiconductor wafer can then be diced or cut to produce discrete individual chips or semiconductor dies 24. The semiconductor wafer 20 can be diced into individual semiconductor dies 24 using a saw blade or laser cutting tool 52 via saw grooves 26.

[0043] Figure 2A A temporary carrier or substrate 56 is shown, containing a temporary or sacrificial substrate material for structural support, such as silicon, polymer, stainless steel, or other suitable low-cost rigid material. An optional interface layer or double-sided adhesive tape 58 may be formed over the carrier 56 as a temporary adhesive bonding film or etch-stop layer. In one embodiment, the carrier 56 may be an annular frame including an open central portion that supports the tape 58 at its periphery. Alternatively, the carrier 56 may be a flat plate without an open central region, supporting the tape 58 across its upper surface. Multiple reference alignment marks may be positioned over or attached to the substrate 56 or interface layer 58 for properly positioning the semiconductor die 24 on the carrier 56. Alternatively, a portion of the substrate 56 or interface layer 58 may be removed or marked to form a reference.

[0044] Figure 2A Also shown in FIG1E is a semiconductor die 24 mounted face-up to a carrier 56 and an interface layer 58, with the back side 28 oriented toward the substrate. The semiconductor die 24 has an active surface 30 and gate posts 43 and source posts 45 oriented away from the carrier. The semiconductor die 24 can be placed over the carrier 56 using pick-and-place operations or other suitable operations. The semiconductor die 24 can be positioned relative to a reference according to its nominal or predetermined position and spacing. The semiconductor die 24 is mounted to the carrier 56 such that it is separated by a space or gap 60 when mounted over the carrier 56. This space or gap provides an area for subsequently formed interconnect structures (such as fan-out interconnect structures) as part of the final semiconductor package, along with an area for subsequent single-cut fully formed FMSP-PD 140. The size of the gap 60 may include sufficient area for optionally mounting semiconductor devices or components (including through-mold interconnect structures 54) within the subsequently formed semiconductor package.

[0045] Figure 2A It is also shown that, prior to the package 63 being configured to surround the semiconductor die 24 and the via interconnect structure 54, the via interconnect structure 54, providing a vertical through-package electrical interconnect from the back side 28 to the active surface 30, can be formed surrounding the semiconductor die 24 and within the periphery of the semiconductor die. The molding or placement of the package 62 will... Figure 2B This will be discussed in more detail. However, in some cases, the via interconnect structure 54 can be placed before the package 62 is positioned above the carrier 56 and the semiconductor die 24 as a pre-formed vertical interconnect assembly on the temporary carrier 56. For example... Figure 2A As shown on the left, the via interconnect structure 54 can be placed on a temporary carrier 56, adjacent to or in the periphery of each semiconductor die 24. In some cases, the via interconnect structures 54 can be coupled together by a connecting portion or frame that helps maintain the relative position and spacing between the via interconnect structures 54, which is then removed, such as in a polishing process.

[0046] Figure 2B The exhibit displays encapsulations 62 deposited using paste printing, compression molding, transfer molding, liquid encapsulation molding, lamination, sheet molding, vacuum lamination, vacuum printing, spin coating, or other suitable applicators or processes. Specifically, Figure 2BA mold 64 with multiple sidewalls 66 is shown, which are assembled with a top portion or top plate 65, a carrier 56, and an interface layer 58 to enclose a semiconductor die 24 within the mold for subsequent packaging. The mold 64 may also include a bottom portion on which the carrier 56 is placed, and the sidewalls 66 are accessible to the bottom portion. In one embodiment, the carrier 56 and the interface layer 58 may be used as a bottom mold portion for subsequent packaging processes. Alternatively, the semiconductor die 24, the carrier 56, and the interface layer 58 may be disposed within a mold comprising multiple portions (such as a top portion and a bottom portion). The mold 64 is assembled by moving the mold 64 around the semiconductor die 24, or alternatively by moving the semiconductor die into the mold.

[0047] Figure 2B The mold 64 is also shown to enclose the semiconductor die 24 within a cavity or open space 70. The cavity 70 extends within the mold 64 to the semiconductor die 24 and the interface layer 58. The volume of the package 62 is positioned above the semiconductor die 24 and the carrier 56. The inlet 68 may be an outlet port that does not provide an escape path for the package 62. The package 62 may be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with a suitable filler. The volume of the package 62 is measured by subtracting the area occupied by the semiconductor die 24 and any additional semiconductor devices that may be present, based on the space requirements of the cavity 70. The package 62 is positioned above and around the semiconductor die 24, including the side surfaces of the semiconductor die 24 and pillars 40, including gate pillars 43 and source pillars 45. Encapsulation or molding can be performed in a single step using a single package 62. Therefore, the package 62 can contact the sidewall of the post 40, so that a single package 62 can directly contact the semiconductor die 24 and the post 40 and extend along the side of the semiconductor die 24 and the post 40 to be disposed above the side surfaces and above the active surface 30 of the semiconductor die 24.

[0048] The top portion 65 of the mold 64 can be moved along the sidewall 66 toward the package 62 and the semiconductor die 24 until the top portion contacts the package, so that the package 62 is evenly dispersed and uniformly distributed within the cavity 70 surrounding the semiconductor die 24. The viscosity and elevated temperature of the package 62 can be selected for uniform coverage; for example, lower viscosity and elevated temperature can improve the flow of the package for molding, paste printing, and spin coating. The temperature of the package 62 can also be controlled within the cavity 70 to promote curing of the package. The semiconductor die 24 is embedded together in the package 62, which is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

[0049] When vacuum compression molding is used, a sacrificial release film may be disposed between the top portion 65 and sidewalls 66 of the cavity 70 and the encapsulated material 62 within the cavity to prevent the encapsulated material from sticking to or attaching to the top portion and sidewalls of the cavity. When other types of molding, such as transfer molding, are used, the sacrificial release film may be omitted, and the encapsulated material 62 may contain a mold release agent, or the inner surface of the cavity 70 may be treated with a mold release agent to prevent the encapsulated material from attaching to the inner surface of the mold.

[0050] exist Figure 2C In this process, the semiconductor die 24 and package 62 are removed from the mold 64 to serve as a panel or embedded die panel 72. Panel 72 may optionally undergo a curing process to cure the package 62. The carrier 56 and interface layer 58 may be removed by chemical etching, mechanical peeling, CMP, mechanical polishing, thermal baking, UV light, laser scanning, wet stripping, or other suitable processes to expose the back surface 76 of the package 62, which is opposite to the front surface 78 of the package. In one embodiment, the package 62 is partially or completely cured before removing the carrier 56, interface layer 58, or both. Alternatively, the package 62 may be partially or completely cured after removing the carrier 56, interface layer 58, or both.

[0051] The package 62 may be formed or disposed over the entire semiconductor die 24 except for the back surface 28. Therefore, the back surface 76 of the panel 72 may be substantially coplanar with the back surface 28 of the semiconductor die 24. Both the back surface 76 and the back surface 28 can be exposed by removing the carrier 56 and the interface layer 58. After removing the carrier 56 and the interface layer 58, Figure 2C The package 62 is configured to surround the semiconductor die 24 within an embedded die panel 72. The panel 72 may include any shape and size of footprint or shape factor that allows and facilitates subsequent processing required to form the semiconductor package, as described in more detail below. As a non-limiting example, the panel 72 may include a shape factor similar to that of a 300 mm semiconductor die and may include a circular footprint with a diameter of 300 mm. The panel 72 may also be any other desired size and may include shapes or forms such as rectangular or square. In one embodiment, the panel 72 may be a reconstituted wafer or reconstituted panel known in the art.

[0052] In some cases, the via interconnect structure 54 is positioned adjacent to the semiconductor die 24 before the molding process or before the package 62 is set or formed to surround the semiconductor die 24; in other cases, the via interconnect structure is formed after the molding process or after the package 62 is set or formed to surround the semiconductor die 24. For example, the via interconnect structure 54 can also be formed by forming vias 53 through the package 62, such as after the panel 72 is removed from the carrier 56. Figure 2C As shown on the right. In other cases, vias 53 may be formed before the panel 72 is removed from the carrier 56. In some cases, vias 53 may be blind vias, which are formed by laser etching of the package 62 from the back side 76 of the panel to expose a portion of the stacked interconnect layer 106, including, for example... Figure 2D RDL 110 is shown. Electroplating processes can also be used to fill via 53 with copper or another suitable conductive material. Electroplating processes may include Cu plating or electroless plating, and other suitable processes may also be used. Once formed, the via interconnect structure 54 provides electrical interconnection between the source bond 34, the gate bond 33, and the back side of the package by extending fully through the package 62.

[0053] Figure 2C The panel 72 is also shown to be able to undergo a polishing operation performed by a polisher 80 to reduce the thickness of the panel 72, to remove surface 78 and expose a portion of the pillars 40 (such as the surfaces of gate pillars 43 and source pillars 45), to expose via interconnect structures 54 where present, and to expose a new front surface 82 of the package 62 or the panel 72, which is substantially coplanar with the surfaces of the pillars 40 (such as the surfaces of gate pillars 43 and source pillars 45). Chemical etching may also be used to remove and planarize a portion of the package 62 in the panel 72. This polishing or removal process may occur before or after the removal of the carrier 56. The pillars 40 coupled to the contact bonding pads 32, and more specifically the gate pillars 43 coupled to the gate bonding pads 33 and the source pillars 45 coupled to the source bonding pads 34, may be exposed at surface 82 of the panel 72 relative to the package 62 to provide electrical connections between the semiconductor die 24 and points outside the subsequently formed semiconductor package. Because the thickness of the package 62 is reduced to expose the pillar 40, the thickness of the package 62 above the active surface 30 of the semiconductor die 24 can also be equal to or substantially equal to the thickness or height of the pillar 40.

[0054] After the reconstituted panel 72 is removed from the temporary carrier 56, a temporary polymer layer may optionally be applied to the back side of the reconstituted panel 72. The top surface or portion of the reconstituted wafer may be subjected to the polishing process described above to expose the ends of the pillars 43, 45 on each die 24 and the ends of the vertical interconnect assembly 54.

[0055] Figure 2D This demonstrates that a stacked interconnect structure 106 can be formed on top of panel 72 after molding and package 62 formation. This stacked interconnect structure 106 provides electrical connections between one or more of the gate bonding pad 33, source bonding pad 34, and drain 35 at the back side 28 of semiconductor die 24 via via interconnect structure 54. The stacked interconnect structure 106 may include one or more insulating layers (containing polyimide or other suitable dielectric materials) and one or more conductive redistribution layers formed on the top side of semiconductor die 24 and package 62, above the gate pillar 43 and source pillar 45. Optionally, a final insulating layer (e.g., insulating layer 112) disposed on the top side of the package may comprise an epoxy resin material or solder shield having a thickness greater than 20 μm.

[0056] Figure 2D A non-limiting example of a stacked interconnect structure 106 is shown, wherein an insulating layer 108 is conformally applied to the top surface 44 of the package 62 and the pillar 40, and the insulating layer 108 may have a first surface along the contour of the top surface 44 of the package 62 and the pillar 40. The insulating layer 108 may have a second flat surface opposite the first surface. The insulating layer 108 may contain one or more layers of low-curing-temperature dielectric photoresist, composite photoresist, polymer, liquid crystal polymer (LCP), composite laminate, filler-containing insulating paste, solder shielding photoresist, liquid molding compound, granular molding compound, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. The insulating layer 108 may be deposited using printing, spin coating, spraying, lamination, or other suitable processes. The insulating layer 108 can then be patterned and cured using UV exposure followed by development, or other suitable processes. A portion of the insulating layer 108 can be removed by laser stripping, etching, or other suitable processes to expose portions of the top surfaces 44 of the pillars 40, 43, 45 and the interconnects 54, depending on the configuration and design of the semiconductor die 24 and the final semiconductor package.

[0057] The conductive layer 110 may be patterned and deposited over and in contact with the pillars 40, the package 62, and the insulating layer 108. The conductive layer or RDL 110 may electrically connect at least the source bonding pads 34 and gate bonding pads 33 on the semiconductor die 24 to one or more vertical interconnects 54. The conductive layer 110 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, and may include one or more seed layers, adhesive layers, or barrier layers. The conductive layer 110 may be deposited using PVD, CVD, electrolytic plating, electroless plating, or other suitable processes. The openings in the insulating layer 108 may extend completely through the pillars 40, 43, 45, and the insulating layer above the interconnects 54. The conductive layer 110 is operable as an RDL comprising a plurality of RDL traces that facilitate the extension of electrical connections from the active surface 30 of the semiconductor die 24 to the back side 28 of the semiconductor die 24 and to points extending outside the semiconductor die 24. In some cases, a portion of the conductive layer 110 within an opening formed in the insulating layer 108 may form a vertical interconnect structure or via providing electrical interconnects through the insulating layer 108. Although Figure 2D A non-limiting example of the stacked interconnect structure 106 illustrated includes a single conductive layer or RDL 110, but additional RDLs may also be formed within the stacked interconnect structure 106 to provide additional flexibility for routing signals between points on and outside the semiconductor die 24.

[0058] Figure 2D The insulating or passivation layer 112 is also shown to be co-applied to the insulating layer 108 and the conductive layer 110 along the contours of the insulating layer 108 and the conductive layer 110. The insulating layer 112 may contain one or more layers of polyimide, epoxy solder shielding, low-curing-temperature dielectric photoresist, composite photoresist, LCP, composite laminate, filler-containing insulating adhesive, solder resist, liquid molding compound, granular molding compound, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials with similar insulating and structural properties. The insulating layer 112 may be deposited using printing, spin coating, spraying, lamination, or other suitable processes. The insulating layer 112 may then be patterned and cured using UV exposure followed by development, or other suitable processes. The insulating layer 112 can be formed without any openings for connections at the top of the FMSP-PD140 or for connections above the active surface 30 of the semiconductor die 24, with such connections from the inside of the FMSP-PD 140 to the outside of the package occurring at the bottom of the package relative to the insulating layer 112.

[0059] Figure 2EThis demonstrates additional layers, structures, and processes associated with the bottom side or above the back surface 76 of the embedded die panel 72 relative to the stacked interconnect structure 106. The bottom surface 76 of the reconstructed panel 72, including each of the uncut semiconductor dies 28, may be ground and polished to thin the semiconductor dies 24 to their final thickness and expose the drain 35 at the back side 28 of the semiconductor dies 24 together with the second surface of the vertical interconnect assembly 54.

[0060] The barrier layer 120 may extend beyond or beyond the edge of the semiconductor die 24 and occupy an area above the drain 35 formed on the back side of the semiconductor die 24, and even over a portion of the molding compound 62 surrounding the periphery of the semiconductor die 24. The barrier layer 120 may comprise one or more layers of titanium (Ti), TiW alloy, or other suitable materials, which(e.g.) may be formed or deposited using sputtering or other suitable processes.

[0061] Optionally, a passivation layer may be formed between the barrier layer 120, the back side 28 of the semiconductor die 24, and the molding compound 62. The passivation layer may be a photosensitive imaging polyimide or other suitable material, or any other suitable passivation or insulating layer. The passivation layer may cover the edge or periphery of the occupied area of ​​the semiconductor die 24, and openings in the passivation layer may allow the barrier layer 120 to contact at least 80% of the area of ​​the back side 28 or the drain 35 of the semiconductor die 24.

[0062] The pads 122 may be formed over the barrier layer 120 and over the back side of the semiconductor die 24, such that the pads 122 and the barrier layer 120 extend beyond or beyond the edge (or beyond the occupied area) of the semiconductor die 24, and over a portion of the package 62 surrounding the periphery of the semiconductor die 24. The pads 122 may be formed of copper or other suitable conductive materials, may comprise one or more layers, and may be formed by electroplating, applied and patterned, and may be formed by any other suitable process. The pads 122 may cover the entire back side or drain 35 of the semiconductor die 24, and may comprise (in all or at least one direction) an area or form factor larger than that of the semiconductor die 24.

[0063] Separate pad bonding points 122a and 122b can be electrically connected to at least the gate bonding point 33 and source bonding point 34 on the active surface 30 of the semiconductor die 24 via the package 62 formed in the periphery of the semiconductor die 24, and via the through-hole interconnect structure 54, RDL 110, and Cu pillars 43 and 45.

[0064] Figure 2FThe embedded die panel or reconstituted wafer 72 is shown to be diced or cut as part of the space or gap 60 of the saw path to produce discrete semiconductor packages or embedded die packages FMSP-PD 140. The reconstituted wafer 72 can be diced using a saw blade, laser cutting tool, or other suitable tool 130. In addition to other advantages described herein, the dicing of FMSP-PD 140 (whether by wafer sawing or other suitable processes) is simplified because no full metallization is applied to the back side of the semiconductor die 20 (or the reconstituted wafer 72) during the wafer fabrication process. Therefore, the wafer saws 52, 130 do not need to cut through the full metallization on the back side of the wafer 20, resulting in a cleaner cutting process. Die breakage and cutting edge wear during sawing are reduced because the cutting edge is not contaminated by metal from the back side of the wafer.

[0065] Figure 3A The display is by Figures 1A to 2F The process illustrated shows the individual semiconductor package or embedded die package FMSP-PD 140 manufactured using the same technology. Figure 3A The overall package size has also been improved, with the overall package height H of the FMSP-PD 140 reduced to less than 0.6 mm. The FMSP-PD 140 can also be formed as a land grid array (LGA) package. As shown in Figure 1, the FMSP-PD 140 may also include a through-hole interconnect structure 54 formed of conductive material, which provides an electrical interconnect between the source solder joint 34 and the gate solder joint 33 and the back side of the package to the solder joint 122 by extending fully through the package 62 and electrically connecting to the solder pad 122.

[0066] By forming the FMSP-PD 140 as described herein, after the native semiconductor die 20 is diced and the semiconductor die 24 is embedded in the package 62, a back metal or barrier layer 120 and pad bonding pads 122 can be applied to the back side of the semiconductor device or FMSP-PD 140 (such as a power transistor). Therefore, the back metallization layer, barrier layer 120, and pad bonding pads 122 can be applied in the back-end packaging process rather than in the front-end wafer fabrication process (such as before the dicing of the native semiconductor die 20). The subsequently formed back metallization layers 120, 122 can extend beyond the edge of the semiconductor die 24, and the pad bonding pads 122 are electroplated above the bottom of the semiconductor die 24, extending above the edge of the semiconductor die 24 and beyond the occupied area of ​​the semiconductor die 24.

[0067] Within the FMSP-PD 140, pillars or conductive layers 40, including gate pillars 43 (if present) and source pillars 45, may be electroplated over the gate bonding pads 33 and source bonding pads 34, respectively, and within corresponding openings 38 in the insulating layer 36 above the active surface 30 of the semiconductor die 24. The pillars or conductive layers 40, including the source pillars 45, can and will reduce the resistance connected to the source bonding pads 34, and promote better current distribution and improved heat dissipation within the FMSP-PD 140.

[0068] Compared to known vertical MOSFETs or IGBT dies, the current design of the FMSP-PD 140 allows the back-side metallization, barrier layer 120, and pad bonding points 122 to be applied in the back-end process, during wafer fabrication, after the wafer has been thinned to its final thickness and the semiconductor die 24 has been further supported by the package 62. The back-side metallization, barrier layer 120, and pad bonding points 122 make final contact in the finished package, eliminating the need for additional wafer thinning after their formation. This avoids the need for additional wafer thinning after the formation of the back-side metallization, barrier layer 120, and pad bonding points 122 to prevent removal or damage to the back-side metallization. However, even if the FMSP-PD 140 is not thinned after the formation of the barrier layer 120 and the pad bonding points 122, the earlier thinning of the semiconductor die 24 does not need to be performed when it is not supported by the package 62, because the back metallization layer, the barrier layer 120, and the pad bonding points 122 are formed during the back-end wafer fabrication process.

[0069] The applicant's FMSP-PD 140 improves upon known vertical MOSFET or IGBT die packages, which also avoid thinning of the semiconductor die or dies after the formation of the interconnect metallization layer (such as after wafer bumping or assembly processes), and thus thinning the native semiconductor die or dies before the formation of the metallization layer, making the disposal of the thinned wafer or dies more difficult. Disposing of the thinned semiconductor die using known vertical MOSFET or IGBT die packages makes it difficult to process the thin wafer during wafer bumping or assembly processes. During wafer disposal, the thinned wafer is more susceptible to damage. The back metal can be damaged by chemicals (such as etchants) used in some wafer bumping and assembly processes. The back metal is also susceptible to mechanical damage or contamination during wafer bumping. This can subsequently lead to defects in soldering or sintering bonding processes, which are generally used to attach vertical semiconductor devices to package or module substrates. The above-mentioned issues can be avoided or minimized by adopting the methods and structures described herein for FMSP-PD 140.

[0070] The FMSP-PD 140 also offers improved thermal performance compared to known packages, such as known vertical MOSFET or IGBT die packages. This improved thermal performance stems from the direct connection or thermal contact between the back side 28 of the semiconductor die 24 and the pad bonding pad 122, which can be a thick Cu layer or other suitable thermally conductive material. The pad bonding pad 122 provides a robust thermal path due to its thermal conductivity and area larger than that of the semiconductor die 24. Furthermore, heat dissipation is further enhanced by eliminating solder or sintered bonding die attachment layers within the package 140, resulting in improved thermal performance for the FMSP-PD 140 compared to other known packages, such as known vertical MOSFET or IGBT die packages.

[0071] In various embodiments, the FMSP-PD 140 can be formed as a multi-chip module containing at least one power transistor and one power diode, and can be assembled using the methods described above. In other embodiments, the FMSP-PD 140 can be formed as an integrated power module such as a half-bridge switching circuit or a full three-phase switching circuit, which can be formed by integrating multiple power transistors and power diodes within a single FMSP-PD 140.

[0072] Figure 3B Exhibition along Figure 3A The enlarged cross-section of FMSP-PD 140 obtained from segment line 3B-3B shown is as follows. Figure 3B As shown, multiple openings in the insulating layer 36 may be formed over the source bonding pad 34 or any bonding pad 32, including over the gate bonding pad 33, to provide different interconnect interfaces between the pillar 40 and the bonding pad or conductive layer 32.

[0073] While this disclosure includes several embodiments of different forms, details of specific embodiments are presented in the accompanying drawings and the description written below. It is understood that this disclosure is considered as an example and principle of the disclosed methods and systems, and is not intended to limit the broad aspects of the disclosed concepts to the illustrated embodiments. Furthermore, those skilled in the art will understand that other structures, manufacturing apparatuses, and examples may be interchanged with or replace the provided structures, manufacturing apparatuses, and examples. Where references have been made to specific embodiments above, it will be apparent that numerous modifications can be made without departing from the spirit of the invention, and that these embodiments and implementations can also be applied to other technologies. Therefore, the subject matter of this disclosure is intended to encompass all such changes, modifications, and variations, all of which fall within the spirit and scope of this disclosure and the knowledge of those skilled in the art. Thus, it will be apparent that various modifications and variations can be made without departing from the broader spirit and scope of such inventions as set forth in the appended claims. Therefore, this specification and the accompanying drawings should be considered in an illustrative rather than restrictive sense.

Claims

1. A method for fabricating a semiconductor device without a carrier in the final semiconductor device, comprising: A semiconductor die is provided, the semiconductor die including a front surface including a gate bonding pad and a source bonding pad, the semiconductor die also including a back surface opposite to the front surface including a drain electrode; A gate pillar coupled to the gate bonding joint is formed above the gate bonding joint; A source post coupled to the source bonding joint is formed above the source bonding joint; An encapsulation is formed on the semiconductor die, and the encapsulation includes a first surface and a second surface opposite to the first surface, the first surface being above the front surface of the semiconductor die, wherein the encapsulation contacts the side surface of the gate pillar and the side surface of the source pillar. A through-hole interconnect structure is formed prior to the formation of the package, such that after the formation of the package, the through-hole interconnect structure extends between the first surface of the package and the second surface of the package; After forming the source pillar and the via interconnect structure, a redistribution layer RDL is formed, which is coupled to the gate pillar, the source pillar, and the via interconnect structure. and After the semiconductor die is diced from its native wafer and the package is formed on top of the semiconductor die, a pad bonding joint coupled to the drain is formed on the back surface of the semiconductor die.

2. The method of claim 1, further comprising forming the package surrounding the semiconductor die.

3. The method of claim 1, further comprising forming the pad bonding joint having an area larger than that of the semiconductor die.

4. The method of claim 1, further comprising forming the source pillar having an area greater than or equal to 50% of the area of ​​the semiconductor die.

5. The method of claim 1, further comprising: The drain is formed extending beyond the occupied area of ​​the semiconductor die, and a barrier layer contacts 80% or more of the back surface of the semiconductor die; and After the barrier layer is formed, the pad bonding pad is formed on top of the barrier layer.

6. The method of claim 1, further comprising forming the pad bonding joint extending beyond the occupied area of ​​the semiconductor die.

7. The method of claim 1, further comprising: Before slicing the semiconductor die from its native wafer, a gate pillar coupled to the gate bond joint is formed above the gate bond joint; and Before slicing the semiconductor die from its native wafer, a source pillar coupled to the source bond is formed above the source bond.

8. A method for manufacturing a semiconductor device, comprising: A semiconductor die is provided, the semiconductor die including a front surface including source bonding pads, the semiconductor die also including a back surface opposite the front surface including a drain. A source post coupled to the source bonding joint is formed above the source bonding joint; An encapsulation is formed on the semiconductor die, and the encapsulation includes a first surface and a second surface opposite to the first surface, the first surface being above the front surface of the semiconductor die, wherein the encapsulation contacts the side surface of the gate pillar and the side surface of the source pillar. A through-hole interconnect structure extending between the first surface and the second surface of the package; and After the semiconductor die is diced from its native wafer, a bonding pad is formed above the back surface of the semiconductor die to couple with the drain electrode. The bonding pad extends beyond the area occupied by the semiconductor die. The semiconductor device is cut out by penetrating a single package and offset from the via interconnect structure.

9. The method of claim 8, further comprising forming the pad bonding joint having an area larger than that of the semiconductor die.

10. The method of claim 8, further comprising forming the package surrounding the semiconductor die.

11. The method of claim 8, further comprising forming the source pillar having an area greater than or equal to 50% of the area of ​​the semiconductor die.

12. The method of claim 8, further comprising: The drain is formed extending beyond the occupied area of ​​the semiconductor die, and a barrier layer contacts 80% or more of the back surface of the semiconductor die; and After the barrier layer is formed, the pad bonding pad is formed on top of the barrier layer.

13. The method of claim 8, further comprising forming the pad bonding joint extending beyond the occupied area of ​​the semiconductor die.

14. The method of claim 8, further comprising: Before slicing the semiconductor die from its native wafer, a gate pillar coupled to the gate bond joint is formed above the gate bond joint; and Before slicing the semiconductor die from its native wafer, a source pillar coupled to the source bond is formed above the source bond.

15. A method of manufacturing a semiconductor device, comprising: A semiconductor die is provided, the semiconductor die including a front surface including source bonding pads, the semiconductor die also including a back surface opposite the front surface including a drain. An encapsulation is formed on the semiconductor die, and the encapsulation includes a first surface and a second surface opposite to the first surface, the first surface being above the front surface of the semiconductor die, wherein the encapsulation contacts the side surface of the gate pillar and the side surface of the source pillar. A through-hole interconnect structure is formed prior to the formation of the package, such that after the formation of the package, the through-hole interconnect structure extends between the first surface of the package and the second surface of the package; After forming the source pillar and the via interconnect structure, a redistribution layer RDL is formed, which is coupled to the gate pillar, the source pillar, and the via interconnect structure. and After the package is formed over the semiconductor die, a pad bonding pad coupled to the drain is formed over the back surface of the semiconductor die.

16. The method of claim 15, further comprising forming the pad bonding joint extending beyond the occupied area of ​​the semiconductor die.

17. The method of claim 15, further comprising: A source post coupled to the source solder joint is formed above the source solder joint; and The package is formed around the semiconductor die.

18. The method of claim 17, further comprising forming the source pillar having an area greater than or equal to 50% of the area of ​​the semiconductor die.

19. The method of claim 15, further comprising: The drain is formed extending beyond the occupied area of ​​the semiconductor die, and a barrier layer contacts 80% or more of the back surface of the semiconductor die; and After the barrier layer is formed, the pad bonding pad is formed on top of the barrier layer.

20. The method of claim 15, further comprising: Before slicing the semiconductor die from its native wafer, a gate pillar coupled to the gate bond joint is formed above the gate bond joint; and Before slicing the semiconductor die from its native wafer, a source pillar coupled to the source bond is formed above the source bond.

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