A dual-output GIP circuit

Abstract

The present invention relates to the technical field of GIP circuits, and in particular to a dual-output GIP circuit, comprising a pre-charging module, a first output module, a second output module, an upper and lower pull-up module, a first pull-down module and a second pull-down module, wherein the first output module is electrically connected to the pre-charging module, the second output module, the upper and lower pull-up module and the first pull-down module respectively, the upper and lower pull-up modules are electrically connected to the pre-charging module and the first pull-down module respectively, and the second pull-down module is electrically connected to the first pull-down module, the second output module and the upper and lower pull-up modules respectively. In this solution, a first-level GIP circuit is used to drive two rows of pixels through cooperation between the pre-charging module, the first output module, the second output module, the voltage stabilizing module, the first pull-down module, the second pull-down module and the upper and lower pull-up modules, thereby improving the screen-to-body ratio of the screen while ensuring that the charging rate of each row of pixels is the same.

Description

Technical Field

[0001] The present invention relates to the technical field of GIP circuits, and in particular to a dual-output GIP circuit. Background Art

[0002] Full-screen displays not only improve the appearance of products, making them look more technological, but also allow the front area of ​​the product to accommodate a larger screen, improving the user's visual experience. Therefore, full-screen technology has become a popular trend in display devices. The current definition of full-screen is a display device with an ultra-high screen-to-body ratio design, pursuing a screen-to-body ratio close to 100%. However, due to current technical limitations, the so-called full-screen products in the industry do not have a screen-to-body ratio of 100%, but are ultra-narrow bezel products with a high screen-to-body ratio. The high screen-to-body ratio design has become a trend, especially in mid-to-high-end models.

[0003] In order to increase the screen-to-body ratio, reducing the screen border has become an inevitable trend in the current technological development. In an active matrix liquid crystal display (active matrix liquid crystal display), each pixel has a TFT (thin film transistor), whose gate is connected to the horizontal scan line (also called scan signal line), the source is connected to the vertical data line (also called source line), and the source is connected to the pixel electrode. If a sufficient positive voltage is applied to a certain horizontal scan line, all the TFTs on the line will be turned on. At this time, the pixel electrode on the line will be connected to the vertical data line, and the video signal voltage on the data line will be written into the pixel, controlling the transmittance of different liquid crystals and thus achieving the effect of controlling color. When designing the scan drive of the panel, the traditional technology used is COF (chip on film, which is a grain soft film assembly technology that fixes the integrated circuit on the flexible circuit board) and COG (chip on Glass, that is, the chip is directly bound to the glass) process. The products obtained by this technology not only have large left and right borders, but also have high costs. Another new GIP (Gate In Panel) technology, the basic concept is to integrate the gate driver of the LCD Panel (that is, the liquid crystal display panel, the full name of LCD in English is Liquid Crystal Display) on a glass substrate to replace a technology that uses an external silicon chip. It not only saves costs and reduces borders, but also eliminates the process of binding in the gate direction, which is extremely beneficial to improving production capacity and increasing the integration of TFT-LCD panels.

[0004] GIP technology reduces the use of gate driver ICs, lowers power consumption and costs, and can reduce the border of the display panel to achieve a narrow border design. It is a technology worthy of attention; however, the current mainstream driving method of GIP circuit technology is a gate method in which a first-level GIP drives a row of pixels, and the screen-to-body ratio of the screen is not high. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a dual-output GIP circuit to improve the screen-to-body ratio of the screen while ensuring that the charging rate of each row of pixels is the same.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A dual-output GIP circuit comprises a pre-charge module, a first output module, a second output module, an upper and lower pull-up module, a first pull-down module and a second pull-down module, wherein the first output module is electrically connected to the pre-charge module, the second output module, the upper and lower pull-up module and the first pull-down module respectively, the upper and lower pull-up modules are electrically connected to the pre-charge module and the first pull-down module respectively, the second pull-down module is electrically connected to the first pull-down module, the second output module and the upper and lower pull-up modules respectively, and the output end of the first output module is connected to the scanning signal line G n The output end of the second output module is electrically connected to the scanning signal line G n+2 Electrically connected, the scanning signal line G n and scanning signal line G n+2 The parameter n in is a positive integer greater than or equal to 2.

[0008] The beneficial effects of the present invention are:

[0009] The pre-charging module is provided to play a pre-charging role; the first output module and the second output module are provided to play the role of outputting signals; the first pull-down module and the second pull-down module are provided to play a role of pulling down the output electrical signal; the first pull-down module is a pull-down module of the first output module, and the second pull-down module is a pull-down module of the second output module. This solution uses a first-level GIP circuit to drive two rows of pixels through the coordination among the pre-charging module, the first output module, the second output module, the voltage stabilizing module, the first pull-down module, the second pull-down module, and the upper and lower pull-down modules. While ensuring that the charging rate of each row of pixels is the same, not only the number of GIPs is reduced, but also the size of the left and right borders of the screen is reduced, thereby increasing the screen-to-body ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A module connection block diagram of a dual-output GIP circuit according to the present invention;

[0011] Figure 2A specific circuit schematic diagram of a dual-output GIP circuit according to the present invention;

[0012] Figure 3 is a timing diagram of a dual-output GIP circuit according to the present invention;

[0013] Figure 4 A circuit diagram of a dual-output GIP circuit during pre-charging according to the present invention;

[0014] Figure 5 A circuit diagram of a dual-output GIP circuit during output according to the present invention;

[0015] Figure 6 A circuit diagram of a dual-output GIP circuit during a pull-down period according to the present invention;

[0016] Figure 7 A circuit diagram of a pull-down maintenance period of a dual-output GIP circuit according to the present invention;

[0017] Figure 8 A simulation result diagram of a dual-output GIP circuit according to the present invention;

[0018] Fig. 9 A simulation result diagram of a dual-output GIP circuit according to the present invention;

[0019] Description of labels:

[0020] 1. Pre-charging module; 2. First output module; 3. Second output module; 4. Pull-up and pull-down module; 5. First pull-down module; 6. Second pull-down module. DETAILED DESCRIPTION

[0021] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0022] Please refer to Figure 1 , the technical solution provided by the present invention:

[0023] A dual-output GIP circuit comprises a pre-charge module, a first output module, a second output module, an upper and lower pull-up module, a first pull-down module and a second pull-down module, wherein the first output module is electrically connected to the pre-charge module, the second output module, the upper and lower pull-up module and the first pull-down module respectively, the upper and lower pull-up modules are electrically connected to the pre-charge module and the first pull-down module respectively, the second pull-down module is electrically connected to the first pull-down module, the second output module and the upper and lower pull-up modules respectively, and the output end of the first output module is connected to the scanning signal line G n The output end of the second output module is electrically connected to the scanning signal line G n+2 Electrically connected, the scanning signal line G nand scanning signal line G n+2 The parameter n in is a positive integer greater than or equal to 2.

[0024] From the above description, it can be seen that the beneficial effects of the present invention are:

[0025] The pre-charging module is provided to play a pre-charging role; the first output module and the second output module are provided to play the role of outputting signals; the first pull-down module and the second pull-down module are provided to play a role of pulling down the output electrical signal; the first pull-down module is a pull-down module of the first output module, and the second pull-down module is a pull-down module of the second output module. This solution uses a first-level GIP circuit to drive two rows of pixels through the coordination among the pre-charging module, the first output module, the second output module, the voltage stabilizing module, the first pull-down module, the second pull-down module, and the upper and lower pull-down modules. While ensuring that the charging rate of each row of pixels is the same, not only the number of GIPs is reduced, but also the size of the left and right borders of the screen is reduced, thereby increasing the screen-to-body ratio.

[0026] Further, the pull-up and pull-down modules include field effect transistors T2, field effect transistors T3, field effect transistors T8, field effect transistors T9, field effect transistors T10, field effect transistors T11, field effect transistors T12 and field effect transistors T13, the drain of the field effect transistor T2 is respectively electrically connected to the gate of the field effect transistor T3, the drain of the field effect transistor T8, the drain of the field effect transistor T10, the source of the field effect transistor T12, the source of the field effect transistor T13, the source of the field effect transistor T11, the first pull-down module and the second pull-down module, the source of the field effect transistor T2 is respectively electrically connected to the gate of the field effect transistor T3, the drain of the field effect transistor T8, the drain of the field effect transistor T10, the source of the field effect transistor T12, the source of the field effect transistor T13, the source of the field effect transistor T11, the first pull-down module and the second pull-down module, The source of the field effect transistor T3, the source of the field effect transistor T10, the first pull-down module and the second pull-down module are electrically connected, the gate of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T12 and the pre-charge module, the gate of the field effect transistor T8 is electrically connected to the source of the field effect transistor T8, the drain of the field effect transistor T12 is electrically connected to the gate of the field effect transistor T13, the drain of the field effect transistor T9, the drain of the field effect transistor T11, the first pull-down module and the second pull-down module, and the gate of the field effect transistor T9 is electrically connected to the source of the field effect transistor T9.

[0027] Further, the first output module includes a field effect transistor T4 and a capacitor C1, the gate of the field effect transistor T4 is electrically connected to one end of the capacitor C1, the pre-charge module and the second output module, and the source of the field effect transistor T4 is electrically connected to the other end of the capacitor C1, the first pull-down module and the scanning signal line G1. n Electrically connected, the drain of the field effect transistor T4 is connected to the clock signal CK1.

[0028] Further, the second output module includes a field effect transistor T14 and a capacitor C2, the gate of the field effect transistor T14 is electrically connected to one end of the capacitor C2, the pre-charge module and the first output module, and the source of the field effect transistor T14 is electrically connected to the other end of the capacitor C2, the second pull-down module and the scanning signal line G n+2 Electrically connected, the drain of the field effect transistor T14 is connected to the clock signal CK3.

[0029] Furthermore, the first pull-down module includes a field effect transistor T5 and a field effect transistor T15, the gate of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, the source of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, the drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T15 and the first output module respectively, the gate of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, and the source of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively.

[0030] Furthermore, the second pull-down module includes a field effect transistor T6 and a field effect transistor T16, the gate of the field effect transistor T6 is electrically connected to the first pull-down module and the upper and lower pull-down modules respectively, the drain of the field effect transistor T6 is electrically connected to the drain of the field effect transistor T16 and the second output module respectively, and the source of the field effect transistor T6 is electrically connected to the source of the field effect transistor T16, the upper and lower pull-down modules and the first pull-down module respectively.

[0031] Furthermore, the pre-charge module includes a field effect transistor T1 and a field effect transistor T7, and the gate of the field effect transistor T1 is connected to the scanning signal line G n-2 The drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the first output module, the second output module and the pull-up and pull-down modules respectively, and the gate of the field effect transistor T7 is electrically connected to the scanning signal line G n+6 Electrically connected, the scanning signal line G n-2 and scanning signal line G n+6 The parameter n in is a positive integer greater than or equal to 2.

[0032] Please refer to Figures 1 to 9 , Embodiment 1 of the present invention is:

[0033] Please refer to Figure 1A dual-output GIP circuit includes a pre-charge module 1, a first output module 2, a second output module 3, an upper and lower pull-up module 4, a first pull-down module 5 and a second pull-down module 6, wherein the first output module 2 is electrically connected to the pre-charge module 1, the second output module 3, the upper and lower pull-up module 4 and the first pull-down module 5, respectively, the upper and lower pull-up modules 4 are electrically connected to the pre-charge module 1 and the first pull-down module 5, respectively, the second pull-down module 6 is electrically connected to the first pull-down module 5, the second output module 3 and the upper and lower pull-up modules 4, and the output end of the first output module 2 is electrically connected to the scanning signal line G n The output end of the second output module 3 is electrically connected to the scanning signal line G n+2 Electrically connected, the scanning signal line G n and scanning signal line G n+2 The parameter n in is a positive integer greater than or equal to 2.

[0034] Please refer to Figure 2 The pull-up and pull-down modules 4 include field effect transistors T2, T3, T8, T9, T10, T11, T12, and T13. The drain of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T3, the drain of the field effect transistor T8, the drain of the field effect transistor T10, the source of the field effect transistor T12, the source of the field effect transistor T13, the source of the field effect transistor T11, the first pull-down module 5, and the second pull-down module 6. The source of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T3, the drain of the field effect transistor T8, the drain of the field effect transistor T10, the source of the field effect transistor T12, the source of the field effect transistor T13, the source of the field effect transistor T11, the first pull-down module 5, and the second pull-down module 6. The source of T3, the source of the field effect transistor T10, the first pull-down module 5 and the second pull-down module 6 are electrically connected, the gate of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T12 and the pre-charging module 1 respectively, the gate of the field effect transistor T8 is electrically connected to the source of the field effect transistor T8, the drain of the field effect transistor T12 is electrically connected to the gate of the field effect transistor T13, the drain of the field effect transistor T9, the drain of the field effect transistor T11, the first pull-down module 5 and the second pull-down module 6 respectively, and the gate of the field effect transistor T9 is electrically connected to the source of the field effect transistor T9.

[0035] Please refer to Figure 2 The first output module 2 includes a field effect transistor T4 and a capacitor C1, the gate of the field effect transistor T4 is electrically connected to one end of the capacitor C1, the pre-charge module 1 and the second output module 3, and the source of the field effect transistor T4 is electrically connected to the other end of the capacitor C1, the first pull-down module 5 and the scanning signal line G n Electrically connected, the drain of the field effect transistor T4 is connected to the clock signal CK1.

[0036] Please refer to Figure 2The second output module 3 includes a field effect transistor T14 and a capacitor C2, the gate of the field effect transistor T14 is electrically connected to one end of the capacitor C2, the pre-charge module 1 and the first output module 2, and the source of the field effect transistor T14 is electrically connected to the other end of the capacitor C2, the second pull-down module 6 and the scanning signal line G n+2 Electrically connected, the drain of the field effect transistor T14 is connected to the clock signal CK3.

[0037] Please refer to Figure 2 The first pull-down module 5 includes a field effect transistor T5 and a field effect transistor T15, the gate of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules 4 and the second pull-down module 6 respectively, the source of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules 4 and the second pull-down module 6 respectively, the drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T15 and the first output module 2 respectively, the gate of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules 4 and the second pull-down module 6 respectively, and the source of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules 4 and the second pull-down modules 6 respectively.

[0038] Please refer to Figure 2 The second pull-down module 6 includes a field effect transistor T6 and a field effect transistor T16, the gate of the field effect transistor T6 is electrically connected to the first pull-down module 5 and the upper and lower pull-down modules 4 respectively, the drain of the field effect transistor T6 is electrically connected to the drain of the field effect transistor T16 and the second output module 3 respectively, and the source of the field effect transistor T6 is electrically connected to the source of the field effect transistor T16, the upper and lower pull-down modules 4 and the first pull-down module 5 respectively.

[0039] Please refer to Figure 2 The pre-charge module 1 includes a field effect transistor T1 and a field effect transistor T7. The gate of the field effect transistor T1 is connected to the scanning signal line G n-2 The drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the first output module 2, the second output module 3 and the pull-up and pull-down modules 4 respectively, and the gate of the field effect transistor T7 is electrically connected to the scanning signal line G n+6 Electrically connected, the scanning signal line G n-2 and scanning signal line G n+6 The parameter n in is a positive integer greater than or equal to 2.

[0040] The working principle of the dual-output GIP circuit described above is:

[0041] Please refer to Figure 3 In this timing diagram, it is divided into four time periods, namely the pre-charge period, the output period, the pull-down period and the pull-down maintenance period. The working state of the TFT (Thin Film Transistor) corresponding to each stage is different, as follows:

[0042] Please refer to Figure 4 , is a schematic diagram of the pre-charge period, which corresponds to Figure 3 At time t1, the scanning signal line G n-2 , the potential signal line FW and the potential signal line V1 are all at high potential, and the corresponding field effect transistors T1, T2, T4, T8, T11, T12 and T14 are all turned on; the scanning signal line G n+6 , potential signal line BW, clock signal CK1, clock signal CK3 and potential signal line V2 are all at low potential, and the corresponding field effect transistors T3, field effect transistor T5, field effect transistor T6, field effect transistor T7, field effect transistor T9, field effect transistor 10, field effect transistor T13, field effect transistor T15 and field effect transistor 16 are all turned off; in this stage, since field effect transistor T1 is turned on, potential signal line FW is at high potential, capacitor C1 and capacitor C2 are charged, and the potential of Q1 node, Q2 node and Q3 node rises to H. At this time, field effect transistors T4 and field effect transistor T14 are both turned on. Since clock signals CK1 and clock signals CK3 are both at low potential, the scanning signal line G n With the scanning signal line G n+2 The outputs of are all low potential, the P1 node is pulled to a low potential by VGL due to the opening of the field effect transistor T2, and the P2 node is pulled to a low potential by VGL due to the opening of the field effect transistors T11 and T12.

[0043] Please refer to Figure 5 , is a schematic diagram of the output period, which corresponds to Figure 3 At time t2, the clock signal CK1, the clock signal CK3, the potential signal line FW, the potential signal line V1 and the Q1 node, the Q2 node and the Q3 node are all at high potential, and the corresponding field effect transistors T2, T4, T8, T11, T12 and T14 are all turned on; the scanning signal line G n-2 , scanning signal line G n+6 , the potential signal line BW, the potential signal line V2, the P1 node and the P2 node are all at low potential, and the corresponding field effect transistors T1, T3, T5, T6, T7, T9, T10, T13, T15 and T16 are all turned off; at this stage, since the field effect transistors T4 and T8 are both turned on, the clock signals CK1 and CK3 are both at high potential, and the GIP signal is output at this time, that is, the scanning signal line G n With the scanning signal line G n+2 The output of is high potential, and due to the coupling effect of capacitors C1 and C2, the Q1 node is coupled to the potential of 2H, stabilizing the scanning signal line G n and scanning signal line Gn+2 The output of , at the same time, stabilizes the opening of field effect transistor T2 and field effect transistor T12, and continues to pull the P1 node and the P2 node from VGL to a low potential.

[0044] Please refer to Figure 6 , is a schematic diagram of the pull-down period, which corresponds to Figure 3 At time t3, the scanning signal line G n+6 , the potential signal line FW and the potential signal line V1 are all at high potential, and the corresponding field effect transistors T7, T8 and T11 are all turned on; the scanning signal line G n-2 , the potential signal line BW, the clock signal CK1, the clock signal CK3 and the potential signal line V2 are all at low potential, and the corresponding field effect transistors T1, T2, T3, T4, T5, T6, T9, T10, T12, T13, T14, T15 and T16 are all turned off; at this stage, since the field effect transistor T7 is turned on, the potential signal line BW is at low potential, and the Q1 node, Q2 node and Q3 node are pulled down to a low potential; since the potentials of the Q1 node, Q2 node and Q3 node are reduced, the field effect transistor T2 is turned off, and the potentials of the P1 node and the P2 node slowly increase.

[0045] Please refer to Figure 7 , is a schematic diagram of the pull-down maintenance period, which corresponds to Figure 3 At time t4, the potential signal line FW and the potential signal line V1 are both at high potential, and the corresponding field effect transistors T8 and T9 are turned on; the scanning signal line G n-2 , scanning signal line G n+6 The potential signal line BW is low, and the corresponding field effect tubes T1 and T7 are turned off. Since the Q1 node, Q2 node and Q3 node are low at this time, the field effect tubes T2, T4, T12 and T14 are all turned off, the P1 node is high, and the field effect tubes T3, T5 and T6 are all turned on. The opening of these TFTs stabilizes the Q1 node, Q2 node, Q3 node, and the scanning signal line G. n and scanning signal line G n+2 of low potential.

[0046] Please refer to Figure 8 and Fig. 9 This is the simulation result diagram of the dual-output GIP circuit designed in this scheme: In this simulation result diagram, we can see the output signal G of each level of GIP n and G n+2The result is normal, the potentials of the Q1 node, Q2 node, Q3 node, P1 node and P2 node are all normal, and the pixel charging rates of the upper and lower levels of the two Gout signals output by the same GIP are also the same (this patent uses a 6.8-inch a-Si HD product as an example for simulation, and the pixel charging rates of adjacent output signals are all 92%). And because the P1 node and the P2 node are charged by TFT, the high potential of the P1 node and the P2 node is effectively maintained, preventing the clock signal from affecting the coupling effect of the Q1 node, the Q2 node and the Q3 node through the off-state capacitance of the field effect transistor T4 and the field effect transistor T14.

[0047] Figure 8 The waveforms in the figure are from top to bottom the scanning signal line G n-2 , output waveform diagram of clock signal CK1 and clock signal CK3;

[0048] Fig. 9 The waveform diagram in the figure is, from top to bottom, the output waveform diagrams of the Q node (the output waveforms of the Q1 node, the Q2 node, and the Q3 node are the same, represented by the Q node in the figure), CL[1] (the gate output signal of the field effect transistor T4), CL[3] (the gate output signal of the field effect transistor T14), and the P node (the output waveforms of the P1 node and the P2 node are the same, represented by the P node in the figure).

[0049] In summary, a dual-output GIP circuit provided by the present invention plays a pre-charging role by setting a pre-charging module; plays an output signal role by setting a first output module and a second output module; plays a role of pulling down the output electrical signal by setting a first pull-down module and a second pull-down module; the first pull-down module is a pull-down module of the first output module, and the second pull-down module is a pull-down module of the second output module. This scheme drives two rows of pixels using a first-level GIP circuit through the coordination between the pre-charging module, the first output module, the second output module, the voltage stabilizing module, the first pull-down module, the second pull-down module, and the upper and lower pull-down modules. While ensuring that the charging rate of each row of pixels is the same, not only the number of GIPs is reduced, but also the size of the left and right borders of the screen is reduced, thereby increasing the screen-to-body ratio of the screen.

[0050] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dual-output GIP circuit, characterized in that: The present invention comprises a pre-charging module, a first output module, a second output module, an upper and lower pull-up module, a first pull-down module and a second pull-down module, wherein the first output module is electrically connected to the pre-charging module, the second output module, the upper and lower pull-up module and the first pull-down module respectively, the upper and lower pull-up modules are electrically connected to the pre-charging module and the first pull-down module respectively, the second pull-down module is electrically connected to the first pull-down module, the second output module and the upper and lower pull-up modules respectively, and the output end of the first output module is electrically connected to the scanning signal line G n The output end of the second output module is electrically connected to the scanning signal line G n+2 Electrically connected, the scanning signal line G n and scanning signal line G n+2 The parameter n in is a positive integer greater than or equal to 2; The pull-up and pull-down modules include field effect transistors T2, T3, T8, T9, T10, T11, T12 and T13. The drain of field effect transistor T2 is electrically connected to the gate of field effect transistor T3, the drain of field effect transistor T8, the drain of field effect transistor T10, the source of field effect transistor T12, the source of field effect transistor T13, the source of field effect transistor T11, the first pull-down module and the second pull-down module. The source of field effect transistor T2 is electrically connected to the gate of field effect transistor T3, the drain of field effect transistor T8, the drain of field effect transistor T10, the source of field effect transistor T12, the source of field effect transistor T13, the source of field effect transistor T11, the first pull-down module and the second pull-down module. The source of the transistor T3, the source of the field effect transistor T10, the first pull-down module and the second pull-down module are electrically connected, the gate of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T12 and the pre-charge module respectively, the gate of the field effect transistor T8 is electrically connected to the source of the field effect transistor T8, the drain of the field effect transistor T12 is electrically connected to the gate of the field effect transistor T13, the drain of the field effect transistor T9, the drain of the field effect transistor T11, the first pull-down module and the second pull-down module respectively, and the gate of the field effect transistor T9 is electrically connected to the source of the field effect transistor T9; The first output module includes a field effect transistor T4 and a capacitor C1. The gate of the field effect transistor T4 is electrically connected to one end of the capacitor C1, the pre-charge module and the second output module respectively. The source of the field effect transistor T4 is electrically connected to the other end of the capacitor C1, the first pull-down module and the scanning signal line G1 respectively. n Electrically connected, the drain of the field effect transistor T4 is connected to the clock signal CK1; The pre-charge module includes a field effect transistor T1 and a field effect transistor T7. The gate of the field effect transistor T1 is connected to the scanning signal line G n-2 The drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the first output module, the second output module and the pull-up and pull-down modules respectively, and the gate of the field effect transistor T7 is electrically connected to the scanning signal line G n+6 Electrically connected, the scanning signal line G n-2 and scanning signal line G n+6 The parameter n in is a positive integer greater than or equal to 2.

2. The dual-output GIP circuit according to claim 1, characterized in that: The second output module includes a field effect transistor T14 and a capacitor C2, the gate of the field effect transistor T14 is electrically connected to one end of the capacitor C2, the pre-charge module and the first output module, and the source of the field effect transistor T14 is electrically connected to the other end of the capacitor C2, the second pull-down module and the scanning signal line G n+2 Electrically connected, the drain of the field effect transistor T14 is connected to the clock signal CK3.

3. The dual-output GIP circuit according to claim 1, characterized in that: The first pull-down module includes a field effect transistor T5 and a field effect transistor T15, the gate of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, the source of the field effect transistor T5 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, the drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T15 and the first output module respectively, the gate of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively, and the source of the field effect transistor T15 is electrically connected to the upper and lower pull-down modules and the second pull-down module respectively.

4. The dual-output GIP circuit according to claim 1, characterized in that: The second pull-down module includes a field effect transistor T6 and a field effect transistor T16, the gate of the field effect transistor T6 is electrically connected to the first pull-down module and the upper and lower pull-down modules respectively, the drain of the field effect transistor T6 is electrically connected to the drain of the field effect transistor T16 and the second output module respectively, and the source of the field effect transistor T6 is electrically connected to the source of the field effect transistor T16, the upper and lower pull-down modules and the first pull-down module respectively.

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