Memory device

Abstract

A memory device is disclosed, the memory device comprising: a plurality of memory chips for writing and reading data in response to a control command and an address signal; and a control logic circuit for transmitting the control command and the address signal to the plurality of memory chips, and receiving a first command from a memory controller, the first command being used to perform a first operation different from a refresh operation on at least one memory chip among the plurality of memory chips. The control logic circuit, in response to the refresh command, sends the first command to at least one memory chip among the plurality of memory chips and performs the first operation during a predetermined refresh time interval without performing the refresh operation.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0083795 filed on Jul. 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a memory device and a memory system including the memory device. Background Art

[0003] The memory device includes a plurality of memory chips capable of writing and reading data, and is applied to various applications such as personal computers, mobile electronic devices, servers, databases, and the like.

[0004] The memory device has a special command mode predefined by the manufacturer inside the device or defined by the standard. In order to implement such a special command mode, it is necessary to apply a special command to the memory device. However, since the special command cannot be applied to the memory device in the runtime environment, there is a limitation that the initialization process must be re-executed by restarting the system. Summary of the invention

[0005] An aspect of the present disclosure provides a memory device capable of performing a first operation requested by a host without rebooting a system in a runtime environment.

[0006] According to one aspect of the present disclosure, a memory device includes: a plurality of memory chips configured to write and read data in response to a control command and an address signal; and a control logic circuit configured to transmit the control command and the address signal to the plurality of memory chips, and receive a first command from a memory controller, the first command being used to perform a first operation different from a refresh operation on at least one of the plurality of memory chips. The control logic circuit sends the first command to at least one of the plurality of memory chips in response to the refresh command, and performs the first operation without performing the refresh operation during a predetermined refresh time interval.

[0007] According to one aspect of the present disclosure, a memory device includes: a plurality of memory chips including a plurality of memory cells connected to a plurality of row lines and a plurality of column lines; and a control logic circuit configured to: send a first command for performing a first operation of inputting / outputting data for the plurality of memory cells in a first state, and perform a second operation of repairing at least one defective memory cell among the plurality of memory cells in a second state. The control logic circuit receives a second command for performing a second operation from a memory controller in the first state, and sends the second command to the plurality of memory chips in the second state.

[0008] According to one aspect of the present disclosure, a memory device includes: a plurality of memory chips; and a control logic circuit, including: a status register configured to save status information indicating whether a register clock driver (RCD) buffer is in a state for receiving a first command; a register clock driver (RCD) buffer configured to save a first command according to the status information of the status register; and a refresh controller configured to control a self-refresh operation for the plurality of memory chips. The control logic circuit performs a first operation of a first command on at least one memory chip of the plurality of memory chips during at least one interval in a plurality of refresh periods according to the self-refresh operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram simply showing a configuration of a memory system according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 and Figure 3 is a diagram illustrating a memory device according to an exemplary embodiment.

[0012] Figure 4 is a block diagram simply illustrating a memory chip according to an exemplary embodiment.

[0013] Figure 5 is a diagram illustrating a bank array included in a memory chip according to an exemplary embodiment.

[0014] Figure 6 , Figure 7 , FIG. 8A to FIG. 8B is a diagram illustrating a memory device according to an exemplary embodiment.

[0015] Fig. 9 , FIG. 10A to FIG. 10B is a diagram illustrating a method of a memory device for storing a special command according to an exemplary embodiment.

[0016] Fig.11 , FIG. 12A to FIG. 12B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0017] Fig.13 , FIG. 14A to FIG. 14B is a diagram illustrating a method of a memory device for storing a special command according to an exemplary embodiment.

[0018] Fig.15A and Fig. 15B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0019] Fig.16 and Fig.17 is a diagram illustrating a memory device for storing a special command according to an exemplary embodiment.

[0020] Fig.18A and Fig.18B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0021] Fig.19 is a block diagram simply illustrating an electronic device including a memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to denote the same components in the drawings, and detailed descriptions thereof will be omitted.

[0023] Figure 1 is a diagram illustrating a configuration of a memory system according to an exemplary embodiment of the present disclosure.

[0024] Reference Figure 1 , a memory system 1 according to an exemplary embodiment of the present disclosure may include a memory controller 2 and a memory device 3 .

[0025] The memory controller 2 controls the overall operation of the memory system 1 and the data (DAT) exchange between the host and the memory device 3. For example, the memory controller 2 can control the memory device 3 to perform data (DAT) write and / or read operations according to a request from the host. To this end, the memory controller 2 can control the operation of the memory device 3 by sending an operation command (CMD) and an address signal (ADDR).

[0026] The memory device 3 may save (ie, store) data received from the memory controller 2. The memory device 3 may include a low power double data rate 2 (LPDDR2) synchronous dynamic random access memory (SDRAM), a double data rate 3 (DDR3) SDRAM, or the like.

[0027] The memory controller 2 may perform a refresh operation in units of a predetermined number of memory cells. For example, the memory device 3 may perform a refresh operation for each memory cell. Alternatively, the memory device 3 may perform a refresh operation for every two memory cells, every four memory cells, or every eight memory cells.

[0028] In an exemplary embodiment, the memory device 3 may receive a refresh (REF) command from the memory controller 2 and perform a refresh operation. The memory controller 2 may send a REF command to the memory device 3 for each refresh operation. For example, when the memory device 3 performs a refresh operation for each memory cell, the memory controller 2 may send a refresh command (REF1 to REFn, n is a positive integer greater than 1) for each memory cell. In an exemplary embodiment, in response to the REF command from the memory controller 2, the memory device 3 may perform a refresh operation on a row of memory cells in response to the REF command, or perform refresh operations on two or more rows of memory cells at the same time.

[0029] In an exemplary embodiment, the memory device 3 may perform a self-refresh operation using an internal clock. In this case, a refresh controller included in the memory device 3 may create a self-refresh start command (SREF) and a self-refresh termination command (SREFX). The memory controller 2 may wait for a maximum time required for self-refresh termination, and send an operation command (CMD) and a special command to the memory device 3.

[0030] The refresh time interval (tRFC) required to complete each refresh operation may vary according to the type and amount of the memory device 3. For example, when the memory device 3 is an 8Gb LPDDR2 SDRAM, the refresh time interval (tRFC) may be 210ns, and when the memory device 3 is an 8Gb DDR SDRAM, the refresh time interval (tRFC) may be 350ns.

[0031] Meanwhile, in order to perform special operations, the memory device 3 may receive a special command from the memory controller 2 and execute the special command during at least one refresh time interval (tRFC). The special operation is an operation other than a basic operation (such as a data write operation and / or a data read operation), and may include a test operation using a test mode register set (TMRS), a soft post package repair (SPPR) defined by the Joint Electron Device Engineering Council (JEDEC) standard, and an operation to repair a defective memory cell, etc.

[0032] Generally, in order to perform a special operation, the memory controller 2 sends a special command to the memory device 3 during system initialization. In this case, there is a limitation that a system restart is required to perform the special operation under the runtime environment of the memory system 1. To solve this problem, the memory system 1 according to an exemplary embodiment may save the special command in the memory device 3 under the runtime environment and execute the saved special command during at least one refresh time interval (tRFC), thereby shortening the time period for performing the special operation.

[0033] Figure 2 and Figure 3 is a diagram illustrating a memory device according to an exemplary embodiment.

[0034] Reference Figure 2 , the memory device 4 according to the exemplary embodiment may include a plurality of memory chips 20 mounted on a substrate 10. Some of the plurality of memory chips 20 may be provided as memory chips having an error correction (ECC) function for data stored and / or output by the plurality of memory chips 20.

[0035] The memory device 4 may further include a control logic 30 that transmits a control command, an address signal, etc. to the plurality of memory chips 20 and an input / output pad 40 disposed at an end of the substrate 10 .

[0036] The control logic 30 may store special commands received from an external source in a runtime environment and execute the stored special commands during a specific refresh time interval (tRFC) to control special operations of the memory device 4. In an exemplary embodiment, the control logic 30 may include a register clock driver (RCD). In an exemplary embodiment, the control logic 30 may include an RCD buffer for storing special commands and a command scheduler for controlling the execution of special commands.

[0037] The input / output pad 40 may be connected to a data input / output (DQ) path of each memory chip 20 .

[0038] At the same time, Figure 2 , a memory device 4 including eight memory chips 20 is shown, but the memory device 4 is only an example, and therefore, the exemplary embodiments of the present disclosure are not limited thereto. For example, Figure 3 The memory device 4A of the exemplary embodiment shown in FIG. 4 may include 16 memory chips 20A. The input / output pad 40A may be connected to a data input / output (DQ) path of each memory chip 20A. Figure 2 The memory device 4 and Figure 3 When the memory device 4A shown in FIG. 4 has the same storage capacity, Figure 2 The storage capacity of each memory chip 20 shown in FIG. 2 may be Figure 3 The storage capacity of each memory chip 20A shown in FIG. Figure 2 The number of data input / output (DQ) paths of the memory chip 20 shown in FIG. 2 may also be Figure 3 The number of data input / output (DQ) paths of the memory chip 20A shown in FIG.

[0039] Figure 4is a block diagram simply illustrating a memory chip according to an exemplary embodiment.

[0040] Figure 4 may be a block diagram illustrating an internal structure of a memory chip included in a memory device according to an exemplary embodiment. Figure 4 The memory chip 100 shown in FIG. 1 may be a memory chip 100 included in Figure 2 The plurality of memory chips 20 in the memory device 4 shown in FIG. Figure 3 An example memory chip of the plurality of memory chips 20A in the memory device 4A shown in FIG. Figure 4 , the memory chip 100 may include a controller 110 and a memory bank array 130. In an exemplary embodiment, the controller 110 may include a control logic 111, a row driver 112, a column driver 113, etc. The memory bank array 130 may include a plurality of memory cells (MCs).

[0041] In an exemplary embodiment, the row driver 112 may be connected to the memory cell (MC) via a word line (WL), and the column driver 113 may be connected to the memory cell (MC) via a bit line (BL). In an exemplary embodiment, the row driver 112 may select a memory cell (MC) for recording or reading data, and the column driver 113 may include a read / write circuit for writing data into or reading data from the memory cell (MC). The operations of the row driver 112 and the column driver 113 may be controlled by the control logic 111.

[0042] Figure 5 is a diagram illustrating a bank array included in a memory chip according to an exemplary embodiment.

[0043] Reference Figure 5 , according to an exemplary embodiment Figure 4 The memory bank array 130 may include a plurality of memory cells (MC). The memory cells (MC) may be arranged at points where a plurality of word lines (WL) and a plurality of bit lines (BL) intersect each other. That is, each memory cell (MC) may be connected to a single word line (WL) and a single bit line (BL).

[0044] Each memory cell (MC) may include a switching element SW and a storage capacitor (C). In an exemplary embodiment, the switching element SW may include a transistor, and a gate terminal of the transistor may be connected to a word line (WL), and a drain terminal / source terminal of the transistor may be connected to a bit line (BL) and a storage capacitor (C), respectively.

[0045] The control logic included in the memory chip may charge a storage capacitor (C) included in each of the plurality of memory cells (MC) via a plurality of word lines (WL) and a plurality of bit lines (BL), or may release the charge charged in the storage capacitor (C) to write data thereto or erase data therefrom. In addition, the control logic may read data from each of the plurality of memory cells (MC) by reading a voltage of the storage capacitor (C), etc.

[0046] The memory controller 2 may perform a refresh operation to rewrite data to a plurality of memory cells (MC) so that the data is not lost due to the natural discharge of the charge already charged in the storage capacitor (C). The control logic may receive a refresh command (REF) from an external source or perform the refresh operation using an internal clock in the absence of an external command.

[0047] In an exemplary embodiment, the control logic may receive and store a special command from the outside in a runtime environment, and execute the stored special command during at least one refresh time interval (tRFC) to perform a special operation such as a test operation or a soft package post repair (SPPR) operation.

[0048] Figure 6 is a diagram illustrating a memory device according to an exemplary embodiment, Figure 7 is a diagram illustrating a configuration of control logic included in a memory device according to an exemplary embodiment.

[0049] Fig. 8A and Figure 8B is a diagram schematically illustrating a flow of execution of a special command in a memory device according to an exemplary embodiment.

[0050] Reference Figure 6 and Figure 7 Both, the memory controller 5 can access the memory device 7 through the interface 6. For example, the memory controller 5 can send an operation command (CMD) and an address signal (ADDR) to the memory device 7 through the interface 6. In addition, the memory controller 5 can exchange various types of data (DAT, for example, DAT1 to DAT8) with the memory device 7 through the interface 6.

[0051] The memory device 7 may include a plurality of memory chips 50 and a control logic 60. The control logic 60 may transmit an operation command (CMD) and an address signal (ADDR) received from the memory controller 5 to the plurality of memory chips 50 to control data writing and / or data reading operations. In addition, the control logic 60 may transmit a refresh command (REF, e.g., REF1 to REF8) received from the memory controller 5 to the plurality of memory chips 50 to control a refresh operation.

[0052] The control logic 60 may include a register clock driver (RCD). In an exemplary embodiment, the control logic 60 may include an RCD buffer 61 for storing a special command received from the memory controller 5 and a status register 63 having status information of the control logic 60.

[0053] The information of the special operation received from the memory controller 5 and the type of the special command may be saved in the RCD buffer 61. For example, when the special command is a test mode register set (TMRS) sequence, the command type information of the special command may be saved in the first storage section of the RCD buffer 61, and the test data used in the test operation may be saved in the second storage section of the RCD buffer 61. In addition, when the special command is a soft package post repair (SPPR) sequence, the command type information of the special command may be saved in the first storage section of the RCD buffer 61, and the address information of the memory chip performing the soft package post repair (SPPR) operation may be saved in the second storage section of the RCD buffer 61. At the same time, referring to Fig. 8A , the test mode register set (TMRS) sequence 800 may include security key information (KEY1, KEY2) 810 for verification of sequence validity, a test mode register set 830, and a sequence termination command (EXIT) 850, which may be transmitted to the memory device in this order. In addition, referring to Figure 8B , a soft post-packaging repair (SPPR) sequence 900 may include a sequence start command (MR4 A5=1) 910, protection key information (MR0 protection key) 920 for verification of sequence validity, an activation command (ACT) 930, a write command (WR or WRADQ=0) 940, a free patch command (PRE) 950, and a sequence termination command (MR4 A5=0) 960, which may be transmitted to the memory device in this order.

[0054] The size of the RCD buffer 61 may vary depending on the type of special command received from the memory controller 5. For example, when the special command is a test mode register set (TMRS) sequence, the size of the RCD buffer 61 may be 4 bytes. When the special command is a soft package post repair (SPPR) sequence, the size of the RCD buffer 61 may be 11 bytes. However, this storage format and size of the RCD buffer 61 are only examples and are therefore not limited thereto. For example, in addition to the special command type, the control logic 60 may store information about a special operation in the RCD buffer 61. In this case, the type of the special command may be determined based on the size of the RCD buffer 61.

[0055] The status register 63 may store a value indicating whether the control logic 60 may be in a state capable of receiving a special command. For example, when the control logic 60 is in a first state (e.g., the value of the status register 63 may be 1), the control logic 60 may receive a special command, and when the control logic 60 is in a second state (e.g., the value of the status register 63 may be 0), the control logic 60 may not be able to receive the special command. The memory controller 5 may determine whether to send a special command to the memory device 7 by verifying the value of the status register 63 via the interface 6. Meanwhile, in the case where a special command is stored in the RCD buffer 61, the control logic 60 may prevent the reception of other special commands by changing the value of the status register 63 to 0.

[0056] The interface 6 may be designed to be able to access a status register 63 and an RCD buffer 61 of the memory device, and in some examples, the interface 6 may include a system management bus (SMBus) or the like.

[0057] Fig. 9 , FIG. 10A to FIG. 10B is a diagram illustrating a method of a memory device for storing a special command according to an exemplary embodiment.

[0058] For ease of description, refer to Fig. 9 and Figure 6 When the system in which the memory device 7 according to the exemplary embodiment is built-in is restarted and starts operation S910, the memory device 7 may start operation. The system may be a computer, a server, a database, a mobile electronic device, etc. in which the memory device 7 is built-in, and by the system restart at S910, the operating system installed in the system may be run.

[0059] Once the system is restarted, the memory controller 5 may determine whether the value of the status register 63 is a first value indicating a first state in which the control logic 60 may receive a special command (S920). The memory controller 5 may determine whether the control logic 60 is in the first state by identifying the value of the status register 63 via a predetermined interface 6.

[0060] When the result of the verification in S920 indicates that the control logic 60 is in the first state, the memory controller 5 may send a special command to the memory device 7 ( S930 ).

[0061] When the result of the determination in S920 indicates that the control logic 60 is not in the first state, the memory controller 5 returns to S920 and continues to verify whether the control logic 60 is in the first state.

[0062] In S940, the memory device 7 may save the special command received from the memory controller 5 in the RCD buffer 61. In an exemplary embodiment, the memory device 7 may save the information of the special operation and the type of the special command in the RCD buffer. In an exemplary embodiment, the memory device 7 may dynamically change the size of the RCD buffer 61 according to the type of the special command. For example, when the received special command is a test mode register set (TMRS) sequence, the memory device 7 may set the size of the RCD buffer 61 to 4 bytes. When the received special command is a soft package post repair (SPPR) sequence, the memory device 7 may set the size of the RCD buffer 61 to 11 bytes.

[0063] Once the special command is saved in the RCD buffer 61, the control logic 60 may change the value of the state register 63 to a second value indicating a second state (S950), in which the control logic 60 may not receive the special command. When the control logic 60 is in the second state, the memory controller 5 may not send other special commands to the memory device 7.

[0064] The state changes of the RCD buffer 61 and the status register 63 before and after the memory device 7 receives and stores the special command are as follows: Fig. 10A and Fig. 10B as shown in . Fig. 10A An exemplary embodiment that may correspond to a special command is a test mode register set (TMRS) sequence, while Fig. 10B An exemplary embodiment that may correspond to a special command is a soft package post repair (SPPR) sequence.

[0065] Reference Fig. 10A , before the memory device 7 receives the special command, the RCD buffer 61 may be in an empty state with no stored data, and the status register 63 may have a first value indicating a first state in which the special command may be received. When the memory device 7 receives a test mode register set (TMRS) sequence as a special command, type information indicating the test mode register set (TMRS) sequence may be stored in a first storage portion (byte 0) of the RCD buffer 61, and test data is stored in a second storage portion (byte 1 to byte 3) of the RCD buffer 61. In addition, the status register 63 may have a second value indicating a second state in which other special commands may not be received.

[0066] Reference Fig. 10B, before the memory device 7 receives the special command, the RCD buffer 61 may be in an empty state with no saved data, and the status register 63 may have a first value indicating a first state in which the special command may be received. When the memory device 7 receives a soft package post repair (SPPR) sequence, type information indicating the soft package post repair (SPPR) sequence is saved in a first storage portion (byte 0) of the RCD buffer 61, and address information of a memory chip for performing a soft package post repair (SPPR) operation may be saved in a second storage portion (byte 1 to byte 10) of the RCD buffer 61. In addition, the status register 63 may have a second value indicating a second state in which other special commands may not be received.

[0067] Fig.11 , FIG. 12A to FIG. 12B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0068] For ease of description, refer to Fig.11 and Figure 6 In S1110, the memory device 7 may receive a first refresh command (REF1) from the memory controller 5. In response to the first refresh command REF1, the memory device 7 may determine whether the control logic 60 is in the second state while having a special command stored in the RCD buffer 61, and the special command cannot be received in the second state (S1120).

[0069] When the result of the verification in S1120 indicates that the status register 63 has a second value representing the second state of the control logic 60 and has a special command stored in the RCD buffer 61, the memory device 7 can transmit the special command stored in the RCD buffer 61 to the memory chip and execute the special command according to the first refresh command (REF1) during the refresh time interval (tRFC) (S1130).

[0070] Once the special command is executed, the memory device 7 may remove the special command that has been stored by clearing the RCD buffer 61 to change the value of the state register 63 to a first value indicating a first state of the control logic 60 ( S1140 ).

[0071] In S1150 , the memory device 7 may then receive the second refresh command ( REF2 ) and execute the second refresh command ( REF2 ) accordingly.

[0072] In an exemplary embodiment, the memory device 7 may skip a refresh operation corresponding to a specific refresh time interval (tRFC) during which a special command has been executed. Fig. 12A, the memory device 7 may execute the special command stored in the RCD buffer 61 during the refresh time interval (interval between t11 and t12, tRFC11) for the first memory cell. The memory device 7 may then sequentially skip the refresh operation for the first memory cell, and respectively perform refresh operations for the second to fourth memory cells during the refresh time interval (interval between t13 and t14, tRFC13) for the second memory cell, the refresh time interval (interval between t15 and t16, tRFC15) for the third memory cell, and the refresh time interval (interval between t17 and t18, tRFC17) for the fourth memory cell. Since the time required for the first memory cell until the next refresh operation of the first memory cell is performed on the first memory cell (i.e., the refresh cycle) is relatively short in consideration of the retention characteristics (e.g., data retention time) of the memory device 7, data is not lost even when the refresh operation for the first memory cell is skipped and the special command is executed.

[0073] In an exemplary embodiment, the memory device 7 may execute a special command during a predetermined refresh time interval (tRFC) to perform multiple refresh operations simultaneously. Fig. 12B , the memory device 7 can execute the special command stored in the RCD buffer 61 during the refresh time interval (interval between t23 and t24, tRFC23) for the second memory cell through command scheduling. That is, even when the first refresh command (REF1) is received, the memory device 7 can execute the special command when receiving the second refresh command (REF2) according to the predetermined command scheduling information. Therefore, the memory device 7 can sequentially perform the refresh operation for the first memory cell during the refresh time interval (interval between t21 and t22, tRFC21) for the first memory cell, skip the refresh operation for the second memory cell during the refresh time interval (interval between t23 and t24, tRFC23) for the second memory cell and perform the special operation thereon, and respectively perform the refresh operations for the third memory cell and the fourth memory cell during the refresh time interval (interval between t25 and t26, tRFC25) for the third memory cell and the refresh time interval (interval between t27 and t28, tRFC27) for the fourth memory cell. This prevents data loss that may result from repeatedly skipping refresh operations for the same memory cell.

[0074] Fig.13 , FIG. 14A to FIG. 14B is a diagram illustrating a method of a memory device for storing a special command according to an exemplary embodiment.

[0075] For ease of description, refer to Fig.13 and Figure 6 , the operation of the memory device 7 according to the exemplary embodiment may be started by rebooting the system in which the memory device 7 is built (S1310).

[0076] Once the system is started, the memory controller 5 may verify whether the control logic 60 has a first value indicating a first state (S1320) in which the control logic 60 may receive a special command. For example, the memory controller 5 may verify whether the control logic 60 is in the first state by measuring the value of the state register 63 via a predetermined interface 6.

[0077] The result of the verification in S1320 indicates that the status register 63 has the first value, and the memory controller 5 may send a special command to the memory device 7 ( S1330 ).

[0078] The result of the verification in S1320 indicates that the state register 63 does not have the first state, and the memory controller 5 returns to S1320 and continues to verify whether the control logic 60 is in the first state.

[0079] In S1340, the memory device 7 may save the special command received from the memory controller 5 in the RCD buffer 61. For example, the test mode register set (TMRS) sequence information or the soft package post repair (SPPR) sequence information may be saved in the RCD buffer 61. In this case, information about each type of special command and special operation may be saved in the RCD buffer. For example, when the special command is a test mode register set (TMRS) sequence, type information indicating the test mode register set (TMRS) sequence may be saved in a first storage unit of the RCD buffer 61, and test data may be saved in a second storage unit of the RCD buffer 61. Alternatively, when the special command is a soft package post repair (SPPR) sequence, type information indicating the soft package post repair (SPPR) sequence may be saved in a first storage unit of the RCD buffer 61, and address information of a memory chip for a soft package post repair (SPPR) operation may be saved in a second storage unit of the RCD buffer 61.

[0080] The size of the RCD buffer 61 may be preset considering the length of the total refresh time interval (tRFC_tot), system request, etc. For example, the size of the RCD buffer 61 may be preset based on the maximum number of special commands executable during the entire refresh time interval considering the retention characteristics of the memory device 7.

[0081] In S1350, the memory device 7 may verify whether the RCD buffer 61 is in a "full" (FULL) state, in which another special command cannot be saved.

[0082] The result of the verification in S1350 indicates that the control logic 60 is in the FULL state ("Yes"), in which state another special command cannot be saved, and the memory device 7 can change the value of the status register 63 to a second value representing a second state, in which state the control logic 60 cannot receive another special command (S1360).

[0083] The result of the verification in S1350 indicates that the control logic 60 is not in the FULL state ("No"). If it is not in the FULL state, the control logic 60 can save another special command, and the memory controller 5 can return to S1320 to execute other special commands requested by the host and continue to verify whether the value of the status register 63 is the first value.

[0084] The state changes of the RCD buffer 61 and the status register 63 before and after the memory device 7 stores the special command are as follows: Fig.14A and Fig. 14B as shown in .

[0085] Reference Fig.14A Before the memory device 7 receives the special command, the RCD buffer 61 is in an "EMPTY" state, in which no data is saved, and the state register 63 may have a first value indicating a first state, in which the state register 63 may receive the special command. When the memory device 7 subsequently receives a test mode register set (TMRS) sequence and a soft package post repair (SPPR) sequence, information of each type of received sequence and special operation may be sequentially saved in the RCD buffer 61.

[0086] The status register 63 may have different values ​​depending on whether the RCD buffer 61 is in the FULL state. Another special command may be saved until the RCD buffer 61 is verified to have the FULL state. For example, when the RCD buffer 61 cannot save another special command, the status register 63 may have a second value indicating a second state. On the contrary, when the RCD buffer 61 saves another special command (i.e., is not in the FULL state), the status register 63 may have a first value indicating a first state.

[0087] Meanwhile, for example, the memory device 7 in the exemplary embodiment may execute a plurality of special commands stored in the RCD buffer 61 using a “first in first out” (FIFO) method during at least one refresh time interval (tRFC).

[0088] Reference Fig. 14B, the RCD buffer 61 is in an EMPTY state, in which no data is saved, and the status register 63 may have a first value indicating a first state, in which the status register 63 may receive a special command. When the memory device 7 subsequently receives a test mode register set (TMRS) sequence and a soft package post repair (SPPR) sequence, information of each type of received sequence and special operation may be sequentially saved in the RCD buffer 61. In addition, the RCD buffer 61 may save priority information of special commands. For example, the priority information may be saved in a first storage portion (byte 0) of the RCD buffer 61, the command type information may be saved in a second storage portion (byte 1) of the RCD buffer 61, and the special operation information is saved in a third storage portion (byte 2 to byte N, N is a positive integer greater than 2).

[0089] The status register 63 may have different values ​​depending on whether the RCD buffer 61 is in the FULL state. Another special command may be saved until the RCD buffer 61 is verified to be in the FULL state. For example, when the RCD buffer 61 may not save another special command (i.e., the RCD buffer 61 may be in the FULL state), the status register 63 may have a second value indicating a second state. On the contrary, when the RCD buffer 61 may save another special command (i.e., the RCD buffer 61 may not be in the FULL state), the status register 63 may have a first value indicating a first state.

[0090] Meanwhile, the memory device 7 in the exemplary embodiment may execute a plurality of special commands stored in the RCD buffer 61 according to the priority of the plurality of special commands stored in the RCD buffer 61 during at least one refresh time interval (tRFC).

[0091] Fig.15A and Fig. 15B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0092] In an exemplary embodiment, the memory device 7 may execute a plurality of special commands in succession and skip a refresh operation corresponding to a specific refresh time interval (tRFC) during which the special commands have been executed. Fig.15A, the memory device 7 may execute the first special command stored in the RCD buffer 61 during a refresh time interval (interval between t31 and t32, tRFC31) for the first memory cell. The memory device 7 may also execute the second special command stored in the RCD buffer 61 during a refresh time interval (interval between t33 and t34, tRFC33) for the second memory cell. The first special command may be saved before the second special command, or may have a higher priority than the second special command. Then, the memory device 7 may sequentially skip the refresh operations for the first memory cell and the second memory cell, and perform refresh operations for the third memory cell and the fourth memory cell during a refresh time interval (interval between t35 and t36, tRFC35) for the third memory cell and a refresh time interval (interval between t37 and t38, tRFC37) for the fourth memory cell, respectively.

[0093] In an exemplary embodiment, the memory device 7 may execute multiple special commands discontinuously. Fig. 15B , the memory device 7 may execute the first special command stored in the RCD buffer 61 during the refresh time interval (interval between t41 and t42, tRFC41) for the first memory cell. The memory device 7 may also execute the second special command stored in the RCD buffer 61 during the refresh time interval (interval between t45 and t46, tRFC45) for the third memory cell. In addition, the memory device 7 may perform refresh operations for the second memory cell and the fourth memory cell during the refresh time interval (interval between t43 and t44, tRFC43) for the second memory cell and the refresh time interval (interval between t47 and t48, tRFC47) for the fourth memory cell, respectively. The first special command may be saved before the second special command, or may have a higher priority than the second special command. In this case, the refresh operations for the first memory cell and the third memory cell may be omitted.

[0094] Fig.16 is a diagram illustrating a memory device according to an exemplary embodiment, Fig.17 is a diagram illustrating a configuration of control logic included in a memory device according to an exemplary embodiment.

[0095] Reference Fig.16 and Fig.17 Both, the memory controller 8 can access the memory device 11 through the interface 9. For example, the memory controller 8 can send an operation command (CMD) and an address signal (ADDR) to the memory device 11 through the interface 9. In addition, the memory controller 8 can exchange various types of data (DAT) with the memory device 11 through the interface 9.

[0096] The memory device 11 may include a plurality of memory chips 70 and a control logic 80. The control logic 80 may include a register clock driver (RCD). In an exemplary embodiment, the control logic 80 may include an RCD buffer 81 and a status register 83, the RCD buffer 81 being used to save a special command received from the memory controller 8, and the status register 83 indicating the state of the control logic 80. The control logic 80 may also include a refresh controller 85 for controlling a self-refresh operation. The refresh controller 85 may generate a self-refresh start command (SREF) and a self-refresh termination command (SREFX), and transmit the self-refresh start command (SREF, for example, SREF1 to SREF8) and the self-refresh termination command (SREFX) to the plurality of memory chips 70 to control the self-refresh operation.

[0097] The interface 9 may be designed to access the status register 83 and the RCD buffer 81 of the control logic 80. In some examples, the interface 9 may include a system management bus (SMBus) or the like.

[0098] The method for storing special commands in the RCD buffer 81 can be similar to that previously described with reference to FIG. 8A to FIG. 10B The method described is the same, therefore, its detailed description will be omitted. Fig.18A and Fig.18B A method of a memory device for executing a special command in an exemplary embodiment is described.

[0099] Fig.18A and Fig.18B is a diagram illustrating a method of a memory device for executing a special command according to an exemplary embodiment.

[0100] For ease of description, refer to Fig.18A and Fig.17, the memory device 11 may execute one or more special commands during the self-refresh time interval between the self-refresh start command (SREF) and the self-refresh end command (SREFX). For example, the memory device 11 may execute a first special command stored in the RCD buffer 81 during a refresh time interval (interval between t51 and t52, tRFC51) for a first memory cell. When the first special command is executed on the first memory cell, the refresh operation on the first memory cell in the interval tRFC51 is skipped. The memory device 11 may also execute a second special command stored in the RCD buffer 81 during a refresh time interval (interval between t53 and t54, tRFC53) for a second memory cell. When the second special command is executed on the second memory cell, the refresh operation on the second memory cell in the interval tRFC53 is skipped. The memory device 11 may sequentially skip refresh operations for the first memory cell and the second memory cell, and perform refresh operations for the third memory cell and the fourth memory cell during a refresh time interval for the third memory cell (an interval between t55 and t56, tRFC55) and a refresh time interval for the fourth memory cell (an interval between t57 and t58, tRFC57), respectively.

[0101] Reference Fig.18B , the memory device 11 can execute the special command stored in the RCD buffer 81 during the refresh time interval (interval between t63 and t64, tRFC63) for the second memory cell through command scheduling. Therefore, the memory device 11 can sequentially perform a refresh operation for the first memory cell during the refresh time interval (interval between t61 and t62, tRFC61) for the first memory cell, perform a special operation for the second memory cell during the refresh time interval (interval between t63 and t64, tRFC63) for the second memory cell, and perform refresh operations for the third memory cell and the fourth memory cell during the refresh time interval (interval between t65 and t66, tRFC65) for the third memory cell and the refresh time interval (interval between t67 and t68, tRFC67) for the fourth memory cell, respectively.

[0102] Fig.19 is a block diagram illustrating an electronic device including a memory device according to an exemplary embodiment.

[0103] Fig.191000 according to an exemplary embodiment may include a display 1010, a communication unit 1020, a memory 1030, a processor 1050, an input / output unit 1040, etc. The elements such as the display 1010, the communication unit 1020, the memory 1030, the processor 1050, the input / output unit 1040, etc. may communicate with each other through a bus 1060. In addition to those elements mentioned above, the electronic device 1000 may further include a power supply device, a port, etc.

[0104] The processor 1050 may perform specific arithmetic operations or commands, tasks, etc. The processor 1050 may be a central processing unit (CPU), a microprocessor unit (MCU), an application processor, etc., and may communicate with other constituent elements such as the display 1010, the communication unit 1020, the memory 1030, the input / output unit 1040, etc.

[0105] Fig.19 The memory 1030 included in the electronic device 1000 shown in FIG. 1 may include a memory device according to various exemplary embodiments of the present disclosure. As an example, the memory 1030 may refer to Figures 1 to 18B The memory 1030 may save, print, or delete data in response to an operation command transmitted from the processor 1040. In addition, the memory 1030 may receive a special command requested by the host while the electronic device 1000 is being operated by the runtime and execute the special command during a predetermined refresh time interval (tRFC).

[0106] A memory device according to an exemplary embodiment of the present disclosure may execute a special command received from a memory controller in a runtime environment, thereby minimizing the time required to perform a special operation and improving efficiency.

[0107] Furthermore, the memory device according to example embodiments may minimize data loss by scheduling a refresh time interval during which a special command is executed.

[0108] The memory device according to the exemplary embodiments may be widely used in all fields where it is necessary to perform a special operation.

[0109] Various advantages and advantageous effects of the present disclosure are not limited to the above description and can be more easily understood through detailed description of exemplary embodiments.

[0110] Various and advantageous advantages and effects of the present disclosure may not be limited to the above description and may be more easily understood in the course of describing specific embodiments of the present disclosure.

[0111] While the present disclosure has been shown and described with reference to example embodiments thereof, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A memory device, include: a plurality of memory chips configured to: write and read data in response to control commands and address signals; as well as a control logic circuit configured to: transmit a control command and an address signal to the plurality of memory chips, and receive a first command from a memory controller, the first command being used to perform a first operation different from a refresh operation on at least one memory chip among the plurality of memory chips, The control logic circuit is further configured to: in response to a refresh command, send a first command to at least one memory chip among the plurality of memory chips, and perform a first operation different from the refresh operation instead of performing the refresh operation during a predetermined refresh time interval, Wherein, the control logic circuit includes: a register clock driver buffer configured to store a first command; and A status register is configured to store a value indicating whether the register clock driver buffer is in a state allowed to receive the first command.

2. The memory device according to claim 1, in, The register clock driver buffer stores information of a command type of the first command and information of the first operation.

3. The memory device according to claim 2, in, The control logic circuit is configured to set a size of the register clock driver buffer according to a command type of the first command.

4. The memory device according to claim 1, in, The register clock driver buffer is enabled to store the first command when a first value is stored in the status register, and the register clock driver buffer is not enabled to store the first command when a second value different from the first value is stored in the status register.

5. The memory device according to claim 4, in, The control logic circuit updates the value of the status register to a second value in response to receiving the first command from the memory controller.

6. The memory device according to claim 4, in, The control logic circuit updates a value of the status register to a first value in response to sending a first command to the plurality of memory chips.

7. The memory device according to claim 1, in, The control logic circuit skips a refresh operation during the predetermined refresh time interval.

8. The memory device according to claim 1, in, The first operation includes at least one of a test mode register set sequence and a post-soft package repair sequence for the plurality of memory chips.

9. The memory device according to claim 6, in, When the first value is saved in the status register, the control logic circuit performs a refresh operation in response to a refresh command received from the memory controller.

10. A memory device, include: a plurality of memory chips including a plurality of memory cells connected to a plurality of row lines and a plurality of column lines; as well as a control logic circuit configured to: send a first command for performing a first operation for inputting / outputting data with respect to the plurality of memory cells in a first state, and perform a second operation for repairing at least one defective memory cell among the plurality of memory cells in a second state, wherein the control logic circuit receives a second command for performing a second operation from the memory controller in the first state, and sends the second command to the plurality of memory chips in the second state, wherein the control logic circuit sends a second command to the plurality of memory chips in response to the refresh command, and performs a second operation different from the refresh operation on the plurality of memory chips instead of performing the refresh operation during a predetermined refresh time interval, Wherein, the control logic circuit includes: a register clock driver buffer configured to store a second command; and A status register is configured to store a value indicating whether the register clock driver buffer is in a state allowed to receive a second command.

11. The memory device according to claim 10, in, The register clock driver buffer is used to store information of a command type of a second command received from the memory controller and information of a second operation.

12. The memory device according to claim 11, in, The control logic circuit receives a third command in the first state, The register clock driver buffer also stores priority information for each of the second command and the third command. An order of executing the second command and the third command is determined based on priority information of each of the second command and the third command.

13. The memory device according to claim 11, in, A size of a register clock driver buffer is determined based on a maximum number of commands to be executed during an entire refresh time interval for the plurality of memory chips according to retention characteristics of the plurality of memory cells.

14. A memory device, include: multiple memory chips; as well as Control logic circuit, including: a status register configured to have status information indicating whether the register clock driver buffer is in a state for receiving a first command; a register clock driver buffer configured to save the first command according to the status information of the status register, and a refresh controller configured to control a self-refresh operation of the plurality of memory chips, The control logic circuit performs a first operation of a first command on at least one memory chip of the plurality of memory chips during at least one refresh time interval of a plurality of refresh time intervals of a self-refresh operation.

15. The memory device according to claim 14, in, The refresh controller is configured to perform the self refresh operation by generating a third command to start the self refresh operation and a second command to terminate the self refresh operation, and transmitting the third command and the second command to the plurality of memory chips.

16. The memory device according to claim 14, in, The first operation includes at least one of a test mode register set sequence and a post-soft package repair sequence for the plurality of memory chips.

17. The memory device according to claim 14, in, The control logic circuit skips a refresh operation during at least one refresh time interval of the plurality of refresh time intervals.

18. The memory device according to claim 14, in, The register clock driver buffer stores information of a command type of the first command and information of the first operation, and has a varying size according to the command type of the first command.

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