Electrostatic protection circuit and chip

Abstract

The present disclosure provides an electrostatic protection circuit, including: a first electrostatic bypass, including a first P-type transistor, a drain coupled to a first node, a source coupled to a first voltage, a gate connected to a second voltage through a first resistor module, and the first node is electrically connected to a signal input pin; a second electrostatic bypass, including a first N-type transistor, a drain coupled to a first node, a source coupled to a second voltage, and a gate connected to the first voltage through a second resistor module; an input buffer circuit, at least including a second N-type transistor and a second P-type transistor whose gate is coupled to the second node; a third P-type transistor, coupled to the first node and the second node, and a control terminal coupled to the third node; a control module, coupled to the first voltage, the second voltage, and the third node, for controlling the third P-type transistor to be turned off when an ESD current is generated. The embodiments of the present disclosure can overcome the problem of failure of the protection function of the GGNMOS circuit caused by the reduction of the thickness of the MOS gate oxide layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an electrostatic protection circuit and a chip using the electrostatic protection circuit. Background Art

[0002] The design of ESD (Electrostatic Discharge) protection circuits is of great significance for integrated circuit chips. When ESD occurs, transient voltage enters the internal circuit through the chip pin (PAD), and the transient accumulation of charge can damage the devices in the chip's internal circuit. The ESD circuit designed next to and coupled to the PAD can provide a low-impedance bypass for these transient voltages, allowing them to enter the power line (VDD or VSS) and protect the chip's internal working circuits.

[0003] The GGNMOS (gate-grounded NMOS) electrostatic protection circuit is a commonly used electrostatic protection circuit, in which a gate-grounded transistor provides a low-resistance bypass for the ESD current to prevent it from breaking through the gate oxide layer of the transistor in the input buffer circuit. In the existing GGNMOS electrostatic protection circuit, the PN junction breakdown voltage of the GGNMOS is lower than the gate oxide breakdown voltage of the transistor in the input buffer circuit (buffer). When the transient ESD current enters through the chip pin (PAD), the PN junction of the GGNMOS is instantly broken down, bypassing the current to the power line to achieve the protection purpose.

[0004] However, with the advancement of technology, the thickness of the transistor gate oxide layer is getting smaller and smaller, which is already lower than the breakdown voltage of the PN junction. The ESD current will first break down the transistor gate oxide of the input buffer circuit, and the existing ESD protection circuit formed by GGNMOS becomes meaningless.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide an electrostatic protection circuit, which is used to overcome, at least to a certain extent, the problem that the GGNMOS electrostatic protection circuit cannot adapt to the reduction of gate oxide layer thickness caused by technological progress due to defects in the related art.

[0007] According to a first aspect of the present disclosure, there is provided an electrostatic protection circuit, comprising:

[0008] A first electrostatic bypass at least comprises a first P-type transistor, wherein a drain of the first P-type transistor is coupled to a first node, a source is coupled to a first voltage, a gate is connected to the first voltage through a first resistor module, and the first node is electrically connected to a signal input pin;

[0009] A second electrostatic bypass at least comprises a first N-type transistor, wherein a drain of the first N-type transistor is coupled to the first node, a source is coupled to the second voltage, and a gate is connected to the second voltage through a second resistor module;

[0010] An input buffer circuit, comprising at least a second N-type transistor and a second P-type transistor, wherein a gate of the second N-type transistor and a gate of the second P-type transistor are coupled to a second node;

[0011] a third P-type transistor, having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a third node;

[0012] A control module, having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and an output terminal coupled to the third node, for controlling the third P-type transistor to be turned off when an ESD current is generated;

[0013] The first resistance module and the second resistance module are used to provide a resistance function.

[0014] In an exemplary embodiment of the present disclosure, the control module includes:

[0015] A first capacitor, a first end of which is coupled to the first voltage, and a second end of which is coupled to a third node;

[0016] The third resistance module is used to provide a resistance function, with a first end coupled to the third node and a second end coupled to the second voltage.

[0017] In an exemplary embodiment of the present disclosure, the first resistance module is implemented by a first resistor, or the first resistance module is implemented by a fourth P-type transistor, the drain of the fourth P-type transistor is coupled to the gate of the first P-type transistor, the source of the fourth P-type transistor is coupled to the first voltage, and the gate of the fourth P-type transistor is connected to the second voltage through a second resistor.

[0018] In an exemplary embodiment of the present disclosure, the second resistance module is implemented by a third resistor, or the second resistance module is implemented by a fourth N-type transistor, the drain of the third N-type transistor is coupled to the gate of the first N-type transistor, the source of the third N-type transistor is coupled to the second voltage, and the gate of the third N-type transistor is connected to the first voltage through a fourth resistor.

[0019] In an exemplary embodiment of the present disclosure, the third resistance module is implemented by a fifth resistor, or the third resistance module is implemented by a fourth N-type transistor, the drain of the fourth N-type transistor is coupled to the third node, the source is coupled to the second voltage, and the gate is coupled to the first voltage through a sixth resistor.

[0020] In an exemplary embodiment of the present disclosure, it further includes:

[0021] A first diode, an anode coupled to the signal input pin, and a cathode coupled to the first voltage;

[0022] A second diode, a cathode coupled to the signal input pin, and an anode coupled to the first voltage;

[0023] A seventh resistor has a first end coupled to the signal input pin, and a second end coupled to the first node.

[0024] In an exemplary embodiment of the present disclosure, the input buffer circuit is implemented by an inverter, which is composed of the second P-type transistor and the second N-type transistor, the first end of the inverter is coupled to the first voltage, the second end is coupled to the second voltage, the third end is coupled to the second node, and the fourth end is coupled to the internal circuit.

[0025] In an exemplary embodiment of the present disclosure, the input buffer circuit is implemented by a Schmitt trigger, and the Schmitt trigger is composed of a fifth P-type transistor, the second P-type transistor, the second N-type transistor, a fifth N-type transistor, a sixth P-type transistor, and a sixth N-type transistor. The first end of the Schmitt trigger is coupled to the first voltage, the second end is coupled to the second voltage, the third end is coupled to the second node, and the fourth end is coupled to the internal circuit.

[0026] According to one aspect of the present disclosure, a chip is provided, wherein one or more pins are electrically connected to the electrostatic protection circuit as described in any one of the above items.

[0027] The electrostatic protection circuit provided by the embodiment of the present disclosure can increase the difficulty of breaking down the input buffer circuit without affecting the normal operation of the circuit by setting a gate-controlled PMOS between the electrostatic protection circuit and the input buffer circuit, thereby effectively overcoming the ESD protection circuit failure problem caused by the reduction of the gate oxide layer thickness.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 Schematic diagram of an electrostatic protection circuit provided by the present invention.

[0031] Figure 2 is a schematic diagram of an electrostatic protection circuit in one embodiment.

[0032] Figure 3A to Figure 3C Schematic diagram of the implementation circuit of each resistance module in the three embodiments of the present disclosure.

[0033] Figure 4 is a schematic diagram of an input buffer circuit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0035] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0036] Figure 1 is a schematic diagram of an electrostatic protection circuit 100 provided by the present disclosure.

[0037] refer to Figure 1, the electrostatic protection circuit 100 may include:

[0038] The first electrostatic bypass 11 at least includes a first P-type transistor MP1, the drain of the first P-type transistor MP1 is coupled to the first node N1, the source is coupled to the first voltage VDD, the gate is connected to the first voltage VDD through the first resistor module MR1, and the first node N1 is electrically connected to the signal input pin IN;

[0039] The second electrostatic bypass 12 at least includes a first N-type transistor MN1, the drain of the first N-type transistor MN1 is coupled to the first node N1, the source is coupled to the second voltage VSS, and the gate is connected to the second voltage VSS through the second resistor module MR2;

[0040] The input buffer circuit 13 at least includes a second N-type transistor MN2 and a second P-type transistor MP2, wherein a gate of the second N-type transistor MN2 and a gate of the second P-type transistor MP2 are coupled to a second node N2;

[0041] A third P-type transistor MP3, having a first terminal coupled to the first node N1, a second terminal coupled to the second node N2, and a control terminal coupled to the third node N3;

[0042] A control module 14, having a first terminal coupled to a first voltage VDD, a second terminal coupled to a second voltage VSS, and an output terminal coupled to a third node N3, for controlling the third N-type transistor MN3 to be turned off when an ESD current is generated;

[0043] The first resistor module MR1 and the second resistor module MR2 are used to provide a resistor function. MR1 and MR2 are equivalent to two resistors, and the resistance values ​​of the two resistors are large, which are used to control MP1 and MN1 to be turned off when no ESD current is generated. When ESD current is generated, MN1 or MP1 is broken down to provide a discharge path for the ESD current.

[0044] In the prior art, assuming that the gate breakdown voltage of MP2 and MN2 is higher than the PN junction breakdown voltage of MP1 and MN1, when the ESD current enters the N1 node, the PN junction of MP1 or MN1 is broken down before the gate of MP2 and MN2, and the ESD current is discharged through MP1 or MN1. However, as the gate oxide thickness is further reduced, the gate breakdown voltage of MP2 and MN2 may be lower than the PN junction breakdown voltage of MP1 and MN1, and the ESD current may directly break down the gate of MP2 and MN2, thereby causing damage to the internal circuit.

[0045] exist Figure 1In the illustrated embodiment, MP3 is in the on state when no ESD current is generated, and does not affect the signal transmission from the signal input pin IN to the input buffer circuit 13. When the ESD current is generated, the control module 14 controls MP3 to be turned off. At this time, only when the voltage of the first node N1 is higher than the sum of the PN junction breakdown voltage of MP3 and the gate oxide breakdown voltage of MN2 and MP2, damage to the gate oxide of MN2 and MP2 may occur. In one embodiment, MP3 can be the same type of device as MN1, with the same PN junction breakdown voltage, so that when the ESD current reaches the signal input pin IN, it is blocked by the turned-off MP3, which buys time for the ESD current to be discharged through the first electrostatic bypass 11 and the second electrostatic bypass 12, and effectively protects the transistors in the input buffer circuit 13 before the electrostatic discharge is successful.

[0046] After the ESD current is discharged through the first electrostatic bypass 11 and the second electrostatic bypass 12 , that is, after the ESD current disappears, the control module 14 controls MP3 to be turned on again, and the input buffer circuit 13 can normally receive the signal input through the signal input pin IN.

[0047] Therefore, without affecting the normal function of the input circuit, the embodiment of the present disclosure can be applied when the gate oxide breakdown voltage of the transistor in the input buffer circuit 13 is less than the breakdown voltage of the PN junction, thereby retaining the performance advantages of the GGNMOS electrostatic protection circuit and overcoming the problem that the existing GGNMOS electrostatic protection circuit cannot adapt to the reduced gate oxide thickness of the new transistor.

[0048] Figure 2 is a schematic diagram of an electrostatic protection circuit 100 in one embodiment.

[0049] refer to Figure 2 In one embodiment, the electrostatic protection circuit 100 may further include:

[0050] A first diode Dp, an anode of which is coupled to the signal input pin IN, and a cathode of which is coupled to the first voltage VDD;

[0051] A second diode Dn, a cathode coupled to the signal input pin IN, and an anode coupled to the first voltage VSS;

[0052] The seventh resistor R7 has a first end coupled to the signal input pin IN, and a second end coupled to the first node N1.

[0053] Dp and Dn exist as electrostatic bypass in the basic ESD protection circuit. The role of R7 is to increase the resistance of the signal input path so that the ESD current can enter the power line through Dp or Dn first. In order to prevent affecting the normal signal processing, the resistance of R7 is generally small, and polysilicon (poly) resistors can be used.

[0054] The control module 14 may include:

[0055] A first capacitor C, a first end of which is coupled to the first voltage VDD, and a second end of which is coupled to the third node N3;

[0056] The third resistor module MR3 is used for providing a resistor function, a first end of which is coupled to the third node N3, and a second end of which is coupled to the second voltage VSS.

[0057] When an ESD positive voltage is generated, the ESD current instantly enters VDD through Dp, increasing the VDD voltage value, and then increasing the plate voltage value of capacitor C. A high voltage pulse is generated on the other plate of C to the gate of MP3, turning off MP3, and cutting off the path between the signal input pin IN and the input cache circuit 13, so that the electrostatic current is discharged to the power line through the first electrostatic bypass or the second electrostatic bypass, thereby realizing the ESD protection function.

[0058] In an exemplary embodiment of the present disclosure, when no electrostatic current occurs, the voltage value of the third node N3 is pulled down to a low level through the third resistor module MR3, and MP3 is controlled to be turned on to avoid affecting the normal operation of the signal input path.

[0059] exist Figure 1 or Figure 2 In the illustrated embodiment, the resistor modules MR1 ​​to MR3 are used to implement the resistor function and provide the resistance value. In the disclosed embodiment, the resistor modules can be implemented in a variety of ways.

[0060] Figure 3A to Figure 3C Schematic diagram of the implementation circuit of each resistance module in the three embodiments of the present disclosure.

[0061] refer to Figure 3A , the first resistance module MR1 can be implemented by the first resistor R1, the second resistance module MR2 can be implemented by the third resistor R3, and the third resistance module MR3 can be implemented by the fifth resistor R5. In order to protect the transistors and control the transistors MP1 and MN1 to be normally turned off, the resistance values ​​of MR1 to MR3 are relatively large. Therefore, although the function of the resistance module can be realized by a single resistor, it can save costs, but it will occupy a larger design area.

[0062] refer to Figure 3B In another embodiment, the first resistor module MR1 can be implemented by a fourth P-type transistor MP4, the drain of MP4 is coupled to the gate of MP1, the source is coupled to the first voltage VDD, and the gate is connected to the second voltage VSS through the second resistor R2.

[0063] The second resistance module MR2 can be implemented by a third N-type transistor MN3 , a drain of MN3 is coupled to the gate of MN1 , a source of MN3 is coupled to the second voltage VSS, and a gate of MN3 is connected to the first voltage VDD through a fourth resistor R4 .

[0064] In the embodiment shown in FIG3 , a resistor module with a higher resistance value is realized by using a normally-open MOS tube instead of a single resistor, which can effectively save device area. The PN junction resistance of the turned-on MOS tube is higher, and the manufacturing area occupied by itself is smaller. Moreover, since the control MOS tube is normally-open, the resistance values ​​of R2 and R4 are also smaller. In some embodiments, a Poly resistor can be used to realize this.

[0065] refer to Figure 3C The third resistor module MR3 can be implemented by a fourth N-type transistor MN4, a drain of MN4 is coupled to the third node N3, a source is coupled to the second voltage VSS, and a gate is coupled to the first voltage VDD through a sixth resistor R6.

[0066] exist Figure 3A to Figure 3C In the illustrated embodiment, the input buffer circuit 13 is implemented by an inverter, which is composed of MP2 and MN2. The first end of the inverter is coupled to the first voltage VDD, the second end is coupled to the second voltage VSS, the third end is coupled to the second node N2, and the fourth end OUT is coupled to the internal circuit to output a CMOS level signal to the internal circuit.

[0067] In other embodiments, the input buffer circuit 13 may also be implemented in other ways.

[0068] Figure 4 is a schematic diagram of an input buffer circuit in one embodiment of the present disclosure.

[0069] refer to Figure 4 The input buffer circuit 13 can be implemented by a Schmitt trigger, which is composed of a fifth P-type transistor MP5, a second P-type transistor MP2, a second N-type transistor MN2, a fifth N-type transistor MN5, a sixth P-type transistor MP6, and a sixth N-type transistor MN6. As the input buffer circuit 13, the first end of the Schmitt trigger is coupled to the first voltage VDD, the second end is coupled to the second voltage VSS, the third end is coupled to the second node N2, and the fourth end OUT is coupled to the internal circuit to output a CMOS level signal to the internal circuit.

[0070] According to another aspect of the present disclosure, a chip is provided, one or more pins of which are electrically connected to the electrostatic protection circuit as described above. Since the chip includes the electrostatic protection circuit as described above, it is possible to utilize the advantages of the ESD protection circuit composed of GGNMOS while overcoming the problem that the GGNMOS circuit cannot adapt to the reduction of the gate oxide layer thickness.

[0071] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. An electrostatic protection circuit, characterized in that: include: A first electrostatic bypass at least comprises a first P-type transistor, wherein a drain of the first P-type transistor is coupled to a first node, a source is coupled to a first voltage, a gate is connected to the first voltage through a first resistor module, and the first node is electrically connected to a signal input pin; A second electrostatic bypass at least comprises a first N-type transistor, wherein a drain of the first N-type transistor is coupled to the first node, a source is coupled to a second voltage, and a gate is connected to the second voltage through a second resistor module; An input buffer circuit, comprising at least a second N-type transistor and a second P-type transistor, wherein a gate of the second N-type transistor and a gate of the second P-type transistor are coupled to a second node; a third P-type transistor, having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a third node; A control module, having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and an output terminal coupled to the third node, for controlling the third P-type transistor to be turned off when an ESD current is generated; The first resistance module and the second resistance module are used to provide a resistance function.

2. The electrostatic protection circuit according to claim 1, characterized in that: The control module comprises: A first capacitor, a first end of which is coupled to the first voltage, and a second end of which is coupled to a third node; The third resistance module is used to provide a resistance function, with a first end coupled to the third node and a second end coupled to the second voltage.

3. The electrostatic protection circuit according to claim 1, characterized in that: The first resistance module is implemented by a first resistor, or the first resistance module is implemented by a fourth P-type transistor, the drain of the fourth P-type transistor is coupled to the gate of the first P-type transistor, the source of the fourth P-type transistor is coupled to the first voltage, and the gate of the fourth P-type transistor is connected to the second voltage through a second resistor.

4. The electrostatic protection circuit according to claim 1, characterized in that: The second resistance module is implemented by a third resistor, or the second resistance module is implemented by a fourth N-type transistor, the drain of the third N-type transistor is coupled to the gate of the first N-type transistor, the source of the third N-type transistor is coupled to the second voltage, and the gate of the third N-type transistor is connected to the first voltage through a fourth resistor.

5. The electrostatic protection circuit according to claim 2, characterized in that: The third resistance module is implemented by a fifth resistor, or the third resistance module is implemented by a fourth N-type transistor, the drain of the fourth N-type transistor is coupled to the third node, the source is coupled to the second voltage, and the gate is coupled to the first voltage through a sixth resistor.

6. The electrostatic protection circuit according to claim 1, characterized in that: Also includes: A first diode, an anode coupled to the signal input pin, and a cathode coupled to the first voltage; A second diode, a cathode coupled to the signal input pin, and an anode coupled to the first voltage; A seventh resistor has a first end coupled to the signal input pin, and a second end coupled to the first node.

7. The electrostatic protection circuit according to claim 1, characterized in that: The input buffer circuit is implemented by an inverter, which is composed of the second P-type transistor and the second N-type transistor. The first end of the inverter is coupled to the first voltage, the second end is coupled to the second voltage, the third end is coupled to the second node, and the fourth end is coupled to the internal circuit.

8. The electrostatic protection circuit according to claim 1, characterized in that: The input buffer circuit is implemented by a Schmitt trigger, which is composed of a fifth P-type transistor, the second P-type transistor, the second N-type transistor, a fifth N-type transistor, a sixth P-type transistor, and a sixth N-type transistor. The first power supply terminal of the Schmitt trigger is coupled to the first voltage, the second power supply terminal is coupled to the second voltage, the input terminal is coupled to the second node, and the output terminal is coupled to the internal circuit.

9. A chip, characterized in that: One or more pins are electrically connected to the electrostatic protection circuit as claimed in any one of claims 1 to 8.

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