A calculation method and related products

Abstract

The present disclosure provides an information processing method, which is applied in a computing device, wherein the computing device includes: a storage medium, a register unit and a matrix computing unit; the method includes the following steps: the computing device controls the matrix computing unit to obtain a first operation instruction, wherein the first operation instruction includes a matrix reading instruction required to execute the instruction; the computing device controls the computing unit to send a read command to the storage medium according to the matrix reading instruction; the computing device controls the computing unit to read the matrix corresponding to the matrix reading instruction in a batch reading manner, and executes the first operation instruction on the matrix. The technical solution provided by the present application has the advantages of fast calculation speed and high efficiency.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a computing method and related products. Background Art

[0002] Data processing is a step or stage that most algorithms need to go through. After computers were introduced into the field of data processing, more and more data processing is implemented through computers. In the existing algorithms, some computing devices are slow and inefficient when calculating matrix data.

[0003] Application Contents

[0004] The embodiments of the present application provide a computing method and related products, which can increase the processing speed of a computing device and improve efficiency.

[0005] In a first aspect, a computing method is provided, which is applied in a computing device, wherein the computing device includes a storage medium, a register unit, and a matrix operation unit, and the method includes:

[0006] The computing device controls the matrix operation unit to obtain a first operation instruction, where the first operation instruction is used to implement an operation between a matrix and a scalar, and the first operation instruction includes a matrix read instruction required to execute the instruction, where the required matrix is ​​at least one matrix, and the at least one matrix is ​​a matrix with the same length or a matrix with different lengths;

[0007] The computing device controls the matrix operation unit to send a read command to the storage medium according to the matrix read instruction;

[0008] The computing device controls the matrix operation unit to read the matrix corresponding to the matrix read instruction from the storage medium in a batch reading manner, and executes the first operation instruction on the matrix.

[0009] In some possible embodiments, executing the first operation instruction on the matrix includes:

[0010] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method to execute the first operation instruction on the matrix.

[0011] In some possible embodiments, each of the multiple pipeline stages includes at least one operator.

[0012] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0013] The computing device controls the matrix operation unit to calculate the matrix according to the selection of the multiplexer using the first selection operator in the first pipeline stage to obtain a first result, inputs the first result to the second selection operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the i-th selection operator in the i-th pipeline stage to perform calculation to obtain the i-th result;

[0014] Inputting the i-th result into the storage medium for storage;

[0015] The number i of the multi-stage pipeline stages is determined according to the computational topology of the first operation instruction, and i is a positive integer.

[0016] In some possible embodiments, each of the multiple pipeline stages is respectively configured with a corresponding multiplexer, and the multiplexer is provided with an empty option, and the empty option is used to indicate that the kth pipeline stage connected to the multiplexer and the subsequent k+1th to ith pipeline stages shall not perform computing operations, wherein k is a positive integer less than or equal to i.

[0017] In some possible embodiments, the operators included in each of the multiple pipeline stages and the number of the operators are custom set by the user side or the computing device side.

[0018] In some possible embodiments, each of the multiple pipeline stages includes a preset fixed operator, and the fixed operators in each pipeline stage are different.

[0019] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0020] The computing device controls the matrix computing unit to use the fixed operator in the first pipeline stage to calculate the matrix to obtain a first result, inputs the first result to the fixed operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the fixed operator in the i-th pipeline stage to perform calculation to obtain the i-th result;

[0021] Inputting the i-th result into the storage medium for storage;

[0022] The number i of the multi-stage pipeline stages is determined according to the computational topology of the first operation instruction, and i is a positive integer.

[0023] In some possible embodiments, the operator in each pipeline stage in the multi-stage pipeline stage includes any one or a combination of the following: a matrix addition operator, a matrix multiplication operator, a matrix scalar multiplication operator, a nonlinear operator, and a matrix comparison operator.

[0024] In some possible embodiments, the first operation instruction includes any one of the following: a matrix determinant instruction MDET, a matrix rank instruction MRANK, a matrix trace instruction MTRA, a matrix zero element ratio instruction MNZ, and a matrix main eigenvalue instruction MEVA.

[0025] In some possible embodiments, the first operation instruction is a matrix determinant instruction MDET,

[0026] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0027] The computing device controls the matrix operation unit to perform a sequence inversion operation on the matrix according to the selection of the multiplexer using the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result into the second pipeline stage to perform all sequence multiplication operations on the first result using the matrix multiplication operator therein to obtain a second result, inputs the second result into the third pipeline stage to perform all sequence summation operations on the second result using the matrix addition operator therein to obtain a third result; and inputs the third result into the storage medium for storage.

[0028] In some possible embodiments, the first operation instruction is a matrix rank instruction MRANK,

[0029] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0030] The computing device controls the matrix operation unit to perform elementary row transformation on the matrix according to the selection of the multiplexer using the matrix adder in the first pipeline stage to obtain a first result, inputs the first result to the matrix comparison operator in the second pipeline stage to count the number of non-zero rows to obtain a second result; and inputs the second result to the storage medium for storage, wherein the second result is the rank of the matrix.

[0031] In some possible embodiments, the first operation instruction is a matrix trace instruction MTRA,

[0032] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0033] The computing device controls the matrix operation unit to select the diagonal elements of the matrix according to the selection of the multiplexer, and uses the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result to the matrix addition operator in the second pipeline stage to sum the diagonal elements of the matrix to obtain a second result; and inputs the second result to the storage medium for storage.

[0034] In some possible embodiments, the first operation instruction is a matrix zero element ratio instruction MNZ,

[0035] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0036] The computing device controls the matrix operation unit to select zero elements from the matrix according to the selection of the multiplexer using the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result into the matrix adder operator in the second pipeline stage to count the number of zero elements in the matrix to obtain a second result, inputs the second result into the matrix multiplication operator in the third pipeline stage to calculate the proportion of zero elements in the matrix to obtain a third result; and inputs the third result into the storage medium for storage.

[0037] In some possible embodiments, the first operation instruction is a matrix principal eigenvalue instruction MEVA,

[0038] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0039] The computing device controls the matrix operation unit to normalize the matrix according to the selection of the multiplexer using the matrix adder in the first pipeline stage to obtain a first result, inputs the first result to the matrix adder in the second pipeline stage to perform normalization again to obtain a second result, inputs the second result to the matrix multiplier in the third pipeline stage to calculate the main eigenvalue to obtain a third result; and inputs the third result to the storage medium for storage.

[0040] In some possible embodiments, the instruction format of the first operation instruction includes an operation code and at least one operation field, the operation code is used to indicate the function of the operation instruction, the operation unit can perform different matrix operations by identifying the operation code, and the operation field is used to indicate the data information of the operation instruction, wherein the data information can be an immediate number or a register number, for example, when a matrix is ​​to be obtained, the matrix starting address and the matrix length can be obtained in the corresponding register according to the register number, and then the matrix stored at the corresponding address can be obtained in the storage medium according to the matrix starting address and the matrix length. Optionally, any one or a combination of multiple items of the following information can be obtained in the corresponding register: the number of rows, the number of columns, the data type, the identifier, the storage address (first address) and the dimension length of the matrix required by the instruction, wherein the dimension length refers to the length of the matrix row and / or the length of the matrix column.

[0041] In some possible embodiments, the matrix read instruction includes: a storage address of a matrix required by the instruction or an identifier of a matrix required by the instruction.

[0042] In some possible embodiments, when the matrix read indicates an identifier of the matrix required by the instruction,

[0043] The computing device controls the matrix operation unit to send a read command to the storage medium according to the matrix read instruction, comprising:

[0044] The computing device controls the matrix operation unit to read the storage address corresponding to the identifier from the register unit in a unit reading manner according to the identifier;

[0045] The computing device controls the matrix operation unit to send a read command for reading the storage address to the storage medium and obtains the matrix in a batch reading manner.

[0046] In some possible embodiments, the computing device further includes: a cache unit, and the method further includes:

[0047] The computing device caches the operation instructions to be executed in the cache unit.

[0048] In some possible embodiments, before the computing device controls the matrix operation unit to obtain the first operation instruction, the method further includes:

[0049] The computing device determines whether the first operation instruction has an association relationship with a second operation instruction preceding the first operation instruction, and if the first operation instruction has an association relationship with the second operation instruction, caches the first operation instruction in the cache unit, and extracts the first operation instruction from the cache unit and transmits it to the operation unit after the second operation instruction is executed;

[0050] The determining whether the first operation instruction has an association relationship with a second operation instruction before the first operation instruction comprises:

[0051] A first storage address interval of a matrix required in the first operation instruction is extracted according to the first operation instruction, and a second storage address interval of a matrix required in the second operation instruction is extracted according to the second operation instruction. If the first storage address interval and the second storage address interval have an overlapping area, it is determined that the first operation instruction and the second operation instruction have an associated relationship. If the first storage address interval and the second storage address interval do not have an overlapping area, it is determined that the first operation instruction and the second operation instruction have no associated relationship.

[0052] According to a second aspect, a computing device is provided, wherein the computing device comprises a functional unit for executing the method according to the first aspect.

[0053] According to a third aspect, a computer-readable storage medium is provided, which stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute the method provided in the first aspect.

[0054] According to a fourth aspect, a computer program product is provided, the computer program product comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute the method provided in the first aspect.

[0055] In a fifth aspect, a chip is provided, wherein the chip includes the computing device provided in the second aspect above.

[0056] In a sixth aspect, a chip packaging structure is provided, wherein the chip packaging structure includes the chip provided in the fifth aspect above.

[0057] In a seventh aspect, a board is provided, wherein the board includes the chip packaging structure provided in the sixth aspect.

[0058] In an eighth aspect, an electronic device is provided, the electronic device comprising the board provided in the seventh aspect.

[0059] In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device.

[0060] In some embodiments, the means of transportation include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound equipment and / or electrocardiographs.

[0061] Implementing the embodiments of the present application has the following beneficial effects:

[0062] It can be seen that through the embodiments of the present application, the computing device is provided with a register unit and a storage medium, which are respectively used to store scalar data and matrix data, and the present application allocates a unit reading mode and a batch reading mode for the two memories. By allocating a data reading mode that matches the characteristics of the matrix data, the bandwidth can be well utilized to avoid the impact of the bandwidth bottleneck on the matrix calculation speed. In addition, for the register unit, since it stores scalar data, a scalar data reading mode is set to improve the bandwidth utilization. Therefore, the technical solution provided by the present application can make good use of the bandwidth and avoid the impact of the bandwidth on the calculation speed. Therefore, it has the advantages of fast calculation speed and high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0064] Figure 1 It is a structural diagram of a computing device provided in an embodiment of the present application.

[0065] Figure 2 It is a structural diagram of a computing unit provided in an embodiment of the present application.

[0066] Figure 3 It is a flowchart of a calculation method provided by an embodiment of the present invention.

[0067] Figure 4A It is a schematic diagram of the architecture of the pipeline stage provided in an embodiment of the present application.

[0068] Figure 4B This is another architectural diagram of the pipeline stage provided in an embodiment of the present application.

[0069] Figure 5 It is a schematic diagram of the structure of the pipeline stage provided in the embodiment of the present application.

[0070] Fig. 6A It is a format diagram of the instruction set provided in the embodiment of the present application.

[0071] Figure 6B This is another format diagram of the instruction set provided in the embodiment of the present application.

[0072] Figure 7 It is a structural diagram of another computing device provided in an embodiment of the present application.

[0073] Figure 8 It is a flow chart of a computing device provided in an embodiment of the present application executing a matrix trace instruction. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0075] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0076] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0077] It should be noted that the matrix involved in this application can be specifically an m*n matrix, where m and N are integers greater than or equal to 1. When m or n is 1, it can be expressed as a 1*n matrix or an m*1 matrix, which can also be called a vector; when m and n are both 1, it can be regarded as a 1*1 special matrix. The following matrices can be any of the three types of matrices mentioned above, which will not be repeated below.

[0078] The present application embodiment provides a calculation method, which can be applied to a computing device. Figure 1 , is a schematic diagram of a possible computing device according to an embodiment of the present invention. Figure 1The computing device shown includes:

[0079] Storage medium 201 is used to store matrices. Preferably, the storage medium can be a high-speed scratchpad memory that can support matrix data of different lengths. The present application temporarily stores the necessary calculation data in the high-speed scratchpad memory (ScratchpadMemory), so that the computing device can more flexibly and effectively support data of different lengths during matrix operations. The above storage medium can also be an off-chip database, a database, or other storage medium, etc.

[0080] The register unit 202 is used to store scalar data, wherein the scalar data includes but is not limited to: the storage address of the matrix data (also referred to as a matrix in this application) in the storage medium 201 and the scalar when the matrix and the scalar are operated. In one embodiment, the register unit can be a scalar register stack, which provides the scalar registers required in the operation process, and the scalar registers not only store the matrix address, but also store the scalar data. It should be understood that the matrix address (i.e., the storage address of the matrix, such as the first address) is also a scalar. When it comes to the operation of the matrix and the scalar, the operation unit must not only obtain the matrix address from the register unit, but also obtain the corresponding scalar from the register unit, such as the number of rows and columns of the matrix, the type of matrix data (also referred to as data type), and the length of the matrix dimension (specifically, the length of the matrix row, the length of the matrix column, etc.).

[0081] The operation unit 203 (also referred to as the matrix operation unit 203 in this application) is used to obtain and execute the first operation instruction. Figure 2 As shown, the operation unit includes multiple operators, which include but are not limited to: a matrix addition operator 2031, a matrix multiplication operator 2032, a size comparison operator 2033 (which can also be a matrix comparison operator), a nonlinear operator 2034 and a matrix scalar multiplication operator 2035.

[0082] This method is Figure 3 As shown, the following steps are included:

[0083] Step S301: The operation unit 203 obtains a first operation instruction, where the first operation instruction is used to implement matrix and scalar operations. The first operation instruction includes: a matrix read instruction required to execute the instruction.

[0084] In step S301, the matrix read instruction required for executing the instruction may be specifically multiple, for example, in an optional technical solution of the present application, the matrix read instruction required for executing the instruction may be the storage address of the required matrix. For another example, in another optional technical solution of the present application, the matrix read instruction required for executing the instruction may be the identifier of the required matrix, and the identifier may be expressed in multiple forms, for example, the name of the matrix, the identification number of the matrix, or the register number or storage address of the matrix in the register unit.

[0085] The following is a practical example to illustrate the matrix read instruction required for executing the instruction contained in the above-mentioned first operation instruction. Here, it is assumed that the matrix operation formula is f(x)=A+B, where A and B are matrices. Then, in addition to carrying the matrix operation formula, the first operation instruction can also carry the storage address of the matrix required by the matrix operation formula. Specifically, for example, the storage address of A is 0000-0FFF, and the storage address of B is 1000-1FFF. For another example, the identifiers of A and B can be carried, for example, the identifier of A is 0101, and the identifier of B is 1010.

[0086] Step S302: The operation unit 203 sends a read command to the storage medium 201 according to the matrix read instruction.

[0087] The implementation method of the above step S302 may specifically be:

[0088] If the matrix read instruction may be a storage address of a required matrix, the operation unit 203 sends a read command for reading the storage address to the storage medium 201 and obtains the corresponding matrix in a batch read manner.

[0089] For example, when the matrix read indication can be the identifier of the required matrix, the operation unit 203 reads the storage address corresponding to the identifier from the register unit using a unit read method based on the identifier, and then the operation unit 203 sends a read command to read the storage address to the storage medium 201 and obtains the corresponding matrix using a batch read method.

[0090] The above-mentioned single reading mode can be specifically that each time the data is read, it is a unit of data, that is, 1 bit of data. The reason for setting the unit reading mode, that is, the 1-bit reading mode, is that for scalar data, the capacity occupied is very small. If the batch data reading mode is adopted, the amount of data read is likely to be greater than the required data capacity, which will lead to a waste of bandwidth. Therefore, the unit reading mode is adopted here for scalar data to reduce the waste of bandwidth.

[0091] Step S303 : The operation unit 203 reads the matrix corresponding to the instruction in a batch reading manner, and executes the first operation instruction on the matrix.

[0092] The batch reading method in the above step S303 can be specifically that each time a multi-bit data is read, for example, the number of data bits read each time is 16 bits, 32 bits or 64 bits, that is, no matter how much data is required, each time a fixed multi-bit data is read. This batch reading method is very suitable for reading large data. For the matrix, due to the large capacity it occupies, if a single reading method is used, the reading speed will be very slow. Therefore, a batch reading method is used here to obtain multi-bit data so as to quickly read the matrix data, thereby avoiding the problem of affecting the matrix calculation speed due to the slow reading of the matrix data.

[0093] The computing device of the technical solution provided in the present application is provided with a register unit and a storage medium, which respectively store scalar data and matrix data, and the present application allocates a unit reading mode and a batch reading mode to the two memories. By allocating a data reading mode that matches the characteristics of the matrix data, the bandwidth can be well utilized to avoid the influence of the bandwidth bottleneck on the matrix calculation speed. In addition, for the register unit, since it stores scalar data, a scalar data reading mode is set to improve the bandwidth utilization. Therefore, the technical solution provided in the present application can make good use of the bandwidth and avoid the influence of the bandwidth on the calculation speed, so it has the advantages of fast calculation speed and high efficiency.

[0094] Optionally, the execution of the first operation instruction on the matrix may specifically be:

[0095] The operation unit 203 may adopt a multi-stage pipeline calculation method, and the embodiment of the present application may adopt an i-stage pipeline calculation method to execute the first operation instruction on the matrix. Specific implementation methods include the following.

[0096] In the first implementation mode, the computing device may further be designed with at least one multiplexer MMUX to implement multi-stage pipeline computing. Figure 4A and Figure 4B Two multi-pipeline implementation architectures are shown respectively. Figure 4A , the computing device may design a multiplexer MMUX for each pipeline stage; Figure 4B It is shown that a multiplexer MMUX is provided for multiple pipeline stages. The multiplexer is connected to the pipeline stage corresponding to the required control / selection, and is used to select the operator in the pipeline stage to implement the relevant calculation. It should be understood that the operator selected by the multiplexer from the pipeline stage is determined according to the computing network topology corresponding to the first operation instruction, which will be described in detail below.

[0097] In a specific implementation, the operation unit 203 can calculate the matrix using the first selection operator selected by the first (level) pipeline stage according to the selection of the multiplexer to obtain the first result, and then input the first result to the second pipeline stage to use the second selection operator selected by the second pipeline stage to perform calculation to obtain the second result, and so on, input the i-1th result to the i-th pipeline stage to use the i-th selection operator selected by it to perform calculation to obtain the i-th result. Here, the i-th result is the output result (specifically, the output matrix). Further, the operation unit 203 can store the output result to the storage medium 201.

[0098] The number i of the multi-stage pipeline is specifically determined according to the computational topology of the first operation instruction, and i is a positive integer. Usually, i=3. A corresponding operator may be provided in each pipeline stage, and the operator includes but is not limited to any one or more of the following combinations: a matrix addition operator, a matrix scalar multiplication operator, a nonlinear operator, a matrix comparison operator, and other matrix operators. That is, the operators and the number of operators included in each pipeline stage may be customized by the user side or the computing device side, and are not limited.

[0099] Taking i=3 and three-stage pipeline as an example, the operation unit can select the operation units (also called operation components) required to be used in the first to third pipeline stages respectively through three multiplexers; at the same time, the first pipeline stage is calculated on the matrix to obtain the first result, (optionally) the first result is input to the second pipeline stage to perform the second pipeline stage calculation to obtain the second result, (optionally) the second result is input to the third pipeline stage to perform the third pipeline stage calculation to obtain the third result, and (optionally) the third result is stored in the storage medium 201. Figure 5 A schematic diagram of the operation flow of a pipeline stage is shown.

[0100] The first pipeline stage includes but is not limited to: a matrix multiplication operator and the like.

[0101] The second pipeline stage includes but is not limited to: a matrix adder, a size comparison operator, and the like.

[0102] The third pipeline stage includes but is not limited to: a nonlinear operator, a matrix scalar multiplication operator, and the like.

[0103] The main purpose of dividing the matrix into three pipeline operations is to improve the speed of the operation. For the calculation of the matrix, for example, when a general processor is used for calculation, the specific operation steps can be: the processor calculates the matrix to obtain a first result, and then stores the first result in the memory, the processor reads the first result from the memory to perform a second calculation to obtain the second result, and then stores the second result in the memory, the processor reads the second result from the memory to perform a third calculation to obtain the third result, and then stores the third result in the memory. It can be seen from the above calculation steps that when the general processor performs matrix calculation, it does not divide the pipeline for calculation, so the calculated data needs to be saved after each calculation, and needs to be read again when the next calculation is performed, so this solution needs to repeatedly store and read multiple data. For the technical solution of this application, the first result calculated by the first pipeline directly enters the second pipeline for calculation, and the second result calculated by the second pipeline directly enters the third pipeline for calculation. The first result and the second result calculated by the first pipeline and the second pipeline do not need to be stored. First, it reduces the occupied space of the memory, and secondly, it avoids multiple storage and reading of results, improves the utilization rate of bandwidth, and further improves the calculation efficiency.

[0104] In another embodiment of the present application, each pipeline component can be freely combined or a single pipeline stage can be adopted. For example, the second pipeline stage and the third pipeline stage can be merged, or the first, second and third pipelines can be merged, or each pipeline stage can be responsible for different operations and can be arranged and combined. For example, the first pipeline stage is responsible for comparison operations, partial multiplication operations, and the second pipeline stage is responsible for nonlinear operations and matrix scalar multiplication and other combinations. That is, the i pipeline stages designed in the present application support any number of pipeline stages in parallel, in series and merged to form different arrangements and combinations, which are not limited in the present application.

[0105] It should be noted that each multiplexer may also be provided with an empty option, that is, the pipeline stage connected to the multiplexer and the subsequent pipeline stages do not participate in the calculation. That is, the empty option in the present application is used to indicate that the kth pipeline stage connected to the multiplexer and the subsequent k+1th to ith pipeline stages do not perform the calculation operation, where k is a positive integer less than or equal to i.

[0106] Taking i=3 and three-stage pipeline as an example, if the multiplexer connected to the third pipeline stage selects the empty option, the third pipeline stage does not participate in the calculation, and the pipeline stage currently performing the calculation operation is less than three; for example, if a certain calculation instruction contains two-stage instructions, the multiplexer corresponding to the third pipeline stage selects the empty option.

[0107] The use of the above-mentioned computing device (i.e., a multi-way selector is designed to select the operator / computational component to be used in each pipeline stage) has the following beneficial effects: in addition to improving the bandwidth, it also has clear logic, no output result of the computational component jumps from the rear pipeline stage to the front pipeline stage, a single input interface and output interface, and good operability.

[0108] In a second implementation mode, the computing device may design a corresponding fixed pipeline implementation architecture for each operation instruction. Figure 5 The implementation architecture of a three-stage pipeline corresponding to an operation instruction is shown. That is, for a certain operation instruction, the operator contained in each pipeline stage is pre-fixed and set by the user side or the computing device side, and the present application may also be referred to as a fixed operator. In addition, the fixed operators in each pipeline stage may be the same or different, and are usually different. For example, the first pipeline stage is a matrix adder operator, the second pipeline stage is a matrix multiplier operator, and the third pipeline stage is a nonlinear operator; for another example, the first pipeline stage is a matrix adder operator, the second pipeline stage is a matrix adder operator, the third pipeline stage is a matrix multiplier operator, and so on. That is, different operation instructions involve different pipeline devices (implementation architectures). It should be understood that according to the implementation requirements of different operation instructions, the number i of pipeline stages involved may be different, and may be increased or decreased accordingly, and the present application does not limit it.

[0109] In a specific implementation, the operation unit 203 sequentially uses the fixed operator in the first (stage) pipeline stage to calculate the matrix to obtain the first result, inputs the first result to the second pipeline stage to use the fixed operator therein to perform the calculation to obtain the second result, and so on, until the i-1th result is input to the i-th pipeline stage to use the fixed operator therein to perform the calculation to obtain the i-th result. Here, the i-th result is the output result (specifically, the output matrix). Further, the operation unit 203 can store the output result to the storage medium 201. For the number i of the multi-stage pipeline stage and the fixed operator designed in each pipeline stage, please refer to the relevant description in the above-mentioned embodiment, which will not be repeated here.

[0110] Take i=3 and three-stage pipeline as an example. Figure 5 , showing a fixed implementation architecture of a pipeline stage corresponding to an operation instruction. Specifically, the operation unit performs a multiplication calculation of the first pipeline stage on the matrix to obtain a first result, inputs the first result to the second pipeline stage to perform an addition calculation of the second pipeline stage to obtain a second result, inputs the second result to the third pipeline stage to perform a nonlinear calculation of the third pipeline stage to obtain a third result, and stores the third result (i.e., the output result) to the storage medium 201.

[0111] It should be noted that the arithmetic units in each pipeline stage in the above-mentioned computing device are pre-customized and cannot be changed once determined; that is, the i-level pipeline stage can be designed as any arrangement and combination of arithmetic units, and the i-level pipeline stage will not be changed once driven, and different i-level pipeline stage devices can be designed for different computing instructions. Among them, the computing device can adaptively increase / reduce the number of pipeline stages according to the requirements of specific instructions. Finally, the pipeline stage devices designed for different instructions can be combined together to form the computing device.

[0112] The use of the above-mentioned computing device (i.e., the design of the operator / computing unit in each pipeline stage is fixed) has the following beneficial effects: in addition to improving the bandwidth, it has the characteristics of high specialization, no unnecessary logical judgment, further improving the computing performance, and fast computing speed.

[0113] Optionally, the computing device may further include: a cache unit 204 for caching the first operation instruction. During the execution process, the instruction is also cached in the instruction cache unit. After an instruction is executed, if the instruction is also the earliest instruction among the uncommitted instructions in the instruction cache unit, the instruction will be committed. Once committed, the change of the device state caused by the operation performed by the instruction cannot be undone. In one embodiment, the instruction cache unit may be a reordering cache.

[0114] Optionally, the above method may further include, before step S301:

[0115] Determine whether the first operation instruction has an association relationship with the second operation instruction before the first operation instruction. If the first operation instruction has an association relationship with the second operation instruction before the first operation instruction, then after the second operation instruction is executed, extract the first operation instruction from the cache unit and transmit it to the operation unit 203. If the first operation instruction has no association relationship with the instruction before the first operation instruction, directly transmit the first operation instruction to the operation unit.

[0116] The specific implementation method for determining whether the first operation instruction has an association relationship with the second operation instruction before the first operation instruction may be:

[0117] A first storage address interval of a matrix required in the first operation instruction is extracted according to the first operation instruction, and a second storage address interval of a matrix required in the second operation instruction is extracted according to the second operation instruction. If the first storage address interval and the second storage address interval have an overlapping area, it is determined that the first operation instruction and the second operation instruction have an associated relationship. If the first storage address interval and the second storage address interval do not have an overlapping area, it is determined that the first operation instruction and the second operation instruction do not have an associated relationship.

[0118] The presence of overlapping areas in this storage area interval indicates that the first operation instruction and the second operation instruction access the same matrix. For matrices, since the storage space is relatively large, for example, the same storage area is used as a condition for judging whether it is an association relationship. It may be that the storage area accessed by the second operation instruction includes the storage area accessed by the first operation instruction. For example, the second operation instruction accesses the A matrix storage area, the B matrix storage area, and the C matrix storage area. If the A and B storage areas are adjacent or the A and C storage areas are adjacent, the storage areas accessed by the second operation instruction are the A and B storage areas and the C storage areas, or the A and C storage areas and the B storage areas. In this case, if the first operation instruction accesses the storage areas of the A matrix and the D matrix, then the storage area of ​​the matrix accessed by the first operation instruction cannot be the same as the storage area of ​​the matrix of the second operation instruction. If the same judgment condition is used, it is determined that the first operation instruction and the second operation instruction are not associated. However, practice has proved that at this time, the first operation instruction and the second operation instruction are in an association relationship. Therefore, the present application uses whether there is an overlapping area to determine whether it is an association relationship to avoid misjudgment of the above situation.

[0119] The following is an actual example to illustrate which situations are associated and which are not. Here, it is assumed that the matrices required by the first operation instruction are A matrix and D matrix, where the storage area of ​​A matrix is ​​[0001, 0FFF], and the storage area of ​​D matrix is ​​[A000, AFFF]. The matrices required by the second operation instruction are A matrix, B matrix and C matrix, and their corresponding storage areas are [0001, 0FFF], [1000, 1FFF], and [B000, BFFF], respectively. For the first operation instruction, the corresponding storage areas are: [0001, 0FFF], [A000, AFFF], and for the second operation instruction, the corresponding storage areas are: [0001, 1FFF], [B000, BFFF]. Therefore, the storage area of ​​the second operation instruction has an overlapping area with the storage area of ​​the first operation instruction [0001, 0FFF], so the first operation instruction and the second operation instruction have an associated relationship.

[0120] Here it is assumed that the matrices required for the first operation instruction are the E matrix and the D matrix, where the storage area of ​​the A matrix is ​​[C000, CFFF], and the storage area of ​​the D matrix is ​​[A000, AFFF]. The matrices required for the second operation instruction are the A matrix, the B matrix, and the C matrix, and their corresponding storage areas are [0001, 0FFF], [1000, 1FFF], and [B000, BFFF], respectively. For the first operation instruction, the corresponding storage areas are: [C000, CFFF], [A000, AFFF], and for the second operation instruction, the corresponding storage areas are: [0001, 1FFF], [B000, BFFF]. Therefore, the storage area of ​​the second operation instruction does not have an overlapping area with the storage area of ​​the first operation instruction, so the first operation instruction has no association with the second operation instruction.

[0121] In this application, if Fig. 6A It is a format diagram of an instruction set of an instruction (which may be a first operation instruction or an operation instruction) provided by the present application, such as Fig. 6A As shown, the operation instruction includes an operation code and at least one operation field, wherein the operation code is used to indicate the function of the operation instruction, and the operation unit can perform different matrix operations by identifying the operation code, and the operation field is used to indicate the data information of the operation instruction, wherein the data information can be an immediate number or a register number. For example, when a matrix is ​​to be obtained, the matrix starting address and the matrix length can be obtained in the corresponding register according to the register number, and then the matrix stored at the corresponding address in the storage medium can be obtained according to the matrix starting address and the matrix length.

[0122] That is, the first operation instruction may include: an operation domain and at least one operation code. Taking the matrix operation instruction as an example, as shown below, register 0, register 1, register stack 2, register 3, and register 4 may be the operation domain. Each register 0, register 1, register 2, register 3, and register 4 is used to identify the number of the register, which may be one or more registers. It should be understood that the number of registers in the operation code is not limited, and each register is used to store the relevant data information of the operation instruction.

[0123]

[0124] like Figure 6B It is a format diagram of an instruction set of another instruction (which may be a first operation instruction, or may also be referred to as an operation instruction) provided by the present application, such as Figure 6BAs shown, the instruction includes at least two operation codes and at least one operation domain, wherein the at least two operation codes include a first operation code and a second operation code (operation code 1 and operation code 2 are shown in the figure). The operation code 1 is used to indicate the type of instruction (i.e., a certain general category of instructions), for example, it can be specifically an IO instruction, a logic instruction, or an operation instruction, etc., and the operation code 2 is used to indicate the function of the instruction (i.e., the interpretation of a specific instruction under a general category of instructions), such as matrix operation instructions in operation instructions (such as matrix multiplication vector instructions MMUL, matrix inversion instructions MINV, etc.), vector operation instructions (such as vector derivative instructions VDIER, etc.), etc., which are not limited in this application.

[0125] It should be understood that the format of the instruction can be customized by the user side or the computing device side. The operation code of the instruction can be designed to be a fixed length, such as 8 bits, 16 bits, etc. Fig. 6A The instruction format shown has the following advantages: the opcode occupies fewer bits and the decoding system is simple to design. Figure 6B The instruction format shown has the following advantages: variable length and higher average decoding efficiency. When there are fewer specific instructions under a certain category of instructions and the calling frequency is high, the length of its second opcode (i.e., opcode 2) is designed to be short, which can improve the decoding efficiency. In addition, it can also enhance the readability and scalability of the instructions and optimize the encoding structure of the instructions.

[0126] In the embodiment of the present application, the instruction set includes operation instructions with different functions, which may be:

[0127] A matrix rank instruction (MRANK), according to which the device fetches matrix data of a set length from a specified address of a memory (preferably a high-speed scratchpad memory or a scalar register file), performs a matrix rank operation in an operation unit, and writes the result back. Preferably, the calculation result is written back to a specified address of the memory (preferably a high-speed scratchpad memory or a scalar register file); it is worth noting that the numerical value can be stored in the memory (preferably a high-speed scratchpad memory or a scalar register file) as a special form of matrix (a matrix with only one row of elements and one column of elements).

[0128] Matrix trace instruction (MTRA), according to which the device fetches matrix data of a set length from a specified address of a memory (preferably a high-speed scratchpad memory or a scalar register file), performs a matrix trace operation in a calculation unit, and writes the result back. Preferably, the calculation result is written back to a specified address of the memory (preferably a high-speed scratchpad memory or a scalar register file); it is worth noting that the numerical value can be stored in the memory (preferably a high-speed scratchpad memory or a scalar register file) as a special form of matrix (a matrix with only one row of elements and one column of elements).

[0129] Matrix determinant instruction (MDET), according to which the device takes out matrix data of a set length from a specified address of a memory (preferably a high-speed scratchpad memory or a scalar register file), performs a matrix determinant operation in an operation unit, and writes the result back. Preferably, the calculation result is written back to a specified address of the memory (preferably a high-speed scratchpad memory or a scalar register file); it is worth noting that the numerical value can be stored in the memory (preferably a high-speed scratchpad memory or a scalar register file) as a special form of matrix (a matrix with only one row of elements and one column of elements).

[0130] Matrix zero element ratio instruction (MNZ), according to which the device takes out matrix data of a set length from a specified address of a memory (preferably a high-speed scratchpad memory or a scalar register file), performs a calculation of the number of zero elements in the matrix in the operation unit, and writes the result back. Preferably, the calculation result is written back to a specified address of the memory (preferably a high-speed scratchpad memory or a scalar register file); it is worth noting that the numerical value can be stored in the memory (preferably a high-speed scratchpad memory or a scalar register file) as a special form of matrix (a matrix with only one row of elements and one column of elements).

[0131] Matrix principal eigenvalue instruction (MEVA), according to which the device takes out matrix data of a set length from a specified address of a memory (preferably a high-speed scratchpad memory or a scalar register file), performs a calculation of the number of zero elements in the matrix in the operation unit, and writes the result back. Preferably, the calculation result is written back to a specified address of the memory (preferably a high-speed scratchpad memory or a scalar register file); it is worth noting that the numerical value can be stored in the memory (preferably a high-speed scratchpad memory or a scalar register file) as a special form of matrix (a matrix with only one row of elements and one column of elements).

[0132] It should be understood that the operation / calculation instructions proposed in this application are mainly used to solve the scalar operations that represent matrix characteristics. Therefore, the operator designed in each pipeline stage includes but is not limited to any one or more of the following combinations: a matrix adder operator, a matrix multiplier operator, a matrix scalar multiplier operator, a nonlinear operator, and a matrix comparison operator.

[0133] The following example illustrates the calculation of the operation instruction (ie, the first operation instruction) involved in the present application.

[0134] Taking the first operation instruction as the matrix determinant instruction MDET as an example, a determinant operation is performed on a given matrix. In a specific implementation, given a square matrix A, the determinant of the matrix A is calculated according to the following formula.

[0135]

[0136] Among them, j 1 ,j 2 ,...j n is any order of 1, 2, .., n. τ(j 1 ,j 2 ,...j n ) is the sequence j 1 ,j 2 ,...j n The reverse number of . is the jth row in the matrix A. n Elements of a column.

[0137] Accordingly, the instruction format of the matrix determinant instruction is as follows:

[0138]

[0139] In combination with the above-mentioned embodiment, the operation unit can obtain the matrix determinant instruction MDET, and after decoding it, use the multiplexer of the first pipeline stage to select the matrix comparison operator to perform sequence inverse number calculation on the matrix to obtain the first result, and then input it into the matrix multiplication operator selected by the multiplexer of the second pipeline stage to perform multiplication operation on all sequences to obtain the second result, and finally input it into the matrix addition operator selected by the multiplexer of the third pipeline stage to perform summation calculation on all sequences to obtain the third result (i.e., output result). Optionally, the third result is stored in a storage medium.

[0140] Taking the first operation instruction as the matrix rank instruction MRANK as an example, the rank of a given matrix is ​​calculated. In specific implementation, a matrix A is given and a rank operation is performed using row elementary transformation.

[0141] Accordingly, the instruction format of the matrix rank instruction MRANK is as follows:

[0142]

[0143] In combination with the above-mentioned embodiment, the operation unit can obtain the matrix rank instruction MRANK, and after decoding it, use the multiplexer of the first pipeline stage to select the matrix adder to perform elementary row transformation on the matrix to obtain the first result, and then input it into the matrix comparison operator selected by the multiplexer of the second pipeline stage to perform statistical calculation of the number of non-zero rows to obtain the second result (i.e., the output result, the rank of the matrix). Optionally, the second result is stored in a storage medium.

[0144] Taking the first operation instruction as the matrix trace instruction MTRA as an example, the trace of a given matrix is ​​calculated. In specific implementation, a matrix A is given, and the trace of the matrix is ​​solved according to the following formula.

[0145]

[0146] Among them, A ii It refers to the element in the i-th row and i-th column of matrix A, where i is a positive integer.

[0147] Accordingly, the instruction format of the matrix trace instruction MTRA is as follows:

[0148]

[0149] In combination with the above-mentioned embodiment, the operation unit can obtain the matrix trace instruction MTRA, and after decoding it, use the multiplexer of the first pipeline stage to select the matrix comparison operator to select the diagonal elements of the matrix to obtain the first result, and then input it into the matrix addition operator selected by the multiplexer in the second pipeline stage to perform the matrix diagonal element summation calculation to obtain the second result (i.e., the output result). Optionally, the second result is stored in a storage medium.

[0150] Taking the first operation instruction as the matrix zero element ratio instruction MNZ as an example, the ratio of zero elements in a given matrix is ​​calculated. In specific implementation, given a matrix A, the number of zero elements in the matrix A is counted according to the following formula and the ratio of zero elements is calculated.

[0151]

[0152] Among them, n ij is the element in the i-th row and j-th column of matrix A, where i and j are both positive integers.

[0153] Accordingly, the instruction format of the matrix zero element ratio instruction MNZ is as follows:

[0154]

[0155]

[0156] In combination with the above-mentioned embodiment, the operation unit can obtain the matrix zero element ratio instruction MNZ, and after decoding it, use the matrix comparison operator selected by the multiplexer in the first pipeline stage to select zero elements of the matrix to obtain a first result, and then input it into the matrix addition operator selected by the multiplexer in the second pipeline stage to perform zero element number statistics to obtain a second result, and then input it into the matrix multiplication operator selected by the multiplexer in the third pipeline stage to calculate the ratio of zero elements in the matrix to obtain a third result (i.e., the output result, the ratio of zero elements in the matrix). Optionally, the third result is stored in a storage medium.

[0157] Taking the first operation instruction as the matrix main eigenvalue instruction MEVA as an example, the main eigenvalue of a given matrix is ​​calculated. In specific implementation, a matrix A is given, and the main eigenvalue of the matrix is ​​calculated according to the following formula.

[0158]

[0159]

[0160] Find the principal eigenvalue:

[0161]

[0162] Among them, a ij is the element in the i-th row and j-th column of matrix A; (CW) i is the i-th component of the matrix product CW.

[0163] Correspondingly, the instruction format of the matrix main eigenvalue instruction MEVA is as follows:

[0164]

[0165] In combination with the above-mentioned embodiment, the operation unit can obtain the matrix main eigenvalue instruction MEVA, and after decoding it, use the matrix adder selected by the multiplexer of the first pipeline stage to perform normalization calculation on the matrix to obtain the first result, and then input it into the matrix adder selected by the multiplexer in the second pipeline stage to perform normalization again to obtain the second result, and then input it into the matrix multiplier selected by the multiplexer in the third pipeline stage to calculate the main eigenvalue to obtain the third result (i.e., the output result). Optionally, the third result is stored in a storage medium.

[0166] It should be noted that the acquisition and decoding of the above-mentioned various operation instructions will be described in detail later. It should be understood that the use of the structure of the above-mentioned computing device to implement the calculation of various operation instructions (such as the matrix rank instruction MRANK, etc.) can obtain the following beneficial effects: the size of the matrix is ​​variable, the number of instructions can be reduced, and the use of instructions can be simplified; matrices of different storage formats (row-major order and column-major order) can be processed, avoiding the cost of transforming the matrix; supporting the matrix format stored at a certain interval, avoiding the execution cost of transforming the matrix storage format and the space occupied by storing intermediate results.

[0167] The set length in the above-mentioned operation instruction (i.e., the matrix operation instruction / first operation instruction) can be set by the user. In an optional implementation scheme, the user can set the set length to a value. Of course, in practical applications, the user can also set the set length to multiple values. The specific implementation mode of the present application does not limit the specific value and number of the set length. In order to make the purpose, technical solution and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0168] See also Figure 7 , Figure 7 Another computing device 50 is provided for a specific embodiment of the present application. Figure 7 As shown, the computing device 50 includes: a storage medium 501, a register unit 502 (preferably a scalar data storage unit, a scalar register unit), an operation unit 503 (also referred to as a matrix operation unit 503) and a control unit 504;

[0169] Storage medium 501, used for storing the matrix;

[0170] A scalar data storage unit 502, used to store scalar data, the scalar data at least including: a storage address of the matrix in the storage medium;

[0171] A control unit 504 is used to control the operation unit to obtain a first operation instruction, where the first operation instruction is used to implement an operation between a matrix and a scalar, and the first operation instruction includes a matrix reading instruction required to execute the instruction;

[0172] The operation unit 503 is used to send a read command to the storage medium according to the matrix read instruction; read the matrix corresponding to the matrix read instruction in a batch read manner, and execute the first operation instruction on the matrix.

[0173] Optionally, the matrix read instruction includes: a storage address of a matrix required by the instruction or an identifier of a matrix required by the instruction.

[0174] Optionally, when the matrix read indication is an identifier of a matrix required for the instruction,

[0175] The control unit 504 is used to control the operation unit to read the storage address corresponding to the identifier from the register unit in a unit reading manner according to the identifier, control the operation unit to send a read command for reading the storage address to the storage medium and obtain the matrix in a batch reading manner.

[0176] Optionally, the operation unit 503 is specifically configured to execute the first operation instruction on the matrix using a multi-stage pipeline calculation method.

[0177] Optionally, each of the multiple pipeline stages includes at least one operator.

[0178] The operation unit 503 is specifically used to calculate the matrix according to the selection of the multi-way selector using the first selection operator in the first pipeline stage to obtain a first result, input the first result to the second selection operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the i-th selection operator in the i-th pipeline stage to perform calculation to obtain the i-th result; input the i-th result to the storage medium for storage; wherein the number i of the multiple pipeline stages is determined according to the calculation topology structure of the first operation instruction, and i is a positive integer.

[0179] Optionally, each pipeline stage in the multi-stage pipeline is configured with a corresponding multiplexer, and the multiplexer is set with an empty option, and the empty option is used to indicate that the k-th pipeline stage connected to the multiplexer and the subsequent k+1 to i-th pipeline stages shall not perform computing operations, where k is a positive integer less than or equal to i.

[0180] Optionally, the operators included in each of the multiple pipeline stages and the number of the operators are custom set by the user side or the computing device side.

[0181] Optionally, each of the multiple pipeline stages includes a preset fixed operator, and the fixed operators in each pipeline stage are different.

[0182] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0183] The computing device controls the matrix computing unit to use the fixed operator in the first pipeline stage to calculate the matrix to obtain a first result, inputs the first result to the fixed operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the fixed operator in the i-th pipeline stage to perform calculation to obtain the i-th result;

[0184] Inputting the i-th result into the storage medium for storage;

[0185] The number i of the multi-stage pipeline stages is determined according to the computational topology of the first operation instruction, and i is a positive integer.

[0186] Optionally, the first operation instruction is a matrix determinant instruction MDET,

[0187] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0188] The computing device controls the matrix operation unit to perform a sequence inversion operation on the matrix according to the selection of the multiplexer using the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result into the second pipeline stage to perform all sequence multiplication operations on the first result using the matrix multiplication operator therein to obtain a second result, inputs the second result into the third pipeline stage to perform all sequence summation operations on the second result using the matrix addition operator therein to obtain a third result; and inputs the third result into the storage medium for storage.

[0189] Optionally, the first operation instruction is a matrix rank instruction MRANK,

[0190] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0191] The computing device controls the matrix operation unit to perform elementary row transformation on the matrix according to the selection of the multiplexer using the matrix adder in the first pipeline stage to obtain a first result, inputs the first result to the matrix comparison operator in the second pipeline stage to count the number of non-zero rows to obtain a second result; and inputs the second result to the storage medium for storage, wherein the second result is the rank of the matrix.

[0192] Optionally, the first operation instruction is a matrix trace instruction MTRA,

[0193] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0194] The computing device controls the matrix operation unit to select the diagonal elements of the matrix according to the selection of the multiplexer, and uses the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result to the matrix addition operator in the second pipeline stage to sum the diagonal elements of the matrix to obtain a second result; and inputs the second result to the storage medium for storage.

[0195] Optionally, the first operation instruction is a matrix zero element ratio instruction MNZ,

[0196] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0197] The computing device controls the matrix operation unit to select zero elements from the matrix according to the selection of the multiplexer using the matrix comparison operator in the first pipeline stage to obtain a first result, inputs the first result into the matrix adder operator in the second pipeline stage to count the number of zero elements in the matrix to obtain a second result, inputs the second result into the matrix multiplication operator in the third pipeline stage to calculate the proportion of zero elements in the matrix to obtain a third result; and inputs the third result into the storage medium for storage.

[0198] Optionally, the first operation instruction is a matrix principal eigenvalue instruction MEVA,

[0199] The computing device controls the matrix operation unit to adopt a multi-stage pipeline calculation method, and executes the first operation instruction on the matrix, including:

[0200] The computing device controls the matrix operation unit to normalize the matrix according to the selection of the multiplexer using the matrix adder in the first pipeline stage to obtain a first result, inputs the first result to the matrix adder in the second pipeline stage to perform normalization again to obtain a second result, inputs the second result to the matrix multiplier in the third pipeline stage to calculate the main eigenvalue to obtain a third result; and inputs the third result to the storage medium for storage.

[0201] Optionally, the computing device further includes:

[0202] A cache unit 505, used for caching operation instructions to be executed;

[0203] The control unit 504 is used to cache the operation instructions to be executed in the cache unit 504 .

[0204] Optionally, the control unit 504 is used to determine whether the first operation instruction is associated with a second operation instruction before the first operation instruction, and if the first operation instruction is associated with the second operation instruction, cache the first operation instruction in the cache unit, and after the second operation instruction is executed, extract the first operation instruction from the cache unit and transmit it to the operation unit;

[0205] The determining whether the first operation instruction has an association relationship with a second operation instruction before the first operation instruction comprises:

[0206] A first storage address interval of a matrix required in the first operation instruction is extracted according to the first operation instruction, and a second storage address interval of a matrix required in the second operation instruction is extracted according to the second operation instruction. If the first storage address interval and the second storage address interval have an overlapping area, it is determined that the first operation instruction and the second operation instruction have an associated relationship. If the first storage address interval and the second storage address interval do not have an overlapping area, it is determined that the first operation instruction and the second operation instruction do not have an associated relationship.

[0207] Optionally, the control unit 503 can be used to obtain arithmetic instructions from the instruction cache unit, and provide the arithmetic instructions to the arithmetic unit after processing. The control unit 503 can be divided into three modules, namely: an instruction fetch module 5031, a decoding module 5032 and an instruction queue module 5033.

[0208] The instruction fetch module 5031 is used to fetch operation instructions from the instruction cache unit;

[0209] A decoding module 5032, used for decoding the acquired operation instruction;

[0210] The instruction queue 5033 is used to sequentially store the decoded operation instructions. Considering that different instructions may have dependencies on the included registers, it is used to cache the decoded instructions and issue the instructions when the dependencies are satisfied.

[0211] See also Figure 8 , Figure 8 is a flow chart of a computing device executing a computing instruction provided by an embodiment of the present application, such as Figure 8 As shown, the hardware structure of the computing device is shown in Figure 7 The structure shown, such as Figure 7 The storage medium shown takes a high-speed temporary storage memory as an example, and the process of executing the matrix trace instruction MTRA includes:

[0212] Step S601: the computing device controls the instruction fetching module to fetch the matrix trace finding instruction, and sends the matrix trace finding instruction to the decoding module.

[0213] Step S602: the decoding module decodes the matrix trace finding instruction and sends the matrix trace finding instruction to the instruction queue.

[0214] Step S603, in the instruction queue, the matrix trace instruction needs to obtain data in the scalar registers corresponding to the three operation fields in the instruction from the scalar register stack, and the data includes the input matrix address, the output vector address and the output vector length.

[0215] Step S604, the control unit determines whether there is an association relationship between the matrix trace instruction and the operation instruction before the matrix trace instruction. If there is an association relationship, the matrix trace instruction is stored in the cache unit. If there is no association management, the matrix trace instruction is transmitted to the operation unit.

[0216] In step S605, the operation unit fetches the required matrix data from the high-speed register according to the data in the scalar register corresponding to the three operation domains, and then completes the trace operation in the operation unit.

[0217] Step S606, after the operation unit completes the operation, the result is written to a specified address of a memory (preferably a high-speed temporary storage memory or a scalar register file), and the matrix trace instruction in the reorder cache is submitted.

[0218] Optionally, in the above step S605, when the operation unit performs the trace operation, the computing device may use a matrix comparison operator to select the matrix diagonal elements, and then use a matrix addition operator to sum the matrix diagonal elements to obtain the trace of the matrix.

[0219] In a specific implementation, after the decoding module decodes the matrix trace instruction, according to the control signal generated by the decoding, the matrix obtained in S603 is input to the matrix comparison operator selected by the first-stage pipeline multiplexer to perform matrix diagonal element calculation to obtain the first result, and then the first result is input to the matrix addition operator selected by the second-stage pipeline multiplexer according to the control signal to perform matrix diagonal element summation calculation to obtain the second result, and the third-stage pipeline multiplexer can know that the stage is an empty option according to the control signal. Accordingly, the second result (i.e., the output result) is directly transmitted to the output end.

[0220] Above Figure 8 The operation instructions in the matrix trace instruction are taken as an example. In practical applications, such as Figure 8 The matrix trace instruction in the illustrated embodiment can be replaced by a matrix operation / manipulation instruction such as a matrix determinant instruction, a matrix rank instruction, a matrix zero element ratio instruction, or a matrix maximum eigenvalue instruction, which are not described in detail here.

[0221] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute any implementation part or all of the steps recorded in the above method embodiment.

[0222] An embodiment of the present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute any implementation part or all of the steps recorded in the above method embodiment.

[0223] An embodiment of the present application also provides an acceleration device, including: a memory: storing executable instructions; a processor: used to execute the executable instructions in the storage unit, and operate according to the embodiments recorded in the above method embodiments when executing the instructions.

[0224] The processor may be a single processing unit, but may also include two or more processing units. In addition, the processor may also include a general-purpose processor (CPU) or a graphics processing unit (GPU); it may also include a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) to set and operate the neural network. The processor may also include on-chip memory for caching purposes (i.e., memory in the processing device).

[0225] In some embodiments, a chip is also disclosed, which includes the neural network processor corresponding to the above-mentioned method embodiment for executing the above-mentioned method embodiment.

[0226] In some embodiments, a chip packaging structure is disclosed, which includes the above-mentioned chip.

[0227] In some embodiments, a board is disclosed, which includes the above chip packaging structure.

[0228] In some embodiments, an electronic device is disclosed, which includes the above-mentioned board.

[0229] Electronic devices include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, household appliances, and / or medical devices.

[0230] The transportation means include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs.

[0231] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0232] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0233] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

[0234] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0235] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software program module.

[0236] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or CD-ROM and other media that can store program codes.

[0237] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (English: Read-Only Memory, abbreviated as: ROM), a random access memory (English: Random Access Memory, abbreviated as: RAM), a magnetic disk or an optical disk, etc.

[0238] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A calculation method, characterized in that: Applied in a computing device, the computing device includes a storage medium, a register unit and a matrix operation unit, and the method includes: The computing device controls the matrix operation unit to obtain a first operation instruction, where the first operation instruction is used to implement an operation between a matrix and a scalar, and the first operation instruction includes a matrix read instruction required to execute the instruction, where the required matrix is ​​at least one matrix, and the at least one matrix is ​​a matrix with the same length or a matrix with different lengths; The computing device controls the matrix operation unit to send a read command to the storage medium according to the matrix read instruction; The computing device controls the matrix operation unit to read the matrix corresponding to the matrix read instruction from the storage medium in a batch reading manner, and executes the first operation instruction on the matrix in a multi-stage pipeline calculation manner; The first operation instruction is: a matrix rank instruction MRANK, and the MRANK includes: TYPE, M, N, A1, LDA, D; wherein the TYPE is the data type involved in the matrix operation, M is the number of rows of the matrix A, N is the number of columns of the matrix A, A1 is the first address of the matrix A, LDA is the low-dimensional length of the matrix A, and D is a scalar; Or the first operation instruction is: a matrix trace instruction MTRA, wherein MTRA includes: TYPE, N, A1, LDA, T; wherein TYPE is the data type involved in the matrix operation, N is the number of rows of the matrix A, A1 is the first address of the matrix A, LDA is the low-dimensional length of the matrix A, and T is a scalar, the trace of the matrix; Or the first operation instruction is: a matrix zero element ratio instruction MNZ, wherein MNZ includes: TYPE, M, N1, A1, LDA, Z; wherein TYPE is the data type involved in the matrix operation, M is the number of rows of matrix A, N1 is the number of columns of matrix A, A1 is the first address of matrix A, LDA is the low-dimensional length of matrix A, and Z is a scalar, the zero element ratio of the matrix; Or the first operation instruction is: matrix main eigenvalue instruction MEVA, and the MEVA includes: TYPE, N, A1, LDA, L; wherein, TYPE is the data type involved in the matrix operation, N is the number of rows of matrix A, A1 is the starting address of matrix A, LDA is the low-dimensional length of matrix A, and L is a scalar, the main eigenvalue of the matrix.

2. The method according to claim 1, characterized in that The first operation instruction includes any one of the following: a matrix rank instruction MRANK, a matrix trace instruction MTRA, a matrix zero element ratio instruction MNZ, and a matrix main eigenvalue instruction MEVA; The instruction format of the first operation instruction includes at least one operation code and at least one operation field, wherein the at least one operation code is used to indicate the function of the first operation instruction, and the at least one operation field is used to indicate data information of the first operation instruction, wherein the data information includes an immediate number or a register number, and is used to store the matrix read indication and the length of the matrix; wherein the at least one operation code includes a first operation code and a second operation code, wherein the first operation code is used to indicate the type of the first operation instruction, and the second operation code is used to indicate the function of the first operation instruction.

3. The method according to claim 1, characterized in that Each of the multiple pipeline stages includes at least one operator. The method of using a multi-stage pipeline to execute the first operation instruction on the matrix includes: The computing device controls the matrix operation unit to calculate the matrix according to the selection of the multiplexer using the first selection operator in the first pipeline stage to obtain a first result, inputs the first result to the second selection operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the i-th selection operator in the i-th pipeline stage to perform calculation to obtain the i-th result; Inputting the i-th result into the storage medium for storage; The i-th result is an output matrix, the number i of the multi-stage pipeline stages is determined according to the computational topology of the first operation instruction, and i is a positive integer.

4. The method according to claim 1, characterized in that Each of the multiple pipeline stages includes a preset fixed operator, and the fixed operators in each pipeline stage are different. The method of using a multi-stage pipeline to execute the first operation instruction on the matrix includes: The computing device controls the matrix computing unit to use the fixed operator in the first pipeline stage to calculate the matrix to obtain a first result, inputs the first result to the fixed operator in the second pipeline stage to perform calculation to obtain a second result, and so on, until the i-1th result is input to the fixed operator in the i-th pipeline stage to perform calculation to obtain the i-th result; Inputting the i-th result into the storage medium for storage; The number i of the multi-stage pipeline stages is determined according to the computational topology of the first operation instruction, and i is a positive integer.

5. The method according to any one of claims 1, 3 and 4, characterized in that: Each of the plurality of pipeline stages is respectively configured with a corresponding multiplexer, and the multiplexer is provided with an empty option, and the empty option is used to indicate that the kth pipeline stage connected to the multiplexer and the subsequent k+1th to ith pipeline stages are not to perform a calculation operation, wherein k is a positive integer less than or equal to i; The operator in each pipeline stage in the multi-stage pipeline stage includes any one or a combination of the following: a matrix addition operator, a matrix multiplication operator, a matrix scalar multiplication operator, a nonlinear operator and a matrix comparison operator.

6. The method according to claim 3, characterized in that If the first operation instruction is: matrix rank instruction MRANK: the execution of the first operation instruction on the matrix specifically includes: the operation unit obtains the matrix rank instruction MRANK, and after decoding it, uses the multiplexer of the first pipeline stage to select the matrix adder to perform elementary row transformation on the matrix to obtain a first result, and then inputs it into the matrix comparison operator selected by the multiplexer of the second pipeline stage to perform statistical calculation of the number of non-zero rows to obtain a second result; If the first operation instruction is: MTRA; the execution of the first operation instruction on the matrix specifically includes: the operation unit obtains the matrix trace instruction MTRA, and after decoding it, uses the multiplexer of the first pipeline stage to select the matrix comparison operator to select the diagonal elements of the matrix to obtain the first result, and then inputs it into the matrix addition operator selected by the multiplexer in the second pipeline stage to perform the matrix diagonal element summation calculation to obtain the second result; If the first operation instruction is: MNZ; the execution of the first operation instruction on the matrix specifically includes: the operation unit obtains MNZ, and after decoding it, uses the matrix comparison operator selected by the multiplexer in the first pipeline stage to select zero elements of the matrix to obtain a first result, and then inputs it into the matrix addition operator selected by the multiplexer in the second pipeline stage to count the number of zero elements to obtain a second result, and then inputs it into the matrix multiplication operator selected by the multiplexer in the third pipeline stage to calculate the proportion of zero elements in the matrix to obtain a third result; If the first operation instruction is: MEVA; the execution of the first operation instruction on the matrix specifically includes: the operation unit obtains MEVA, and after decoding it, uses the matrix adder operator selected by the multiplexer of the first pipeline stage to normalize the matrix to obtain a first result, and then inputs it into the matrix adder operator selected by the multiplexer in the second pipeline stage to normalize it again to obtain a second result, and then inputs it into the matrix multiplier operator selected by the multiplexer in the third pipeline stage to calculate the main eigenvalue to obtain a third result.

7. A computing device, characterized in that: The computing device includes a storage medium, a register unit, a matrix operation unit and a controller unit; The storage medium is used to store the matrix; The register unit is used to store scalar data, and the scalar data at least includes: a storage address of the matrix in the storage medium; The controller unit is used to control the matrix operation unit to obtain a first operation instruction, where the first operation instruction is used to implement an operation between a matrix and a scalar, and the first operation instruction includes a matrix reading instruction required to execute the instruction, where the required matrix is ​​at least one matrix, and the at least one matrix is ​​a matrix with the same length or a matrix with different lengths; The matrix operation unit is used to send a read command to the storage medium according to the matrix read instruction; read the matrix corresponding to the matrix read instruction in a batch read manner, and use a multi-stage pipeline calculation method to execute the first operation instruction on the matrix; The first operation instruction is: a matrix rank instruction MRANK, and the MRANK includes: TYPE, M, N, A1, LDA, D; wherein the TYPE is the data type involved in the matrix operation, M is the number of rows of the matrix A, N is the number of columns of the matrix A, A1 is the first address of the matrix A, LDA is the low-dimensional length of the matrix A, and D is a scalar; Or the first operation instruction is: a matrix trace instruction MTRA, wherein MTRA includes: TYPE, N, A1, LDA, T; wherein TYPE is the data type involved in the matrix operation, N is the number of rows of the matrix A, A1 is the first address of the matrix A, LDA is the low-dimensional length of the matrix A, and T is a scalar, the trace of the matrix; Or the first operation instruction is: a matrix zero element ratio instruction MNZ, wherein MNZ includes: TYPE, M, N1, A1, LDA, Z; wherein TYPE is the data type involved in the matrix operation, M is the number of rows of matrix A, N1 is the number of columns of matrix A, A1 is the first address of matrix A, LDA is the low-dimensional length of matrix A, and Z is a scalar, the zero element ratio of the matrix; Or the first operation instruction is: matrix main eigenvalue instruction MEVA, and the MEVA includes: TYPE, N, A1, LDA, L; wherein, TYPE is the data type involved in the matrix operation, N is the number of rows of matrix A, A1 is the starting address of matrix A, LDA is the low-dimensional length of matrix A, and L is a scalar, the main eigenvalue of the matrix.

8. A chip, characterized in that: The chip comprises the computing device as claimed in claim 7 above.

9. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 8 above.

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