Apparatus and method for filtering a plurality of pulse signals

Abstract

The invention relates to a filter unit for filtering a plurality of pulse signals, the filter unit comprising a plurality of filter circuits connected in parallel. Each filter circuit comprises an input and an output, wherein the input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has a specified filter level and further comprises a pulse level detection circuit configured to detect a state change of a pulse level of the input signal. The state change comprises a transition from a first pulse level to a second pulse level and the output of the filter circuit is activated if the pulse level corresponds to the specified filter level of the filter circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to a filter unit for filtering a plurality of pulsed signals, the filter unit comprising a plurality of filter circuits connected in parallel. BACKGROUND

[0002] It is known that radio frequency (RF) generators can provide power in a variety of applications, including in plasma tools used for manufacturing semiconductors (e.g. deposition of thin films, etching and modification).

[0003] RF generators can also be used in medical devices (e.g. electrosurgical devices and medical imaging machines such as magnetic resonance imaging (MRI) machines), food packaging and commercial surface modification and coating.

[0004] One particularly demanding application is to provide power for generating and controlling plasma processing steps due to the complexity of the plasma constituents (ions, electrons, neutral atoms and reactive species) which are usually confined within a dedicated plasma processing chamber. For example, in a conventional plasma etch, continuous wave RF power (so-called "CW RF power") is delivered to the plasma processing chamber. RF generally refers to frequencies in the range of 20 kHz to 300 GHz, however, more specific frequencies are commonly used in industrial plasma processes, including in particular 2 MHz, 6.78 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, or / and any other suitable frequency or combination of frequencies.

[0005] Irrespective of the frequency employed, one problem with plasma processing using continuous wave RF power is that charge-up damage can occur. Delivering pulsed power instead of continuous wave RF power can prevent charge accumulation and can mitigate charge-up damage effects. Systems for delivering pulsed power signals exist in the prior art.

[0006] However, these systems have various drawbacks and disadvantages. One technical problem area is that the prior art systems do not address the complexity and difficulty in accurately measuring the power delivered by a pulsed signal. This can result in inaccurate repeatability of critical processing steps. For example, due to the filters present in such power generators, the pulse duration of the generated pulses, in particular narrow pulses, is limited. In practice, the filter needs to be built up and activated to allow an accurate power measurement of the desired pulse. The settling time of the filter therefore typically has a negative impact on the pulse duration, as it does not allow a sufficiently accurate measurement within a short pulse. In other words, for the prior art systems, either longer pulses than actually required by the manufacturing process have to be accepted, or typically less accurate measurements, and thus power controlled power, have to be accepted.

[0007] Thus, being able to realize a filter with a faster build-up time will no longer limit the pulse duration, and thus, will allow to provide accurate pulse power in a well-controlled manner, also when very short pulses are provided. Very short pulses are beneficial, especially for powering the most demanding plasma processing tools for manufacturing semiconductors. SUMMARY

[0008] It is an object of the present invention to provide a filter unit and a method that reduce the build-up time of the filter and that provide a better measurement of the pulse characteristics for plasma processing, especially for plasma etching processes.

[0009] According to a first aspect of the present invention, the object is solved by a filter unit for filtering a plurality of pulse signals. The filter unit comprises a plurality of filter circuits connected in parallel to each other. Each filter circuit comprises an input and an output. The input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has a specified filter level and further comprises a pulse level detection circuit configured to detect a state change of a pulse level, wherein the state change comprises a transition from a first pulse level to a second pulse level. The output of said filter circuit is activated if the pulse level corresponds to the specified filter level of the filter circuit.

[0010] Due to the filter being in a steady state, the build-up time of the filter unit can be greatly reduced. Further, this can provide a better and faster measurement of the amplitude of the input signal. The filter unit is beneficial for measuring pulses with a duration shorter than the build-up time of the filter circuits.

[0011] In a first embodiment according to the first aspect of the present invention, the number of filter circuits corresponds to the number of pulse levels of the input signal.

[0012] This allows the overall build-up time of the filter unit to be advantageously adapted to a variation or dynamic use of the necessary pulse levels, for example for diverting pulse energy to the plasma.

[0013] In a second embodiment according to the first aspect of the present invention, the number of filter circuits corresponds to the number of pulse level transitions of the plurality of pulse signals.

[0014] This is beneficial for dynamically reducing the build-up time of the filter unit according to a number of pulse level transitions, for example a transition from a first "non-zero" pulse level to a further "non-zero" pulse level.

[0015] In a third embodiment according to the first aspect of the present invention, the pulse level detection circuit and / or at least one filter circuit comprises a logic gate element.

[0016] This facilitates an increased signal processing speed of the filter circuit to reduce the filter unit's set-up time.

[0017] In a fourth embodiment according to the first aspect of the application, the pulse level detection circuit comprises at least one AND gate arranged to receive at least one pulse level and at least one specified filter level.

[0018] In a fifth embodiment according to the first aspect of the application, the pulse level detection circuit and / or at least one filter circuit is configured as a field programmable gate array (FPGA) or other programmable logic element.

[0019] This facilitates a fast measurement process of the standard pulse.

[0020] In a sixth embodiment according to the first aspect of the application, the pulse level detection circuit is connected to a further input of the filter unit and the further input is arranged to enable the output signal at the output of the filter unit.

[0021] In a seventh embodiment according to the first aspect of the application, the filter unit further comprises a multiplexer connected to the output of the filter circuit.

[0022] By multiplexing the necessary output signals to transfer the pulse energy to the application, e.g. to a plasma processing application, this can reduce the global set-up time of the final output.

[0023] In an eighth embodiment according to the first aspect of the application, the filter unit is connected in series to at least one further filter unit.

[0024] In a ninth embodiment according to the first aspect of the application, the number of filter circuits is 4.

[0025] Such an arrangement is very advantageous when implementing a filter for a dual pulse level RF generator, as it provides a simple filter unit with a limited number of filter circuits, while still providing enough filters for all possible state changes of this particular pulse signal.

[0026] In a tenth embodiment according to the first aspect of the application, the number of filter circuits is 8.

[0027] This arrangement is a particularly good configuration compromise between a moderately complex filter unit and a true multi-level pulse (more than 3 non-zero levels).

[0028] However, it should be understood that the number of filter circuits used in the filter unit of the present invention is not limited per se. Depending on the number of pulse levels and the number of transitions between these pulse levels (often referred to as "state changes"), a device according to the present invention can comprise a plurality (n > 8 or even n > 24) of filter circuits. As an illustrative example, one can envision an advanced RF generator to output RF power with pulses of various amplitudes and various widths, and this requires a filter unit capable of quickly processing a large number of state changes of the RF power signal provided to the plasma process. Such an advanced multi-pulse RF generator has the advantage that the plasma composition can be better controlled compared to a continuous wave RF generator. Basically, it provides more "knobs" to tune the plasma processing tool when energized by such a generator. The filter device of the present invention improves such an advanced generator, benefiting from the ability of narrow pulse durations.

[0029] In an eleventh embodiment according to the first aspect of the present invention, the filter unit further comprises means for storing data into the storage device.

[0030] The storage device advantageously enables a historical storage of data related to the pulse, the pulse level, the activation period or the setup time. The storage device as part of the filter unit can be implemented as a digital device or an analog device.

[0031] In a twelfth embodiment according to the second aspect of the present invention, a filter unit for filtering a plurality of pulse signals comprises means for storing data into a storage device. A filter circuit comprising at least one input and an output, wherein the at least one input is configured to receive an amplitude of an input signal, the output is configured to output signal information to the storage device. The filter circuit has a specified filter value (fvl) at a given time (tl), and further comprises at least one pulse level detection circuit configured to detect a state change of a main pulse level of the input signal. The state change can comprise a transition from a first pulse level to a second pulse level, and if the main pulse level corresponds to the specified filter value (fvl) of the filter circuit, the output and the state of the filter circuit is stored into a memory ml of the storage device. The specified filter value of the filter circuit is changed to a new value (fv2) in order to detect a different state change of the main pulse level at a time t2 later than tl.

[0032] According to a third aspect of the present application, a method of filtering a plurality of pulse signals is provided, wherein the filter unit comprises a plurality of filter circuits connected in parallel. Each filter circuit comprises an input and an output. The input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has a specified filter level and further comprises a pulse level detection circuit. The method comprises the steps of detecting a state change of a pulse level of the input signal and activating the output of the specified filter circuit if the pulse level corresponds to the specified filter level of the filter circuit.

[0033] The settling time of the filter unit can be greatly reduced since the filter is in a stable state. BRIEF DESCRIPTION OF DRAWINGS

[0034] The application will be described below with reference to different exemplary embodiments explained in detail in the following drawings:

[0035] Figure 1 A schematic diagram of an embodiment of a filter unit according to the present application is shown,

[0036] Figure 2 A schematic diagram of another embodiment of a filter unit according to the present application is shown,

[0037] Figure 3 A schematic diagram of another embodiment of a filter unit according to the present application is shown,

[0038] Figure 4 Simulation results of the state of the filter circuits and power measurements of the output signal of an embodiment of a filter unit according to the present application are shown. DETAILED DESCRIPTION

[0039] Figure 1 A schematic diagram of an embodiment of a filter unit 100 according to the present application is shown, which comprises three filter circuits 110, 120, 130 connected in parallel. The concept of a multi-level pulse in a three-level example case is also shown. There is no theoretical limit to the number of levels or filter circuits. Alternatively, a filter unit 100 with 4 or 8 filter circuits or any other number n of filter circuits can also be configured or set.

[0040] Each filter circuit 110, 120, 130 receives three different input signals.

[0041] The first input signal is a latency pulse level signal 1. Signal 1 is based on a pulse set level input signal (not shown in Figure 1 ) which is delayed by an IQ demodulation delay time and a first stage filter delay time (not shown in Figure 1 ).

[0042] The second input signal, the delay setup time pulse level signal 2, is delayed by the setup time of the first stage filter (not shown in the middle). Figure 1

[0043] The third input signal is the first stage level pulse (LP) filtered IQ signal 3, which is based on the input signal (not shown), which is modified by the IQ demodulation filter and the first stage level pulse (LP) filter. This signal is related to the amplitude of the input signal.

[0044] The three input signals represent the input of each filter circuit 110, 120, 130 of the filter unit 100.

[0045] The delayed pulse level signal 1 and the delay setup time pulse level signal 2 are compared with the pulse filter level.

[0046] This comparison is effectively made by the pulse level detection circuit, which is configured to detect a state change of the pulse level of the input signal. The state change comprises a transition from a first pulse level to a second pulse level.

[0047] For example, this state change can be a change from a "pulse on" mode to a "pulse off" mode. Each mode comprises a related pulse level and a related pulse level amplitude. Thus, this change can also be a state change from one "non-zero" pulse level to another "non-zero" pulse level. "Non-zero" is defined by a positive or negative amplitude value of the pulse level, which value is not equal to the zero value.

[0048] Functionally, in case of a new pulse level, the filter unit 100, comprising the filter circuits 110, 120, 130, is disabled for the setup time of the first stage filter. During this setup time, the state of the filter unit 100 and thus of each filter circuit 110, 120, 130 is suspended. The IQ output signals 4, 5, 6 of the filter unit 100 keep their last calculated values, which values are obtained at the end of the last enabled state of the filter circuits 110, 120, 130.

[0049] After the setup time of the first stage filter, the filter unit 100, comprising the filter circuits 110, 120, 130, is enabled. Now, depending on the specific filter characteristics of each filter circuit 110, 120, 130, the values of the IQ output signals 4, 5, 6 are calculated and adjusted.

[0050] The filter characteristics of the filter circuits 110, 120, 130 comprise, for example, the configuration or design of the filter circuits 110, 120, 130 or the configuration or design of the pulse level detection circuits 111, 121, 131.

[0051] ​At least one of the filter circuits 110, 120, 130 and / or the pulse level detection circuit comprises a logic gate element for calculating the IQ output signal 4, 5, 6.

[0052] As an example, each or at least one of the pulse level detection circuits 111, 121, 131 optionally comprises an AND gate arranged to receive at least one pulse level and at least one specified filter level. The specified filter level is one of the filter characteristics.

[0053] Optionally, the pulse level detection circuit and / or at least one filter circuit is configured as a field programmable gate array (FPGA) or other programmable logic element.

[0054] The pulse level detection circuits 111, 121, 131 are connected to a further input of the filter unit 100, and this input is arranged to enable the output signal at the output of the filter unit 100. As Figure 1 shown, this further input is a "filter enable" unit configured to enable the provision of the output signal 4, 5, 6 of the filter unit 100.

[0055] After the setup time has elapsed, and only in case the pulse level is equal to the specified filter level of the pulse level detection circuit 111, 121, 131, the respective filter circuit 110, 120, 130 is enabled to provide one of the IQ output signals 4, 5, 6, the remaining filter circuits 110, 120, 130 will be disabled or in a suspended state.

[0056] In another embodiment, the filter unit 100 for filtering a plurality of pulse signals comprises means for storing data into a storage device (not shown). The filter circuits 110, 120, 130 comprise at least one input and an output. The at least one input is configured to receive the amplitude of the input signal 3, and the output is configured to output signal information to the storage device. The filter circuits 110, 120, 130 have a specified filter value (fvl) at a given time (tl). The filter circuits 110, 120, 130 further comprise at least one pulse level detection circuit 111, 121, 131 arranged to detect a state change of the main pulse level of the input signal. The state change can comprise a transition from a first pulse level to a second pulse level. If the main pulse level corresponds to the specified filter value (fvl) of the filter circuit, the output and state of this filter circuit 110, 120, 130 is stored in a memory ml of the storage device, and the specified filter value of the filter circuit 110, 120, 130 is changed to a new value (fv2) in order to detect a different state change of the main pulse level at a time t2 later than tl.

[0057] In the above embodiment, a method of filtering a plurality of pulse signals is provided. The filter unit 100 comprises a plurality of filter circuits 110, 120, 130 connected in parallel. Each filter circuit 110, 120, 130 comprises an input and an output. The input of the filter unit 100 is configured to receive the amplitude of the input signal 3, and the output is configured to activate the output signals 4, 5, 6, as shown in Figure 1 and Figure 2 Each filter circuit 110, 120, 130 has a specified filter level, for example, as shown in Figure 1 and Figure 2 The levels are level 0 to level 2. Each filter circuit 110, 120, 130 further comprises a pulse level detection circuit 111, 121, 131. The pulse level detection circuit 111, 121, 131 detects a state change of the pulse level of the input signal, and if this pulse level corresponds to the specified filter level of the filter circuit 110, 120, 130, the filter unit 100 activates the output of the specified filter circuit 110, 120, 130.

[0058] Figure 2 Another embodiment of the filter unit 100 according to the present application is schematically shown. The same components and signals depicted in the figures or embodiments contain the same reference signs in order to make it easier to understand.

[0059] As shown in Figure 2 This embodiment of the filter unit 100 also comprises three filter circuits 110, 120, 130, which are connected in parallel as already explained. Figure 1

[0060] In this embodiment, the filter unit 100 further comprises a multiplexer 140 for multiplexing the output signals 4, 5, 6 of the filter unit 100. The multiplexer 140 is configured to receive four input signals. These four signals comprise the IQ output signals 4, 5, 6 and the delayed time pulse level signal 1, which have already been explained in Figure 1

[0061] Figure 2 The concept of multi-level pulses in the case of three levels and multiplexed output is also shown. There is no theoretical limit to the number of levels or filter circuits.

[0062] In Figure 2 The filter circuits 110, 120, 130 and the pulse level detection circuits 111, 121, 131 are designed or configured in the same way as explained in Figure 1 Each function of these circuits is the same, which has already been described according to Figure 1 ​​​

[0063] Functionally, in this embodiment, the filter unit 100 comprising the filter circuits 110, 120, 130 is enabled after a set-up time period passed the first stage filter. Now, the values of the IQ output signals 4, 5, 6 are calculated and adjusted according to the specific filter characteristics of each filter circuit 110, 120, 130.

[0064] Only in case the actually selected pulse level equals the specified filter level of the pulse level detection circuit 111, 121, 131, the respective filter circuit 110, 120, 130 can be enabled to provide one of the IQ output signals 4, 5, 6, the remaining filter circuits will be disabled or in a suspended state.

[0065] The filter characteristics of the filter circuits 110, 120, 130 comprise for example the configuration or design of the filter circuits 110, 120, 130 or the configuration or design of the pulse level detection circuits 111, 121, 131.

[0066] At least one of the filter circuits 110, 120, 130 and / or the pulse level detection circuits comprises logic gate elements for calculating the IQ output signals 4, 5, 6.

[0067] As an example, each or at least one of the pulse level detection circuits 111, 121, 131 optionally comprises an AND gate arranged to receive at least one pulse level and at least one specified filter level. The specified filter level is one of the filter characteristics.

[0068] Optionally, the pulse level detection circuits and / or at least one filter circuit are configured as a field programmable gate array (FPGA) or other programmable logic elements.

[0069] The pulse level detection circuits 111, 121, 131 are connected to a further input of the filter unit 100 and this input is arranged to enable the output signals at the output of the filter unit 100. As Figure 2 shown, this further input is a "filter enable" unit which is configured to enable the provision of the output signals 4, 5, 6 of the filter unit 100.

[0070] Figure 3 Another embodiment of the filter unit 100 according to the present application is depicted. Identical components and signals depicted in the drawings or embodiments contain identical reference numerals in order to facilitate easier understanding.

[0071] In Figure 3 , the filter circuits 110, 120, 130 and the pulse level detection circuits 111, 121, 131 are in a first stage filter. Figure 1 or Figure 2The circuits are designed or configured in the same manner as described herein. The functions of these circuits have been based on… Figure 1 or Figure 2 It has been described.

[0072] Apart from Figure 1 and Figure 2 In addition, Figure 3 In this embodiment, alternatively, the filter unit 100 according to the invention is connected in series with another filter unit. For example... Figure 3 As shown, the additional filter unit is the first-stage level pulse filter unit 150.

[0073] The first input signal to filter unit 150 is a delayed pulse level signal 1. Signal 1 is based on the pulse-set level input signal ( Figure 1 (Not shown in the image), the pulse setting level input signal is delayed by the IQ demodulation delay time and the first-stage filter delay time ( Figure 1 (Not shown in the image).

[0074] The second input signal, namely the delayed setup time pulse level signal 2, is delayed by the setup time of the first-stage filter.

[0075] The third input signal is the IQ signal 3, which is filtered by the first-stage level pulse (LP) filter and is based on the input signal 1. This signal is modified by the IQ demodulation filter and the first-stage level pulse (LP) filter.

[0076] These three input signals represent the inputs of each filter circuit 110, 120, and 130 of the filter unit 100.

[0077] Figure 4 Simulation results are depicted for an example embodiment of a filter unit 100 having three pulse levels and three filter circuits 110, 120, and 130.

[0078] In this example, the pulse width is 8µs. Intermediate curves 44, 45, and 46 illustrate how the pulse levels shown relative to the top curves 40, 41, and 42 (upper part of the figure) activate (“enable”) filter circuits 110, 120, and 130. Each filter circuit 110, 120, and 130 is initialized in the first cycle of its corresponding pulse level. Figure 4 The first cycle corresponds to the initial 24µs.

[0079] Then, the bottom curve (lower part of the figure) shows the power setpoint and the actual power value for each pulse level 40, 41, 42. It can be seen that the actual power value corresponds to the set value and that the delay is reduced to only 0.45 μβ. It can also be seen that during the 3 initialization pulses the delay is about 4 μβ. The reduced time 0.45 μβ corresponds to the system delay (independent of the filter itself), which can be seen when comparing the bottom curve with the top curve, which means that the settling time has effectively been reduced to 0 μβ. In a real situation, instead of this simulated value, the value can be non-zero, but will be small.

[0080] It should be expressly stated that one subject matter of the present application can advantageously be combined with another subject matter of the above-mentioned aspects of the present application and / or with the features shown in the figures, i.e. individually or in any combination.

[0081] List of reference signs

[0082] 1 delay pulse level signal

[0083] 2 delay settling time pulse level signal

[0084] 3 first stage level pulse (LP) filtered IQ signal

[0085] 4 IQ output signal

[0086] 5 IQ output signal

[0087] 6 IQ output signal

[0088] 40 pulse set level

[0089] 41 delay settling time pulse level

[0090] 42 delay pulse level

[0091] 44 pulse curve of filter circuit 0

[0092] 45 pulse curve of filter circuit 1

[0093] 46 pulse curve of filter circuit 2

[0094] 100 filter unit, second stage LP filter

[0095] 110 filter circuit, level filter stage 0

[0096] 111 pulse level detection circuit

[0097] 120 filter circuit, level filter stage 1

[0098] 121 pulse level detection circuit

[0099] 130 filter circuit, level filter stage 2

[0100] 131 pulse level detection circuit

[0101] 140 multiplexer

[0102] 150 further filter unit, first stage LP filter

Claims

1. A filter unit (100) for filtering multiple pulse signals, comprising: A plurality of filter circuits (110, 120, 130) connected in parallel, each of the filter circuits (110, 120, 130) including an input and an output, wherein the input is configured to receive the amplitude of an input signal (3), and the output is configured to activate an output signal (4, 5, 6), characterized in that: Each of the filter circuits (110, 120, 130) has a specified filter level and further includes a pulse level detection circuit (111, 121, 131) configured to detect state changes in the pulse level of the input signal, the state changes including a transition from a first pulse level to a second pulse level. The pulse level detection circuit (111, 121, 131) and / or at least one of the filter circuits (110, 120, 130) are configured as a field-programmable gate array (FPGA) or other programmable logic element. If the pulse level corresponds to the specified filter level of the filter circuit (110, 120, 130), then the output of the filter circuit (110, 120, 130) is activated.

2. The filter unit (100) according to claim 1, characterized in that, The number of filter circuits (110, 120, 130) corresponds to the number of pulse levels of the input signal.

3. The filter unit (100) according to claim 1, characterized in that, The number of filter circuits (110, 120, 130) corresponds to the number of pulse level transitions in the multi-pulse signal.

4. The filter unit (100) according to any one of claims 1-3, characterized in that, The pulse level detection circuit (111, 121, 131) and / or at least one of the filter circuits (110, 120, 130) include logic gate elements.

5. The filter unit (100) according to any one of claims 1-3, characterized in that, The pulse level detection circuit (111, 121, 131) includes at least one AND gate, which is arranged to receive at least one pulse level and at least one specified filter level.

6. The filter unit (100) according to any one of claims 1-3, characterized in that, The pulse level detection circuits (111, 121, 131) are connected to an additional input of the filter unit (100), and the additional input is arranged to enable the output signals (4, 5, 6) at the output of the filter unit (100).

7. The filter unit (100) according to any one of claims 1-3, characterized in that, The filter unit (100) also includes a multiplexer (140) connected to the output of the filter circuits (110, 120, 130).

8. The filter unit (100) according to any one of claims 1-3, characterized in that, The filter unit (100) is connected in series with at least one other filter unit (150).

9. The filter unit (100) according to any one of claims 1-3, characterized in that, The number of filter circuits (110, 120, 130) is 4.

10. The filter unit (100) according to any one of claims 1-3, characterized in that, The number of filter circuits (110, 120, 130) is 8.

11. The filter unit (100) according to any one of claims 1-3, characterized in that, The filter unit (100) also includes means for storing data in a storage device.

12. A filter unit (100) for filtering multiple pulse signals, comprising: A device for storing data to a storage device. Includes at least one input and output filter circuit (110, 120, 130). Wherein, at least one of the inputs is configured to receive the amplitude of an input signal, and the output is configured to output signal information to the storage device, characterized in that: The filter circuits (110, 120, 130) at a given time t1 With specified filter values fv1 It also includes at least one pulse level detection circuit (111, 121, 131), said at least one pulse level detection circuit (111, 121, 131) being arranged to detect state changes in the main pulse level of the input signal, wherein said state changes include a transition from a first pulse level to a second pulse level; and If the main pulse level corresponds to the specified filter value of the filter circuit (110, 120, 130) fv1 The output and state of the filter circuits (110, 120, 130) are then stored in the memory of the storage device. m1 In the process, the specified filter values ​​of the filter circuits (110, 120, 130) are changed to new values. fv2 This allows for the detection of different state changes in the main pulse level at a time t2, which is later than t1.

13. A method for filtering multiple pulse signals. in, The filter unit (100) includes a plurality of filter circuits (110, 120, 130) connected in parallel, each of the filter circuits (110, 120, 130) including an input and an output, wherein the input is configured to receive the amplitude of an input signal, and the output is configured to activate an output signal, each of the filter circuits (110, 120, 130) has a specified filter level, and further includes a pulse level detection circuit (111, 121, 131), characterized in that the method includes the following steps: The pulse level detection circuit (111, 121, 131) and / or at least one of the filtering circuits (110, 120, 130) are configured as field-programmable gate arrays (FPGAs) or other programmable logic elements to detect state changes in the pulse level of the input signal, including transitions from a first pulse level to a second pulse level. If the pulse level corresponds to the specified filter level of the filter circuit (110, 120, 130), then the specified output of the filter circuit (110, 120, 130) is activated.

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