Semiconductor device

Abstract

A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers alternately and repeatedly stacked on a substrate, and a second stack group including second interlayer insulating layers and second gate layers alternately and repeatedly stacked on the first stack group. A separation structure passes through the first stack group and the second stack group, and includes a first separation region and a second separation region. A vertical structure passes through the first stack group and the second stack group, and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and the upper surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0092534, filed on July 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to semiconductor devices having gate layers, vertical structures and discrete structures in multiple stacks, and methods for forming the same. Background Technology

[0004] There is significant interest in increasing the integration level of semiconductor devices to improve the price competitiveness of electronic devices. Semiconductor devices with three-dimensional memory cells have been developed, offering increased integration compared to two-dimensional semiconductor devices. Summary of the Invention

[0005] One aspect of the present invention provides a semiconductor device and a method for forming the same, which improves the integration density of semiconductor devices.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes a first stack group comprising a first interlayer insulating layer and a first gate layer alternately and repeatedly stacked on a substrate. A second stack group comprises a second interlayer insulating layer and a second gate layer alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and are spaced apart from each other in a first direction parallel to the upper surface of the substrate. Each of the separation structures includes a first separation region and a second separation region disposed on the first separation region in a second direction that is the thickness direction of the substrate. A vertical structure passes through the first and second stack groups and is disposed between the separation structures in a first direction. The vertical structure includes a first vertical region and a second vertical region disposed on the first vertical region in the second direction. Conductive lines are electrically connected to the vertical structure on the second stack group. The first vertical region includes a first upper vertical region adjacent to the second vertical region and a first lower vertical region adjacent to the substrate. The second vertical region includes a second lower vertical region and a second upper vertical region. The second lower vertical region is adjacent to the first vertical region, and the width of the second lower vertical region is smaller than the width of the first upper vertical region. The second upper vertical region is adjacent to the conductive line. The first separation region includes a first upper separation region adjacent to the second separation region and a first lower separation region adjacent to the substrate. The second separation region includes a second lower separation region and a second upper separation region. The second lower separation region is adjacent to the first separation region, and the width of the second lower separation region is smaller than the width of the first upper separation region. The second upper separation region is adjacent to the conductive line. The distance between the upper end of the first vertical region and the upper surface of the substrate is greater than the distance between the upper end of the first separation region and the upper surface of the substrate.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate. First gate layers are stacked on the upper surface of the substrate and spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. An interlayer insulating layer is disposed on a first uppermost gate layer located at the uppermost position within the first gate layers. Second gate layers are stacked on the interlayer insulating layer and spaced apart from each other in a vertical direction. A vertical structure extends through the first gate layer, the interlayer insulating layer, and the second gate layer. A separation structure extends through the first gate layer, the interlayer insulating layer, and the second gate layer. The vertical structure has a first curved portion extending from the portion extending through the interlayer insulating layer to the upper surface of the interlayer insulating layer. The separation structure has a second curved portion extending from the portion extending through the interlayer insulating layer to the lower surface of the interlayer insulating layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate. A first stacked assembly includes a first interlayer insulating layer and a first gate layer alternately and repeatedly stacked on the substrate. The first stacked assembly includes a first uppermost interlayer insulating layer disposed at the uppermost position among the first interlayer insulating layers. A second stacked assembly includes a second interlayer insulating layer and a second gate layer alternately and repeatedly stacked on the first stacked assembly. The second stacked assembly includes a second lowermost interlayer insulating layer disposed at the lowermost position among the second interlayer insulating layers. A vertical structure passes through the first stacked assembly and the second stacked assembly in a vertical direction perpendicular to the upper surface of the substrate. A separation structure passes through the first stacked assembly and the second stacked assembly in a vertical direction.

[0009] The vertical structure has a first lower bend adjacent to the first uppermost interlayer insulation layer and a first upper bend adjacent to the second lowermost interlayer insulation layer. The split structure has a second bend adjacent to the first uppermost interlayer insulation layer. The second bend is configured to be lower than each of the first lower bend and the first upper bend.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate. A first stacked assembly includes a first interlayer insulating layer and a first gate layer alternately and repeatedly stacked on the substrate. The first stacked assembly includes a first uppermost interlayer insulating layer disposed at the uppermost position among the first interlayer insulating layers. A second stacked assembly includes a second interlayer insulating layer and a second gate layer alternately and repeatedly stacked on the first stacked assembly. The second stacked assembly includes a second lowermost interlayer insulating layer disposed at the lowermost position among the second interlayer insulating layers. A vertical structure passes through the first stacked assembly and the second stacked assembly in a vertical direction perpendicular to the upper surface of the substrate. The vertical structure has a first vertical region and a second vertical region disposed on the first vertical region. The first vertical region and the second vertical region have first side surfaces aligned with each other in the vertical direction and second side surfaces misaligned with each other in the vertical direction. A separation structure passes through the first stacked assembly and the second stacked assembly in a vertical direction. The vertical structure has a first curved portion on the second side surface. The first curved portion is adjacent to the second lowermost interlayer insulating layer. The separation structure has a second curved portion that is adjacent to the first uppermost interlayer insulation layer and is positioned at a lower level than the first curved portion. Attached Figure Description

[0011] The above and other aspects, features, and advantages of exemplary embodiments of the inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a top view of a semiconductor device according to an exemplary embodiment of the present invention.

[0013] Figure 2A and Figure 2B These are respectively the exemplary embodiments of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines I-I', II-II', III-III', and IV-IV'.

[0014] Figures 2C to 2E These are exemplary embodiments based on the concept of the present invention. Figure 2A Enlarged partial cross-sectional views of parts A-1, A-2, and B.

[0015] Figure 3 and Figure 4 This is a cross-sectional view illustrating an exemplary semiconductor device according to a concept conceived in the present invention.

[0016] Figures 5 to 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0017] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0018] Reference Figure 1 and Figures 2A to 2E A semiconductor device is described in accordance with an exemplary embodiment of the concept of the present invention. Figure 1 This is a top view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 2A These are exemplary embodiments of the present invention, respectively along Figure 1 The cross-sectional view of the semiconductor device taken by lines I-I' and II-II'. Figure 2B These are exemplary embodiments of the present invention, respectively along Figure 1 Cross-sectional views of the semiconductor device taken by lines III-III' and IV-IV'. Figure 2C This is an exemplary embodiment of the concept of the present invention. Figure 2A A magnified view of part A-1. Figure 2D This is an exemplary embodiment of the concept of the present invention. Figure 2A Part A-2 is the larger image. Figure 2E This is an exemplary embodiment of the concept of the present invention. Figure 2A A magnified view of part B.

[0019] Reference Figure 1 and Figures 2A to 2E The semiconductor device 1000 according to an exemplary embodiment of the present invention may include a substrate 10, a horizontal connection pattern 30, a stacked structure GS, a plurality of vertical structures 80 and 80', a plurality of discrete structures 180, and conductive lines 240.

[0020] In an exemplary embodiment, the semiconductor device 1000 may include at least one region selected from a first region R1 and a second region R2 on the substrate 10. For example, the semiconductor device 1000 may include either the first region R1 or the second region R2, or both the first region R1 and the second region R2.

[0021] In an exemplary embodiment, the first region R1 may be a region in which the upper and lower portions of the stacked structure GS are aligned (e.g., aligned in the Z direction), and the second region R2 may be a region in which the upper and lower portions of the stacked structure GS are not aligned (e.g., not aligned in the Z direction). The first vertical structure 80 and the first separation structure 180a may be arranged in the first region R1, and the second vertical structure 80' and the second separation structure 180b may be arranged in the second region R2. For example, as... Figure 1 In the exemplary embodiment shown, four first vertical structures 80 spaced apart in the X and / or Y directions and two first separation structures 180a spaced apart in the Y direction can be arranged in the first region R1, and four second vertical structures 80' spaced apart in the X and / or Y directions and two second separation structures 180b spaced apart in the Y direction can be arranged in the second region R2. However, the exemplary embodiments of the inventive concept are not limited thereto. In the exemplary embodiment, the first vertical structures 80 and the second vertical structures 80' can be arranged to form a grid pattern, or arranged in a zigzag pattern in one direction. A detailed description of the first region R1 and the second region R2 will follow.

[0022] The substrate 10 may have an upper surface 10s extending in the X and Y directions. In an exemplary embodiment, the substrate 10 may include a semiconductor material such as a group IV semiconductor or a group III-V compound semiconductor. For example, a group IV semiconductor may include at least one compound selected from silicon, germanium, and silicon-germanium. The substrate 10 may be configured as a polycrystalline silicon layer or an epitaxial layer. The X and Y directions may be parallel to the upper surface 10s of the substrate 10. The X and Y directions may be perpendicular to each other.

[0023] A stacked structure GS may be disposed on a substrate 10. The stacked structure GS may include a first stack group 100 located on the substrate 10 and a second stack group 200 located on the first stack group 100. The first stack group 100 and the second stack group 200 may be arranged in the Z direction. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the stacked structure GS may include three or more stack groups.

[0024] The stacked structure GS can include alternating and repeatedly stacked interlayer insulating layers and gate layers. For example, as... Figure 2AIn the exemplary embodiment shown, the first stack group 100 may include a first interlayer insulating layer 110 and a first gate layer 120 that are alternately and repeatedly stacked (e.g., stacked in the Z direction), and the second stack group 200 may include a second interlayer insulating layer 210 and a second gate layer 220 that are alternately and repeatedly stacked (e.g., stacked in the Z direction). The first gate layer 120 and the second gate layer 220 may be substantially parallel to the upper surface 10s of the substrate 10. For example, as Figure 2A In the exemplary embodiment shown, the first gate layer 120 and the second gate layer 220 may extend in the Y direction. The first stack assembly 100 may include a first uppermost gate layer 120U disposed at the uppermost position (e.g., in the Z direction) and a first lowermost gate layer 120L disposed at the lowermost position (e.g., in the Z direction) in the first gate layer 120. The first stack assembly 100 may also include a first uppermost interlayer insulating layer 110U disposed at the uppermost position (e.g., in the Z direction) and a first lowermost interlayer insulating layer 110L disposed at the lowermost position (e.g., in the Z direction) in the first interlayer insulating layer 110.

[0025] The second stack assembly 200 may include a second uppermost gate layer 220U disposed at the uppermost position (e.g., in the Z direction) and a second lowermost gate layer 220L disposed at the lowermost position (e.g., in the Z direction) in the second gate layer 220. The second stack assembly 200 may also include a second uppermost interlayer insulating layer 210U disposed at the uppermost position (e.g., in the Z direction) and a second lowermost interlayer insulating layer 210L disposed at the lowermost position (e.g., in the Z direction) in the second interlayer insulating layer 210.

[0026] The semiconductor device 1000 may further include an intermediate interlayer insulating layer 115 disposed between the first stack group 100 and the second stack group 200 (e.g., in the Z direction). The intermediate interlayer insulating layer 115 may be interposed between a first uppermost interlayer insulating layer 110U and a second lowermost interlayer insulating layer 210L, and may be configured to extend in the X and / or Y directions. In an exemplary embodiment, the intermediate interlayer insulating layer 115 may be a layer that distinguishes multiple stacks of a three-dimensional semiconductor device. However, exemplary embodiments of the inventive concept are not limited thereto. Figure 2A In the exemplary embodiment, the bottom surface of the intermediate interlayer insulating layer 115 can contact the top surface of the first uppermost interlayer insulating layer 110U, and the top surface of the intermediate interlayer insulating layer 115 can contact the bottom surface of the second lowermost interlayer insulating layer 210L.

[0027] The first gate layer 120 may be stacked on the substrate 10 and spaced apart from each other in the Z direction. The second gate layer 220 may be stacked on the intermediate interlayer insulating layer 115 and spaced apart from each other in the Z direction. The first gate layer 120 and the second gate layer 220 may be arranged to extend in the Y direction. The Z direction may be a direction perpendicular to the upper surface 10s of the substrate 10 (e.g., the thickness direction of the substrate).

[0028] In an exemplary embodiment, the first gate layer 120 and the second gate layer 220 may include a conductive material layer. For example, the first gate layer 120 and the second gate layer 220 may include a metallic material such as tungsten (W). However, the exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment, the first gate layer 120 and the second gate layer 220 may include a polycrystalline silicon material or a metal silicide material. In an exemplary embodiment, the first gate layer 120 and the second gate layer 220 may also include a diffusion barrier layer. For example, in an exemplary embodiment, the diffusion barrier layer may include at least one material selected from tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), and combinations thereof. In an exemplary embodiment of the present invention, each of the first gate layer 120 and the second gate layer 220 may include a conductive material layer and a dielectric layer covering the upper and lower surfaces of the conductive material layer and extending between the vertical structure 80 and the conductive material layer. In the first gate layer 120 and the second gate layer 220, the portion formed of the conductive material may be a gate electrode. Therefore, the first gate layer 120 and the second gate layer 220 may be referred to as gate electrodes.

[0029] The first interlayer insulating layer 110 may be disposed between the first gate layers 120 (e.g., in the Z direction), and the second interlayer insulating layer 210 may be disposed between the second gate layers 220 (e.g., in the Z direction). The first interlayer insulating layer 110 and the second interlayer insulating layer 210 may be arranged to be spaced apart from each other in the Z direction and extend in the Y direction.

[0030] In an exemplary embodiment, the first interlayer insulating layer 110, the second interlayer insulating layer 210, and the intermediate interlayer insulating layer 115 may comprise an insulating material such as silicon oxide or silicon nitride. However, exemplary embodiments of the present invention are not limited thereto.

[0031] In an exemplary embodiment, the first gate layer 120 may include one or more first lower gate layers and a plurality of first upper gate layers located on the one or more first lower gate layers, and the second gate layer 220 may include a plurality of second lower gate layers and one or more second upper gate layers located on the plurality of second lower gate layers.

[0032] Within the first gate layer 120 and the second gate layer 220, a plurality of first upper gate layers and a plurality of second lower gate layers may include word lines. At least one of the one or more first lower gate layers may be a lower select gate line, and at least one of the one or more second upper gate layers may be an upper select gate line.

[0033] The semiconductor device 1000 according to an exemplary embodiment may further include: an upper interlayer insulating layer 215 disposed on the second stack assembly 200 (e.g., in the Z direction); and a capping layer 232 disposed on the upper interlayer insulating layer 215 (e.g., in the Z direction). Conductive lines 240 may be disposed on the capping layer 232. For example, as Figure 2A In the exemplary embodiment, the bottom surface of the upper interlayer insulating layer 215 can contact the top surface of the second uppermost interlayer insulating layer 210U. The bottom surface of the capping layer 232 can contact the top surface of the upper interlayer insulating layer 215. The bottom surface of the conductive wire 240 can contact the top surface of the capping layer 232.

[0034] The first vertical structure 80 may extend in the Z direction through the first stack group 100, the second stack group 200, and the intermediate interlayer insulating layer 115. In an exemplary embodiment, the first vertical structure 80 may have substantially coplanar upper surfaces (e.g., the upper surfaces of the respective first vertical structures are equidistant from the upper surface of the substrate 10 in the Z direction). In an exemplary embodiment, the first vertical structure 80 may have substantially the same width (e.g., length in the Y direction).

[0035] like Figure 2CIn the exemplary embodiment shown, each of the first vertical structures 80 may include a gap-filling insulating pattern 81, a vertical channel pattern 82 located on the gap-filling insulating pattern 81, a tunneling insulating film 83 located on the vertical channel pattern 82, a charge storage film 84 located on the tunneling insulating film 83, a barrier insulating film 85 located on the charge storage film 84, and a capping pattern 86 covering the upper surface of the gap-filling insulating pattern 81 and connected to the vertical channel pattern 82. The barrier insulating film 85, the charge storage film 84, the tunneling insulating film 83, the vertical channel pattern 82, and the gap-filling insulating pattern 81 may be arranged sequentially toward the interior of the first vertical structure 80 from the sidewalls of the first stack assembly 100 and the second stack assembly 200, as well as the side and bottom surfaces of the substrate 10. For example, the vertical channel pattern 82 can cover the side and bottom surfaces of the gap-filling insulating pattern 81 (e.g., the surfaces of the gap-filling insulating pattern extending in the Z and Y directions, respectively), the tunneling insulating film 83 can cover the side and bottom surfaces of the vertical channel pattern 82, the charge storage film 84 can cover the side and bottom surfaces of the tunneling insulating film 83, and the barrier insulating film 85 can cover the side and bottom surfaces of the charge storage film 84. The vertical channel pattern 82 can be disposed between the gap-filling insulating pattern 81 and the tunneling insulating film 83, the tunneling insulating film 83 can be disposed between the vertical channel pattern 82 and the charge storage film 84, and the charge storage film 84 can be disposed between the tunneling insulating film 83 and the barrier insulating film 85.

[0036] In an exemplary embodiment, the tunneling insulating film 83 of the first vertical structure 80 allows charge to tunnel to the charge storage film 84. In an exemplary embodiment, the tunneling insulating film 83 may include at least one compound selected from silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof. The charge storage film 84 may be a charge trapping layer or a floating gate conductive layer. In an exemplary embodiment, the barrier insulating film 85 may include at least one compound selected from silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k dielectric materials, and combinations thereof.

[0037] In an exemplary embodiment, the charge storage film 84 of the first vertical structure 80 may include a region capable of storing information in a semiconductor device such as a vertical NAND flash memory device. For example, the region of the charge storage film 84 disposed between the gate layer, which can serve as a word line, and the vertical channel pattern 82 within the first gate layer 120 and the second gate layer 220 may be a region capable of storing data in a vertical NAND flash memory device.

[0038] In an exemplary embodiment, the vertical channel pattern 82 of the first vertical structure 80 may be a channel layer or channel region of a vertical NAND flash memory device.

[0039] The semiconductor device 1000 may further include a contact plug 235 disposed on the first vertical structure 80 and passing through the upper interlayer insulating layer 215 to contact the cap pattern 86. The contact plug 235 may be electrically connected to the cap pattern 86 and the conductive line 240. For example, as Figure 2A In the exemplary embodiment shown, the contact plug 235 may extend in the Z direction from the bottom of the conductive line 240 to the top of the cap pattern 86. The conductive line 240 may be electrically connected to the first vertical structure 80 via the contact plug 235.

[0040] The first vertical structures 80a1 and 80b1 in the first region R1 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be described.

[0041] The first vertical structures 80a1 and 80b1 may each include a first vertical region 80V1 and a second vertical region 80V2 located on the first vertical region 80V1. Each of the first vertical region 80V1 and the second vertical region 80V2 may have an inclined side surface whose width (e.g., the length in the Y direction between the opposite sidewalls of the first vertical region 80V1 and the second vertical region 80V2) narrows toward the substrate 10.

[0042] The first vertical region 80V1 may include a first upper vertical region 80u1 adjacent to the second vertical region 80V2 (e.g., adjacent in the Z direction) and a first lower vertical region 80l1 adjacent to the substrate 10 (e.g., adjacent in the Z direction). The width of the first lower vertical region 80l1 is smaller than the width of the first upper vertical region 80u1.

[0043] The second vertical region 80V2 may include: a second lower vertical region 80l2, which is adjacent to the first vertical region 80V1 (e.g., adjacent in the Z direction) and its width is less than the width of the first upper vertical region 80u1; and a second upper vertical region 80u2, which is adjacent to the conductive line 240 (e.g., adjacent in the Z direction) and its width is greater than the width of the second lower vertical region 80l2.

[0044] like Figure 2C In the exemplary embodiment shown, the first vertical structures 80a1 and 80b1 may include a first curved portion b80, which is formed by the width difference between the first upper vertical region 80u1 and the second lower vertical region 80l2. The first curved portion b80 may be inserted between the first stack group 100 and the second stack group 200 (e.g., in the Z direction).

[0045] The first bent portion b80 can be disposed at the same height as the upper surface of the intermediate interlayer insulation layer 115 in the Z direction. The first bent portion b80 can contact the second bottommost interlayer insulation layer 210L. For example, as Figure 2C In the exemplary embodiment, the first curved portion b80 can directly contact the bottom surface of the second lowest interlayer insulation layer 210L.

[0046] The first curved portion b80 can extend from the first vertical structures 80a1 and 80b1 through its portion passing through the intermediate interlayer insulation layer 115 to the upper surface of the intermediate interlayer insulation layer 115.

[0047] The second vertical structures 80a2 and 80b2 in the second region R2 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be described.

[0048] The second vertical structures 80a2 and 80b2 may each include a first vertical region 80V1 and a second vertical region 80V2 located on the first vertical region 80V1. The descriptions of the first vertical region 80V1 and the second vertical region 80V2 may be the same as those described above with reference to the first vertical structures 80a1 and 80b1, and will therefore be omitted.

[0049] The second vertical structures 80a2 and 80b2 may have a structure in which the central portions of the first vertical region 80V1 and the second vertical region 80V2 are not aligned in the Z direction. For example, the second vertical structures 80a2 and 80b2 may have a structure in which the central portion of the second vertical region 80V2 is offset by a predetermined distance (e.g., offset by a predetermined distance in the Y direction) relative to the central portion of the first vertical region 80V1. For example, as Figure 2A and Figure 2B In the exemplary embodiment, the midpoint of the width of the first upper vertical region 80u1 of the second vertical structures 80a2 and 80b2 (e.g., the length between opposite sidewalls in the Y direction) can be offset in the Y direction from the midpoint of the width of the adjacent second lower vertical region 80l2 of the second vertical structures 80a2 and 80b2 (e.g., the length between opposite sidewalls in the Y direction).

[0050] In an exemplary embodiment, since the second vertical structures 80a2 and 80b2 have a structure in which the first vertical region 80V1 and the second vertical region 80V2 are misaligned in the Z direction, the second vertical structures 80a2 and 80b2 may include a first upper curved portion ub80 and a first lower curved portion lb80. The first lower curved portion lb80 is configured such that its height (distance from the substrate 10 in the Z direction) is lower than the height of the first upper curved portion ub80. The first lower curved portion lb80 may be bent from a portion of the first upper vertical region 80u1 in the lateral direction (e.g., the Y direction) and subsequently may be bent in the Z direction.

[0051] Multiple separation structures 180a and 180b may extend in the Z direction through the first stack group 100 and the second stack group 200, the upper interlayer insulation layer 215, and the intermediate interlayer insulation layer 115. The multiple separation structures 180a and 180b may extend upward (e.g., in the Z direction) from portions extending through the second stack group 200 to extend through the upper interlayer insulation layer 215. The multiple separation structures 180a and 180b may have upper surfaces that are substantially coplanar with each other. For example, as... Figure 2A and Figure 2B In the exemplary embodiment shown, the separation structures 180a and 180b may each have an upper surface that terminates at the bottom surface of the capping layer 232 and is coplanar with each other. The plurality of separation structures 180a and 180b may have substantially the same width (e.g., length in the Y direction).

[0052] The multiple separation structures 180a and 180b may include a first separation structure 180a and a second separation structure 180b. The first separation structure 180a may be disposed in a first region R1, and the second separation structure 180b may be disposed in a second region R2.

[0053] The first separation structure 180a in the first region R1 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be described.

[0054] The first separation structure 180a may include a first separation region 180V1 and a second separation region 180V2 located on the first separation region 180V1. For example, as Figure 2A and Figure 2B In the exemplary embodiment shown, the second separation region 180V2 may be directly disposed on the first separation region 180V1 (e.g., in the Z direction). Each of the first separation region 180V1 and the second separation region 180V2 may have an inclined side surface whose width (e.g., the length between opposite sidewalls in the Y direction) narrows toward the substrate 10.

[0055] The first separation region 180V1 may include: a first upper separation region 180u1, which is adjacent to the second separation region 180V2 (e.g., adjacent in the Z direction); and a first lower separation region 180l1, which is adjacent to the substrate 10 (e.g., adjacent in the Z direction), and its width is smaller than the width of the first upper separation region 180u1.

[0056] The second separation region 180V2 may include a second lower separation region 180l2, which is adjacent to the first separation region 180V1 (e.g., adjacent in the Z direction), and its width (e.g., the length between opposite sidewalls in the Y direction) is smaller than the width of the first upper separation region 180u1. The second upper separation region 180u2 is adjacent to the second lower separation region 180l2 (e.g., adjacent in the Z direction), and its width (e.g., the length between opposite sidewalls in the Y direction) is wider than the width of the second lower separation region 180l2.

[0057] The first separation structure 180a may include a second curved portion b180, formed by the width difference between the first upper separation region 180u1 and the second lower separation region 180l2. The width difference between the upper separation region 180u1 and the second lower separation region 180l2 located on the right and left sides (e.g., in the Y direction) may be substantially the same, and the second curved portion b180 located on the left and right sides may be substantially the same. The second curved portion b180 may be inserted between the first stack group 100 and the second stack group 200 (e.g., in the Z direction).

[0058] The second curved portion b180 may be disposed at the same height as the lower surface of the intermediate interlayer insulating layer 115 (e.g., the distance from the substrate 10 in the Z direction). The second curved portion b180 may contact the upper end of the first uppermost interlayer insulating layer 110U.

[0059] The second curved portion b180 can extend from the separation structure 180 through its portion passing through the intermediate interlayer insulation layer 115 to the lower surface of the intermediate interlayer insulation layer 115.

[0060] The second separation structure 180b in the second region R2 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be described.

[0061] The second separation structure 180b may include a first separation region 180V1 and a second separation region 180V2 located on the first separation region 180V1. The descriptions of the first separation region 180V1 and the second separation region 180V2 may be the same as those described above with reference to the first separation structure 180a, and will therefore be omitted.

[0062] The second separation structure 180b may be a structure in which the central portion of the first separation region 180V1 and the central portion of the second separation region 180V2 are not aligned in the Z direction. For example, the second separation structure 180b may have a structure in which the central portion of the second separation region 180V2 is offset from the central portion of the first separation region 180V1 by a predetermined distance in the Y direction. For example, as Figure 2A , Figure 2B and Figure 2D In an exemplary embodiment, the midpoint of the width of the first upper separation region 180u1 of the second separation structure 180b (e.g., the length between opposite sidewalls in the Y direction) can be offset in the Y direction from the midpoint of the width of the adjacent second lower separation region 180l2 of the second separation structure 180b (e.g., the length between opposite sidewalls in the Y direction).

[0063] Reference Figure 2A and Figure 2C The first vertical structures 80a1 and 80b1 and the first separation structure 180a in the first region R1 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be further described.

[0064] The distance (e.g., length in the Z direction) between the upper end of the first vertical region 80V1 (e.g., the top of the first upper vertical region 80u1) and the upper surface 10s of the substrate 10 can be greater than the distance (e.g., length in the Z direction) between the upper end of the first separation region 180V1 (e.g., the top of the first upper separation region 180u1) and the upper surface 10s of the substrate 10. For example, the first vertical region 80V1 of the first vertical structures 80a1 and 80b1 extends in the Z direction above the first separation region 180V1 of the first separation structure 180a.

[0065] In an exemplary embodiment, the distance of the second separation region 180V2 in the vertical direction (e.g., in the Z direction) can be greater than the distance of the second vertical region 80V2 in the vertical direction (e.g., in the Z direction). For example, as Figure 2A In the exemplary embodiment, the second separation region 180V2 can extend in the Z direction from the bottom surface of the intermediate interlayer insulation layer 115 to the bottom surface of the capping layer 232 with a length greater than the length of the second vertical region 80V2 in the Z direction from the upper portion of the intermediate interlayer insulation layer 115 to the bottom surface of the upper interlayer insulation layer.

[0066] The first distance D1 (e.g., the distance in the Z direction) between the upper end of the first curved portion b80 and the top surface of the first uppermost gate layer 120U can be greater than the second distance D2 (e.g., the distance in the Z direction) between the upper end of the second curved portion b180 and the top surface of the first uppermost gate layer 120U.

[0067] The third distance D3 (e.g., the distance in the Z direction) between the upper end of the first curved portion b80 and the bottom surface of the second lowermost gate layer 220L may be shorter than the fourth distance D4 between the upper end of the second curved portion b80 and the bottom surface of the second lowermost gate layer 220L.

[0068] like Figure 2C In the exemplary embodiment shown, the first gap G1 between the upper end of the first curved portion b80 of the first vertical structure 80a and the upper end of the second curved portion b180 of the first separation structure 180a can be substantially equal to the thickness of the interlayer insulating layer 115 (e.g., the distance between the top and bottom surfaces of the interlayer insulating layer 115 in the Z direction). The second curved portion b180 can be disposed below the first curved portion b80 with the first gap G1 (e.g., in the Z direction). The first gap G1 can be configured to prevent the first separation structure 180a from contacting the first vertical structures 80a1 and 80b1. Therefore, defects in the semiconductor device that may be caused by the removal of portions of the barrier insulating film 85, charge storage film 84, tunneling insulating film 83, and vertical channel pattern 82 that may be included in the first vertical structures 80a1 and 80b1 can be prevented.

[0069] For example, in a comparative embodiment where the second curved portion b180 in the first region R1 is disposed above the first curved portion b80, the first upper vertical region 80u1 can be configured to be adjacent to the first upper separating region 180u1 (e.g., adjacent in the Y direction) and thus in contact with the first upper separating region 180u1. However, in an exemplary embodiment of the inventive concept where the second curved portion b180 is disposed below the first curved portion b80, the first upper vertical region 80u1 can be configured to be adjacent to the second lower separating region 180l2 (e.g., adjacent in the Y direction). Because the width of the second lower separating region 180l2 is smaller than the width of the first upper separating region 180u1, it is relatively difficult for the first upper vertical region 80u1 to contact the second lower separating region 180l2.

[0070] like Figure 2CIn the exemplary embodiment, the first uppermost gate layer 120U and the second lowermost gate layer 220L may be spaced apart from each other (e.g., spaced apart in the Z direction) by a second gap G2. The second gap G2 may be the distance in the vertical direction (e.g., the Z direction) between regions where the first vertical structures 80a1 and 80b1 are not subjected to field effects caused by the voltage applied to the first gate layer 120 and the second gate layer 220. In the exemplary embodiment, the second gap G2 may be maintained at a predetermined value. For example, in embodiments where the second gap G2 is greater than the predetermined value, electrons in the vertical channel pattern 82 will not flow smoothly. In embodiments where the second gap G2 is less than the predetermined value, the first curved portion b80 may contact the first gate layer 120, which could lead to a defect in the semiconductor device 1000.

[0071] Therefore, a predetermined value for the second gap G2 can be appropriately maintained, which allows electrons in the vertical channel pattern 82 to flow smoothly and prevents the first curved portion b80 from contacting the first gate layer 120.

[0072] In an exemplary embodiment where the first curved portion b80 is positioned at a height greater than the second curved portion b180 (e.g., the distance from the substrate 10 in the Z direction), the distance between the second vertical region 80V2 and the first separation structure 180a can be relatively large. Therefore, since the first gap G1 is not required to be equal to or greater than a predetermined value, the structure can be controlled to appropriately maintain the second gap G2 to provide a semiconductor device with a higher integration level and improved reliability.

[0073] Reference Figure 2A and Figure 2D The second vertical structures 80a2 and 80b2 and the second separation structure 180b in the second region R2 of the semiconductor device 1000 according to an exemplary embodiment of the present invention will be further described.

[0074] As previously described, the second vertical structures 80a2 and 80b2 may be structures in which the central portions of the first vertical region 80V1 and the central portions of the second vertical region 80V2 are not aligned in the Z direction.

[0075] In an exemplary embodiment, the second vertical structures 80a2 and 80b2 may include a first side surface 80s1 extending from the first lower curved portion 1b80 toward the first stack assembly 100 (e.g., extending in the Z direction) and a second side surface 80s2 extending from the first lower portion 1b80 toward the second stack assembly 200 (e.g., extending in the Z direction). The first lower curved portion 1b80 may extend from the first side surface 80s1 toward the second separation structure 180b to connect to the second side surface 80s2.

[0076] In an exemplary embodiment, the first upper curved portion ub80 can be positioned closer to the second lowermost gate layer 220L (e.g., in the Z direction) than the first lower curved portion lb80. For example, as Figure 2D In the exemplary embodiment, the first upper curved portion ub80 may contact the lower surface of the second lowest interlayer insulation layer 210L and may be disposed at the same height as the upper end of the intermediate interlayer insulation layer 115 in the Z direction. Conversely, the first lower curved portion lb80 may be disposed at a lower height than the upper end of the intermediate interlayer insulation layer 115 in the Z direction. For example, the first lower curved portion lb80 may be disposed on the middle portion of the intermediate interlayer insulation layer 115 (e.g., in the Z direction).

[0077] The first upper curved portion ub80 can be configured to be substantially coplanar with the upper surface of the interlayer insulation layer 115, and the second curved portion b180 can be configured to be substantially coplanar with the lower surface of the interlayer insulation layer 115. Since the first separation region 180V1 and the second separation region 180V2 are not aligned in the second region R2, the difference in width (e.g., in the Y direction) between the first upper separation region 180u1 and the second lower separation region 180l2 on the right and left sides can be different. For example, the second curved portion b180 on the left side can extend further in the Y direction compared to the second curved portion on the right side.

[0078] In an exemplary embodiment, the distance between the first upper curved portion ub80 and the top surface of the first uppermost gate layer 120U (e.g., in the Z direction) may be greater than the distance between the first lower curved portion lb80 and the top surface of the first uppermost gate layer 120U (e.g., in the Z direction). The distance between the upper end of the first vertical region 80V1 and the upper surface 10s of the substrate 10 (e.g., in the Z direction) may be greater than the distance between the lower end of the second vertical region 80V2 and the upper surface 10s of the substrate 10 (e.g., in the Z direction).

[0079] For example, the second curved portion b180 of the second separation structure 180b can be set lower than the first lower curved portion lb80 and the first upper curved portion ub80 of the second vertical structures 80a2 and 80b2, respectively (e.g., in the Z direction). The first lower curved portion lb80 can be positioned higher than the second curved portion b180 in the Z direction. For example, as... Figure 2D In the exemplary embodiment shown, when the fictitious line extends from the first lower curved portion lb80 in the Y direction, the fictitious line can be spaced apart from the second curved portion b180 by a first distance G1a in the Z direction.

[0080] Since the first lower curved portion lb80 is set to be higher than the second curved portion b180 by a first distance G1a in the Z direction, the first lower curved portion lb80 is prevented from contacting the second separation structure 180b.

[0081] Since the semiconductor device 1000 according to the exemplary embodiment of the present invention can sufficiently ensure the first distance G1a in the Z direction between the first lower curved portion lb80 and the second curved portion b180, the second recess RC2 used to form the first lower curved portion lb80 (see Figure 9 The distance can be maintained at a predetermined value, and can prevent the first lower bending portion lb80 from contacting the second separation structure 180b.

[0082] Figure 2E The second vertical region 80V2 of a semiconductor device 1000 according to an exemplary embodiment of the present invention is shown.

[0083] Reference Figure 2A and Figure 2E A horizontal connection pattern 30 may be disposed between the substrate 10 and the first stack group 100 (e.g., in the Z direction). The horizontal connection pattern 30 may include a first horizontal connection pattern 32 and a second horizontal connection pattern 34 disposed on the first horizontal connection pattern 32. The first horizontal connection pattern 32 may be disposed between the substrate 10 and the first stack group 100, and the second horizontal connection pattern 34 may be disposed between the first horizontal connection pattern 32 and the first stack group 100. The first horizontal connection pattern 32 and the second horizontal connection pattern 34 may be arranged to extend parallel to the upper surface 10s of the substrate 10 (e.g., extending in the Y direction).

[0084] In an exemplary embodiment, the first horizontal connection pattern 32 may be formed of silicon. The second horizontal connection pattern 34 may be formed of silicon. The first horizontal connection pattern 32 and the second horizontal connection pattern 34 may be formed of doped polysilicon. For example, the first horizontal connection pattern 32 and the second horizontal connection pattern 34 may be formed of polysilicon having N-type conductivity. In another exemplary embodiment, at least one of the first horizontal connection pattern 32 and the second horizontal connection pattern 34 may include a metal (e.g., W, etc.) or a metal nitride (e.g., WN, TiN, etc.). The first horizontal connection pattern 32 may be in contact with the substrate 10. For example, as Figure 2A In an exemplary embodiment, the bottom surface of the first horizontal connection pattern 32 may be directly disposed on the top surface of the substrate 10 (e.g., in the Z direction).

[0085] Multiple vertical structures 80, 80' can pass through the stacked structure GS and the horizontal connection pattern 30, and can extend into the substrate 10.

[0086] The first horizontal connection pattern 32 may contact the first vertical lower region 80l1 and may extend from the barrier insulating layer 85 toward the gap-filling insulating pattern 81 to contact the vertical channel pattern 82. For example, the first horizontal connection pattern 32 may extend in the Y direction through the barrier insulating layer 85, the charge storage film 84, and the tunneling insulating film 83 to contact the vertical channel pattern 82. The first horizontal connection pattern 32 includes a first extension portion 32e1 that extends in the Z direction from a portion of the contacting vertical channel pattern 82 to a portion between the second horizontal connection pattern 34 and the vertical channel pattern 82. The first horizontal connection pattern 32 also includes a second extension portion 32e2 that extends in the Z direction between the substrate 10 and the vertical channel pattern 82.

[0087] In an exemplary embodiment, the length (e.g., in the Z direction) of each of the first extension portion 32e1 and the second extension portion 32e2 of the first horizontal connecting pattern 32 may be shorter than the thickness of the second horizontal connecting pattern 34 (e.g., the distance in the Z direction between the top and bottom surfaces of the second horizontal connecting pattern 34). For example, as Figure 2E In the exemplary embodiment shown, the first extension portion 32e1 of the first horizontal connecting pattern 32 has a length extending (e.g., extending in the Z direction) to the middle portion of the thickness of the second horizontal connecting pattern 34. The second extension portion 32e2 of the first horizontal connecting pattern 32 has substantially the same length as the first extension portion 32e1.

[0088] Reference Figure 3 A semiconductor device 2000 is described according to a modified exemplary embodiment. Figure 3 They respectively show along Figure 1 A cross-sectional view of the region intercepted by lines I-I' and II-II'. In the following text, the modified elements of the above components will be described primarily, and explanations of other components may be omitted.

[0089] In the second region R2, the second vertical structure 80a2' may include a first vertical region 80V1' and a second vertical region 80V2' located on the first vertical region 80V1'. The central portions of the second vertical region 80V2' and the central portions of the first vertical region 80V1' may be misaligned in the Z direction in a manner different from that of aligning the second separate structure 180b. However, exemplary embodiments of the inventive concept are not limited thereto. Figure 3 In the exemplary embodiment shown, the side surfaces of the first vertical region 80V1' and the second vertical region 80V2' can be substantially coplanar with each other. For example, the right side wall of the first upper vertical portion 80u1' and the right side wall of the second lower vertical portion 80l2' can be aligned and may not form a downwardly curved portion.

[0090] In accordance with the above references Figures 2A to 2E In a similar manner, since the distance between the second vertical structure 80a2' and the upper surface 10s of the substrate 10 is greater than the distance between the second curved portion of the second separation structure 180b and the upper surface 10s of the substrate 10, defects that could be caused by contact between the second vertical structure 80a2 and the second separation structure 180b can be prevented.

[0091] Reference Figure 4 A semiconductor device 3000 according to a modified embodiment is described. Figure 4 These are respectively shown along Figure 1 The cross-sectional view of the region corresponding to the area intercepted by lines I-I' and II-II'. In the following text, the modified elements of the above components will be described primarily, and other components will be directly referenced or their explanations will be omitted.

[0092] In the semiconductor device 3000, the peripheral circuit region may be disposed below the substrate 10 (e.g., in the Z direction).

[0093] The peripheral circuit area may include a substrate 310 and circuit elements 320, circuit contact plugs 340 and circuit wiring 350 disposed on the substrate 310.

[0094] The substrate 310 may have an upper surface extending in both the X and Y directions. In an exemplary embodiment, a discrete element separation layer may be formed in the substrate 310 to define an active region. Source / drain regions 315 containing impurities may be disposed within a portion of the active region. In an exemplary embodiment, the substrate 310 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. However, exemplary embodiments of the inventive concept are not limited thereto.

[0095] Circuit element 320 may include a planar transistor. Each of circuit elements 320 may include a circuit gate dielectric layer 322, a spacer layer 324, and a circuit gate 325. Source / drain regions 315 may be disposed in a substrate 310 on both sides of the circuit gate 325 (e.g., in the Y direction).

[0096] The peripheral insulating layer 330 can be disposed on the circuit elements 320 on the substrate 310. For example, as Figure 4In the exemplary embodiment shown, the bottom surface of the peripheral region insulating layer 330 can be directly disposed on the top surface of the substrate 310 (e.g., in the Z direction). A circuit contact plug 340 can pass through the peripheral region insulating layer 330 to connect to the source / drain region 315. Electrical signals can be applied to the circuit element 320 through the circuit contact plug 340. The circuit contact plug 340 can also be connected to the circuit gate 325. Circuit wiring 350 can be connected to the circuit contact plug 340 and can be arranged in multiple layers.

[0097] Reference Figure 1 and Figures 5 to 14 A method for forming a semiconductor device according to an exemplary embodiment of the present invention is described. Figures 5 to 14 The formation of reference is shown Figure 1 and Figures 2A to 2D An exemplary embodiment of the method for constructing the described semiconductor device 1000.

[0098] Reference Figure 5 A first horizontal insulating layer 22 may be formed on the substrate 10 (e.g., in the Z direction). A first initial horizontal connection pattern 24 may be formed on the first horizontal insulating layer 22 (e.g., in the Z direction). A second horizontal insulating layer 26 may be formed on the first initial horizontal connection pattern 24 (e.g., in the Z direction). A second horizontal connection pattern 34 may be formed on the second horizontal insulating layer 26 (e.g., in the Z direction).

[0099] A first molded structure 101 may be formed on substrate 10. In an exemplary embodiment, substrate 10 may include a semiconductor substrate. Figure 5 As shown in the exemplary embodiment, the first molding structure 101 can be formed directly on the second horizontal connection pattern 34 (e.g., in the Z direction).

[0100] The formation of the first molded structure 101 may include forming a first interlayer insulating layer 110 and a first initial gate layer 130 that are alternately and repeatedly stacked (e.g., stacked in the Z direction) on the substrate 10. In an exemplary embodiment, the first interlayer insulating layer 110 may include an insulating material such as silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0101] In an exemplary embodiment, the first initial gate layer 130 may be made of a different material than the first interlayer insulating layer 110. For example, the first initial gate layer 130 may include silicon nitride.

[0102] In another exemplary embodiment, the first initial gate layer 130 may include polysilicon.

[0103] A first trench T1 may be formed on the substrate 10 to pass through the first molded structure 101 and expose the second horizontal connection pattern 34. The first trench T1 may have a width (e.g., a length in the Y direction) that decreases toward the upper surface 10s of the substrate. Figure 6 In an exemplary embodiment, a first separation separator 151 may be formed on a side surface of the first trench T1 to cover a portion of the exposed upper surface of the second horizontal connection pattern 34. In an exemplary embodiment, the first separation separator 151 may be a removable film in subsequent operations. The first separation separator 151 may include, but is not limited to, silicon nitride.

[0104] Reference Figure 6 A first recess RC1 can be formed extending from the first trench T1 toward the substrate 10 (e.g., extending in the Z direction). For example, the first recess RC1 can pass through the second horizontal connection pattern 34 and the second horizontal insulating layer 26 to contact the first initial horizontal connection pattern 24. Figure 6 In an exemplary embodiment, the first recess RC1 may extend to a position between the upper and lower surfaces of the first initial horizontal connection pattern 24.

[0105] A first sacrificial separation structure 161 can be formed to fill the first trench T1 and the first recess RC1. In an exemplary embodiment, the first sacrificial separation structure 161 may include polysilicon. However, exemplary embodiments of the inventive concept are not limited thereto.

[0106] In an exemplary embodiment, the thickness of the first uppermost interlayer insulating layer disposed at the uppermost position (e.g., the length in the Z direction between the top and bottom surfaces) of the first interlayer insulating layer 110 may be greater than the thickness of each of the remaining first interlayer insulating layers 110.

[0107] In an exemplary embodiment, the upper region of each of the first uppermost interlayer insulating layer, the first separation separator 151, and the first sacrificial separation structure 161 may be removed, for example, by a chemical mechanical polishing operation.

[0108] Reference Figure 7 The upper region of the first sacrificial separation structure 161 can be etched to form the first initial separation structure 162. A capping separation spacer 152 can be formed covering the first initial separation structure 162 (e.g., the top surface of the first initial separation structure). The side surfaces of the capping separation spacer 152 (e.g., the side ends in the Y direction) can contact the first separation spacer 151. In an exemplary embodiment, the capping separation spacer 152 may include silicon nitride. However, exemplary embodiments of the inventive concept are not limited thereto.

[0109] The upper surface of the sealing separation spacer 152 can be substantially coplanar with the upper surface of the first uppermost interlayer insulation layer and the upper surface of the first separation separator 151.

[0110] Reference Figure 8 An intermediate interlayer insulating layer 115 can be formed on the first molded structure 101. For example, such as... Figure 8 In the exemplary embodiment, the bottom of the intermediate interlayer insulation layer 115 can be directly disposed on top of the cap separation spacer 152 and the first uppermost interlayer insulation layer 110. In the exemplary embodiment, the intermediate interlayer insulation layer 115 may include an insulating material such as silicon oxide. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0111] The first vertical aperture may be formed to pass through the intermediate interlayer insulating layer 115, the first molding structure 101, the second horizontal connection pattern 34, the second horizontal insulating layer 26, the first initial horizontal connection pattern 24, and the first horizontal insulating layer 22, and extend below the upper surface 10s of the substrate 10. The first vertical aperture may have a width (e.g., a length in the Y direction) that decreases toward the upper surface 10s of the substrate.

[0112] A first vertical separator 51 may be formed to cover the lower surface and side surfaces of the first vertical hole. In an exemplary embodiment, the first vertical separator 51 may include silicon nitride. However, exemplary embodiments of the present invention are not limited thereto.

[0113] A first initial vertical structure 61 can be formed that fills the first vertical hole and contacts the first vertical separator 51. In an exemplary embodiment, the first initial vertical structure 61 may include polysilicon. However, exemplary embodiments of the inventive concept are not limited thereto.

[0114] The upper surface of the first initial vertical structure 61 can be substantially coplanar with the upper surface of the intermediate interlayer insulation layer 115 and the upper surface of the first vertical separator 51.

[0115] Reference Figure 9 A second molding structure 201 can be formed on the first molding structure 101. An intermediate interlayer insulating layer 115 can be inserted between the first molding structure 101 and the second molding structure 201. The bottom surface of the second molding structure 201 can be directly disposed on the top surface of the intermediate interlayer insulating layer 115.

[0116] The formation of the second molding structure 201 may include forming a second interlayer insulating layer 210 and a second initial gate layer 230 that are alternately and repeatedly stacked (e.g., stacked in the Z direction) on the intermediate interlayer insulating layer 115. In an exemplary embodiment, the second interlayer insulating layer 210 may include an insulating material such as silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0117] In an exemplary embodiment, the second initial gate layer 230 may be made of a different material than the second interlayer insulating layer 210. For example, the second initial gate layer 230 may include silicon nitride.

[0118] In another exemplary embodiment, the second initial gate layer 230 may include polysilicon.

[0119] An initial upper interlayer insulation layer 214 can be formed on the second uppermost interlayer insulation layer 210U, which is located at the uppermost position within the second interlayer insulation layer 210. For example, as... Figure 9 In the exemplary embodiment, the bottom surface of the initial upper interlayer insulating layer 214 can be directly disposed on the top surface of the second uppermost interlayer insulating layer 210U. In the exemplary embodiment, the initial upper interlayer insulating layer 214 may include silicon nitride.

[0120] The second vertical aperture can be formed to pass through the initial upper interlayer insulating layer 214 and the second molded structure 201, and to contact the upper region of the first initial vertical structure 61. The second vertical aperture can have a width (e.g., a length in the Y direction) that decreases toward the upper surface 10s of the substrate. A second vertical separator 52 can be formed covering the side surface of the second vertical aperture.

[0121] A second recess RC2 may be formed extending from the second vertical hole toward the first initial vertical structure 61 to a predetermined depth (e.g., extending in the Z direction). The second recess RC2 may contact the upper region of the first initial vertical structure 61.

[0122] In an exemplary embodiment, since the upper end of the first initial vertical structure 61 can be set higher than the upper end of the first initial separation structure 162 and the upper end of the capping separation spacer 152 (e.g., in the Z direction), the second recess RC2 can be recessed to the desired depth without contacting the first initial separation structure 162, the capping separation spacer 152 and the first initial gate layer 130.

[0123] exist Figure 9 In another exemplary embodiment shown, the second vertical hole and the first vertical hole may be misaligned in the Z direction. Therefore, the lower end of the second vertical hole may partially contact the intermediate interlayer insulating layer 115, and the second recess RC2 may partially contact the intermediate interlayer insulating layer 115.

[0124] Reference Figure 10The first initial vertical structure 61, the first vertical separator 51, and the second vertical separator 52 filling the first vertical hole can be removed, and a first vertical structure 80a1 and a second vertical structure 80a2 can be formed. As previously described, the first vertical structure 80a1 and the second vertical structure 80a2 may include a gap-filling insulating pattern 81, a vertical channel pattern 82 located on the gap-filling insulating pattern 81, a tunneling insulating film 83 located on the vertical channel pattern 82, a charge storage film 84 located on the tunneling insulating film 83, a barrier insulating film 85 located on the charge storage film 84, and a capping pattern 86 covering the upper surface of the gap-filling insulating pattern 81. The barrier insulating film 85, the charge storage film 84, the tunneling insulating film 83, the vertical channel pattern 82, and the gap-filling insulating pattern 81 can be formed sequentially inward from the side surfaces of the vertical structures 80a1 and 80a2.

[0125] The upper surface of the capping pattern 86 and the upper surface of the second uppermost interlayer insulation layer 210, which is located at the uppermost position, can be substantially coplanar with each other.

[0126] The upper interlayer insulation layer 215 can be formed to cover the upper surface of the capping pattern 86 and the upper surface of the second uppermost interlayer insulation layer 210. For example, as Figure 14 In the exemplary embodiment shown, the upper interlayer insulating layer 215 may be directly disposed on the second uppermost interlayer insulating layer 210U and the capping pattern 86 (e.g., in the Z direction). In the exemplary embodiment, the upper interlayer insulating layer 215 may include an insulating material such as silicon oxide. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0127] Reference Figure 11 The second trench can be formed through the upper interlayer insulating layer 215, the second molding structure 201, the intermediate interlayer insulating layer 115, and the capping separation spacer 152. The second trench can have a width (e.g., a length in the Y direction) that decreases toward the upper surface 10s of the substrate. The second separation spacer 153 can be formed to cover the side surface of the second trench.

[0128] The upper region UR of the second trench can expose the first initial separation structure 162. The first initial separation structure 162 can be removed through the upper region UR of the second trench to form the lower region LR of the second trench.

[0129] like Figure 11In the exemplary embodiment shown, after removing the first initial separation structure 162, the second horizontal insulating layer 26, the first initial horizontal connection pattern 24, and the first horizontal insulating layer 22 can be removed to form a horizontal region HR. During the operation of forming the horizontal region HR, portions of the barrier insulating film 85, the charge storage film 84, and the tunneling insulating film 83 of the vertical structures 80a1 and 80a2 can be removed to form a vertical region VR, which includes a portion extending between the second horizontal connection pattern 34 and the vertical channel pattern 82 and a portion extending between the substrate 10 and the vertical channel pattern 82.

[0130] The upper surface 10s of the substrate 10 can be exposed through the horizontal region HR, and the side surface of the vertical trench pattern 82 can be exposed through the vertical region VR.

[0131] Reference Figure 12 This allows the formation of a first horizontal interconnect layer that fills the horizontal region HR and the vertical region VR. The lower surface of the first horizontal interconnect layer can contact the substrate, and the upper surface of the first horizontal interconnect layer can contact the second horizontal interconnect pattern.

[0132] The portion of the first horizontal connection layer exposed by the upper region UR and lower region LR through the second trench can be removed to form the first horizontal connection pattern 32.

[0133] Then, the first separation partition 151 and the second separation partition 153 can be removed.

[0134] Reference Figure 13 The first initial gate layer 130 and the second initial gate layer 230 exposed through the upper region UR and the lower region LR can be removed to form a first void space and a second void space.

[0135] Reference Figure 14 A first gate layer 120 can be formed to fill the first gap space formed by removing the first initial gate layer 130, and a second gate layer 220 can be formed to fill the second gap space formed by removing the second initial gate layer 230. For example, in an exemplary embodiment, the first gate layer 120 and the second gate layer 220 can be formed simultaneously.

[0136] Next refer to Figure 2AThe upper region UR and the lower region LR can be filled to form a separation structure 180. A capping layer 232 can be formed covering the separation structure 180 and the upper surface of the upper interlayer insulation layer 215. A contact plug 235 can be formed to pass through the capping layer 232 and the upper interlayer insulation layer 215 and contact the capping pattern 86 of the vertical structure 80. A conductive wire 240 can be formed to contact the contact plug 235 and disposed on the capping layer 232. In an exemplary embodiment, the conductive wire 240 may include at least one metallic material selected from tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), and combinations thereof. However, exemplary embodiments of the inventive concept are not limited thereto.

[0137] According to exemplary embodiments of the present invention, a method for manufacturing a semiconductor device is provided, wherein trench forming operations for separating a gate layer from a plurality of stacked components of the semiconductor device precede via forming operations. This sequence of operations prevents defects between the separated and vertical structures, even if the distance between the separated structure and the vertical structure may be reduced. Therefore, this method provides a semiconductor device with improved integration and reliability.

[0138] Although exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first stack assembly includes a first interlayer insulating layer and a first gate layer that are alternately and repeatedly stacked on a substrate; The second stack group includes a second interlayer insulating layer and a second gate layer that are alternately and repeatedly stacked on the first stack group; An interlayer insulating layer is disposed on the second stack assembly; A separation structure that passes through the first stack, the second stack and the upper interlayer insulating layer and is spaced apart from each other in a first direction parallel to the upper surface of the substrate, each of the separation structures including a first separation region and a second separation region, the second separation region being disposed on the first separation region in a second direction that is the thickness direction of the substrate; A vertical structure that passes through the first stacked assembly and the second stacked assembly and is disposed between the separation structures in the first direction, the vertical structure including a first vertical region and a second vertical region disposed on the first vertical region in the second direction; as well as Conductive wires, electrically connected to the vertical structures on the second stacked assembly, The first vertical region includes a first upper vertical region adjacent to the second vertical region and a first lower vertical region adjacent to the substrate. The second vertical region includes a second lower vertical region and a second upper vertical region. The second lower vertical region is adjacent to the first vertical region, and the width of the second lower vertical region is smaller than the width of the first upper vertical region. The second upper vertical region is adjacent to the conductive wire. The first separation region includes a first upper separation region adjacent to the second separation region and a first lower separation region adjacent to the substrate. The second separation region includes a second lower separation region and a second upper separation region. The second lower separation region is adjacent to the first separation region, and the width of the second lower separation region is smaller than the width of the first upper separation region. The second upper separation region is adjacent to the conductive line. Wherein, the distance between the upper end of the first vertical region and the upper surface of the substrate is greater than the distance between the upper end of the first separation region and the upper surface of the substrate, and The distance between the upper end of the second separation region and the upper surface of the substrate is greater than the distance between the upper end of the second vertical region and the upper surface of the substrate.

2. The semiconductor device according to claim 1, wherein: The vertical structure includes a first curved portion, which is formed by the difference between the width of the first upper vertical region and the width of the second lower vertical region; and Each of the separation structures includes a second curved portion, which is formed by the difference between the width of the first upper separation region and the width of the second lower separation region.

3. The semiconductor device according to claim 1, wherein: The width of the first lower vertical region is smaller than the width of the first upper vertical region; and The width of the second lower vertical region is smaller than the width of the second upper vertical region.

4. The semiconductor device according to claim 1, wherein: The width of the first lower separation region is smaller than the width of the first upper separation region, and The width of the second lower separation region is smaller than the width of the second upper separation region.

5. The semiconductor device according to claim 1, wherein, Each of the first separation region and the second separation region, as well as each of the first vertical region and the second vertical region, includes an inclined side surface that narrows toward the substrate.

6. The semiconductor device according to claim 1, wherein, The length of the second separation region in the second direction is greater than the length of the second vertical region in the second direction.

7. The semiconductor device according to claim 1, wherein: The first stacked assembly includes a first uppermost gate layer disposed at the uppermost position within the first gate layer, and the second stacked assembly includes a second lowermost gate layer disposed at the lowermost position within the second gate layer. Wherein, the upper end of the first lower vertical region is spaced apart from the first uppermost gate layer by a first distance, and the upper end of the first lower separation region is spaced apart from the first uppermost gate layer by a second distance smaller than the first distance.

8. The semiconductor device according to claim 1, wherein: The vertical structure includes: a gap-filling insulating pattern; a vertical channel pattern covering the side and bottom surfaces of the gap-filling insulating pattern; a tunneling insulating film covering the side and bottom surfaces of the vertical channel pattern; a charge storage film covering the side and bottom surfaces of the tunneling insulating film; and a barrier insulating film covering the side and bottom surfaces of the charge storage film. The barrier insulating film, the charge storage film, the tunneling insulating film, the vertical channel pattern, and the gap-filling insulating pattern are arranged sequentially from the side surface of the vertical structure inward.

9. The semiconductor device according to claim 8, further comprising: A contact plug, located on the vertical structure. The vertical structure further includes a capping pattern that covers the upper portion of the gap-filling insulation pattern and connects to the vertical channel pattern. The capping pattern includes doped polycrystalline silicon, and The contact plug is electrically connected to the cap pattern and the conductive wire.

10. The semiconductor device according to claim 1, wherein, In the second direction, the center portion of the first vertical region is aligned with the center portion of the second vertical region.

11. The semiconductor device according to claim 1, further comprising: A first horizontal connection pattern is disposed between the substrate and the first stacked assembly; as well as A second horizontal connecting pattern is disposed between the first horizontal connecting pattern and the first stacked component group. The first horizontal connection pattern and the second horizontal connection pattern extend parallel to the upper surface of the substrate and contact the vertical structure.

12. The semiconductor device according to claim 11, wherein, The first horizontal connection pattern also includes an extension portion that contacts the first lower vertical region and extends in the second direction.

13. The semiconductor device according to claim 1, further comprising: The peripheral circuit region is disposed beneath the substrate and includes circuit elements.

14. A semiconductor device, comprising: Substrate; A first gate layer is stacked on the upper surface of the substrate and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate; An interlayer insulating layer is disposed within the first gate layer and on the uppermost gate layer at the uppermost position. A second gate layer is stacked on the intermediate interlayer insulating layer and spaced apart from each other in the first direction; An interlayer insulating layer is disposed within the second gate layer and on the uppermost second gate layer at the uppermost position; A vertical structure that passes through the first gate layer, the intermediate interlayer insulating layer, and the second gate layer; as well as A separation structure that passes through the first gate layer, the intermediate interlayer insulating layer, the second gate layer, and the upper interlayer insulating layer. The vertical structure has a first curved portion extending from the portion passing through the interlayer insulation layer to the upper surface of the interlayer insulation layer, and the separating structure has a second curved portion extending from the portion passing through the interlayer insulation layer to the lower surface of the interlayer insulation layer. The distance between the upper end of the separation structure and the upper surface of the substrate is greater than the distance between the upper end of the vertical structure and the upper surface of the substrate.

15. The semiconductor device according to claim 14, wherein: The first curved portion is at the same height as the upper surface of the intermediate interlayer insulation layer; and The second curved portion is positioned at the same height as the lower surface of the intermediate interlayer insulation layer.

16. The semiconductor device according to claim 14, wherein, The first curved portion contacts the second lowest interlayer insulation layer disposed on the top surface of the intermediate interlayer insulation layer.

17. The semiconductor device according to claim 14, wherein, The second curved portion is positioned below the first curved portion with a first gap.

18. A semiconductor device, comprising: Substrate; A first stack assembly includes a first interlayer insulating layer and a first gate layer that are alternately and repeatedly stacked on the substrate, the first stack assembly including a first uppermost interlayer insulating layer disposed at the uppermost position among the first interlayer insulating layers; The second stack assembly includes a second interlayer insulating layer and a second gate layer that are alternately and repeatedly stacked on the first stack assembly, the second stack assembly including a second bottommost interlayer insulating layer disposed at the bottommost position among the second interlayer insulating layers; An interlayer insulating layer is disposed on the second stack assembly; A vertical structure that passes through the first stack and the second stack in a first direction perpendicular to the upper surface of the substrate; as well as A separation structure that passes through the first stack group, the second stack group, and the upper interlayer insulation layer in the first direction. The vertical structure has a first downwardly curved portion adjacent to the first uppermost interlayer insulation layer and a first upwardly curved portion adjacent to the second lowermost interlayer insulation layer. The separation structure has a second curved portion adjacent to the first uppermost interlayer insulating layer. The second curved portion is configured to be lower than each of the first lower curved portion and the first upper curved portion. The distance between the upper end of the separation structure and the upper surface of the substrate is greater than the distance between the upper end of the vertical structure and the upper surface of the substrate.

19. The semiconductor device according to claim 18, wherein: The vertical structure has a first side surface and a second side surface, the first side surface extending in the first direction from the first lower curved portion toward the first stacked assembly, and the second side surface extending in the first direction from the first lower curved portion toward the second stacked assembly. The first downwardly curved portion extends from the first side surface toward the separation structure and connects to the second side surface.

20. The semiconductor device of claim 19, further comprising: An interlayer insulating layer is disposed between the first stacked assembly and the second stacked assembly. The upper surface of the intermediate interlayer insulation layer is substantially coplanar with the first upper curved portion, and the lower surface of the intermediate interlayer insulation layer is substantially coplanar with the second curved portion.

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