Vertical memory device

Abstract

A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction and separating the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a barrier pattern disposed on an upper surface, a lower surface, and sidewalls of each of the gate electrodes, the sidewalls of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0092970, filed on July 31, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Methods and apparatuses consistent with embodiments relate to a vertical memory device. BACKGROUND

[0003] In a method of manufacturing a VNAND flash memory device, a module including an insulating layer and a sacrificial layer can be formed on a substrate, an opening extending through the module can be formed, the sacrificial layer can be removed through the opening to form a gap, and a gate electrode filling the gap can be formed. However, as the number of sacrificial layers included in the module and stacked in a vertical direction increases, the aspect ratio of the module can increase, and thus the module can be tilted after the opening is formed. SUMMARY

[0004] Example embodiments provide a vertical memory device with improved integration.

[0005] According to an example embodiment, a vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including first gate electrodes and second gate electrodes interposed between the first gate electrodes and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrodes in the first direction and separating the first gate electrodes in a second direction substantially parallel to the upper surface of the substrate; and a barrier pattern disposed on an upper surface, a lower surface, and a sidewall of each of the gate electrodes, the sidewall of the gate electrode facing the channel. The insulating isolation pattern directly contacts the first gate electrodes.

[0006] According to an example embodiment, a vertical memory device is provided. The vertical memory device includes: a channel extending on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, the channel including a plurality of portions, each of the plurality of portions of the channel having a width gradually increasing as a distance from the substrate increases, the plurality of portions being sequentially stacked and connected to each other; gate electrodes separated from each other on the substrate in the vertical direction, each of the gate electrodes surrounding the channel in a horizontal direction substantially parallel to the upper surface of the substrate and including a gate conductive pattern and a gate blocking pattern covering upper and lower surfaces and sidewalls of the gate conductive pattern, the sidewalls of the gate conductive pattern facing the channel; and an insulating isolation pattern extending through a first gate electrode and at least one gate electrode interposed between the substrate and the first gate electrode, the insulating isolation pattern separating the first gate electrode in the horizontal direction. The first gate electrode surrounds a first portion of the plurality of portions of the channel, and remaining portions of the plurality of portions of the channel are interposed between the substrate and the first portion. The first portion of the channel has a length in the vertical direction shorter than a length in the vertical direction of each of the remaining portions of the plurality of portions of the channel.

[0007] According to an example embodiment, a vertical memory device is provided. The vertical memory device includes: gate electrodes disposed on a substrate and separated from each other in a first direction substantially perpendicular to an upper surface of the substrate; a plurality of common source lines (CSLs) separated from each other along a second direction substantially parallel to the upper surface of the substrate, each of the plurality of CSLs extending in the first direction through each of the gate electrodes and extending in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction; channels separated from each other along each of the second and third directions between two adjacent CSLs among the plurality of CSLs, each of the channels extending in the first direction through the gate electrodes; a charge storage structure disposed on an outer sidewall of each of the channels, the charge storage structure including a tunnel insulating pattern, a charge storage pattern, and a first blocking pattern sequentially stacked; a pad formed on each of the channels; an insulating isolation pattern extending in the first direction through a first gate electrode among the gate electrodes and directly contacting the first gate electrode among the gate electrodes and extending in the third direction to separate the first gate electrode in the second direction, the first gate electrode serving as a string selection line (SSL) and being formed at an uppermost layer among the gate electrodes; a second blocking pattern covering upper and lower surfaces and sidewalls of each of the gate electrodes, the sidewalls of the gate electrodes facing one of the channels; and a plurality of bit lines separated from each other and electrically connected to the pads, each of the plurality of bit lines extending in the second direction.

[0008] In a method of manufacturing the vertical memory device according to an example embodiment, the first openings can be formed through all layers of the module in a vertical direction substantially perpendicular to the upper surface of the base, a metal can be injected through the first openings to form the gate electrodes, and the second openings extending through at least the uppermost layer of the module in the vertical direction can be formed. Accordingly, the gate electrodes can be formed before the second openings are formed, so that the gate electrodes can be properly formed even when a plurality of second openings are formed between two first openings adjacent to each other. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Figure 2A Figure 2B Figure 3 are plan and sectional views showing a vertical memory device according to an example embodiment.

[0010] Figures 4 to 16 Figure 17A Figure 17B are plan and sectional views showing stages of a method of manufacturing a vertical memory device according to an example embodiment.

[0011] Figure 18A Figure 18B are sectional views showing a vertical memory device according to an example embodiment.

[0012] Figure 19A Figure 19B are sectional views showing a vertical memory device according to an example embodiment.

[0013] Figures 20 to 22 is a plan view showing a vertical memory device according to an example embodiment. DETAILED DESCRIPTION

[0014] A vertical memory device according to an example embodiment and a method of manufacturing the same will be described more fully hereinafter with reference to the accompanying drawings, in which

[0015] It will be understood that when an element or layer is referred to as being "on", "above", "over", "connected to" or "coupled to" another element or layer, it can be directly on, above, over, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly above", "directly over", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] ​​​​​​​For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “over,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another (other) element or feature as shown in the figure. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “under” another element or feature would then be positioned “above” said other element or feature. Thus, the term “below” can cover both above and below orientations. The device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0017] Figure 1 , Figure 2A , Figure 2B and Figure 3 These are plan views and cross-sectional views illustrating a vertical memory device according to an example embodiment. Figure 1 It's a floor plan. Figure 2A It is along Figure 1 The sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 2B yes Figure 2A An enlarged sectional view of region X.

[0018] In the following detailed description (excluding the claims), a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two intersecting directions among the horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. In an example embodiment, the second direction and the third direction may be orthogonal to each other.

[0019] Reference Figures 1 to 3 The vertical memory device may include a gate electrode structure, an insulating pattern structure, a connection pattern 145, a first structure, and an insulating isolation pattern 335, the first structure being formed on a substrate 100 to extend through the gate electrode structure, the insulating pattern structure, and the connection pattern 145. The vertical memory device may also include a first impurity region 102 and a second impurity region 104, a pad 240, a second barrier pattern 285, a second spacer 300, a CSL 310, a contact plug 340, a bit line 360, and a first insulating intermediate layer 250, a second insulating intermediate layer 330, and a third insulating intermediate layer 350.

[0020] The substrate 100 can include silicon, germanium, silicon germanium, or a group III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] The first impurity region 102 can be formed at an upper portion of the substrate 100. The first impurity region 102 can include carbon or an n-type or p-type impurity.

[0022] The gate electrode structure can include a plurality of gate electrodes respectively located at a plurality of layers spaced apart from each other in the first direction. In addition, the gate electrode structure can extend in the third direction, and the plurality of gate electrode structures can be formed in the second direction. That is, each of the plurality of gate electrode structures can extend in the third direction at the same layer, and the plurality of gate electrode structures can be separated in the second direction by the second spacers 300 and the common source lines (CSLs) 310 located in the first openings 260 (see Figure 12 and Figure 13 ) extending in the third direction. Furthermore, the uppermost gate electrode among the gate electrodes of each of the gate electrode structures can be separated from each other by the insulating isolation patterns 335 in the second openings 320 (see Figure 16 and Figure 17A and Figure 17B ) extending in the third direction.

[0023] In an example embodiment, the CSLs 310 extending in the third direction can be formed in the first openings 260, and a plurality of CSLs 310 can be formed along the second direction. The second spacers 300 can be formed on each of opposite sidewalls of the CSLs 310 in the second direction. The second impurity region 104 can be formed at an upper portion of the substrate 100 adjacent to a lower surface of the CSLs 310.

[0024] The insulating isolation patterns 335 extending in the third direction can be formed in the second openings 320 and can be in contact with a lower surface of the second insulating intermediate layer 330. The insulating isolation patterns 335 can be integrally formed with the second insulating intermediate layer 330, and thus can be seen to protrude from the second insulating intermediate layer 330 in the first direction. In an example embodiment, a plurality of insulating isolation patterns 335 can be formed to be separated from each other in the second direction between two CSLs 310 adjacent to each other in the second direction. Figure 1 Two insulating isolation patterns 335 formed between two adjacent CSLs 310 are described, however, embodiments are not limited thereto.

[0025] The CSL 310 can include a metal, a metal nitride, and / or a metal silicide, the second spacer 300 can include an oxide such as silicon oxide, and the second impurity region 104 can include an n-type impurity such as phosphorus, arsenic, or the like.

[0026] Each of the gate electrode structures can include at least one third gate electrode 296, a plurality of second gate electrodes 294, and at least one first gate electrode 292 sequentially stacked in the first direction.

[0027] In an example embodiment, the third gate electrode 296 can function as a ground select line (GSL), each of the second gate electrodes 294 can function as a word line, and the first gate electrode 292 can function as a string select line (SSL).

[0028] Figure 2A It is shown that the third gate electrode 296 is formed at one layer, the second gate electrodes 294 are respectively formed at nine layers, and the first gate electrodes 292 are respectively formed at two layers, however, embodiments are not limited thereto. That is, each of the first gate electrodes 292 and the third gate electrode 296 can be formed at one or more layers, and the second gate electrodes 294 can be formed at a plurality of layers. Specifically, the second gate electrodes 294 can be formed at at least nine layers, and some of the second gate electrodes 294 adjacent to the first gate electrodes 292 and / or the third gate electrode 296 can function as dummy word lines.

[0029] Each of the first gate electrodes 292, the second gate electrodes 294, and the third gate electrode 296 can include a gate conductive pattern extending in the second direction and a gate blocking pattern covering a portion of upper and lower surfaces and side walls of the gate conductive pattern. The gate conductive pattern can include a low-resistance metal such as tungsten, titanium, tantalum, platinum, or the like, and the gate blocking pattern can include a metal nitride such as titanium nitride, tantalum nitride, or the like.

[0030] In an example embodiment, the insulating isolation pattern 335 can extend through the first gate electrode 292 formed at or below at least one layer of the uppermost layer among the gate electrodes, and thus can directly contact side walls of each of the first gate conductive pattern 292a and the first gate blocking pattern 292b of the first gate electrode 292. Accordingly, each of the first gate conductive pattern 292a and the first gate blocking pattern 292b of the first gate electrode 292 can surround the insulating isolation pattern 335.

[0031] The insulating pattern structure can include a plurality of insulating patterns 115 stacked at a plurality of layers in the first direction, respectively. Each of the insulating patterns 115 can be formed between the upper surface of the first impurity region 102 at the upper portion of the substrate 100 and the third gate electrode 296, between the first gate electrode 292, the second gate electrode 294, and the third gate electrode 296 among the gate electrodes adjacent in the first direction, and on the first gate electrode 292.

[0032] In an example embodiment, each of the insulating patterns 115 at the respective plurality of layers can extend in the third direction, the plurality of insulating patterns 115 can be separated from each other in the second direction by the first openings 260, the insulating patterns 115 formed between the first gate electrodes 292 and on and under the first gate electrodes 292 can be separated from each other in the second direction by the second openings 320. The insulating patterns 115 can include an oxide such as silicon oxide.

[0033] In an example embodiment, the connection patterns 145 can be formed between two insulating patterns 115 in the middle layer, respectively. The connection patterns 145 can include a material having a low gap fill characteristic or a low step coverage characteristic, for example, tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxide, etc.

[0034] The first structure can extend through the gate electrode structure, the connection patterns 145, and the insulating pattern structure in the first direction on the first impurity region 102, and the pad 240 can be formed on the first structure. The first structure can include a channel 225 extending in the first direction from the upper surface of the first impurity region 102, a charge storage structure 210 covering the outer sidewall of the channel 225, and a fill pattern 230 filling an inner space defined by the channel 225.

[0035] Since the first structure extends through the gate electrode structure, each of the first gate electrode 292, the second gate electrode 294, and the third gate electrode 296 of the gate electrode structure can surround the channel 225 and the charge storage structure 210 of the first structure.

[0036] In an example embodiment, the channel 225 can have a hollow cylindrical shape or a cup shape, and the fill pattern 230 can fill the inner space formed by the channel 225. That is, the lower surface and the sidewall of the fill pattern 230 can be covered by the channel 225.

[0037] The channel 225 can include, for example, crystalline silicon, and the fill pattern 230 can include an oxide such as silicon oxide.

[0038] In an example embodiment, a plurality of trenches 225 can be formed to be spaced apart from each other along each of the second direction and the third direction between two CSLs 310 adjacent to each other in the second direction. The trenches 225 arranged in the third direction can collectively form a trench column, a plurality of trench columns can be formed to be spaced apart from each other along the second direction, and the plurality of trench columns can collectively form a trench block. In one embodiment, a trench block including at least 14 trench columns can be formed between two CSLs 310 adjacent to each other in the second direction.

[0039] In an example embodiment, the charge storage structure 210 covering the outer sidewall of the trench 225 can have a cup shape in which a central bottom is opened. The charge storage structure 210 can include the tunnel insulating pattern 200, the charge storage pattern 190, and the first blocking pattern 180 sequentially stacked in a horizontal direction from the outer sidewall of the trench 225.

[0040] The tunnel insulating pattern 200 and the first blocking pattern 180 can include an oxide such as silicon oxide, and the charge storage pattern 190 can include a nitride such as silicon nitride. The pad 240 can include crystalline silicon doped with an impurity, for example.

[0041] In an example embodiment, the trench 225 can include a third portion, a second portion, and a first portion sequentially stacked to contact each other in the first direction, and each of the first portion to the third portion of the trench 225 can have a sidewall inclined to the upper surface of the substrate 100. The first portion of the trench 225 can be formed at an upper portion of the trench 225 to have a length shorter than the second portion and the third portion in the first direction. In one embodiment, each of the first portion to the third portion of the trench 225 can have a width gradually increasing from a bottom to a top.

[0042] The contact plug 340 can be formed on the upper surface of the pad 240, and the bit line 360 can be formed on the upper surface of the contact plug 340. The contact plug 340 can extend through the first insulating interlayer 250 and the second insulating interlayer 330 to contact the upper surface of the pad 240, and the bit line 360 can extend through the third insulating interlayer 350 to contact the upper surface of the contact plug 340.

[0043] The contact plug 340 and the bit line 360 can include a metal such as copper, aluminum, tungsten, titanium, tantalum, etc., and / or a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., and the first insulating interlayer 250, the second insulating interlayer 330, and the third insulating interlayer 350 can include an oxide such as silicon oxide.

[0044] The second barrier pattern 285 can be formed on the upper surface of each of the gate electrodes and a portion of the side walls and the side walls of each of the insulating patterns 115, and can include a metal oxide. However, the second barrier pattern 285 can not be formed on the side walls of the insulating isolation pattern 335 facing the first gate electrode 292 among the gate electrodes. Accordingly, the insulating isolation pattern 335 can directly contact the side walls of the first gate conductive pattern 292a and the first gate barrier pattern 292b of the first gate electrode 292 and the side walls of the second barrier pattern 285. The second barrier pattern 285 can also contact the side walls of the charge storage structure 210.

[0045] In the vertical memory device, a channel block including a plurality of channels 225 extending through the gate electrode structures formed between two CSLs 310 adjacent to each other in the second direction can be formed, and the channel block can include at least 14 channel columns including a plurality of channels 225 disposed in the third direction and arranged in the second direction. In the method of manufacturing the vertical memory device described later, since the plurality of channels 225 are formed to support the module structure to prevent tilting and extend through the gate electrode structures, the vertical memory device can have a stable structure that does not tilt.

[0046] Since the plurality of channel columns are formed between two CSLs 310 adjacent to each other in the second direction, a plurality of insulating isolation patterns 335 separated by the first gate electrodes 292 serving as SSLs can also be formed between two CSLs 310 adjacent to each other in the second direction. However, as will be described later, the insulating isolation patterns 335 are formed after the first gate electrodes 292 are formed. This avoids the case where the gap 270 (see Figure 13 ) is partially blocked by the insulating isolation patterns 335 if the insulating isolation patterns 335 are formed before the first gate electrodes 292 are formed.

[0047] The insulating isolation patterns 335 can extend through the upper portions of the channels 225 included in some of the channel columns, and the channels 225 through the upper portions of which the insulating isolation patterns 335 penetrate can serve only as dummy channels. Accordingly, for example, when a channel block includes 14 channel columns arranged in the second direction and two insulating isolation patterns 335 are formed, 12 channel columns can include channels and two channel columns can include dummy channels. However, in the example embodiment described later, the insulating isolation patterns 335 can also be formed between the channels 225 without extending through the upper portions of the channels 225.

[0048] Figures 4 to 16 、 Figure 17A and Figure 17B are plan views and sectional views showing stages of a method of manufacturing a vertical memory device according to an example embodiment. Specifically, Figure 5 、 Figure 12 andFigure 16 is a plan view, Figure 4 , Figures 6 to 11 and Figure 17A are cross-sectional views taken along lines A-A' of the respective plan views, Figures 13 to 15 are cross-sectional views taken along lines B-B' of the respective plan views. Figure 17B is Figure 17A an enlarged cross-sectional view of a region X of

[0049] Referring to Figure 4 , after forming the first impurity region 102 on the upper portion of the substrate 100, the insulating layers 110 and the first sacrificial layers 120 can be alternately and repeatedly stacked on the first impurity region 102 in the first direction to form a first module.

[0050] The first impurity region 102 can be formed by doping carbon or an n-type or p-type impurity on the upper portion of the substrate 100.

[0051] Figure 4 It is shown that the first module includes the insulating layers 110 and the first sacrificial layers 120 stacked at seven layers and six layers, respectively, however, embodiments are not limited thereto. That is, the first module can include more or less of the insulating layers 110 and the first sacrificial layers 120.

[0052] The insulating layers 110 and the first sacrificial layers 120 can be formed by, for example, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or the like. The insulating layers 110 can include an oxide such as silicon oxide, and the first sacrificial layers 120 can include a nitride such as silicon nitride.

[0053] Referring to Figure 5 and Figure 6 , a first channel hole 130 extending through the first module and exposing the first impurity region 102 on the upper portion of the substrate 100 can be formed.

[0054] Specifically, a first photoresist pattern can be formed on the uppermost insulating layer 110 among the insulating layers 110 of the first module, and the insulating layers 110 and the first sacrificial layers 120 of the first module can be etched using the first photoresist pattern as an etching mask to form the first channel hole 130 exposing the upper surface of the first impurity region 102. In an example embodiment, a plurality of first channel holes 130 can be formed in each of the second direction and the third direction.

[0055] In an example embodiment, the first impurity region 102 can be used as an etching stopper in an etching process for forming the first trench holes 130. That is, by doping an impurity on an upper portion of the substrate 100 including, for example, silicon, etching selectivity of the insulating layers 110 and the first sacrificial layers 120 including, for example, silicon oxide and silicon nitride, respectively, can be increased. Accordingly, the first trench holes 130 can be formed to have a uniform depth in the etching process.

[0056] However, in some cases, the process of forming the first impurity region 102 can be omitted.

[0057] In an example embodiment, a width of each of the first trench holes 130 can gradually decrease as a depth of each of the first trench holes 130 increases. That is, a sidewall of each of the first trench holes 130 can be inclined to an upper surface of the substrate 100. Accordingly, an upper portion of each of the first trench holes 130 can have a greater width than a lower portion of each of the first trench holes 130.

[0058] Referring to Figure 7 After the connection layer 140 is formed on the uppermost insulating layer 110 among the insulating layers 110 of the first module, an upper portion of the connection layer 140 can be planarized, and the insulating layers 110 and the first sacrificial layers 120 can be alternately and repeatedly formed again on the connection layer 140 to form a second module.

[0059] Figure 7 It is shown that the second module includes the insulating layers 110 and the first sacrificial layers 120 stacked at five layers and four layers, respectively, however, embodiments are not limited thereto. That is, the second module can include more or less of the insulating layers 110 and the first sacrificial layers 120.

[0060] In an example embodiment, the connection layer 140 can include a material having a low gap fill property or a low step coverage property, for example, tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxide, or the like. Accordingly, the first trench holes 130 can not be filled with the connection layer 140.

[0061] Figure 7 It is shown that the connection layer 140 has a flat lower surface, however, embodiments are not limited thereto. That is, a portion of the connection layer 140 facing the upper portion of each of the first trench holes 130 can also be formed, and thus, the connection layer 140 can also have a non-flat lower surface.

[0062] Referring to Figure 8 A second trench hole 150 extending through the second module and the connection layer 140 to expose the first trench holes 130 can be formed.

[0063] Specifically, a second photoresist pattern can be formed on the uppermost insulating layer 110 among the insulating layers 110 of the second module, the insulating layers 110 and the first sacrificial layers 120 and the connection layers 140 of the second module can be etched using the second photoresist pattern as an etching mask to form second channel holes 150 that expose the first channel holes 130. Since a plurality of first channel holes 130 are formed in each of the second direction and the third direction, a plurality of second channel holes 150 can also be formed in each of the second direction and the third direction.

[0064] Like the first channel holes 130, the width of each of the second channel holes 150 can also gradually decrease as the depth of each of the second channel holes 150 increases, and the sidewall of each of the second channel holes 150 can also be inclined to the upper surface of the substrate 100. Accordingly, the top of each of the second channel holes 150 can have a greater width than the bottom of each of the second channel holes 150.

[0065] Referring to Figure 9 A process similar to the process described in Figure 7 and Figure 8 may be performed.

[0066] Specifically, after the connection layers 140 are formed on the uppermost insulating layer 110 among the insulating layers 110 of the second module, the upper portion of the connection layers 140 can be planarized, and the insulating layers 110 and the first sacrificial layers 120 can be formed again alternately and repeatedly on the connection layers 140 to form a third module. Then, a third photoresist pattern can be formed on the uppermost insulating layer 110 among the insulating layers 110 of the third module, and the insulating layers 110 and the first sacrificial layers 120 and the connection layers 140 of the third module can be etched using the third photoresist pattern as an etching mask to form third channel holes 160 that expose the second channel holes 150. Since a plurality of second channel holes 150 are formed in each of the second direction and the third direction, a plurality of third channel holes 160 can also be formed in each of the second direction and the third direction.

[0067] Figure 9 It is shown that the third module includes the insulating layers 110 and the first sacrificial layers 120 stacked at three layers and two layers, respectively, however, embodiments are not limited thereto. That is, the third module can include more or less of the insulating layers 110 and the first sacrificial layers 120.

[0068] Like the first and second channel holes 130 and 150, the width of each of the third channel holes 160 can also gradually decrease as the depth of each of the third channel holes 160 increases, and the sidewall of each of the third channel holes 160 can be inclined to the upper surface of the substrate 100. Accordingly, the top of each of the third channel holes 160 can have a greater width than the bottom of each of the third channel holes 160.

[0069] Each of the first, second, and third channel hole structures 130, 150, and 160 can form a channel hole structure 170. In addition, the first to third modules sequentially stacked on the substrate 100 can be collectively referred to as a module structure. In an example embodiment, the channel hole structure 170 can extend in the first direction through the module structure.

[0070] Referring to Figure 10 A charge storage structure 210 can be formed on the sidewall of the channel hole structure 170 and a portion of the exposed upper surface of the first impurity region 102, and a channel layer 220 can be formed on the charge storage structure 210, the portion of the exposed upper surface of the first impurity region 102, and the uppermost insulating layer 110 of the insulating layers 110 of the module structure.

[0071] Specifically, a charge storage structure layer and a second sacrificial layer can be sequentially formed on the sidewall of the channel hole structure 170, the exposed upper surface of the first impurity region 102, and the upper surface of the uppermost insulating layer 110 of the insulating layers 110 of the module structure. A first spacer layer can be formed on the second sacrificial layer, and the first spacer layer can be anisotropically etched to form first spacers only on the sidewall of the channel hole structure 170. The second sacrificial layer can include, for example, polysilicon, and the first spacers can include, for example, silicon oxide or silicon nitride.

[0072] The second sacrificial layer and the charge storage structure layer can be etched using the first spacers as an etching mask to form a second sacrificial pattern and the charge storage structure 210, respectively, having a cup-like shape with their bottoms opened on the upper surface of the first impurity region 102. The exposed upper portion of the first impurity region 102 can also be partially removed. In an example embodiment, the charge storage structure 210 can include the first blocking pattern 180, the charge storage pattern 190, and the tunnel insulating pattern 200 sequentially stacked.

[0073] After the first spacers and the second sacrificial pattern are removed, the channel layer 220 can be formed on the first impurity region 102, the charge storage structure 210, and the uppermost insulating layer 110 of the insulating layers 110 of the module structure.

[0074] The channel layer 220 can include polysilicon or amorphous silicon. When the channel layer 220 includes amorphous silicon, the channel layer 220 can be converted into crystalline silicon by heat generated during a process of forming other layers. Alternatively, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process can be further performed so that the amorphous silicon can be transformed into crystalline silicon.

[0075] Referring to Figure 11 A fill layer filling the remaining portion of the channel hole structure 170 can be formed on the channel layer 220, and the fill layer and the channel layer 220 can be planarized until an upper surface of an uppermost insulating layer 110 among the insulating layers 110 of the module structure is exposed, so that a fill pattern 230 filling the remaining portion of the channel hole structure 170 can be formed, and the channel layer 220 can be transformed into a channel 225.

[0076] Accordingly, the charge storage structure 210, the channel 225, and the fill pattern 230 can be sequentially stacked on the first impurity region 102 in the channel hole structure 170.

[0077] The portions of the channel 225 formed in the first channel hole 130, the second channel hole 150, and the third channel hole 160 of the channel hole structure 170 can be referred to as first to third portions, respectively, and each of the first to third portions of the channel 225 can have a sidewall having a constant slope and inclined to the upper surface of the substrate 100. In an example embodiment, each of the first to third portions of the channel 225 can have a width gradually increasing from a bottom to a top.

[0078] In an example embodiment, the third portion of the channel 225 can have a length in the first direction shorter than a length in the first direction of each of the first and second portions of the channel 225.

[0079] The channel 225 having a shape of a cup with its bottom being opened, the charge storage structure 210 covering the outer sidewall of the channel 225, and the fill pattern 230 filling an inner space formed by the inner sidewall of the channel 225 can form a first structure having a shape of a column.

[0080] An upper portion of the first structure can be removed to form a trench, and a pad 240 filling the trench can be formed.

[0081] In an example embodiment, the pad 240 can include doped polysilicon or amorphous silicon, and when the pad 240 includes amorphous silicon, a crystallization process can be further performed thereon.

[0082] Referring to Figure 12 and Figure 13A first insulating intermediate layer 250 can be formed on the uppermost insulating layer 110 among the insulating layers 110 and the pad 240, and a first opening 260 can be formed through the first insulating intermediate layer 250, the insulating layers 110 and the first sacrificial layers 120 of the module structure, and the first impurity region 102. During the formation of the first opening 260, a portion of the substrate 100 located below the first impurity region 102 can also be partially removed.

[0083] In an example embodiment, the first openings 260 can extend in the third direction, and a plurality of the first openings 260 can be formed in the second direction.

[0084] As the first openings 260 are formed, the module structure can be split along the second direction, the insulating layers 110 can be transformed into insulating patterns 115 each extending in the third direction, the first sacrificial layers 120 can be transformed into first sacrificial patterns each extending in the third direction, and the connection layers 140 can be transformed into connection patterns 145 each extending in the third direction.

[0085] In an example embodiment, on the module structure formed between the first openings 260 adjacent to each other in the second direction, a channel block including a plurality of channels 225 extending in the first direction through the module structure can be formed, the channel block can include at least 14 channel columns including a plurality of channels 225 arranged in the third direction, and the channel columns can be separated from each other in the second direction. Thus, as the plurality of channels 225 can support the module structure, the module structure can have improved stability and can not be tilted toward the first openings 260 even when the number of the first sacrificial patterns of the module structure increases and the aspect ratio of the module structure is large.

[0086] The first sacrificial patterns exposed by the first openings 260 can be removed to form gaps 270 between adjacent ones of the insulating patterns 115 at the respective layers. A portion of the outer sidewall of the first barrier pattern 180 can be exposed by the gaps 270.

[0087] In an example embodiment, the first sacrificial patterns exposed by the first openings 260 can be removed by a wet etching process using a solution containing phosphoric acid or sulfuric acid.

[0088] Referring to Figure 14 A second barrier layer 280 can be formed on the exposed outer sidewall of the first barrier pattern 180, the inner wall of the gap 270, the surface of the insulating pattern 115, the upper surface of the substrate 100, and the upper surface of the first insulating intermediate layer 250, and a gate electrode can be formed on the second barrier layer 280 to at least partially fill the gap 270.

[0089] The gate electrode can be formed by forming a gate electrode layer that sufficiently fills the gap 270 on the second barrier layer 280 and partially removing the gate electrode layer. In an example embodiment, the gate electrode layer can be partially removed by a wet etching process.

[0090] In an example embodiment, the gate electrode can include a gate conductive pattern and a gate barrier pattern that covers lower and upper surfaces and sidewalls of the gate conductive pattern. The gate conductive pattern can include a low-resistance metal such as tungsten, titanium, tantalum, etc., and the gate barrier pattern can include a metal nitride such as titanium nitride, tantalum nitride, etc.

[0091] The gate electrode can extend in the third direction, and a plurality of gate electrodes can be formed in the second direction.

[0092] In an example embodiment, the gate electrode can be formed at a plurality of layers that are spaced apart from each other in the first direction, and the gate electrodes located at the plurality of layers can form a gate electrode structure. The gate electrode structure can include at least one first gate electrode 292, a plurality of second gate electrodes 294, and at least one third gate electrode 296 that are sequentially stacked.

[0093] In an example embodiment, the channel 225 can extend in the first direction through the plurality of gate electrodes. Specifically, a first portion of the channel 225 can extend through the first gate electrode 292, a second portion of the channel 225 can extend through some of the second gate electrodes 294, and a third portion of the channel 225 can extend through some of the second gate electrodes 294 and the third gate electrode 296.

[0094] Referring to Figure 15 Impurities can be injected into the upper portion of the substrate 100 through a portion of the second barrier layer 280 located on the bottom of the first opening 260 to form a second impurity region 104. In an example embodiment, the impurities can include n-type impurities such as phosphorus, arsenic, etc.

[0095] A second spacer layer can be formed on the second barrier layer 280, and the second spacer layer can be anisotropically etched to form a second spacer 300 on the sidewall of the first opening 260, and thus a portion of the second barrier layer 280 on the second impurity region 104 can be exposed.

[0096] A portion of the second barrier layer 280 that is not covered by the second spacer 300 can be etched, and a portion of the second barrier layer 280 on the upper surface of the first insulating intermediate layer 250 can also be removed. During the etching process, a portion of the second impurity region 104 at the upper portion of the substrate 100 can also be partially removed.

[0097] An electrically conductive layer filling the remaining portion of the first opening 260 can be formed on the upper surface of the second impurity region 104, the second spacer 300, and the first insulating intermediate layer 250, and the electrically conductive layer can be planarized until the upper surface of the first insulating intermediate layer 250 can be exposed to form a common source line (CSL) 310.

[0098] As the CSL 310 is formed, the second barrier layer 280 can be transformed into a second barrier pattern 285.

[0099] In an example embodiment, the CSL 310 can extend in the first direction, and can extend in the third direction. The lower surface of the CSL 310 can be covered by the second impurity region 104. In an example embodiment, a plurality of CSLs 310 can be formed spaced apart from each other along the second direction.

[0100] Referring to Figure 16 , Figure 17A and Figure 17B , a fourth photoresist pattern can be formed on the first insulating intermediate layer 250, and the first insulating intermediate layer 250, the second barrier pattern 285, the first gate electrode 292, and the insulating pattern 115 formed on and under the first gate electrode 292 can be etched using the fourth photoresist pattern as an etching mask to form a second opening 320 exposing the upper surface of the uppermost connection pattern 145.

[0101] Accordingly, the sidewall of the first gate conductive pattern 292a of each of the first gate electrodes 292, the sidewall of the first gate barrier pattern 292b covering a portion of the lower surface and the upper surface and the sidewall of the first gate conductive pattern 292a, and the sidewall of the second barrier pattern 285 covering a portion of the lower surface and the upper surface and the sidewall of the first gate barrier pattern 292b can be exposed through the second opening 320, and the first gate electrodes 292 can be separated in the second direction by the second opening 320.

[0102] In an example embodiment, the second opening 320 can extend in the third direction, and a plurality of second openings 320 can be formed along the second direction. In an example embodiment, at least two second openings 320 can be formed between two CSLs 310 adjacent to each other in the second direction.

[0103] In an example embodiment, the second opening 320 can have a sidewall substantially perpendicular to the upper surface of the substrate 100, however, the embodiment is not limited thereto.

[0104] The second opening 320 can extend partially through the pad 240 and the upper portion of the first structure. The trench 225 formed under the second opening 320 and included in the first structure of which the upper portion is partially extended can be a dummy trench.

[0105] Referring again to Figure 1 、 Figure 2A 、 Figure 2B and Figure 3 A second insulating intermediate layer 330 can be formed on the first insulating intermediate layer 250, the CSL 310, the second spacer 300, and the second barrier pattern 285.

[0106] The second insulating intermediate layer 330 can be formed to fill the second openings 320, and thus a lower surface of the second insulating intermediate layer 330 can have protrusions 335 protruding in the first direction.

[0107] The protrusions 335 of the second insulating intermediate layer 330 can directly contact a sidewall of the first gate conductive pattern 292a of each of the first gate electrodes 292 exposed by the second openings 320, a sidewall of the first gate barrier pattern 292b covering a lower surface and an upper surface and a portion of a sidewall of the first gate conductive pattern 292a, and a sidewall of the second barrier pattern 285 covering a lower surface and an upper surface and a portion of a sidewall of the first gate barrier pattern 292b.

[0108] Hereinafter, the protrusions 335 of the second insulating intermediate layer 330 are referred to as insulating isolation patterns 335.

[0109] In an example embodiment, the insulating isolation patterns 335 can extend through at least an uppermost first gate electrode 292 among the gate electrodes in the first direction, and can separate the uppermost first gate electrode 292 in the second direction.

[0110] In an example embodiment, the insulating isolation patterns 335 can extend in the third direction, and a plurality of the insulating isolation patterns 335 can be formed to be spaced apart from each other between two CSLs 310 adjacent to each other in the second direction.

[0111] In an example embodiment, a channel block including at least 14 channel columns can be formed between two CSLs 310 adjacent to each other in the second direction. However, channels 225 included in two channel columns under the insulating isolation patterns 335 among the channel columns can be used as dummy channels, so that only channels 225 included in twelve channel columns can be used as channels.

[0112] A contact plug 340 can be formed to pass through the first insulating intermediate layer 250 and the second insulating intermediate layer 330 to contact an upper surface of the pad 240, a third insulating intermediate layer 350 can be formed on the second insulating intermediate layer 330 and the contact plug 340, and a bit line 360 can be formed to pass through the third insulating intermediate layer 350 to contact an upper surface of the contact plug 340.

[0113] In an example embodiment, the bit line 360 can extend in the second direction, and a plurality of bit lines 360 can be formed in the third direction.

[0114] The vertical memory device can be manufactured by the above process.

[0115] As described above, the channel block including 14 or more channel columns arranged in the second direction can be formed on the module structure between the first openings 260 adjacent to each other in the second direction, and thus the module structure can have improved stability and not be tilted even when the aspect ratio of the module structure is large.

[0116] Since the channel block includes a plurality of channel columns, two or more insulating isolation patterns 335 can be formed to separate the first gate electrodes 292 serving as SSLs, however, the second openings 320 for forming the insulating isolation patterns 335 can be formed after the gate electrodes are formed. Thus, in the case where a plurality of second openings 320 are formed before the gate electrodes are formed, when the gate electrodes are formed through the gaps 270, a gap due to the gaps 270 being partially blocked by the second openings 320 can not occur.

[0117] Figure 18A and Figure 18B is a cross-sectional view illustrating a vertical memory device according to an example embodiment. Figure 18A is a cross-sectional view taken along line A-A' of Figure 1 , Figure 18B is an enlarged cross-sectional view of region X of Figure 18A .

[0118] The vertical memory device can be substantially the same as or similar to the vertical memory device of Figure 2A and Figure 2B except for the shape of the gate blocking pattern. Thus, the same reference numerals denote the same elements, and detailed descriptions thereof are omitted here.

[0119] Referring to Figure 18A and Figure 18B , in the process described in Figure 16 , Figure 17A and Figure 17B , after the second openings 320 are formed, the second gate blocking patterns 293 covering the sidewalls and the bottom of the second openings 320 can be formed.

[0120] Specifically, the second gate blocking patterns 293 can be formed by conformally forming a second gate blocking layer on the sidewalls and the bottom of the second openings 320 and the upper surface of the first insulating intermediate layer 250 and planarizing the second gate blocking layer until the upper surface of the first insulating intermediate layer 250 is exposed.

[0121] Accordingly, the second gate barrier pattern 293 can directly contact the sidewalls of the first gate electrode 292 facing the insulating isolation pattern 335, i.e., each of the sidewalls of the first gate conductive pattern 292a and the first gate barrier pattern 292b facing the insulating isolation pattern 335. The second gate barrier pattern 293 can also directly contact the portions of the second barrier pattern 285 on the upper and lower surfaces of the first gate electrode 292.

[0122] In an example embodiment, the second gate barrier pattern 293 can include a material substantially the same as that of the first gate barrier pattern 292b of the first gate electrode 292, e.g., a metal nitride such as titanium nitride, tantalum nitride, etc., in which case the second gate barrier pattern 293 contacting the first gate electrode 292 can be considered to be included in the first gate electrode 292 by merging with the first gate barrier pattern 292b.

[0123] Alternatively, the second gate barrier pattern 293 can include a metal nitride but can include a material different from that of the first gate barrier pattern 292b of the first gate electrode 292, in which case the second gate barrier pattern 293 can not merge with the first gate barrier pattern 292b.

[0124] Figure 19A and Figure 19B is a cross-sectional view showing a vertical memory device according to an example embodiment. Figure 19A is a cross-sectional view taken along the line A-A' of Figure 1 , Figure 19B is Figure 19A is an enlarged cross-sectional view of the region X of

[0125] The vertical memory device can be substantially the same as or similar to the vertical memory device of Figure 2A and Figure 2B except for the shape of the gate barrier pattern. Accordingly, like reference numerals denote like elements, and detailed descriptions thereof are omitted here.

[0126] Referring to Figure 19A and Figure 19B , the sidewalls of the insulating isolation pattern 335 can have a shape in which the portions in contact with the first gate electrode 292 are concave, and thus can have a concave-convex shape as a whole.

[0127] Specifically, during the etching process for forming the second opening 320, the gate electrode 292 can be etched less than the insulating pattern 115 depending on the characteristics of the etching process, and thus the insulating isolation pattern 335 can be formed to have sidewalls having a concave-convex shape.

[0128] Figures 20 to 22 is a plan view showing a vertical memory device according to an example embodiment.

[0129] In addition to the number of channel columns included in the channel block and the arrangement of the insulating isolation pattern, those vertical memory devices can be substantially the same as or similar to the vertical memory device of Figure 1 Therefore, the same reference numerals indicate the same elements, and detailed descriptions thereof are omitted here.

[0130] Referring to Figure 20 , the channel block can include 12 channel columns arranged along the second direction, and the insulating isolation pattern 335 can be formed between the channels 225, instead of extending through the upper portions of the channels 225. Accordingly, all of the channels 225 included in each channel column can function as channels, and dummy channels can not be formed. In one embodiment, 2 insulating isolation patterns 335 can be formed on one channel block, and 4 channel columns can be disposed between two adjacent insulating isolation patterns 335. Further, 4 channel columns can be disposed between the insulating isolation pattern 335 and the CSL 310 adjacent thereto.

[0131] Referring to Figure 21 , the channel block can include 19 channel columns arranged along the second direction, and the insulating isolation pattern 335 can be formed to extend through the upper portions of each of the channels 225 included in 3 channel columns among the 19 channel columns. Accordingly, the channels 225 of the 3 channel columns can be dummy channels, and 4 channel columns functioning as channels can be disposed between two adjacent insulating isolation patterns 335. Further, 4 channel columns can be disposed between the insulating isolation pattern 335 and the CSL 310 adjacent thereto.

[0132] Referring to Figure 22 , the channel block can include 24 channel columns arranged along the second direction, and the insulating isolation pattern 335 can be formed to extend through the upper portions of each of the channels 225 included in 4 channel columns among the 24 channel columns. Accordingly, the channels 225 of the 4 channel columns can be dummy channels, and 4 channel columns functioning as channels can be disposed between two adjacent insulating isolation patterns 335. Further, 4 channel columns can be disposed between the insulating isolation pattern 335 and the CSL 310 adjacent thereto.

[0133] Although embodiments have been described above, it will be readily apparent to those skilled in the art that many modifications of the basic teachings can be made without departing from the scope of the present disclosure.

Claims

1. A vertical memory device, the vertical memory device comprising: A gate electrode is formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate. The gate electrode includes a first gate electrode, a plurality of second gate electrodes interposed between the first gate electrode and the substrate, and a third gate electrode interposed between the substrate and the plurality of second gate electrodes. Multiple common source electrode lines are separated from each other along a second direction that is substantially parallel to the upper surface of the substrate. Each of the multiple common source electrode lines extends through each gate electrode in a first direction and extends upward in a third direction that is substantially parallel to the upper surface of the substrate and intersects the second direction. Multiple channels, each separated from the other in a second direction and a third direction between two adjacent common source lines, each channel extending through the gate electrode in a first direction, each channel comprising multiple portions, each of the multiple portions having a width that gradually increases with increasing distance from the substrate, the multiple portions of each channel being sequentially and continuously stacked on the substrate and connected to each other. A charge storage structure is disposed on the outer wall of each channel. The charge storage structure includes a tunnel insulation pattern, a charge storage pattern and a first blocking pattern stacked sequentially. Each of the tunnel insulation pattern, the charge storage pattern and the first blocking pattern has a horizontal portion at the interface between two portions of the plurality of portions of the channel that extends substantially parallel to the upper surface of the substrate. Two or more insulating isolation patterns are separated from each other along a second direction between two adjacent common source lines among the plurality of common source lines, each insulating isolation pattern extending through the first gate electrode in a first direction and separating the first gate electrode in the second direction; as well as A blocking pattern is provided on the upper surface, lower surface, and sidewall of each gate electrode, with the sidewall of the gate electrode facing the channel. In this configuration, the insulating isolation pattern directly contacts the first gate electrode. The first gate electrode is used as a serial select line, each of the plurality of second gate electrodes is used as a word line, and the third gate electrode is used as a ground select line.

2. The vertical memory device according to claim 1, wherein, The blocking pattern includes metal oxides.

3. The vertical memory device according to claim 1, wherein, Each gate electrode includes: Gate conductive pattern, including metal; and A first gate blocking pattern covers the upper surface, lower surface, and sidewalls of a gate conductive pattern, with the sidewalls of the gate conductive pattern facing the channel. The first gate blocking pattern comprises a metal nitride. In this configuration, the insulating isolation pattern directly contacts each of the gate conductive pattern and the first gate blocking pattern of the first gate electrode.

4. The vertical memory device according to claim 1, wherein, Each gate electrode includes: Gate conductive pattern, including metal; and A first gate blocking pattern covers the upper surface, lower surface, and first sidewall of a gate conductive pattern. The first sidewall of the gate conductive pattern faces the channel. The first gate blocking pattern comprises a metal nitride. The first gate electrode further includes a second gate blocking pattern covering the second sidewall of the gate conductive pattern, the second sidewall of the gate conductive pattern facing the insulating isolation pattern, and the second gate blocking pattern comprising a metal nitride. In this case, the insulating isolation pattern directly contacts the second gate blocking pattern.

5. The vertical memory device according to claim 4, wherein, The second gate blocking pattern directly contacts the portion of the blocking pattern formed on the upper and lower surfaces of the first gate electrode.

6. The vertical memory device according to claim 4, wherein, The second gate barrier pattern includes a material different from that of the first gate barrier pattern.

7. The vertical memory device according to claim 1, wherein, The first gate electrode includes two first gate electrodes formed in the uppermost layer of the gate electrode and at least one layer below it, and The third gate electrode is formed in the bottommost layer of the gate electrode.

8. The vertical memory device according to claim 1, in, The first of the plurality of portions extends through the first gate electrode.

9. The vertical memory device according to claim 8, wherein, The first portion of the channel has a length in the first direction that is smaller than the length in the first direction of each of the remaining portions of the channel.

10. The vertical memory device according to claim 1, wherein, in, The multiple channels between two adjacent common source poles among the multiple common source poles form a channel block. The plurality of channels in the channel block includes at least 12 channels.

11. The vertical memory device according to claim 10, wherein, The plurality of channels includes dummy channels, and The insulating pattern extends through the upper part of the dummy trench.

12. The vertical memory device according to claim 10, wherein, The insulating isolation pattern is offset upwards in the second and third directions from each of the plurality of channels.

13. A vertical memory device, the vertical memory device comprising: Multiple common source pole lines are separated from each other along a horizontal direction that is substantially parallel to the upper surface of the substrate, and each of the multiple common source pole lines extends upward at a third point that is substantially parallel to the upper surface of the substrate and intersects the horizontal direction. Multiple channels extend on the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate. Each channel comprises multiple sections, each of the multiple sections of each channel having a width that gradually increases with increasing distance from the substrate. The multiple sections are stacked sequentially and continuously and connected to each other. A charge storage structure is disposed on the outer wall of each channel. The charge storage structure includes a tunnel insulation pattern, a charge storage pattern and a first blocking pattern stacked sequentially. Each of the tunnel insulation pattern, the charge storage pattern and the first blocking pattern has a horizontal portion at the interface between two portions of the plurality of portions of the channel that extends substantially parallel to the upper surface of the substrate. Gate electrodes are vertically spaced apart on a substrate. Each gate electrode surrounds a channel in a horizontal direction substantially parallel to the upper surface of the substrate and includes a gate conductive pattern and a gate blocking pattern covering the upper surface, lower surface and sidewalls of the gate conductive pattern. The sidewalls of the gate conductive pattern face the channel. The gate electrode includes a first gate electrode, a plurality of second gate electrodes interposed between the first gate electrode and the substrate, and a third gate electrode interposed between the substrate and the plurality of second gate electrodes. as well as Two or more insulating isolation patterns are horizontally separated from each other between two adjacent common source lines among the plurality of common source lines. Each insulating isolation pattern extends through a first gate electrode and at least one of a plurality of second gate electrodes, and each insulating isolation pattern horizontally separates the first gate electrode. Each of the plurality of common source electrode lines extends vertically through each gate electrode. The first gate electrode surrounds a first portion of the plurality of portions of the channel, and the remaining portions of the plurality of portions of the channel are inserted between the substrate and the first portion. The first portion of the channel has a vertical length shorter than that of each of the remaining portions of the channel. The first gate electrode is used as a serial select line, each of the plurality of second gate electrodes is used as a word line, and the third gate electrode is used as a ground select line.

14. The vertical memory device according to claim 13, wherein, The insulating isolation pattern directly contacts each of the gate conductive pattern and the gate blocking pattern of the first gate electrode.

15. The vertical memory device according to claim 13, wherein, The gate barrier pattern is the first gate barrier pattern. The vertical memory device further includes a second gate barrier pattern covering the sidewalls and lower surface of the insulating isolation pattern. The second gate blocking pattern directly contacts each of the gate conductive pattern and the first gate blocking pattern of the first gate electrode.

16. The vertical memory device according to claim 13, wherein, The sidewalls of the insulating pattern have a concave-convex shape.

17. A vertical memory device, the vertical memory device comprising: A gate electrode is disposed on a substrate and separated from each other in a first direction substantially perpendicular to the upper surface of the substrate. The gate electrode includes a first gate electrode, a plurality of second gate electrodes interposed between the first gate electrode and the substrate, and a third gate electrode interposed between the substrate and the plurality of second gate electrodes. Multiple common source electrode lines are separated from each other along a second direction that is substantially parallel to the upper surface of the substrate. Each of the multiple common source electrode lines extends through each gate electrode in a first direction and extends upward in a third direction that is substantially parallel to the upper surface of the substrate and intersects the second direction. Multiple channels, each separated from the other in a second direction and a third direction between two adjacent common source lines, each channel extending through the gate electrode in a first direction, each channel comprising multiple portions, each of the multiple portions having a width that gradually increases with increasing distance from the substrate, the multiple portions of the channel being sequentially and continuously stacked on the substrate and connected to each other. A charge storage structure is disposed on the outer wall of each channel. The charge storage structure includes a tunnel insulation pattern, a charge storage pattern and a first blocking pattern stacked sequentially. Each of the tunnel insulation pattern, the charge storage pattern and the first blocking pattern has a horizontal portion at the interface between two portions of the plurality of portions of the channel that extends substantially parallel to the upper surface of the substrate. Pads are formed on each channel; Two or more insulating isolation patterns are separated from each other along a second direction between two adjacent common source lines among the plurality of common source lines, each insulating isolation pattern extends through and directly contacts the first gate electrode in a first direction, and extends upward in a third direction to separate the first gate electrode in a second direction. A second blocking pattern covers the upper surface, lower surface, and sidewalls of each gate electrode, with the sidewalls of the gate electrode facing one of the channels; as well as Multiple bit lines, spaced apart from each other and electrically connected to the pad, each of the multiple bit lines extending in a second direction. The first gate electrode is used as a serial select line, each of the plurality of second gate electrodes is used as a word line, and the third gate electrode is used as a ground select line.

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