Thin film transistor, display panel having the same, and method of manufacturing display panel

Abstract

The present application relates to a thin film transistor, a display panel, and a method of manufacturing a display panel. The display panel includes a base layer, a first thin film transistor on the base layer, a second thin film transistor electrically connected to the first thin film transistor, and a light emitting element electrically connected to the second thin film transistor. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern including gallium (Ga) oxide and zinc (Zn) oxide on the first semiconductor pattern, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern. Accordingly, a signal transmission speed of the display panel can be improved, and electrical characteristics and reliability of the thin film transistor included in the display panel can be improved.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0092417, filed on July 30, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to thin-film transistors, display panels including thin-film transistors, and methods of manufacturing display panels. For example, embodiments of this disclosure relate to thin-film transistors having improved electrical characteristics and reliability, display panels including the thin-film transistors, and methods of manufacturing display panels. Background Technology

[0004] The display device includes signal lines, pixels, and driving circuitry for controlling the pixels, such as gate driving circuitry and data driving circuitry. Each pixel includes a display element and pixel driving circuitry for controlling that display element. The pixel driving circuitry includes thin-film transistors interconnected with each other. Summary of the Invention

[0005] Embodiments of this disclosure provide a display panel with improved signal transmission speed.

[0006] Embodiments of this disclosure provide a thin-film transistor with improved electrical characteristics and reliability.

[0007] Embodiments of this disclosure provide a method for manufacturing a display panel in which the occurrence of process defects is reduced.

[0008] Embodiments of this disclosure provide a display panel including a substrate, a first thin-film transistor on the substrate, a second thin-film transistor electrically connected to the first thin-film transistor, and a light-emitting element electrically connected to the second thin-film transistor. The first thin-film transistor includes a first semiconductor pattern on the substrate, a first barrier pattern on the first semiconductor pattern including gallium (Ga) oxide and zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern.

[0009] The first thin-film transistor includes a first input electrode and a first output electrode coupled to a first semiconductor pattern.

[0010] The display panel also includes a first insulating layer on the substrate to cover the first semiconductor pattern, and the first insulating layer is between the first semiconductor pattern and the first barrier pattern.

[0011] The first insulating layer is in contact with the first semiconductor pattern, the first barrier pattern is in contact with the first insulating layer, and the first control electrode is in contact with the first barrier pattern.

[0012] The display panel further includes a second insulating layer on the first insulating layer to cover the first control electrode. The second thin film transistor includes a second semiconductor pattern on the base layer, a second barrier pattern on the second insulating layer and including gallium (Ga) oxide and zinc (Zn) oxide, a second control electrode on the second barrier pattern and overlapping the second semiconductor pattern, and a second input electrode and a second output electrode coupled to the second semiconductor pattern.

[0013] The display panel further includes a third barrier pattern on the first insulating layer and a gate line electrically coupled to the first thin film transistor on the third barrier pattern.

[0014] The display panel further includes a capacitor electrically coupled to the second thin film transistor. The capacitor includes a fourth barrier pattern on the first insulating layer, a first electrode on the fourth barrier pattern, a fifth barrier pattern on the second insulating layer, and a second electrode on the fifth barrier pattern.

[0015] The third barrier pattern, the fourth barrier pattern, and the fifth barrier pattern include the same material as the first barrier pattern.

[0016] The first control electrode includes a first layer including titanium (Ti) and a second layer on the first layer and including copper (Cu).

[0017] The gallium oxide has a content of about 4 at% to about 8 at% with respect to a total amount of atoms in the first barrier pattern, and the zinc oxide has a content of about 92 at% to about 96 at% with respect to the total amount of atoms in the first barrier pattern.

[0018] The first semiconductor pattern includes gallium (Ga) oxide, zinc (Zn) oxide, and indium (In) oxide.

[0019] The first barrier pattern has a thickness equal to or greater than about 100 angstroms and equal to or less than about 200 angstroms.

[0020] An embodiment of the disclosure provides a thin film transistor including a first semiconductor pattern including a channel region and a contact region, a first insulating layer on the first semiconductor pattern, a first barrier pattern on the first insulating layer and including gallium (Ga) oxide and zinc (Zn) oxide, a first control electrode on the first barrier pattern and overlapping the channel region of the first semiconductor pattern, a first input electrode coupled to the contact region of the first semiconductor pattern, and a first output electrode coupled to the contact region of the first semiconductor pattern.

[0021] The first barrier pattern and the first control electrode overlap the channel region of the first semiconductor pattern.

[0022] Embodiments of the present disclosure provide a method of manufacturing a display panel, the method including: forming a semiconductor pattern on a base layer; forming a barrier pattern on the semiconductor pattern using gallium (Ga) oxide and zinc (Zn) oxide; forming a control electrode on the barrier pattern to overlap the semiconductor pattern; forming an input electrode and an output electrode on the base layer such that the input electrode and the output electrode are coupled to the semiconductor pattern; and forming a light emitting element on the base layer.

[0023] The semiconductor pattern is formed using gallium (Ga) oxide, zinc (Zn) oxide, and indium (In) oxide, and forming the semiconductor pattern is performed at an oxygen partial pressure equal to or less than about 40%.

[0024] The method further includes, after forming the control electrode, forming an insulating layer to cover the barrier pattern and the control electrode, and forming the insulating layer is performed by a chemical vapor deposition (CVD) method.

[0025] Forming the barrier pattern and the control electrode includes forming a preliminary barrier layer using gallium (Ga) oxide and zinc (Zn) oxide, depositing a metal material on the preliminary barrier layer to form a preliminary electrode layer, and etching the preliminary barrier layer and the preliminary electrode layer.

[0026] Embodiments of the present disclosure provide a display panel including: a base layer; a buffer layer on the base layer; a first thin film transistor on the buffer layer; a second thin film transistor on the buffer layer and electrically coupled to the first thin film transistor; a pixel definition layer on the buffer layer and disposed to define an opening through the pixel definition layer; a light emitting element in the opening and electrically coupled to the second thin film transistor; and a thin film encapsulation layer on the pixel definition layer and the light emitting element. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern on the first semiconductor pattern and including gallium (Ga) oxide and zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern.

[0027] According to the above, the barrier pattern is under the control electrode, and the barrier pattern is formed of a metal oxide not including indium. Thus, even if the oxide semiconductor is formed at a low oxygen partial pressure, the reliability of the oxide semiconductor can not be reduced or decreased, and degradation of layer uniformity due to indium metal particles in a manufacturing process of the thin film transistor can be prevented or reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other features of embodiments of the present disclosure will become more apparent by referring to the following detailed description when considered in connection with the accompanying drawings, in which:

[0029] Figure 1 is a perspective view illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 2 is a plan view illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0031] Figure 3 is a cross-sectional view illustrating a portion of a pixel according to an exemplary embodiment of the present disclosure;

[0032] Figure 4 is a cross-sectional view illustrating a transistor according to an exemplary embodiment of the present disclosure;

[0033] Figures 5A to 5K is a cross-sectional view illustrating a manufacturing process of a display panel according to an exemplary embodiment of the present disclosure;

[0034] Figure 6A is a graph illustrating an electrical characteristic of a transistor according to an exemplary embodiment of the present disclosure; and

[0035] Figure 6B is a graph illustrating an electrical characteristic of a transistor according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Hereinafter, it will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer, directly connected to or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.

[0037] The same reference numerals are used throughout the drawings to refer to the same or like elements. In the drawings, the thickness, proportions and dimensions of components can be exaggerated for effective description of the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, a first component, a first region, a first layer or a first section discussed below could be termed a second element, a second component, a second region, a second layer or a second section without departing from the spirit and scope of the present disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] For ease of description, spatial relative terms, such as "below", "under", "lower", "above", "upper", and the like, can be used herein to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures.

[0040] It will also be understood that, when used in this specification, the terms "includes" and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0041] Hereinafter, a thin film transistor and a display panel including the same according to the present disclosure will be explained in detail with reference to the accompanying drawings. Figures 1 to 4 A thin film transistor according to the present disclosure and a display panel including the same will be explained in more detail.

[0042] Figure 1 is a perspective view illustrating a display panel DP according to an exemplary embodiment of the present disclosure. Figure 2 is a plan view illustrating a display panel DP according to an exemplary embodiment of the present disclosure. Figure 2 A connection relationship between a pixel PX, a driving circuit GDC, and a plurality of signal lines SGL is schematically illustrated.

[0043] A front surface DP-FS of the display panel DP is substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 represents a normal direction of the front surface DP-FS of the display panel DP, for example, a thickness direction of the display panel DP. An upper surface (or a front surface) and a lower surface (or a rear surface) of each layer of the display panel DP are distinguished from each other in the third direction DR3.

[0044] Referring to Figure 1 , the display panel DP includes a display area DP-DA in which the pixels PX are located on the front surface DP-FS and a non-display area DP-NDA defined adjacent to the display area DP-DA. The pixels PX are not arranged in the non-display area DP-NDA. Some of the plurality of signal lines SGL and / or the driving circuit GDC are arranged in the non-display area DP-NDA.

[0045] As Figure 1As shown in FIG. 1, the display region DP-DA can have a quadrilateral shape, but the present disclosure is not limited thereto. The non-display region DP-NDA can surround the display region DP-DA, however, it should not be limited thereto or thereby. The shape of the display region DP-DA and the shape of the non-display region DP-NDA can be relative designed, and the display region DP-DA and the non-display region DP-NDA can each have any suitable shape commonly used in the art. For example, the non-display region DP-NDA can be provided only in regions facing each other along the first direction DR1. The display region DP-DA can have a circular shape.

[0046] Referring to Figure 2 The display panel DP includes a drive circuit GDC, a plurality of signal lines SGL, a plurality of signal plates DP-PD (hereinafter, referred to as "signal plates"), and pixels PX.

[0047] The pixels PX can be classified into a plurality of groups according to colors displayed by the pixels PX. The pixels PX can include, for example, red pixels, green pixels, and / or blue pixels. The pixels PX can also include white pixels. Although the pixels PX are classified into different groups from each other according to colors displayed by the pixels PX, pixel drive circuits of the pixels PX can be substantially the same as each other.

[0048] The drive circuit GDC includes a gate drive circuit. The gate drive circuit generates a plurality of gate signals (hereinafter, referred to as "gate signals") and sequentially outputs the gate signals to a plurality of gate lines GL (hereinafter, referred to as "gate lines") described in more detail below. The gate drive circuit can also output other control signals to the pixel drive circuits of the pixels PX.

[0049] The gate drive circuit can include a plurality of thin film transistors formed by the same (e.g., substantially the same) process as the pixel drive circuits of the pixels PX (e.g., a low temperature polysilicon (LTPS) process or a low temperature polyoxide (LTPO) process).

[0050] The plurality of signal lines SGL includes the gate lines GL, the data lines DL, the power lines PL, and the control signal lines CSL. Each of the gate lines GL is coupled to a corresponding pixel of the pixels PX, and each of the data lines DL is coupled to a corresponding pixel of the pixels PX. The power lines PL are coupled to the pixels PX. The control signal lines CSL provide control signals to the gate drive circuit. Each of the signal plates DP-PD is coupled to a corresponding signal line of the plurality of signal lines SGL. In some embodiments, the plurality of signal lines SGL can also include light emission signal lines.

[0051] In an embodiment of the disclosure, each of the pixels PX can be a light emitting type pixel. For example, each of the pixels PX can include an organic light emitting diode or a quantum dot light emitting diode as a light emitting element. A light emitting layer of the organic light emitting diode can include an organic light emitting material. A light emitting layer of the quantum dot light emitting diode can include a quantum dot or a quantum rod. Hereinafter, an organic light emitting type pixel will be described as a representative example of the pixel PX, but the disclosure is not limited thereto.

[0052] The pixel PX can include an organic light emitting diode and a pixel driving circuit for driving the organic light emitting diode. The organic light emitting diode can be a front surface light emitting type diode or a rear surface light emitting type diode. The pixel driving circuit can include at least a switching thin film transistor, a driving thin film transistor, and a capacitor. A high power voltage can be supplied to the driving thin film transistor, and a low power voltage can be supplied to one electrode of the organic light emitting diode. The driving thin film transistor can control a driving current flowing through the organic light emitting diode in response to a charged amount of the capacitor (for example, according to an amount of charge stored in the capacitor). The switching thin film transistor outputs a data signal applied to the switching thin film transistor through a data line DL in response to a gate signal applied to the switching thin film transistor through a gate line GL. The capacitor is charged with a voltage corresponding to the data signal from the switching thin film transistor.

[0053] The pixel driving circuit can include six or seven thin film transistors including the switching thin film transistor and the driving thin film transistor. The configuration of the pixel driving circuit should not be particularly limited. A plurality of signal lines SGL can be designed according to the configuration of the pixel driving circuit.

[0054] Figure 3 is a cross-sectional view illustrating a portion of the pixel PX according to an exemplary embodiment of the disclosure. Figure 3 A cross section corresponding to a switching thin film transistor T1 (hereinafter, referred to as a "first thin film transistor"), a driving thin film transistor T2 (hereinafter, referred to as a "second thin film transistor"), a capacitor Cst, and an organic light emitting diode OLED which are portions of the pixel PX is illustrated. Further, Figure 3 A cross section corresponding to a gate line GL is illustrated. Figure 4 is a cross-sectional view illustrating a transistor according to an exemplary embodiment of the disclosure. Figure 4 A cross section corresponding to the first thin film transistor T1 of Figure 3

[0055] Referring to Figure 3 ​The display panel DP can include a base layer BL, a circuit element layer DP-CL on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. In an exemplary embodiment of the disclosure, the thin film encapsulation layer TFE can be replaced with an encapsulation substrate, for example, a metal substrate and / or a glass substrate. The display panel DP can further include functional layers such as an anti-reflection layer and a refractive index control layer. The circuit element layer DP-CL can include at least a plurality of insulating layers and circuit elements. Hereinafter, the insulating layers can include organic layers and / or inorganic layers.

[0056] The circuit elements can include signal lines and pixel driving circuits. The circuit element layer DP-CL can be formed by using a coating and deposition process for the insulating layers, the semiconductor layers, and the conductive layers and by using a photolithography process to pattern the insulating layers, the semiconductor layers, and the conductive layers. The display element layer DP-OLED can include light emitting elements. The display element layer DP-OLED can include the same (e.g., substantially the same) organic layers as the pixel definition layer PDL.

[0057] The base layer BL can include a synthetic resin layer. The synthetic resin layer can include a thermosetting resin. For example, the synthetic resin layer can be a polyimide-based resin layer, however, it should not be limited thereto or thereby. The synthetic resin layer can include at least one selected from the group consisting of an acrylic-based resin, a methacrylic-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Further, the base layer BL can include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0058] At least one inorganic layer can be formed on an upper surface of the base layer BL. The inorganic layer can include at least one selected from the group consisting of aluminum oxide, titanium oxide, silicon nitride, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer can have a multi-layer structure. The inorganic layer having the multi-layer structure can form a buffer layer BFL. The buffer layer BFL can prevent or reduce entry of foreign substances from the outside of the display panel DP. Further, the buffer layer BFL can improve the bonding strength between the base layer BL and the conductive pattern and / or the semiconductor pattern, as compared to a case in which the conductive pattern and / or the semiconductor pattern is directly formed on the base layer BL.

[0059] The first thin film transistor T1 and the second thin film transistor T2 are on the buffer layer BFL. The second thin film transistor T2 is electrically coupled to the first thin film transistor T1. The gate line GL and the capacitor Cst are also on the buffer layer BFL. The gate line GL is electrically coupled to the first thin film transistor T1, and the capacitor Cst is electrically coupled to the second thin film transistor T2.

[0060] The first and second semiconductor patterns PS1 and PS2 can be on the buffer layer BFL. Each of the first and second semiconductor patterns PS1 and PS2 can include an oxide semiconductor, however, it should not be limited thereto or thereby. The first and second semiconductor patterns PS1 and PS2 can include polycrystalline silicon semiconductor, amorphous silicon, and / or oxide semiconductor in the same proportion or different proportions. The first and second semiconductor patterns PS1 and PS2 can include an oxide semiconductor containing gallium (Ga) oxide, zinc (Zn) oxide, and / or indium (In) oxide. The first and second semiconductor patterns PS1 and PS2 can include an oxide semiconductor containing indium gallium zinc oxide (IGZO) obtained by doping indium and gallium in zinc oxide.

[0061] Each of the first and second semiconductor patterns PS1 and PS2 can include a contact region and a channel region. In more detail, each of the first and second semiconductor patterns PS1 and PS2 can include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) defined between the input region and the output region. The channel region of the first semiconductor pattern PS1 can be defined to correspond to the first blocking pattern BR1 and the first control electrode GE1 described in more detail herein below, and the channel region of the second semiconductor pattern PS2 can be defined to correspond to the second blocking pattern BR2 and the second control electrode GE2 described in more detail herein below. The input region and the output region can be doped with a dopant, and thus, can have a relatively high conductivity compared to the channel region. The input region and the output region can be doped with an n-type dopant. In the present exemplary embodiment, an n-type first semiconductor pattern PS1 and an n-type second semiconductor pattern PS2 are described as a representative example, however, each of the first and second semiconductor patterns PS1 and PS2 can be a p-type semiconductor pattern, and can be doped with a dopant different from each other.

[0062] The first insulating layer 10 is on the buffer layer BFL. The first insulating layer 10 overlaps the pixel PX (refer to FIG. 1) in common, and covers the first and second semiconductor patterns PS1 and PS2. Figure 1 and Figure 2 ) The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single layer or a multi-layer structure.

[0063] The first blocking pattern BR1 and the first control electrode GE1 are on the first insulating layer 10. The first blocking pattern BR1 and the first control electrode GE1 overlap the channel region of the first semiconductor pattern PS1. The first insulating layer 10 is positioned in contact (e.g., direct contact) with the first semiconductor pattern PS1, the first blocking pattern BR1 is positioned in contact (e.g., direct contact) with the first insulating layer 10, and the first control electrode GE1 is positioned in contact (e.g., direct contact) with the first blocking pattern BR1.

[0064] The first blocking pattern BR1 can include gallium (Ga) oxide and zinc (Zn) oxide. The first blocking pattern BR1 can include a material in which gallium oxide and zinc oxide are mixed. The first blocking pattern BR1 can include gallium zinc oxide (GZO) obtained by doping zinc oxide with gallium. According to an embodiment, the content of gallium oxide is about 4 at% to about 8 at% with respect to the total amount of atoms in the first blocking pattern BR1, and the content of zinc oxide is about 92 at% to about 96 at% with respect to the total amount of atoms in the first blocking pattern BR1. The first blocking pattern BR1 can have a thickness of about 100 angstroms to about 200 angstroms. Because the first blocking pattern BR1 has the composition ratio and thickness range described herein, problems caused by differences in etching rates between different materials can be prevented or reduced in a process of etching the first blocking pattern BR1 and the first control electrode GE1.

[0065] The first control electrode GE1 can have a two-layer stacked structure. The first control electrode GE1 can include a first layer containing titanium (Ti) and a second layer containing copper (Cu) on the first layer. The first layer of the first control electrode GE1 can be in contact with the first blocking pattern BR1, and the second layer can be spaced apart from the first blocking pattern BR1 with the first layer interposed therebetween.

[0066] In some embodiments, a third blocking pattern BR3 and a fourth blocking pattern BR4 can be on the first insulating layer 10. A gate line GL can be on the third blocking pattern BR3. A first electrode CE1 of a capacitor Cst can be on the fourth blocking pattern BR4.

[0067] The third blocking pattern BR3 and the fourth blocking pattern BR4 can be formed by substantially the same process as the first blocking pattern BR1. For example, the third blocking pattern BR3 and the fourth blocking pattern BR4 can include substantially the same material as the first blocking pattern BR1. The third blocking pattern BR3 and the fourth blocking pattern BR4 can include gallium (Ga) oxide and zinc (Zn) oxide.

[0068] The gate line GL and the first electrode CE1 can be formed by substantially the same process as the first control electrode GE1, and thus, the gate line GL and the first electrode CE1 can have substantially the same stack structure as the first control electrode GE1. In some embodiments, the first control electrode GE1 can be coupled to the gate line GL in a plan view. The gate line GL can apply a conduction signal to the first thin film transistor T1.

[0069] The second insulating layer 20 is on the first insulating layer 10 to cover the first barrier pattern BR1, the first control electrode GE1, the third barrier pattern BR3, the gate line GL, the fourth barrier pattern BR4, and the first electrode CE1. The second insulating layer 20 is commonly overlapped with the pixel PX. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single layer or a multi-layer structure. According to embodiments, the second insulating layer 20 can be an inorganic layer formed by a chemical vapor deposition (CVD) method.

[0070] The second barrier pattern BR2 and the fifth barrier pattern BR5 can be on the second insulating layer 20. The second control electrode GE2 can be on the second barrier pattern BR2. The second electrode CE2 of the capacitor Cst can be on the fifth barrier pattern BR5. The second barrier pattern BR2 and the second control electrode GE2 can overlap with a channel region of the second semiconductor pattern PS2.

[0071] The second barrier pattern BR2 and the fifth barrier pattern BR5 can include substantially the same material as the first barrier pattern BR1. The second barrier pattern BR2 and the fifth barrier pattern BR5 can include gallium (Ga) oxide and zinc (Zn) oxide. The second control electrode GE2 and the second electrode CE2 can be formed by substantially the same process, and thus, can have substantially the same stack structure. The second control electrode GE2 and the second electrode CE2 can include substantially the same material as the first control electrode GE1, and can have substantially the same stack structure as the first control electrode GE1. In some embodiments, the second control electrode GE2 can be on substantially the same layer as the first control electrode GE1 according to another embodiment.

[0072] The third insulating layer 30 can be on the second insulating layer 20 to cover the second barrier pattern BR2, the second control electrode GE2, the fifth barrier pattern BR5, and the second electrode CE2. The third insulating layer 30 can be an inorganic layer and / or an organic layer, and can have a single layer or a multi-layer structure. The first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 can include at least one selected from aluminum oxide, titanium oxide, silicon nitride, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present exemplary embodiment, the third insulating layer 30 can have a single layer structure of silicon oxide.

[0073] The connection signal lines and the input / output electrodes can be on the third insulating layer 30. The first input electrode DE1 and the first output electrode SE1 can be on the third insulating layer 30 to be coupled to the input region and the output region of the first semiconductor pattern PS1 through the first contact hole CH1 and the second contact hole CH2, respectively. The second input electrode DE2 and the second output electrode SE2 can be on the third insulating layer 30 to be coupled to the input region and the output region of the second semiconductor pattern PS2 through the third contact hole CH3 and the fourth contact hole CH4, respectively. The first to fourth contact holes CH1 to CH4 can pass through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0074] The first and second connection signal lines CNL1 and CNL2 can be on the third insulating layer 30. The first connection signal line CNL1 can be coupled to the gate line GL through the fifth contact hole CH5, and the second connection signal line CNL2 can be coupled to the second electrode CE2 through the sixth contact hole CH6. In some embodiments, the first connection signal line CNL1 can be coupled to another thin film transistor of the pixel driving circuit.

[0075] The fourth insulating layer 40 can be on the third insulating layer 30 to cover the connection signal lines and the input / output electrodes. The material of the fourth insulating layer 40 should not be particularly limited. The connection electrode CNE can be on the fourth insulating layer 40. The connection electrode CNE can be directly or indirectly coupled (e.g., electrically coupled through another connection signal line) to the second output electrode SE2 through the seventh contact hole CH7 defined to pass through the fourth insulating layer 40. The fifth insulating layer 50 (or a passivation layer) can be on the fourth insulating layer 40 to cover the connection electrode CNE. The fifth insulating layer 50 can be an organic layer and can have a single layer or a multi-layer structure.

[0076] In the present exemplary embodiment, each of the fourth and fifth insulating layers 40 and 50 can be a single layer structure of a polyimide-based resin layer, however, it should not be limited thereto or thereby. For example, each of the fourth and fifth insulating layers 40 and 50 can include at least one selected from an acrylic-based resin, a methacrylic-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0077] The organic light emitting diode OLED is on the fifth insulating layer 50. The anode AE of the organic light emitting diode OLED is on the fifth insulating layer 50. The anode AE is coupled to the connection electrode CNE through the eighth contact hole CH8 defined to pass through the fifth insulating layer 50. The pixel definition layer PDL is on the fifth insulating layer 50.

[0078] At least a portion of the anode AE can be exposed through the opening OP of the pixel defining layer PDL. The opening OP of the pixel defining layer PDL can define a light emitting area PXA of the pixel. For example, the pixel PX (refer to Figure 1 ) can be arranged in the display panel DP (refer to Figure 1 ) in a plan view. An area in which the pixel PX is arranged can be defined as a pixel area, and one pixel area can include the light emitting area PXA and a non-light emitting area NPXA defined adjacent to the light emitting area PXA. The non-light emitting area NPXA can surround the light emitting area PXA.

[0079] The hole control layer HCL is commonly located in the light emitting area PXA and the non-light emitting area NPXA. A common layer such as the hole control layer HCL can be commonly formed in the pixel PX (refer to Figure 1 and Figure 2 ). The hole control layer HCL can include a hole transport layer and a hole injection layer.

[0080] The organic emitting layer EML can be on the hole control layer HCL. The organic emitting layer EML can be only in an area corresponding to the opening OP. For example, the organic emitting layer EML of the pixel PX can have a boundary between the organic emitting layers EML of the pixel PX.

[0081] In the present exemplary embodiment, the organic emitting layer EML is patterned. However, the organic emitting layer EML can be commonly located in the pixel PX. In this case, the organic emitting layer EML can generate white light or blue light. Further, the organic emitting layer EML can have a multi-layer structure.

[0082] The electron control layer ECL can be on the organic emitting layer EML. The electron control layer ECL can include an electron transport layer and an electron injection layer. The cathode CE can be on the electron control layer ECL. The electron control layer ECL and the cathode CE can be commonly located in the pixel PX.

[0083] The thin film encapsulation layer TFE is on the cathode CE. The thin film encapsulation layer TFE is commonly located in the pixel PX. In the present exemplary embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In the exemplary embodiment of the disclosure, a capping layer can be included to cover the cathode CE. In the exemplary embodiment of the disclosure, the stack structure of the organic light emitting diode OLED can have a structure inverted (e.g., flipped 180°) from the structure shown in Figure 3 .

[0084] The thin film encapsulation layer TFE can include at least an inorganic layer and an organic layer. In an exemplary embodiment of the disclosure, the thin film encapsulation layer TFE can include two inorganic layers and an organic layer between the two inorganic layers. In an exemplary embodiment of the disclosure, the thin film encapsulation layer TFE can include a plurality of inorganic layers and a plurality of organic layers alternately stacked with the inorganic layers.

[0085] The encapsulating inorganic layer can protect the organic light emitting diode OLED from moisture and oxygen, and the encapsulating organic layer can protect the organic light emitting diode OLED from foreign substances such as dust particles. The encapsulating inorganic layer can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer, however, it should not be particularly limited. The encapsulating organic layer can include an acrylic-based organic layer, however, it should not be particularly limited.

[0086] Unlike Figure 3 According to an exemplary embodiment of the disclosure, the fourth insulating layer 40 and the connection electrode CNE can be omitted. The fifth insulating layer 50 can cover the second output electrode SE2, and the anode AE can be directly or indirectly coupled to the second output electrode SE2. According to the present exemplary embodiment, in terms of an equivalent circuit, the second thin film transistor T2 and the organic light emitting diode OLED are directly electrically coupled, however, the disclosure should not be limited thereto or thereby. In an exemplary embodiment of the disclosure, in terms of an equivalent circuit, there can be another thin film transistor between the second thin film transistor T2 and the organic light emitting diode OLED.

[0087] The first thin film transistor included in the display panel according to an exemplary embodiment of the disclosure includes a first barrier pattern under the first control electrode, and the first barrier pattern includes a metal oxide. For example, the first barrier pattern includes gallium oxide and zinc oxide. Because the thin film transistor according to the exemplary embodiment includes a barrier pattern including gallium zinc oxide, even if the oxide semiconductor pattern is formed in a low oxygen partial pressure process, the stability and reliability of the oxide semiconductor pattern can be improved by providing oxygen in a process of forming the barrier pattern formed of gallium zinc oxide on the oxide semiconductor pattern. Accordingly, the conductivity of the oxide semiconductor pattern is increased by the low oxygen partial pressure process, while maintaining the high stability and reliability of the oxide semiconductor pattern.

[0088] Hereinafter, a manufacturing method of a display panel according to an exemplary embodiment of the disclosure will be described with reference to Figures 5A to 5K

[0089] Figures 5A to 5K is a cross-sectional view illustrating a manufacturing method of a display panel according to an exemplary embodiment of the disclosure. Figures 5A to 5E and Figures 5H to 5K illustrates a manufacturing method of a display panel according to an exemplary embodiment of the disclosure. Figure 3 ​corresponding regions. In Figures 5A to 5K the repeated description of elements identical to those described with reference to Figures 1 to 4 the repeated description of elements identical to those described with reference to

[0090] Referring to Figure 5A An inorganic layer is formed on the base layer BL. The inorganic layer is formed by depositing an inorganic material, and in the manufacturing method of the display panel, a plurality of inorganic layers can be formed by sequentially depositing a plurality of inorganic materials. For example, in the manufacturing method of the display panel, the buffer layer BFL can be formed by sequentially forming a silicon oxide layer and a silicon nitride layer.

[0091] As shown in Figure 5A A first preliminary semiconductor pattern PS1-P and a second preliminary semiconductor pattern PS2-P are formed on the buffer layer BFL. The first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P are formed by forming and patterning a semiconductor layer. The semiconductor layer is crystallized before and after the patterning. The first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P are formed of gallium (Ga) oxide, zinc (Zn) oxide, and / or indium (In) oxide. At the time of forming the first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P, the oxygen partial pressure can be equal to or less than about 40%. Since the first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P are formed under the condition that the oxygen partial pressure is equal to or less than about 40%, the electrical properties such as conductivity (e.g., electrical conductivity) of the semiconductor pattern can be improved.

[0092] As shown in Figure 5A A first insulating layer 10 is formed on the buffer layer BFL. The first insulating layer 10 is formed by a deposition, coating, or printing process. The method of forming the first insulating layer 10 can be appropriately or suitably selected depending on the material of the first insulating layer 10. For example, the first insulating layer 10 can be formed by depositing silicon oxide and / or silicon nitride using a chemical vapor deposition (CVD) method.

[0093] Referring to Figure 5B A first preliminary barrier layer BR-P can be formed on the first insulating layer 10 using a metal oxide. The first preliminary barrier layer BR-P can be formed of gallium (Ga) oxide and zinc (Zn) oxide. At the time of forming the first preliminary barrier layer BR-P, zinc doped with gallium can be deposited under the condition that the oxygen partial pressure is equal to or greater than about 60%, so that the first preliminary barrier layer BR-P is formed of gallium zinc oxide (GZO). In the first preliminary barrier layer BR-P, the content of gallium oxide can be about 4 at% to about 8 at%, and the content of zinc oxide can be about 92 at% to about 96 at%.

[0094] Referring to Figure 5CThe first layer CL1 and the second layer CL2 can be formed continuously on the first preliminary barrier layer BR-P. The first layer CL1 and the second layer CL2 can be formed by depositing different metal materials from each other. The first layer CL1 can be formed by depositing titanium (Ti). The second layer CL2 can be formed by depositing copper (Cu). Hereinafter, the first layer CL1 and the second layer CL2 can be referred to as preliminary electrode layers, which form electrodes and wirings through an etching process.

[0095] Referring to Figure 5D The patterned first preliminary barrier layer BR-P, the first layer CL1, and the second layer CL2. When the first preliminary barrier layer BR-P is patterned, the first barrier pattern BR1, the third barrier pattern BR3, and the fourth barrier pattern BR4 are formed. When the first layer CL1 and the second layer CL2 are patterned, the first control electrode GE1, the gate line GL, and the first electrode CE1 are formed. The first preliminary barrier layer BR-P, the first layer CL1, and the second layer CL2 can be patterned by any suitable wet etching method or dry etching method used in the art. The first preliminary barrier layer BR-P, the first layer CL1, and the second layer CL2 can be simultaneously patterned by the same (e.g., substantially the same) etching process.

[0096] In the method of manufacturing the display panel, the barrier pattern is formed of gallium zinc oxide after the semiconductor pattern is formed and before the control electrode is formed. Accordingly, although the oxide semiconductor pattern is formed in a condition of low oxygen partial pressure, the stability and reliability of the oxide semiconductor pattern can be improved by supplying oxygen in a process of forming the barrier pattern of gallium zinc oxide on the oxide semiconductor pattern.

[0097] Referring to Figure 5E The second insulating layer 20 can be formed by depositing an inorganic material or an organic material using a chemical vapor deposition (CVD) method. According to an embodiment, the second insulating layer 20 can be formed by depositing silicon oxide or silicon nitride using a chemical vapor deposition (CVD) method.

[0098] Figure 5F And Figure 5G are enlarged views showing a state of the first insulating layer, the barrier pattern, the first control electrode, and the second insulating layer when the barrier pattern BR1' is formed of a material different from the material of the exemplary embodiment of the disclosure. Figure 5F And Figure 5G show a state when the barrier pattern BR1' is formed of a material containing indium.

[0099] As Figure 5F And Figure 5GAs shown in FIG. 1B, when the barrier pattern BR1' is formed of a material including indium (e.g., indium gallium zinc oxide (IGZO)), indium oxide included in the barrier pattern BR1' can be reduced to indium metal under high-temperature conditions in subsequent processes. For example, when a temperature equal to or greater than about 200 °C is applied in a process of forming the second insulating layer 20 on the barrier pattern BR1' and the first control electrode GE1 by a chemical vapor deposition method, the indium oxide can be reduced to indium metal by hydrogen gas. The reduced indium metal can diffuse to the first control electrode GE1, or can generate voids due to metal particles PT at the interface between the first control electrode GE1 and the first insulating layer 10. Thus, uniformity of the insulating layer can be deteriorated or reduced, and can cause an increased haze.

[0100] In an exemplary embodiment of the present disclosure, the barrier pattern is formed of a material not including indium (e.g., gallium zinc oxide (GZO)), and thus, even if heat is generated in subsequent processes, reduced metal particles are not generated. Thus, deterioration of layer uniformity such as the insulating layer and the occurrence of defects such as haze can be prevented or reduced.

[0101] Referring to Figure 5H A second barrier pattern BR2 and a fifth barrier pattern BR5 are formed on the second insulating layer 20, a second control electrode GE2 is formed on the second barrier pattern BR2, and a second electrode CE2 is formed on the fifth barrier pattern BR5. The second control electrode GE2 and the second electrode CE2 can have a single layer or a multi-layer structure. The second barrier pattern BR2, the second control electrode GE2, the fifth barrier pattern BR5, and the second electrode CE2 can be formed by a process as shown in FIG. 1C. Figures 5B to 5D

[0102] The first control electrode GE1 and the second control electrode GE2 can be used as a mask to dope the first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P. Regions (hereinafter, referred to as "channel regions") overlapping the first control electrode GE1 and the second control electrode GE2, respectively, are not doped, and two adjacent regions (input regions and output regions) of each channel region are doped. In the present exemplary embodiment, the two adjacent regions can be doped with an n-type dopant, such as a pentavalent element (e.g., a five-valent element).

[0103] After this, a heat treatment process can be performed. The first semiconductor pattern PS1 and the second semiconductor pattern PS2 are heat-treated at a temperature of about 400 °C to about 500 °C (e.g., about 450 °C). The dopant can be uniformly (e.g., substantially uniformly) diffused into the input regions and the output regions by the heat treatment process.

[0104] Referring to Figure 5I ​A third insulating layer 30 can be formed on the second insulating layer 20. The third insulating layer 30 can be formed through a deposition, coating, and / or printing process. Then, first to sixth contact holes CH1 to CH6 can be formed. In this case, some portions of the first and second semiconductor patterns PS1 and PS2 exposed through the first to fourth contact holes CH1 to CH4 can be oxidized. A cleaning process can be performed to reduce contact resistance of the first and second semiconductor patterns PS1 and PS2. A cleaning solution can remove silicon dioxide or the like formed around the first to fourth contact holes CH1 to CH4.

[0105] Referring to Figure 5J A conductive pattern is formed on the third insulating layer 30 through a deposition process. The first input electrode DE1, the first output electrode SE1, the second input electrode DE2, the second output electrode SE2, the first connection signal line CNL1, and the second connection signal line CNL2 can be formed. The conductive pattern can have a three-layer structure of Ti / Al / Ti.

[0106] Referring to Figure 5K A subsequent process is performed to complete the display panel. A fourth insulating layer 40 is formed, and a seventh contact hole CH7 is formed. A connection electrode CNE is formed on the fourth insulating layer 40. A fifth insulating layer 50 is formed, and an eighth contact hole CH8 is formed. An organic light emitting diode OLED is formed on the fifth insulating layer 50.

[0107] An anode AE is formed on the fifth insulating layer 50 to be coupled to the connection electrode CNE through the eighth contact hole CH8. A pixel definition layer PDL is formed on the fifth insulating layer 50 to expose a central portion of the anode AE.

[0108] Then, a hole control layer HCL, an organic emitting layer EML, an electron control layer ECL, and a cathode CE are sequentially formed. A thin film encapsulation layer TFE is formed on the cathode CE. An encapsulating organic layer and / or an encapsulating inorganic layer are formed through a deposition process and / or an inkjet printing process.

[0109] Figure 6A is a graph showing electrical characteristics of a transistor of the related art. Figure 6B is a graph showing electrical characteristics of a transistor according to an exemplary embodiment of the present disclosure. Figure 6B Electrical characteristics of a transistor in which a barrier pattern is positioned to overlap a semiconductor pattern and a control electrode is on the barrier pattern are shown. Figure 6A Electrical characteristics of a transistor of the related art from which a barrier pattern is omitted are shown.

[0110] Referring to Figure 6A and Figure 6BSince the transistor according to the example embodiment of the present disclosure includes the barrier pattern overlapping the semiconductor pattern, the stability and reliability of the semiconductor pattern can be improved, and the electrical characteristics of the transistor can be stably maintained. In Figure 6A In the results of the region A, in the case of the existing transistor in which the barrier pattern is omitted, a short circuit occurs in the oxide semiconductor pattern formed at a low oxygen partial pressure, and thus, the current density cannot be measured at a voltage lower than a certain voltage. In the transistor according to the example embodiment of the present disclosure, oxygen can be supplied to the oxide semiconductor pattern in a process of forming the barrier pattern overlapping the semiconductor pattern. Thus, the stability and reliability of the semiconductor pattern can be improved, and a short circuit can be prevented from occurring (or the possibility or degree of such a short circuit can be reduced), so that the electrical characteristics of the transistor can be stably maintained.

[0111] Although the example embodiments of the present disclosure have been described, it should be understood that the present disclosure is not limited to these example embodiments, but various changes and modifications can be made by those having ordinary skill in the art within the spirit and scope of the present disclosure as claimed below.

[0112] Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather the scope of the present disclosure should be according to the appended claims, and their equivalents.

Claims

1. Display panel, including: grassroots level; A first thin-film transistor is located on the substrate; The second thin-film transistor is electrically connected to the first thin-film transistor; as well as A light-emitting element is electrically connected to the second thin-film transistor, wherein the first thin-film transistor includes: A first semiconductor pattern is present on the substrate; A first barrier pattern, on the first semiconductor pattern, and comprising gallium oxide and zinc oxide; and A first control electrode is located on the first blocking pattern and overlaps with the first semiconductor pattern. The content of gallium oxide is 4 at% to 8 at% relative to the total number of atoms in the first blocking pattern, and the content of zinc oxide is 92 at% to 96 at% relative to the total number of atoms in the first blocking pattern.

2. The display panel according to claim 1, further comprising a first insulating layer, the first insulating layer being on the base layer to cover the first semiconductor pattern, wherein, The first insulating layer is located between the first semiconductor pattern and the first barrier pattern.

3. The display panel according to claim 2, wherein, The first insulating layer is in contact with the first semiconductor pattern, the first barrier pattern is in contact with the first insulating layer, and the first control electrode is in contact with the first barrier pattern.

4. The display panel according to claim 2, further comprising a second insulating layer, the second insulating layer being on the first insulating layer to cover the first control electrode, wherein, The second thin-film transistor includes: A second semiconductor pattern is formed on the substrate; A second barrier pattern is formed on the second insulating layer and includes the gallium oxide and the zinc oxide; A second control electrode is located on the second blocking pattern and overlaps with the second semiconductor pattern; and The second input electrode and the second output electrode are connected to the second semiconductor pattern.

5. The display panel according to claim 4, further comprising: A third blocking pattern is formed on the first insulating layer; as well as The gate line is on the third blocking pattern and is electrically connected to the first thin-film transistor.

6. The display panel according to claim 5, further comprising a capacitor electrically connected to the second thin-film transistor, wherein, The capacitor includes: The fourth blocking pattern is on the first insulating layer; The first electrode is on the fourth blocking pattern; The fifth barrier pattern is on the second insulating layer; and The second electrode is on the fifth blocking pattern.

7. The display panel according to claim 6, wherein, The third, fourth, and fifth blocking patterns comprise the same material as the first blocking pattern.

8. Thin-film transistors, including: The first semiconductor pattern includes a channel region and a contact region; A first insulating layer is formed on the first semiconductor pattern; A first barrier pattern is formed on the first insulating layer and includes gallium oxide and zinc oxide; A first control electrode is located on the first blocking pattern and overlaps with the channel region of the first semiconductor pattern; The first input electrode is connected to the contact area of ​​the first semiconductor pattern; as well as The first output electrode is connected to the contact area of ​​the first semiconductor pattern. The content of gallium oxide is 4 at% to 8 at% relative to the total number of atoms in the first blocking pattern, and the content of zinc oxide is 92 at% to 96 at% relative to the total number of atoms in the first blocking pattern.

9. A method for manufacturing a display panel, comprising: Forming semiconductor patterns on the substrate; Barrier patterns are formed on the semiconductor pattern using gallium oxide and zinc oxide; A control electrode is formed on the blocking pattern to overlap with the semiconductor pattern; An input electrode and an output electrode are formed on the substrate, and the input electrode and the output electrode are connected to the semiconductor pattern; as well as Light-emitting elements are formed on the substrate. The content of gallium oxide is 4 at% to 8 at% relative to the total number of atoms in the blocking pattern, and the content of zinc oxide is 92 at% to 96 at% relative to the total number of atoms in the blocking pattern.

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