A low capacitance protection device and a manufacturing method thereof

Abstract

The present invention discloses a low capacitance protection device and a manufacturing method thereof. The device comprises a P-type substrate material (101), a P-type epitaxial layer (102) is arranged on the P-type substrate material (101); a P-type buried layer (103) and a dielectric layer (104) are arranged on the P-type epitaxial layer (102); an N-type diffusion region (105) is arranged on the P-type buried layer (103); an isolation dielectric layer (106) is arranged on the dielectric layer (104) and the N-type diffusion region (105); and a metal region 1 (107) and a metal region 2 (108) are arranged on both sides of the isolation dielectric layer (106). The present invention can reduce capacitance and obtain a lower clamping voltage.

Description

Technical Field

[0001] The invention belongs to the field of electronic science and technology, and mainly relates to the field of integrated circuit electrostatic discharge (ESD) protection, and specifically is a low-capacitance protection device and a manufacturing method thereof. Background Art

[0002] Electrostatic discharge (ESD) is widely present in daily environment. It is the phenomenon that electrostatic charge transfers between two media with different electrostatic potentials. ESD is an over-speed discharge phenomenon. Its instantaneous large current and high voltage can damage IC components or degrade them. ESD can cause latent damage to semiconductor devices, such as increased leakage current and the appearance of logic errors; as well as permanent damage, including PN junction burning, metal layer failure or oxide layer breakdown. No matter what kind of damage, it may cause great losses in production and life, so ESD protection devices are needed to discharge large currents to achieve the purpose of protecting working devices.

[0003] With the advancement of semiconductor technology, the feature size and gate oxide thickness of integrated circuits are constantly decreasing, while the operating frequency is constantly increasing, which puts more stringent requirements on ESD protection devices. ESD protection devices are not only required to meet the requirements of the design window, but also to consider the impact of their parasitic capacitance on the internal circuit. ESD protection devices need to carry a large current when an ESD event occurs, so a larger chip area is required to release heat, which will increase the manufacturing cost of the chip and cause the high-frequency characteristics of the circuit to degrade. For integrated circuits, high-speed signal transmission does not allow signal loss, so the demand for low capacitance is very critical.

[0004] Since ESD pulses appear in both positive and negative directions when they appear on IC pins, it is necessary to consider discharge paths in both directions when designing the protection network. Traditional ESD protection devices can only provide unidirectional protection. At least one protection device needs to be placed in each mode, which takes up a large amount of layout area. In addition, the integration of multiple devices on a single chip will bring other parasitic effects. Therefore, the emergence of bidirectional ESD protection devices is inevitable. The structure of the traditional triode bidirectional ESD protection device is as follows: Figure 2As shown, it includes: P-type single crystal material 109, P-type adjustment area 110, N-type diffusion area 105, isolation dielectric layer 106, metal area 107, and metal area 2 108. Bidirectional ESD protection structure, when metal area 1 107 is added with a positive potential and metal area 2 108 is added with a negative potential, or metal area 2 108 is added with a positive potential and metal area 1 107 is added with a negative potential, the ESD pulse can be discharged through the lateral NPN transistor. In order to reduce the capacitance, the P-type single crystal material 109 adopts high resistivity material. High resistivity will cause the avalanche voltage of the device to increase. In order to reduce the avalanche voltage, a P-type adjustment area 110 with a higher doping concentration is added. The contradiction between low capacitance and low avalanche voltage can be alleviated by a P-type adjustment area with a higher doping concentration, but on this basis, Figure 1 The structure shown can further reduce the capacitance of the bidirectional ESD protection device and obtain a low avalanche voltage.

[0005] The present invention provides an optimization solution, which can provide a low-capacitance protection device and obtain a controllable breakdown voltage and a lower clamping voltage. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a low-capacitance protection device, including a P-type substrate material, a P-type epitaxial layer is arranged on the P-type substrate material; a P-type buried layer and a dielectric layer are arranged on the P-type epitaxial layer; an N-type diffusion region is arranged on the P-type buried layer; an isolation dielectric layer is arranged on the dielectric layer and the N-type diffusion region; and a metal region 1 and a metal region 2 are respectively arranged on both sides of the isolation dielectric layer.

[0007] A method for manufacturing a low capacitance protection device comprises the following steps:

[0008] Step 1: Perform the first epitaxial growth of P-type material on the P-type substrate material.

[0009] Step 2: grow a sacrificial oxide layer on the P-type epitaxial layer, photolithography the P-type buried layer pattern, and perform boron implantation.

[0010] Step 3: Remove the oxide layer and continue the second epitaxial growth of the P-type material. Boron diffuses in the P-type epitaxial layer to form a P-type buried layer.

[0011] Step 4: grow an oxide layer on the P-type epitaxial layer, photolithograph the groove area pattern, and etch the groove. After the groove etching is completed, grow an oxide layer with P-type impurities, perform chemical mechanical polishing, and form a dielectric layer with negative charge.

[0012] Step 5: grow an oxide layer on the P-type epitaxial layer 102, photolithography the preliminary N-type diffusion region 105 pattern, and implant phosphorus and push the junction.

[0013] Step 6: Wet etch the surface oxide layer completely and grow a sacrificial oxide layer. Photolithography of dielectric layer pattern and N-type diffusion region pattern. Phosphorus implantation and junction push to form N-type diffusion region and complete dielectric layer.

[0014] Step 7: Grow an oxide layer on the P-type epitaxial layer, photolithography a dielectric layer pattern with negative charge, and etch the dielectric layer. Deposit an isolation dielectric layer on the front side.

[0015] Step 8: Photolithography on the front side to form the contact hole area. Sputter or evaporate metal. Photolithography on the front side to form the metal area. Alloy.

[0016] Furthermore, the first P-type epitaxial resistivity in step 1 is 0.01-100Ω·cm.

[0017] Furthermore, in step 2, the boron implantation dosage is 1E13-2E15 cm-2, the energy is 30-80 KeV, and the temperature condition of boron push junction is 1000-1250° C., and the time is 30-150 min.

[0018] Furthermore, the second P-type epitaxial resistivity in step three is the same as the first P-type epitaxial resistivity in step one.

[0019] Furthermore, the groove depth in step 4 is 0.5-2 μm.

[0020] Furthermore, the phosphorus implantation dosage in step 5 is 1E14-1E16 cm-2, the energy is 60-120 KeV, and the temperature condition of phosphorus push junction is 1000-1250° C., and the time is 30-150 min.

[0021] Furthermore, the phosphorus implantation dosage in step 6 is 1E13-2E15 cm-2, the energy is 40-80 KeV, and the temperature condition of phosphorus push junction is 950-1250° C., and the time is 25-120 min.

[0022] Furthermore, the isolation dielectric layer in step seven is tetraethoxysilane TEOS, and has a thickness of 5000-10000Å.

[0023] Furthermore, after the contact hole is photolithographically formed in step eight, a layer of TI / TIN is deposited; the metal sputtered or evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 2-4um. The alloy temperature is 300-600°C, and the time is 20-50min.

[0024] The beneficial effects of the present invention are as follows:

[0025] 1. The negatively charged dielectric layer introduced in the present invention can further reduce the capacitance of the bidirectional ESD protection device.

[0026] 2. The capacitance reduction of the present invention can be achieved by adjusting the resistivity of the P-type epitaxial layer to obtain the required capacitance value.

[0027] 3. The P-type buried layer structure of the present invention and the concentration distribution of the N-type diffusion region obtained by two separate injections can adjust the breakdown voltage of the device and reduce the influence of the resistivity of the epitaxial layer on the breakdown voltage.

[0028] 4. The negatively charged dielectric layer introduced in the present invention enables the ESD protection device provided by the present invention to use a higher epitaxial layer resistivity under the same capacitance as the traditional triode structure, thereby obtaining a lower clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a cross-sectional structural diagram of the present invention.

[0030] Figure 2 It is a schematic diagram of the cross-section structure of a traditional bidirectional transistor ESD protection device.

[0031] Figure 3-10 It is a schematic diagram of the production method of the present invention.

[0032] In the figure, 101. P-type substrate material, 102. P-type epitaxial layer, 103. P-type buried layer, 104. dielectric layer, 105. N-type diffusion region, 106. isolation dielectric layer, 107. metal region one, 108. metal region two. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and implementation modes. A detailed description is given by taking a 5V voltage level as an example.

[0034] This implementation case uses a 5V voltage level for detailed explanation.

[0035] like Figure 1 As shown, a low capacitance protection device includes: a P-type substrate material 101, a P-type epitaxial layer 102, a P-type buried layer 103, a dielectric layer 104, an N-type diffusion region 105, an isolation dielectric layer 106, a metal region 107, and a metal region 2 108. A P-type epitaxial layer 102 is disposed on the P-type substrate material 101; a P-type buried layer 103 and a dielectric layer 104 are disposed on the P-type epitaxial layer 102; an N-type diffusion region 105 is disposed on the P-type buried layer 103; an isolation dielectric layer 106 is disposed on the dielectric layer 104 and the N-type diffusion region 105; and metal regions 107 and 108 are disposed on both sides of the isolation dielectric layer 106.

[0036] A method for manufacturing a low capacitance protection device comprises the following steps:

[0037] like Figure 3As shown, a P-type epitaxial layer 102 is first grown on a P-type substrate material 101, and the first P-type epitaxial resistivity is 0.01-100Ω·cm.

[0038] like Figure 4 As shown, a sacrificial oxide layer is grown on the P-type epitaxial layer 102. The P-type buried layer 103 is patterned and boron is implanted. The boron implantation dose is 1E13-2E15cm-2, and the energy is 30-80KeV. The temperature condition of the boron push junction is 1000-1250°C, and the time is 30-150min.

[0039] like Figure 5 As shown, the oxide layer is removed, and the P-type material is grown for the second time, and boron diffuses in the P-type epitaxial layer 102 to form a P-type buried layer 103. The resistivity of the second P-type epitaxial growth is the same as that of the first P-type epitaxial growth in step one.

[0040] like Figure 6 As shown, an oxide layer is grown on the P-type epitaxial layer 102, the groove area pattern is photolithographically formed, and the groove is etched. After the groove etching is completed, an oxide layer with P-type impurities is grown, and chemical mechanical polishing is performed to form a dielectric layer 104 with negative charges. The groove depth is 0.5-2μm.

[0041] like Figure 7 As shown, an oxide layer is grown on the P-type epitaxial layer 102, a preliminary N-type diffusion region 105 pattern is photolithographically formed, and phosphorus is implanted and junction is pushed. The phosphorus implantation dose is 1E14-1E16cm-2, and the energy is 60-120KeV. The temperature condition of phosphorus junction is 1000-1250℃, and the time is 30-150min.

[0042] like Figure 8 As shown, the surface oxide layer is completely wet-etched to grow a sacrificial oxide layer. The dielectric layer 104 pattern and the N-type diffusion region 105 pattern are photolithographically processed. Phosphorus is implanted and the junction is pushed to form the dielectric layer 104 and the complete N-type diffusion region 105. The phosphorus implantation dose is 1E13-2E15cm-2, and the energy is 40-80KeV. The temperature condition of phosphorus push junction is 950-1250℃, and the time is 25-120min.

[0043] like Fig. 9 As shown, an oxide layer is grown on the P-type epitaxial layer 102, a dielectric layer 104 with negative charge is patterned by photolithography, and the dielectric layer is etched. An isolation dielectric layer 106 is deposited on the front side. The isolation dielectric layer 106 is tetraethoxysilane TEOS, and has a thickness of 5000-10000Å.

[0044] like Fig.10As shown, the front side is photolithographically formed into a contact hole area. Metal is sputtered or evaporated. The front side metal is photolithographically formed into a metal area 107 and a metal area 2 108. Alloy. After the contact hole is photolithographically formed, a layer of TI / TIN is deposited. While reducing the contact resistance, the failure rate of metal overheating can be effectively reduced. The metal sputtered or evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 2-4um. The temperature of the alloy is 300-600℃, and the time is 20-50min.

[0045] The bidirectional ESD protection structure provided by the present invention can further reduce the device capacitance. The negatively charged dielectric layer 104 and the N-type diffusion region 105 are of the same charge type, thereby reducing the device capacitance. To further reduce the device capacitance, the N-type diffusion region 105 is injected twice separately to achieve a concentration distribution in which the doping concentration is low on the side close to the isolation dielectric layer 106 and high on the side away from the isolation dielectric layer 106. The surface doping concentration is low, and the junction capacitance is further reduced. In order to reduce the avalanche voltage of the ESD protection device, the surface breakdown point of the device is transferred to the body, and a trenching process is used so that the dielectric layer 104 and the isolation dielectric layer 106 block the breakdown path of the surface PN junction, and the avalanche breakdown point of this structure is transferred to the body. In order to make the avalanche voltage of this low capacitance protection device controllable, a P-type buried layer 103 with a higher doping concentration is used, and the N-type diffusion region 105 with a laterally variable doping also has a high doping concentration above the P-type buried layer 103, so that the peak electric field of the device can be transferred from the surface to the PN junction formed by the P-type buried layer 103 and the N-type diffusion region 105 in the body, and then the breakdown voltage of the device can be adjusted by adjusting the doping concentration of the P-type buried layer 103. The low capacitance bidirectional ESD protection device provided by the present invention further reduces the capacitance of the traditional triode structure ESD protection device, so at the same capacitance level, the ESD protection device provided by the present invention can use an epitaxial layer with a lower resistivity, so when the same current flows, a lower clamping voltage can be obtained. In the low capacitance bidirectional ESD protection device provided by the present invention, when a positive potential is applied to the metal region 1 107 and a negative potential is applied to the metal region 2 108, or a positive potential is applied to the metal region 2 108 and a negative potential is applied to the metal region 1 107, the ESD pulse can be discharged through the lateral NPN triode.

Claims

1. A low capacitance protection device, comprising a P-type substrate material (101), a P-type epitaxial layer (102) arranged on the P-type substrate material (101); a P-type buried layer (103) and a dielectric layer (104) arranged on the P-type epitaxial layer (102); the dielectric layer (104) has a negative charge; an N-type diffusion region (105) is arranged on the P-type buried layer (103); the dielectric layer (104) and the N-type diffusion region (105) are adjacent; an isolation dielectric layer (106) is arranged on the dielectric layer (104) and the N-type diffusion region (105); the isolation dielectric layer (106) covers the P-type epitaxial layer (102), The invention relates to a dielectric layer (104) and an N-type diffusion region (105); a metal region 1 (107) and a metal region 2 (108) are respectively arranged on both sides of the isolation dielectric layer (106); the metal region 1 (107) and the metal region 2 (108) are respectively in contact with an N-type diffusion region (105); the number of P-type buried layers (103) is two, the number of dielectric layers (104) is two, and the number of N-type diffusion regions (105) is two; an N-type diffusion region (105) is arranged on each P-type buried layer (103); and each N-type diffusion region (105) has a dielectric layer (104) adjacent thereto.

2. A method for manufacturing a low capacitance protection device, characterized in that: The following steps are involved: Step 1: performing a first epitaxial growth of a P-type material on a P-type substrate material (101) to form a P-type epitaxial layer (102); Step 2: growing a sacrificial oxide layer on the P-type epitaxial layer (102); photolithography of the P-type buried layer (103) and performing boron implantation; Step 3: remove the oxide layer, continue to perform the second epitaxial growth of the P-type material, and diffuse boron in the P-type epitaxial layer to form a P-type buried layer (103); Step 4, growing an oxide layer on the P-type epitaxial layer, photolithography of the groove area pattern, and etching the groove; after the groove etching is completed, growing an oxide layer with P-type impurities, performing chemical mechanical polishing, and forming a dielectric layer with negative charge (104); Step 5: growing an oxide layer on the P-type epitaxial layer (102), photolithography of the preliminary N-type diffusion region (105), phosphorus implantation, and junction pushing; Step 6: wet-etch the entire surface oxide layer and grow a sacrificial oxide layer; photolithography the dielectric layer pattern and the N-type diffusion region pattern; implant phosphorus and push the junction to form an N-type diffusion region (105) and a complete dielectric layer; Step 7, growing an oxide layer on the P-type epitaxial layer, photolithography of a dielectric layer pattern with a negative charge, etching the dielectric layer; and depositing an isolation dielectric layer (106) on the front side; Step 8: Photolithography on the front side to form a contact hole area; sputtering or evaporating metal; photolithography on the front side to form metal area 1 (107) and metal area 2 (108); alloy.

3. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The first P-type epitaxial resistivity in step 1 is 0.01-100Ω·cm.

4. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The boron implantation dose in step 2 is 1E13-2E15cm-2, and the energy is 30-80KeV; the temperature condition of boron push junction is 1000-1250°C, and the time is 30-150min.

5. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The second P-type epitaxial resistivity in step three is the same as the first P-type epitaxial resistivity in step one.

6. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The groove depth in step 4 is 0.5-2 μm.

7. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The phosphorus implantation dosage in step 5 is 1E14-1E16 cm-2, and the energy is 60-120 KeV; the temperature condition of phosphorus push junction is 1000-1250° C., and the time is 30-150 min.

8. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The phosphorus implantation dosage in step six is ​​1E13-2E15 cm-2, and the energy is 40-80 KeV; the temperature condition of phosphorus push junction is 950-1250° C., and the time is 25-120 min.

9. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: The isolation dielectric layer in step seven is tetraethoxysilane TEOS, and has a thickness of 5000-10000Å.

10. A method for manufacturing a low capacitance protection device according to claim 2, characterized in that: After the contact hole is photolithographically formed in step eight, a layer of TI / TIN is deposited; the metal sputtered or evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper with a thickness of 2-4um; the temperature of the alloy is 300-600°C for 20-50min.

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