Integrated circuit and method for forming the same

Abstract

This case provides an integrated circuit element, including a plurality of metal gates and a plurality of polysilicon gates. Each metal gate has a metal electrode and a high-k dielectric, and each polysilicon gate has a polysilicon electrode and a conventional (non-high-k) dielectric. The polysilicon gate has been improved for operation as a high-voltage gate, which includes a thick dielectric layer and an area greater than 1 μm<supgt;2< / supgt>. The polysilicon gate with these improvements can operate at a gate voltage of 10 V or higher and can be used in embedded memory elements.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit (IC) and a method for forming the same. Background Art

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As ICs have evolved, functional density (i.e., the number of interconnected components per chip area) has increased while feature size has decreased. Other advances include the introduction of embedded memory technology and high-K metal gate (HKMG) technology. Embedded memory technology is the integration of memory elements with logic elements on the same semiconductor chip. Memory elements support the operation of logic elements and improve performance compared to using separate chips for different types of components. High-K metal gate (HKMG) technology is the use of metal gate electrodes and high-K gate dielectric layers to manufacture semiconductor elements. Summary of the invention

[0003] An integrated circuit (IC) according to some embodiments of the present disclosure includes: a plurality of metal gates and a plurality of polysilicon gates. The plurality of metal gates each include a metal electrode and a high-k dielectric; a plurality of polysilicon gates each include a polysilicon electrode, a channel region, and one or more dielectrics spanning from the channel region to the polysilicon electrode; wherein each of the one or more dielectrics of the polysilicon gate has a dielectric constant that is lower than the dielectric constant of any high-k dielectric; and one or more of the polysilicon gates is a high voltage component.

[0004] According to some embodiments of the present disclosure, an integrated circuit (IC) includes: a semiconductor substrate, a memory element, a high-k metal gate, and a polysilicon gate. The semiconductor substrate includes a memory region and a peripheral region; the memory element is formed in the memory region; the high-k metal gate is formed in the peripheral region; and the polysilicon gate is formed in the peripheral region; wherein the polysilicon gate has an area that is larger than an area of ​​the high-k metal gate.

[0005] According to some embodiments of the present disclosure, a method for forming an integrated circuit (IC) includes the following steps: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region; forming a gate oxide layer in the first region; forming a polysilicon layer above the first region and the second region, thereby forming a polysilicon layer above the gate oxide layer; forming a protection layer above the polysilicon layer; masking the first region; selectively removing the protection layer and the polysilicon layer from the second region while masking the first region; forming a high-k dielectric layer above the first region and the second region; forming a dummy electrode layer above the high-k dielectric layer; The invention relates to a method for planarizing a dummy electrode layer and a high-k dielectric layer to form a plurality of dummy gates in a second region and removing the dummy electrode layer and the high-k dielectric layer from a first region; patterning a protective layer and a polysilicon layer to define a plurality of polysilicon gates in the first region; forming a plurality of spacers adjacent to the dummy gates; filling an area adjacent to the spacers; planarizing the first region and the second region; removing the dummy electrode layer from the dummy gates to form a plurality of void areas; depositing metal over the first region and the second region, thereby filling the void areas with metal to form a plurality of high-k metal gates; and planarizing the first region and the second region to remove excess metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of one embodiment of the present disclosure may be better understood from the following detailed description. In accordance with standard industry practice, features are not drawn to scale. In addition, the dimensions of different features within individual drawings may be arbitrarily increased or decreased relative to one another to facilitate illustration or provide emphasis.

[0007] Figure 1 depicts a cross-sectional view of an integrated circuit (IC) according to some aspects of the present disclosure;

[0008] Figures 2 to 52 depicts a series of cross-sectional views of an IC according to some aspects of the present disclosure undergoing a manufacturing process according to some aspects of the present disclosure;

[0009] Fig.53A and Fig.53B A flow chart of a manufacturing process according to some aspects of the present disclosure is presented.

[0010]

Explanation of symbols

[0011] 1...IC components

[0012] 2...Metal wire

[0013] 3... Dielectric

[0014] 5...ILD1 layer

[0015] 7...Control gate electrode

[0016] 9...Siliconized pad

[0017] 11...Control gate spacer

[0018] 13...Control gate dielectric

[0019] 14...Floating gate electrode

[0020] 15...Floating Gate Dielectric

[0021] 17...Siliconized pad

[0022] 18...Erase gate electrode

[0023] 19...Erasing the gate dielectric

[0024] 21...Lightly doped memory source / drain regions

[0025] 22...Selecting the gate dielectric

[0026] 23...Selection gate electrode

[0027] 25...Memory area

[0028] 26...Heavily doped memory source / drain regions

[0029] 27... Implanting memory source / drain regions

[0030] 29...ILD0 layer

[0031] 30...Siliconized pad

[0032] 31...Through hole

[0033] 33...Select gate sidewall spacer

[0034] 34...Siliconized pad

[0035] 38...Second sidewall spacer

[0036] 39...Spacer

[0037] 41...Deep well planting

[0038] 43...Substrate

[0039] 45...High Voltage Gate Dielectric

[0040] 46...High-voltage area

[0041] 47...High voltage gate electrode

[0042] 49...Heavily doped high voltage gate source / drain regions

[0043] 50...Lightly doped high voltage source / drain region

[0044] 51...Siliconized pad

[0045] 57...Metal gate electrode

[0046] 59...Deep well planting

[0047] 62...Core Area

[0048] 63...Lightly doped HKMG source / drain regions

[0049] 65...Heavily doped HKMG source / drain regions

[0050] 68...Oxide dielectric

[0051] 69...High dielectric constant dielectric

[0052] 70...HKMG gate

[0053] 71...High voltage grid

[0054] 73...Split-gate flash memory

[0055] 74...Channel area

[0056] 81...pad oxide layer

[0057] 82...Pad nitride layer

[0058] 84...Oxide layer

[0059] 85...Isolated area

[0060] 86...Nitride capping layer

[0061] 87...Oxide coating

[0062] 90...Memory area

[0063] 91...Surrounding Areas

[0064] 200...Cross-section view

[0065] 201...pad oxide layer

[0066] 202...Pad nitride layer

[0067] 203...Photoresist

[0068] 300...Cross-sectional view

[0069] 400...Cross-section view

[0070] 500...Cross-section view

[0071] 600...Cross-section view

[0072] 700...Cross-section view

[0073] 701...Photoresist

[0074] 800...Cross-section view

[0075] 900...Cross-section view

[0076] 901...Floating gate electrode layer

[0077] 902...Floating gate dielectric layer

[0078] 903...Border Area

[0079] 904...Boundary Isolation Structure

[0080] 1000...Cross-sectional view

[0081] 1100...Cross-section view

[0082] 1101...Control gate dielectric layer

[0083] 1102...Control gate electrode layer

[0084] 1103...Control gate hard mask layer

[0085] 1105...Control Gate Stack

[0086] 1106...lower oxide layer

[0087] 1107...Intermediate nitride layer

[0088] 1108...Oxide layer

[0089] 1110...first nitride layer

[0090] 1111...Oxide layer

[0091] 1112...Second nitride layer

[0092] 1200...Cross-section view

[0093] 1201...Control gate hard mask

[0094] 1203...Photoresist layer

[0095] 1300...Cross-section view

[0096] 1400...Cross-section view

[0097] 1401...Floating gate spacer

[0098] 1500...Cross-section view

[0099] 1501...Photoresist layer

[0100] 1502...Shared source / drain gap

[0101] 1600...Cross-section view

[0102] 1700...Cross-section view

[0103] 1800...Cross-section view

[0104] 1801...Photoresist layer

[0105] 1802...Select gate gap

[0106] 1900...Cross-section view

[0107] 2000...Cross-section view

[0108] 2001...Selecting the gate electrode layer

[0109] 2002...Memory anti-reflective coating

[0110] 2100...Cross-section view

[0111] 2200...Cross-section view

[0112] 2201...Memory select gate hard mask layer

[0113] 2300...Cross-section view

[0114] 2302...Erase gate hard mask

[0115] 2400...Cross-section view

[0116] 2401...Mask

[0117] 2500...Cross-section view

[0118] 2600...Cross-sectional view

[0119] 2700...Cross-section view

[0120] 2701...Memory Overlay

[0121] 2702...Bottom anti-reflective coating

[0122] 2800...Cross-section view

[0123] 2900...Cross-section view

[0124] 2901...Photoresist mask

[0125] 3000...Cross-section view

[0126] 3100...Cross-section view

[0127] 3101...Hard Mask

[0128] 3400...Cross-section view

[0129] 3401...Polysilicon electrode layer

[0130] 3402...High voltage gate hard mask

[0131] 3403...High Voltage Gate Stack

[0132] 3404...Thick gate oxide layer

[0133] 3500...Cross-section view

[0134] 3501...Photoresist

[0135] 3600...Cross-section view

[0136] 3601...Oxide layer

[0137] 3602...High dielectric constant dielectric layer

[0138] 3603...Dummy gate electrode layer

[0139] 3604...Dummy gate hard mask layer

[0140] 3605...Dummy Gate Stack

[0141] 3700...Cross-section view

[0142] 3701...Photoresist

[0143] 3702...Dummy gate electrode

[0144] 3703...Dummy gate

[0145] 3800...Cross-section view

[0146] 3801...Photoresist

[0147] 3802...High voltage gate hard mask

[0148] 3900...Cross-section view

[0149] 4000...Cross-section view

[0150] 4001...Photoresist

[0151] 4100...Cross-section view

[0152] 4101...Photoresist

[0153] 4200...Cross-section view

[0154] 4201...Photoresist

[0155] 4300...Cross-section view

[0156] 4400...Cross-section view

[0157] 4500...Cross-section view

[0158] 4600...Cross-section view

[0159] 4700...Cross-section view

[0160] 4800...Cross-section view

[0161] 4900...Cross-section view

[0162] 5000...Cross-section view

[0163] 5001...Photoresist

[0164] 5002...Gap area

[0165] 5100...Cross-section view

[0166] 5101...Upper surface

[0167] 5102...Upper surface

[0168] 5200...Cross-section view

[0169] 5201...Hard Mask

[0170] 5300...Process

[0171] 5301...Action

[0172] 5302...Action

[0173] 5303...Action

[0174] 5304...Action

[0175] 5305...Action

[0176] 5306...Action

[0177] 5307...Action

[0178] 5308...Action

[0179] 5309...Action

[0180] 5310...Action

[0181] 5311...Action

[0182] 5312...Action

[0183] 5313...Action

[0184] 5314...Action

[0185] 5315...Action

[0186] 5316...Action

[0187] 5317...Action

[0188] 5318...Action

[0189] 5319...Action

[0190] 5320...Action

[0191] 5321...Action

[0192] 5322...Action

[0193] 5323...Action

[0194] 5324...Action

[0195] 5325...Action

[0196] 5326...Action

[0197] 5327...Action

[0198] 5328...Action

[0199] 5329...Action

[0200] 5330...Action

[0201] 5331...Action

[0202] 5332...Action

[0203] 5333...Action

[0204] 5334...Action

[0205] 5335...Action

[0206] 5336...Action

[0207] 5337...Action

[0208] 5338...Action

[0209] 5339...Action

[0210] 5340...Action

[0211] 5341...Action

[0212] 5342...Action

[0213] 5343...Action

[0214] 5344...Action

[0215] 5345...Action

[0216] 5346...Action

[0217] 5347...Action

[0218] 5348...Action

[0219] 5349...Action

[0220] 5350...Action

[0221] 5351...Action

[0222] 5352...Action DETAILED DESCRIPTION

[0223] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are only examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the subsequent description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact.

[0224] Spatially relative terms, such as "under", "below", "lower", "above", "upper" and the like, are used here for ease of description to describe the relationship between an element or feature shown in the figures and another (some) element or (multiple) features. In addition to the directions depicted in the figures, these spatially relative terms are intended to include different directions of the elements or devices in use or operation. The elements or devices may be in different orientations (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein may therefore be interpreted in the same manner. The terms "first", "second", "third", "fourth", etc. are only general identifiers and are therefore interchangeable in different embodiments. For example, when an element (e.g., an opening) may be referred to as a "first element" in some embodiments, the element may be referred to as a "second element" in other embodiments.

[0225] One embodiment of the present disclosure provides a structure and a manufacturing process for incorporating a high voltage component into a component having an HKMG, which includes a component having an embedded memory. The component having an embedded memory may be a split gate flash memory component. In a split gate flash memory component, an array of memory cells is disposed in or above a semiconductor substrate. Peripheral circuitry, including logic components such as an address decoder and / or a read / write circuitry and / or a microcontroller, is disposed outside the memory array and may control the operation of the memory cells and / or perform other tasks. An isolation region having an isolation structure separates the memory array from the peripheral circuitry.

[0226] One embodiment of the present disclosure is particularly related to HKMG elements formed using a replacement gate process or a gate last process, which is a process for depositing the metal of the HKMG electrode after annealing the source / drain region. The source / drain region is doped using a self-aligned process performed after the initial gate formation. The substrate is doped and then annealed, which can be a heat treatment at 1000°C for at least 5 seconds. The high-k dielectric and the metal gate electrode interact under the annealing heat treatment, which changes the threshold voltage of the HKMG gate. The replacement gate process controls the threshold voltage of the HKMG gate by doping the source / drain region, and the doping of the source / drain region is achieved by aligning the dummy gate. The dummy gate has a dummy electrode (which can be polysilicon) that is replaced by the desired gate metal after annealing.

[0227] In the replacement gate process, metal is deposited to fill the area left vacant by the removal of the dummy gate electrode. This metal deposition is followed by chemical mechanical polishing (CMP) to remove the metal deposited outside the gate area. A limitation of this process is that the gate metal is more sensitive to CMP than other materials, which results in recessing that thins the metal gate electrode. Some of this thinning can be offset by recessing the substrate relative to the isolation structure. But the thinning becomes more severe as the gate area increases, which leads to a well-known design limit on the metal gate area. That limit is less than 1 μm. 2 This limitation is an obstacle to the introduction of high voltage components into devices with HKMG gates.

[0228] According to some aspects of the present teachings, the problem of incorporating a high voltage component into a component having a HKMG gate is solved by implementing the high voltage component using a polysilicon gate with a thick gate oxide. The polysilicon gate uses a conventional dielectric that is different from the high-k dielectric. The problem of forming both the high-k dielectric and the conventional dielectric gate is solved by a process comprising the steps of forming a thick gate oxide, depositing a polysilicon electrode layer, covering the polysilicon electrode layer with a hard mask, etching away the layer from the area of ​​the intended HKMG gate, depositing a dummy gate stack, patterning the dummy gate, patterning the polysilicon gate, forming a spacer adjacent to the dummy gate, doping the source / drain region aligned to the spacer, and continuing the replacement gate process. This process allows etching of the high-k dielectric from the polysilicon gate area without damaging the thick oxide.

[0229] Figure 1 A cross-sectional view of selected portions of an IC device 1 according to some aspects of the present teachings is provided. These portions include portions of a memory region 25, portions of a high voltage region 46, and portions of a core region 62, all of which are formed on a substrate 43. The high voltage region 46 includes a high voltage gate 71, the core region 62 includes a high dielectric constant metal gate 70, and the memory region 25 includes a split gate flash memory cell 73. Although the IC device 1 includes the split gate flash memory cell 73 and the process of one embodiment of the present disclosure is compatible with embedded flash memory, one embodiment of the present disclosure is suitable for IC devices without embedded memory.

[0230] The high voltage gate 71 is an element that can operate at a high gate voltage. The high gate voltage can be a voltage greater than 5V. In some of these teachings, the high voltage gate 71 can operate at a gate voltage of 10V or higher. In some of these teachings, the high voltage gate 71 can operate at a gate voltage of 20V or higher.

[0231] The high voltage gate 71 has a thick oxide layer that forms all or part of the high voltage gate dielectric 45. The high voltage gate dielectric 45 may have In some of these teachings, the high voltage gate dielectric 45 may have a thickness of In some of these teachings, the high voltage gate dielectric 45 may have a thickness of or greater thickness. The high voltage gate dielectric 45 may include one or more dielectric layers. The area of ​​the substrate 43 directly below the high voltage gate dielectric 45 is the channel region 74 of the high voltage gate 71. The high voltage gate dielectric 45 includes all layers between the channel region 74 and the high voltage gate electrode 47. According to some of the present teachings, none of the layers in the high voltage gate dielectric 45 is a high dielectric constant dielectric. A high dielectric constant dielectric is a dielectric having a dielectric constant greater than about 7. The IC device 1 may also include a low voltage gate (such as a 5V gate) having the same or similar dielectric and electrode composition as the high voltage gate 71, but with a thinner gate oxide.

[0232] The high voltage gate 71 has a high voltage gate electrode 47 of polysilicon or the like. The high voltage gate electrode 47 may have any suitable thickness. In some of these teachings, the thickness of the high voltage gate electrode 47 ranges from to The high voltage gate 71 can be a large area device. A large area device has a size greater than 1 μm. 2 The area of ​​the high voltage gate electrode 47 is 3 μm. 2 or larger gate area. In some of these teachings, the high voltage gate 71 has a gate area of ​​8 μm 2 or larger gate area.

[0233] The high voltage gate 71 may be formed above the deep well implant 41. The lightly doped high voltage gate source / drain region 50 and the heavily doped high voltage gate source / drain region 49 may provide source / drain regions for the high voltage gate 71 and may be aligned to the spacers 38 and 39, respectively. The heavily doped high voltage gate source / drain region 49 may have a silicide pad 51 on its surface. The silicide pad 34 may also be formed above the high voltage gate electrode 47.

[0234] HKMG gate 70 includes high-k dielectric 69 and metal gate electrode 57. The high-k dielectric may be a metal oxide or silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), etc. Examples of high-k dielectrics include TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4、ZrO 2 and ZrSiO 2 The high dielectric constant dielectric 69 may have a range of about to about In some of these teachings, the high dielectric constant dielectric 69 may have a thickness in the range of about to about The high-k dielectric 69 may be separated from the substrate 43 by an oxide dielectric 68. The oxide dielectric 68 is a non-high-k dielectric. The IC device 1 may include various HKMG gates 70 having oxide dielectrics 68 of different thicknesses. Some HKMG gates may have a thickness ranging from about to about Other HKMG gates may have a thickness ranging from about to about Oxide dielectric 68.

[0235] The upper surface of the metal gate electrode 57 can be aligned with the upper surface of the high voltage gate electrode 47 relative to the distance above the substrate 43. The metal gate electrode 57 can have any suitable thickness. In some of these teachings, the thickness of the metal gate electrode 57 ranges from to The HKMG gate 70 may have a smaller area than the high voltage gate 71. 2 of gate area.

[0236] The HKMG gate 70 may be formed above the deep well implant 59. The lightly doped HKMG source / drain region 63 and the heavily doped HKMG source / drain region 65 may provide source / drain regions for the HKMG gate 70 and may be aligned to the sidewall spacer 39 and the second sidewall spacer 38, respectively. The heavily doped HKMG source / drain region 65 may have a silicide pad 51 on its surface. The HKMG gate 70 may be formed by a gate last process. Therefore, the HKMG gate 70 has not yet been subjected to the conditions required to anneal the implants in the heavily doped HKMG source / drain region 65. If the HKMG gate 70 has been subjected to such conditions, the high-k dielectric 69 and the metal gate electrode 57 will interact in a manner that changes the threshold voltage of the HKMG gate 70.

[0237] Split gate flash memory cell 73 includes floating gate electrode 14 separated from substrate 43 by floating gate dielectric 15, control gate electrode 7 separated from floating gate electrode 14 by control gate dielectric 13, erase gate electrode 18 separated from substrate 43 by erase gate dielectric 19, and select gate electrode 23 separated from substrate 43 and floating gate electrode 14 by select gate dielectric 22. Heavily doped memory source / drain regions 26 are formed in substrate 43 by doping aligned to select gate sidewall spacers 33.

[0238] Different metallization layers may be formed over the split gate flash memory cell 73, HKMG gate 70, and high voltage gate 71. These include a first metallization layer including metal lines 2 formed in a dielectric 3. The dielectric 3 may be a low-k dielectric. Additional metallization layers may be formed over the metallization layers shown. The metallization layers are coupled to the source / drain regions through vias 31. The vias 31 pass through the dielectric layers, which include an ILD0 layer 29 at the height of the split gate flash memory cell 73, HKMG gate 70, and high voltage gate 71, and an ILD1 layer 5 over the split gate flash memory cell 73, HKMG gate 70, and high voltage gate 71.

[0239] The substrate 43 is a semiconductor and may be or otherwise include, for example, a bulk silicon substrate, an SOI substrate, a III-V substrate, and another suitable semiconductor substrate. The substrate 43 may also be a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a high-order semiconductor substrate.

[0240] Figures 2 to 44 A series of cross-sectional views 600 to 4400 are provided, which illustrate an integrated circuit device according to an embodiment of the present disclosure at various stages of a manufacturing process according to an embodiment of the present disclosure. Figures 2 to 44 The description is about a series of actions, but it should be understood that in some cases the order of these actions can be changed and this series of actions is suitable for structures other than the illustrated structure. In some embodiments, some of these actions can be omitted in whole or in part. In addition, Figures 2 to 44 Regarding a series of action descriptions, it should be understood Figures 2 to 44 The structure shown in the figure is not limited to the manufacturing method, but can be used as a separate structure from this method.

[0241] Figure 2 A cross-sectional view 200 is provided, illustrating the initial step of forming a pad oxide layer 201 and a pad nitride layer 202 over a substrate 43. A photoresist 203 may be formed and patterned to cover the pad nitride layer 202 in the peripheral region 91. Figure 3As shown in the cross-sectional view 300, the photoresist 203 can be used to selectively etch the pad nitride layer 202 from the memory region 90. Figure 3 300 further illustrates that after stripping the photoresist 203, an oxidation process may be performed to recess the substrate 43 in the memory region 90. Recessing the substrate 43 in the region 90 allows the top of the split-gate flash memory cell 73 to be aligned with the top of the HKMG gate 70 and the high voltage gate 71, despite the split-gate flash memory cell 73 having a greater height. The oxidation process produces an oxide layer 84. The oxidation process may be a wet oxidation process. Alternatively, the oxidation may be performed using dry oxidation, steam oxidation, or some other suitable process.

[0242] The oxide layer 84 may be thinned to approach the thickness of the pad oxide layer 201, such as Figure 4 The original pad oxide layer 201 and the pad nitride layer 202 may then be stripped and replaced with the pad oxide layer 81 and the pad nitride layer 82, as shown in FIG. Figure 5 The isolation region 85 may then be formed by placing a patterned mask, etching through the pad oxide layer 81, the pad nitride layer 82 and into the substrate 43, and forming an oxide of the isolation region 85 by depositing an oxide or an oxide precursor. After the oxide is formed, chemical mechanical polishing (CMP) may be used to produce the oxide. Figure 5 The cross-sectional view 500 shows a horizontal surface.

[0243] like Figure 6 600, a nitride capping layer 86 and an oxide capping layer 87 may then be formed. The oxide capping layer 87 may be a photoresist protective oxide, or some other suitable type of oxide. Alternative processes that do not include a nitride capping layer 86 or an oxide capping layer 87 are also possible.

[0244] like Figure 7 The cross-sectional view 700 of FIG. 7 illustrates that the photoresist 701 can be used to protect the peripheral area when the pad layer is removed from the memory area 90. The photoresist 701 can then be stripped, followed by the deposition of the floating gate dielectric layer 902 and the floating gate electrode layer 901, and then CMP is performed to remove these layers and the oxide cap layer 87 from the peripheral area 91, as shown in FIG. Figure 8 800 is shown. The floating gate dielectric layer 902 may be any suitable dielectric layer. The floating gate dielectric layer 902 may be grown on the substrate 43 or deposited on the substrate 43. The floating gate electrode layer 901 may be conformally deposited on the floating gate dielectric layer 902 and may be doped polysilicon, etc. The floating gate electrode layer 901 may be formed by CVD, PVD, sputtering, etc.

[0245] like Fig. 9As shown in the cross-sectional view 900 of FIG. 1 , an etching process may be subsequently performed to reduce the floating gate electrode layer 901 to a desired thickness. This etching back may be accomplished using a hydrofluoric acid (HF) soak or the like. Fig. 9 The memory region 90 and the peripheral region 91 are shown separated by a boundary region 903 having a boundary isolation structure 904 . Fig. 9 Memory region 25 is also identified, which is an exemplary region within memory region 90 . Fig. 9 High pressure region 46 and core region 62 are further identified as two exemplary regions within peripheral region 91 that undergo different types of processing. Fig.10 Plot corresponding to Fig. 9 The cross-sectional view 900 is a cross-sectional view 1000 , except that it focuses on only these three aspects, as are the subsequent cross-sectional views.

[0246] like Fig.11 1100, a control gate stack 1105 may be formed above the floating gate electrode layer 901. The control gate stack 1105 includes a control gate dielectric layer 1101, a control gate electrode layer 1102, and a control gate hard mask layer 1103. The control gate dielectric layer 1101 may include one or more layers of oxide, nitride, another suitable dielectric, etc. The control gate dielectric layer 1101 may include multiple different dielectric layers. In some embodiments, the control gate dielectric layer 1101 includes: an ONO film having a lower oxide layer 1106, an intermediate nitride layer 1107 covering the lower oxide layer 1106, and an upper oxide layer 1108 covering the intermediate nitride layer 1107. The control gate dielectric layer 1101 may be formed by CVD, PVD, another suitable deposition process, any combination thereof, etc.

[0247] The control gate dielectric layer 1101 is very thin. The lower oxide layer 1106 may have a thickness in the range of 10 to 100 angstroms. In some embodiments, the lower oxide layer 1106 may have a thickness in the range of 20 to 50 angstroms, for example, about 40 angstroms. The middle nitride layer 1107 may have a thickness in the range of 25 to 200 angstroms. In some embodiments, the middle nitride layer 1107 may have a thickness in the range of 50 to 100 angstroms, for example, about 80 angstroms. The upper oxide layer 1108 may have a thickness in the range of 10 to 100 angstroms. In some embodiments, the upper oxide layer 1108 has a thickness in the range of 20 to 50 angstroms, for example, about 40 angstroms. In some embodiments, the total thickness of the control gate dielectric layer 1101 ranges from 25 to 400 angstroms. In some embodiments, the total thickness of the control gate dielectric layer 1101 ranges from 50 to 200 angstroms.

[0248] The control gate electrode layer 1102 may be conformally formed and may be formed of doped polysilicon or the like. In some embodiments, the process of forming the control gate electrode layer 1102 includes the following steps: depositing a material, implanting a dopant into the material, and annealing to activate the dopant. The material of the control gate electrode layer 1102 may be deposited by CVD, PVD, or another appropriate deposition process. In some embodiments, the control gate electrode layer 1102 has a thickness ranging from 600 to 2000 angstroms. In some embodiments, the control gate electrode layer 1102 has a thickness ranging from 300 to 1000 angstroms. In some embodiments, the control gate electrode layer 1102 has a thickness of approximately 600 angstroms.

[0249] The control gate hard mask layer 1103 may include multiple layers of different materials. The control gate hard mask layer 1103 may include an oxide, a nitride, or other suitable materials. In some embodiments, the control gate hard mask layer 1103 includes an oxide layer 1111 above a first nitride layer 1110. In some embodiments, the thickness of these layers ranges from 100 to 3000 angstroms. In some embodiments, the thickness of these layers ranges from, for example, 200 to 700 angstroms. In some embodiments, these layers are approximately 400 angstroms thick. In some embodiments, the control gate hard mask layer 1103 further includes a second nitride layer 1112 above the oxide layer 1111. The control gate hard mask layer 1103 may be formed by CVD, PVD, another suitable deposition process, any combination of the above, and the like.

[0250] like Fig.12 1200, a selective etch may be performed to remove a portion of the control gate stack 1105 from the memory region 25, thereby forming a control gate hard mask 1201, a control gate electrode 7, and a control gate dielectric 13 above the floating gate layer 901. In some embodiments, the process of performing the selective etch includes forming and patterning a photoresist layer 1203. The photoresist layer 1203 may be patterned to cover the high voltage region 46, the core region 62, and a portion of the memory region 25 to form a negative image of the control gate electrode 7. An etching process may be applied with the photoresist layer 1203 in place until the floating gate electrode layer 901 is exposed. The photoresist layer 1203 may then be stripped.

[0251] like Fig.131300 shows a cross-sectional view of a control gate spacer 11 that can be formed adjacent to the control gate hard mask 1201. The control gate spacer 11 covers the sidewalls of the control gate electrode 7. The control gate spacer 11 can be formed by depositing a layer of spacer material and then etching it. The control gate spacer 11 can have any suitable composition. The control gate spacer 11 can include one or more layers of oxide, nitride, another suitable dielectric, etc. In some embodiments, the control gate spacer 11 includes an ONO film, such as a lower oxide layer, an intermediate nitride layer, and an upper oxide layer. The spacer material can be deposited by CVD, PVD, or another suitable deposition process. The etching process can include plasma etching or any other suitable etching process that selectively removes the thinnest position of the spacer material relative to the vertical plane. For ease of illustration, the control gate spacer 11 is shown as having vertical sidewalls. The etching process for spacer formation can produce rounded corners and smooth tapered sidewalls.

[0252] like Fig.14 1400, the floating gate electrode layer 901 and the floating gate dielectric layer 902 may be etched (see FIG. Fig.13 ) to form the floating gate electrode 14 and the floating gate dielectric 15. The control gate spacer 11 and the control gate hard mask 1201 can act as a mask for this etching. Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a floating gate spacer 1401 may be formed on the sidewalls of the floating gate electrode 14 and the control gate spacer 11. The floating gate spacer 1401 may be an oxide, another suitable dielectric, etc. The process of forming the floating gate spacer 1401 may include the following steps: Fig.14 A floating gate spacer layer is deposited over the structure depicted in cross-sectional view 1400 of FIG. 1 , followed by a plasma etch or any other suitable etch process that selectively removes the floating gate spacer layer at its thinnest relative to the vertical plane. The floating gate spacer layer may be conformally deposited by CVD, PVD, or another suitable deposition process.

[0253] like Fig.15 1500, a lightly doped memory source / drain region 21 may be formed in the substrate 43, laterally between the floating gate electrodes 14. The process of forming the lightly doped memory source / drain region 21 may include the following steps: forming and patterning a photoresist layer 1501, the photoresist layer 1501 covering the high voltage region 46, the core region 62, and the portion of the memory region 25 outside the common source / drain gap 1502. With the photoresist layer 1501 in place, ion implantation or another appropriate doping process may be performed. The photoresist layer 1501 may be patterned using photolithography.

[0254] like Fig.161600, the floating gate spacer 1401 within the common source / drain gap 1502 may be removed. The process for removing the floating gate spacer 1401 may include etching with the photoresist layer 1501 in place. Thereafter, the photoresist layer 1501 may be stripped.

[0255] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , an erase gate dielectric 19 may be formed to cover the memory source / drain regions 21 and the line sidewalls of the floating gate electrode 14 and the control gate spacer 11 within the common source / drain gap 1502. The erase gate dielectric 19 may be formed of an oxide, a nitride, or another suitable dielectric. The process of forming the erase gate dielectric 19 may include high temperature oxidation (HTO), in situ steam generation (ISSG) oxidation, another suitable deposition or growth process, any combination thereof, and the like. In some embodiments, the erase gate dielectric 19 is formed by an oxide deposition process followed by an oxide growth process. In some embodiments, the erase gate dielectric 19 forms a curved or spherical profile due to ion implantation in the memory source / drain regions 21. The central region of the memory source / drain region 21 receives a larger dose of dopants and thus experiences more damage than the edge region of the memory source / drain region 21. The oxide may necessarily grow faster in the central region than in the edge region.

[0256] like Fig.18 1800, a photoresist layer 1801 may be formed to cover the high voltage region 46, the core region 62, and the portion of the memory region 25 outside the select gate gap 1802, and to remove the floating gate spacer 1401 and erase the gate dielectric 1701 from the select gate gap 1802 (see FIG. Fig.17 1700). Fig.19 1900 shows that after removing the photoresist layer 1801, the select gate dielectric 22 may then be formed in the select gate gap 1802. The select gate dielectric 22 may be one or more layers of oxide, nitride, another suitable dielectric, etc. The select gate dielectric 22 may be formed by HTO, ISSG oxidation, another suitable deposition or growth process, any combination thereof, etc.

[0257] Another example Fig. 202000, a select gate electrode layer 2001 may be formed to cover the select gate dielectric 22 and other structures in the high voltage region 46, the core region 62, and the memory region 25. The select gate electrode layer 2001 may be formed of doped polysilicon or another suitable conductive material, and may be formed by CVD, PVD, or another suitable deposition process. Fig. 20 The cross-sectional view 2000 also shows a memory antireflective coating (ARC) 2002 formed above the select gate electrode layer 2001. The memory ARC 2002 can be formed, for example, from a flowable organic material by a spin coating process, wherein the wafer of the substrate 43 is rotated about its center and a liquid ARC coating is applied to the surface of the wafer. Due to its flowability, the liquid ARC coating tends to form a horizontal surface. After the liquid ARC coating is spun on, a baking step can be performed to harden the memory ARC 2002.

[0258] like Fig.21 2100, a process may be performed to remove the memory ARC 2002 (see Fig. 20 ) and thin the select gate electrode layer 2001. This process forms the erase gate electrode 18. The removal and thinning may be performed using an etching process, wherein the memory ARC 2002 and the select gate electrode layer 2001 have approximately equal sensitivity. The memory ARC 2002 may be etched back until the select gate electrode layer 2001 is exposed, after which the select gate electrode layer 2001 and the memory ARC 2002 may be etched back together until the memory ARC 2002 is completely removed. The select gate electrode layer 2001 may then be etched back until its top surface is approximately aligned with the top surface of the control gate electrode 7. The etching process leaves a recessed select gate electrode layer 2001 having a substantially flat surface. Dopants may be implanted into the select gate electrode layer 2001, and then annealed to activate the dopants.

[0259] like Fig. 22 A cross-sectional view 2200 is shown, which may be Fig.21 A memory select gate hard mask layer 2201 is conformally formed over the structure shown in the cross-sectional view 2100 of FIG. The memory select gate hard mask layer 2201 may be formed of nitride, oxide, or another suitable hard mask material. The memory select gate hard mask layer 2201 may be formed by CVD, PVD, or another suitable deposition process.

[0260] like Fig.23 The cross-sectional view 2300 of FIG. 1 shows that etching can be used to select the gate hard mask layer 2201 from the memory. Fig. 22) to form a selection gate hard mask 2301 and an erase gate hard mask 2302. The selection gate hard mask 2301 covers the selection gate electrode 23. The erase gate hard mask 2302 covers the erase gate electrode 18. This etching process does not require a mask. This desired structure can be formed by removing the thinnest part of the memory selection gate hard mask layer 2201 relative to the vertical plane.

[0261] like Fig.24 2400 shows that additional etching can be performed with mask 2401 covering portions of the illustrated memory region 25. This additional etching can terminate the conductive lines formed by some of the illustrated structures in the page direction. This etching can thin the control gate hard mask layer 1103 over the high voltage region 46 and the core region 62.

[0262] like Fig.25 A cross-sectional view 2500 is shown, which may be Fig.24 A second ARC 2501 is formed above the structure shown in the cross-sectional view 2400 of FIG. The second ARC 2501 may be formed to have a flat or substantially flat top surface. The second ARC 2501 may be used in conjunction with a non-selective etch back process to recess the Fig.24 The cross-sectional view 2400 depicts the highest portion of the structure to produce Fig.26 The etch-back process may stop on or in the control gate hard mask layer 1103, the control gate hard mask 1201, and the select gate hard mask 2301. After the etch-back process, the second ARC 2501 may be removed, such as Fig.26 A cross-sectional view 2600 is shown.

[0263] like Fig. 27 A cross-sectional view 2700 is shown, which may be Fig.26 A memory cap layer 2701 is formed over the structure shown in the cross-sectional view 2600 of FIG. 26 , and a bottom anti-reflective coating (BARC) 2702 is formed over the memory cap layer 2701. The memory cap layer 2701 may be polysilicon, but another suitable material may be used. The memory cap layer 2701 may partially conform to the surface it covers. The memory cap layer 2701 may be formed by CVD, PVD, another suitable deposition process, any combination of the above, and the like. The BARC 2702 may be formed by a liquid coating that is spin-coated over the memory cap layer 2701 to provide a flat or substantially flat top surface. After the BARC 2702 is spin-coated, a baking step may be performed to harden the BARC 2702.

[0264] like Fig.28As shown in cross-sectional view 2800, a process may be performed to remove BARC 2702 (see Fig.24 ) and leaves the memory cap layer 2701 with a recess and relatively horizontal surface. The process may be an etch under which the BARC 2702 and the memory cap layer 2701 have very similar etch rates. Initially, the etch continues to penetrate the BARC 2702 until the memory cap layer 2701 is exposed. The etch continues to etch the BARC 2702 and the memory cap layer 2701 simultaneously until the BARC 2702 is completely removed. This etching process may leave the memory cap layer 2701 with a well-defined thickness above the memory region 25.

[0265] like Fig.29 , cross-sectional view 2900 illustrates that in the memory region 25, a photoresist mask 2901 may be formed and patterned over the memory cap layer 2701. Similar to other photoresist masks, the photoresist mask 2901 may be formed by a process including the steps of spin coating or otherwise forming a photoresist on a surface of a structure, selectively exposing the photoresist to light through a master mask or other photolithography mask, and removing exposed or unexposed portions using a chemical developer. With the mask 2901 in place, etching may be performed to remove the control gate electrode layer 1102 and the control gate hard mask layer 1103 from the high voltage region 46 and the core region 62. After etching, the photoresist mask 2901 may be removed. Similar to other photoresist masks, the photoresist 2901 may be removed by full exposure and development, etching, ashing, or any other suitable removal process. As Fig.30 As shown in cross-sectional view 3000 of , additional etching may be performed to remove the control gate dielectric layer 1101 and the nitride capping layer 86 from the high voltage region 46 and the core region 62 .

[0266] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 1 , a hard mask 3101 may be formed over the memory region 25, the high voltage region 46, and the core region 62. The hard mask 3101 may be silicon nitride, oxide, etc. Fig.32 As shown in the cross-sectional view 3200 of FIG. 1 , a photoresist 3201 may be formed and patterned to cover the memory region 25 and the core region 62 while removing the hard mask 3101, the pad oxide layer 81, and the pad nitride layer 82 from the high voltage region 46. Fig.33 3300 shows that the photoresist 3201 can be removed and ion implantation can be performed to form deep well implants 41 in the high voltage region 46.

[0267] like Fig.343400, a high voltage gate stack 3403 may then be formed. The high voltage gate stack 3403 includes a thick gate oxide layer 3404, a polysilicon electrode layer 3401, and a high voltage gate hard mask 3402. The thick gate oxide layer 3404 may be grown from the substrate 43 by a wet or dry oxidation process. Alternatively, the thick gate oxide layer 3404 may be deposited by CVD or the like. The thick gate oxide layer 3404 may also be formed by a combination of oxidation growth and deposition. The polysilicon electrode layer 3401 may be deposited by CVD. Outside the high voltage region 46, the polysilicon electrode layer 3401 may be deposited over the hard mask 3101, which may facilitate the later removal of the polysilicon electrode layer 3401 from these other regions. In some embodiments, dopants may be implanted into the polysilicon electrode layer 3401 and then annealed to activate the dopants. Photoresist masks may be used to allow the dopant type to vary between N-type and P-type, or otherwise allow different doping in different regions and device types. The high voltage gate hard mask 3402 may be formed on the polysilicon electrode layer 3401 and may be formed of nitride, oxide, polysilicon, etc.

[0268] like Fig.35 The cross-sectional view 3500 of FIG. 3 shows that after masking the memory region 25 and the high voltage region 46 with the photoresist 3501, the high voltage gate hard mask 3402, the hard mask 3101, the polysilicon electrode layer 3401, the pad oxide layer 81 and the pad nitride layer 82 can be removed from the core region 62. Fig.35 As further shown in the cross-sectional view 3500 , ion implantation and annealing may then be performed to form deep well implants 59 in the core region 62 .

[0269] like Fig.36 The cross-sectional view 3600 shows that after removing the photoresist 3501, Fig.35 A dummy gate stack 3605 is formed above the structure depicted in the cross-sectional view 3500 of FIG. 3501. The dummy gate stack 3605 may include an oxide layer 3601, a high-k dielectric layer 3602, a dummy gate electrode layer 3603, and a dummy gate hard mask layer 3604. In general, the dummy gate stack dielectric may include any suitable number and combination of dielectric layers, and may be made of thickness and / or composition that varies between different elements in the core region 62. The dummy gate electrode layer 3603 may be polysilicon, etc. or another suitable material. The dummy gate hard mask layer 3604 may be a nitride, an oxide, polysilicon, etc. The layers of the dummy gate stack 3605 may be conformally formed by CVD, PVD, chemical plating, electroplating, another suitable growth or deposition process, any combination of the above, etc. The oxide layer 3601 may be grown on the substrate 43 in particular.

[0270] like Fig.373700, a photoresist 3701 may be used to define a dummy gate 3703 in the core region 62 while removing the oxide layer 3601, the high-k dielectric layer 3602, the dummy gate electrode layer 3603, and the dummy gate hard mask layer 3604 from other locations. This etch forms an oxide dielectric 68 from the oxide layer 3601, a high-k dielectric 69 from the high-k dielectric layer 3602, and a dummy gate electrode 3702 from the dummy gate electrode layer 3603. This process effectively removes the high-k dielectric layer 3602 from areas outside the core region 62. The high-voltage gate hard mask 3402 and the polysilicon electrode layer 3401 protect the thick gate oxide layer 3404 during this process.

[0271] like Fig.38 3800, a cross-sectional view of the process 3800 is shown, where a photoresist 3801 may be formed, patterned, and subsequently used to mask the core region 62 while selectively etching the high voltage gate stack 3403 to form the high voltage gate 71 and remove the high voltage gate stack 3403 from the memory region 25. This etch forms a high voltage gate hard mask 3802 from the high voltage gate hard mask 3402, a high voltage gate electrode 47 from the polysilicon electrode layer 3401, and a high voltage gate dielectric 45 from the thick gate oxide layer 3404. The selective etch may include a series of plasma etches to etch through different layers. The photoresist 3801 may be removed at the end of this process.

[0272] like Fig.39 3900, sidewall spacers 39 may then be formed along the outer sidewalls of the high voltage gate 71 and the dummy gate 3703. The sidewall spacers 39 may be an oxide, a nitride, another suitable dielectric, any combination thereof, or the like. The sidewall spacers 39 may be formed by depositing a spacer material and then etching to remove the spacer material from the thinnest portion thereof. The spacer material may be conformally deposited by CVD, PVD, another suitable deposition process, any combination thereof, or the like. The spacer material may be etched by any suitable etching process to form the sidewall spacers 39.

[0273] like Fig.40 As shown in the cross-sectional view 4000 of FIG. 4 , the photoresist 4001 may then be used to mask the high voltage region 46 and the core region 62 while etching the memory cap layer 2701 from the memory region 25. Dopants may then be implanted to form the memory source / drain region 27 in the memory region 25. Fig.41 4100, the photoresist 4101 can then be used to mask the core region 62 and the memory region 25, while forming the lightly doped high voltage drain region 50 in the high voltage region 46. Fig.42As shown in the cross-sectional view 4200 of , a photoresist 4201 may then be applied to the memory region 25 and the high voltage region 46 , while forming a lightly doped core source / drain region 63 in the core region 62 .

[0274] like Fig.43 4300, a second sidewall spacer 38 may then be formed adjacent to the high voltage gate 71 and the dummy gate 3703. Optionally, select gate sidewall spacers 33 may be simultaneously formed adjacent to the select gate electrode 23. These spacers may be formed by conformally depositing a spacer material and then etching until material is left only where the spacers are needed.

[0275] like Fig.44 4400, a heavily doped memory source / drain region 26, a heavily doped high voltage gate source / drain region 49, and a heavily doped HKMG source / drain region 65 may then be formed in the memory region 25, the high voltage region 46, and the core region 62, respectively. Doping may be performed in a series of steps to provide a range of doping concentrations and different device types while masking different regions and sub-regions. After doping, an anneal may be performed to activate the dopants in the substrate 43. Fig.44 The cross-sectional view 4400 further illustrates that a silicide process may be performed to form silicide pads 30, silicide pads 51, and silicide pads 67 on the heavily doped memory source / drain regions 26, the heavily doped high voltage gate source / drain regions 49, and the heavily doped HKMG source / drain regions 65, respectively. The silicide may be nickel silicide, titanium silicide, cobalt silicide, another silicide, etc., and may be formed by any suitable silicide process.

[0276] like Fig.45 A cross-sectional view 4500 is shown, which may be Fig.44 A contact etch stop layer 8 and a second ARC 4501 are formed on the structure shown in the cross-sectional view 4400 of FIG. The second ARC 4501 may be formed to have a flat or substantially flat top surface. The process of forming the second ARC 4501 may include spin coating an organic ARC coating. Fig.46 A cross-sectional view 4600 is shown, and a process may then be performed to obtain Fig.44 The top layer is removed from the structure depicted in the cross-sectional view 4400 of FIG. This may be a CMP process. However, in some embodiments, the removal is accomplished by etching using a process for which the different materials being removed have similar sensitivities, whereby the top surface remains substantially flat. A suitable etching process may be a dry etch including plasma from a fluorocarbon and He etchant.

[0277] like Fig.47 As shown in the cross-sectional view 4700, the second ARC 4501 may then be removed, followed by forming the ILD0 layer 29. Fig.48 The cross-sectional view 4800 of FIG. 4800 is shown. The ILD0 layer 29 may be an oxide, a low-k dielectric, another suitable dielectric, any combination thereof, etc. The second ARC 4501 may be removed by etching or any other suitable removal process. The process for forming the ILD0 layer 29 may include CVD, PVD, sputtering, or any other suitable process. Fig.49 As shown in cross-sectional view 4900, the ILD0 layer 29 may be planarized and its top surface may be recessed to expose the dummy gate electrode 3702. The planarization and recessing may be accomplished by CMP or any other suitable process or combination of processes.

[0278] like Fig.50 As shown in the cross-sectional view 5000 of FIG. 5 , a photoresist 5001 may be used to cover the memory region 25 and the high voltage region 46 , while etching is performed to remove the dummy gate electrode 3702 , thereby leaving a void region 5002 . Fig.51 5100, a metal gate electrode 57 may then be formed by filling the void region 5002. The filling step may include one or more layers of different metals formed by CVD, PVD, chemical plating, electroplating, or another suitable growth or deposition process. The metal deposited or grown outside the void region 5002 may then be removed by planarization. The planarization process may be CMP, etc.

[0279] like Fig.52 As shown in the cross-sectional view 5200 of FIG. 5 , a hard mask 5201 may be formed and patterned to cover the core region 62 and the control gate electrode 7, while forming a silicide pad 9, a silicide pad 17, and a silicide pad 34 on the select gate electrode 23, the erase gate electrode 18, and the high voltage gate electrode 47, respectively. The silicide may be nickel silicide, another silicide, etc., and may be formed by any appropriate silicide process.

[0280] Additional operations may occur to form Figure 1 This additional operation forms the ILD1 layer 5, the dielectric 3, the via 31, and the metal line 2. These can be formed by any suitable process or combination of processes, such as a damascene process, a dual damascene process, etc.

[0281] Fig.53A and Fig.53BA flow chart of a process 5300 according to some aspects of the present disclosure is provided, which can be used to produce an integrated circuit element according to an embodiment of the present disclosure. Although process 5300 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted as limiting. For example, in addition to those illustrated and / or described herein, some actions may be performed in a different order from other actions and / or synchronously with other actions. In addition, not all of the illustrated actions are necessary for implementing one or more aspects or embodiments described herein. In addition, one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0282] Process 5300 begins at action 5301. Figure 2 The illustrated substrate 43 is formed with a pad layer, which may be a pad oxide layer 201 and a pad nitride layer 202. The process 5300 continues with action 5302, where the pad oxide layer 201 and the pad nitride layer 202 are removed from the memory region 90, such as Figure 3 Action 5303 is to recess the substrate 43 in the memory area 90, as shown in FIG. Figure 3 shown.

[0283] Action 5304 is to remove the pad oxide layer 201 and the pad nitride layer 202. Action 5305 is to form a new pad oxide layer 81 and a new pad nitride layer 82. Figure 5 Action 5306 is to form an isolation region 85, such as Figure 8 Drawing.

[0284] Action 5307 is to form a nitride capping layer 86 and an oxide capping layer 87, such as Figure 6 Action 5308 is to remove the nitride capping layer 86 and the oxide capping layer 87 from the memory region 90, such as Figure 7 Action 5309 is to form a floating gate stack including a floating gate dielectric layer 902 and a floating gate electrode layer 901. Action 5310 is to planarize to remove the floating gate from the peripheral region 91, such as Figure 8 Action 5311 is to thin the floating gate electrode layer 901 to a desired thickness, such as Fig. 9 and Fig.10 Drawing.

[0285] Action 5312 is to form a control gate stack 1105 including a control gate dielectric layer 1101, a control gate electrode layer 1102, and a control gate hard mask 1103, such as Fig.11 Action 5313 is patterning to define a control gate including a control gate dielectric 13, a control gate electrode 7, and a control gate hard mask 1201, such as Fig.12 Action 5314 is to form a control gate spacer 11, such as Fig.13 Drawing.

[0286] Action 5315 is etching to define a floating gate including a floating gate dielectric 15 and a floating gate electrode 14. Action 5316 is forming a floating gate spacer 1401, such as Fig.14 Action 5317 is to dope to provide memory source / drain regions 21 in the memory region 25, such as Fig.15 Drawing.

[0287] Action 5318 is to form an erase gate dielectric 19, such as Fig.17 Action 5319 is to form a select gate dielectric 22, such as Fig.19 Action 5320 is to deposit the select gate electrode layer 2001, such as Fig. 20 Action 5321 is to etch back the selection gate electrode layer 2001 to a height approximately equal to that of the control gate electrode 7 to define the erase gate electrode 18. Fig.21 Drawing.

[0288] Action 5322 is to form a selection gate hard mask layer 2201, such as Fig. 22 Action 5323 is self-aligned etching to define the select gate electrode 23 from the select gate electrode layer 2001, such as Fig.23 Action 5324 is a strip removal etch. This results in thinning of the control gate hard mask 1103 in the high voltage region 46 and the core region 62, as shown in FIG. Fig.24 Action 5325 is to form a second ARC 2501, such as Fig.25 Action 5326 is a planarization etch to reduce the height of the memory stack, such as Fig.26 Action 5327 is to deposit the memory cap layer 2701 and the dummy BARC 2702, such as Fig. 27 Action 5328 is to remove the planarization etching of the dummy BARC 2702, such as Fig.28 Action 5329 is to remove the memory cell stack from the high voltage region 46 and the core region 62, such as Fig.30 Drawing.

[0289] Ongoing Fig.53B Following the flowchart above, process 5300 continues with action 5330 to form hard mask 3101, such as Fig.30 Action 5330 is to form a photoresist and remove the hard mask 3101, the pad nitride layer 82, and the pad oxide layer 81 from the high voltage region 46, as shown in FIG. Fig.32 Action 5331 is to form a deep well implantation in the high pressure area 46, such as Fig.33 Drawing.

[0290] Action 5332 is to form a high voltage gate stack 3403, such as Fig.34 The high voltage gate stack 3403 includes a thick gate oxide layer 3404, a polysilicon electrode layer 3401, and a high voltage gate hard mask 3402. Fig.34 As shown, among these layers, at least a polysilicon electrode layer 3401 and a high voltage gate hard mask 3402 are formed over the hard mask 3101 in the memory region 25 and the core region 62 .

[0291] Action 5333 is to form a photoresist 3501 and remove the high voltage gate stack 3403, the hard mask 3101, the pad nitride layer 82, and the pad oxide layer 81 from the core region 62, such as Fig.35 Action 5334 is to form a deep well in the core area 62, as shown in FIG. Fig.35 Drawing.

[0292] Action 5335 is to form a dummy gate stack 3605, such as Fig.36 The dummy gate stack 3605 may include an oxide layer 3601, a high-k dielectric layer 3602, a dummy electrode layer 3603, and a dummy gate hard mask layer 3604. Fig.36 As shown, among these layers, at least a high-k dielectric layer 3602 , a dummy gate electrode layer 3603 , and a dummy gate hard mask layer 3604 are formed over the high voltage region 46 and the high voltage gate hard mask 3402 in the memory region 25 .

[0293] Action 5336 is patterning to remove the dummy gate stack 3605 from the high voltage region 46 and the memory region 25, while defining the dummy gate 3703 in the core region 62, such as Fig.37 The high voltage gate hard mask 3402 can provide an etch stop for this process.

[0294] Action 5337 is patterning to remove the high voltage gate stack 3403 from the memory region 25 and define the high voltage gate 71 in the high voltage region 46, such as Fig.38 The hard mask 3101 can provide an etch stop for this process.

[0295] Action 5338 is to form a spacer 39 adjacent to the dummy gate 3703 and the high voltage gate 71. Fig.39 Action 5339 is to remove the hard mask 3101 and the memory overlay 2701 from the memory region 25, as shown in FIG. Fig.40 Action 5340 is to implant the memory source / drain region 27, the lightly doped high voltage source / drain region 50, and the lightly doped HKMG source / drain region 63, respectively. Fig.40 , Fig.41 and Fig.42 The number of masking and doping steps depends on the desired number of different source / drain doping types and concentrations.

[0296] Action 5341 is to form a second sidewall spacer 38 and a select gate sidewall spacer 33, such as Fig.43 These spacers may be formed separately or simultaneously. Action 5342 is to implant heavily doped memory source / drain regions 26, heavily doped high voltage gate source / drain regions 49, and heavily doped HKMG source / drain regions 65, such as Fig.44 . In addition, the number of masking and doping steps depends on the required number of different source / drain doping types and concentrations. Action 5342 is annealing. This annealing repairs the damage to the substrate 43 caused by implantation and activation implantation. Action 5343 is silicidation to form silicide pads 30, silicide pads 51, and silicide pads 67 in the memory region 25, the high voltage region 46, and the core region 62, respectively, as shown in FIG. Fig.44 Drawing.

[0297] Action 5344 is to remove the select gate hard mask 2301, the control gate hard mask 1201, and the erase gate hard mask 2302 from the memory region 25. This can be done by depositing a second ARC 4501 (e.g. Fig.45 ) and non-selective etching to recess the resulting surface (e.g. Fig.46 The second ARC 4501 may then be removed, as shown. Fig.47 Drawing.

[0298] Action 5345 is to deposit a first interlayer dielectric layer, ILD0 layer 29, such as Fig.48 This action is followed by action 5346, exposing the dummy gate electrode 3702. This action can be achieved by planarization, such as Fig.49 Action 5347 is to remove the dummy gate electrode 3702, such as Fig.50 Drawing.

[0299] Action 5348 is to deposit and / or grow metal for HKMG gate 70. This action is followed by action 5349, where CMP is performed to remove excess metal, leaving only the metal that forms metal electrode 57, such as Fig.51 This CMP can be performed at 1 μm. 2 After CMP, the upper surface 5101 of the high voltage gate 71 is aligned with the upper surface 5102 of the HKMG gate 70 .

[0300] Action 5350 is to perform silicide to form silicide pads 9, silicide pads 17, and silicide pads 34 on the selection gate electrode 23, the erase gate electrode 18, and the high voltage gate electrode 47, respectively. Fig.52 The mask can be used to prevent silicide from being formed on the control gate electrode 7 .

[0301] Action 5351 is to form a first metal interconnect layer including vias 31, metal lines 2, and ILD1 layer 5, such as Figure 1 Action 5352 is an additional operation to complete the formation of the IC device, including further back-end-of-line (BEOL) processing. It should be understood that process 5300 is a replacement gate process or a gate last process.

[0302] Some aspects of the present teachings relate to an IC including a plurality of metal gates and a plurality of polysilicon gates, each metal gate having a metal electrode and a high-k dielectric, and each polysilicon gate having a polysilicon electrode and a conventional (non-high-k) dielectric. The polysilicon gates are high voltage gates with thick dielectric layers. The polysilicon gates may be adapted to operate at gate voltages of 10V or higher. In some of these teachings, the dielectric of the polysilicon gates is thicker than the dielectric of the metal gates. In some of these teachings, the area of ​​the polysilicon gates is greater than 1 μm. 2 In some of these teachings, the area of ​​the polysilicon gate is greater than 3 μm 2 In some of these teachings, a top surface of the polysilicon electrode is aligned with a top surface of the metal electrode. In some of these teachings, the IC device includes an embedded flash memory. In some of these teachings, the metal gate is a product of a replacement gate process. The metal gate may have a threshold voltage that is changed by a 5 second heat treatment at 1000°C.

[0303] In the IC, the polysilicon gate has an area that is larger than the design limit of the high-k metal gate.

[0304] In the IC, the semiconductor substrate has dopants implanted in source and drain regions, the source and drain regions are operably associated with the high-k metal gate; the source and drain regions have a physical structure resulting from annealing after the implantation of the dopants; and the high-k metal gate has a structure that would not be possible if the high-k metal gate had been subjected to an annealing step.

[0305] In the IC, the polysilicon gate includes a polysilicon electrode, a channel region, and one or more dielectrics spanning from the channel region to the polysilicon electrode; and each of the one or more dielectrics of the polysilicon gate has a dielectric constant that is lower than the dielectric constant of any high dielectric constant dielectric.

[0306] Some aspects of the present teachings relate to an IC including a semiconductor substrate having a memory region and a peripheral region. A memory element is formed in the memory region, and a high-k metal gate is formed in the peripheral region. A polysilicon gate is also formed in the peripheral region. The polysilicon gate has an area that is greater than an area of ​​the high-k metal gate. The polysilicon gate may have an area that is greater than a design limit of the high-k metal gate, which is less than 1 μm. 2 In some of these teachings, a semiconductor substrate is implanted with dopants in source and drain regions operatively associated with a high-k metal gate, and the high-k metal gate has a threshold voltage that will be changed by a minimal thermal treatment that anneals the semiconductor substrate implanted with the dopants. The minimal thermal treatment may be greater than a 5 second thermal treatment at 1000°C.

[0307] Some aspects of the present teachings relate to a method of forming an IC, the method comprising the steps of forming a gate oxide layer in a first region of a substrate, forming a polysilicon layer over each of the first region of the substrate and a second region of the substrate, and forming a protective layer over the polysilicon layer. While masking the first region, removing the protective layer and the polysilicon layer from the second region. Subsequently forming a high-k dielectric layer and a dummy electrode layer over the first region and the second region. Subsequently patterning the dummy electrode layer and the high-k dielectric layer to form a dummy gate in the second region and removing the dummy electrode layer and the high-k dielectric layer from the first region. Subsequently patterning the protective layer and the polysilicon layer to define a polysilicon gate in the first region. Forming spacers adjacent to the dummy gate. After filling the adjacent spacers, planarizing the first region and the second region. Then removing the dummy electrode layer from the dummy gate and replacing it with metal. Then planarizing the first region and the second region to remove excess metal.

[0308] In some of these teachings, a hard mask is formed over the dummy electrode layer before patterning the dummy electrode layer and the high-k dielectric layer to form the dummy gate. In some of these teachings, a hard mask is formed and selectively removed from the first region before forming the gate oxide layer. In some of these teachings, source / drain regions are implanted after forming the spacers, and the implanted regions are annealed before replacing the dummy electrode layer with metal. After planarizing the first region and the second region to remove excess metal, a silicidation process is performed on the polysilicon gate. In some of these teachings, the method further includes the step of forming a flash memory element in a third region of the substrate.

[0309] In the method described, each polysilicon gate has a thickness greater than 1 μm 2 area.

[0310] In the described method, the polysilicon gate can be operated as a high voltage gate.

[0311] In the method described herein, the gate oxide has a thickness suitable for a gate voltage of 10 V or more.

[0312] The features or examples of several embodiments are summarized above so that those skilled in the art can better understand the aspects of an embodiment of the present disclosure. Those skilled in the art should understand that an embodiment of the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present disclosure, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. An integrated circuit, It is characterized in that include: A semiconductor substrate including a memory region and a peripheral region; a memory device in the memory area; A plurality of metal gates, each comprising a metal electrode and a high-k dielectric in the peripheral region; as well as A plurality of polysilicon gates, each of which includes a polysilicon electrode, a channel region, and one or more dielectrics extending from the channel region to the polysilicon electrode in the peripheral region; wherein each of the one or more dielectrics of the polysilicon gates has a dielectric constant that is lower than a dielectric constant of any high-k dielectric; An area of ​​the polysilicon electrode is larger than an area of ​​the metal electrode; A top surface of the polysilicon electrode is flush with a top surface of the metal electrode; and One or more of the polysilicon gates is a high voltage device.

2. The integrated circuit according to claim 1, It is characterized in that The memory device is an embedded flash memory.

3. The integrated circuit according to claim 1, It is characterized in that The one or more dielectrics have a thickness that is greater than a thickness of the high-k dielectric.

4. The integrated circuit according to claim 1, It is characterized in that Each of the polysilicon gates has a thickness greater than 1 μm 2 An area of ​​.

5. The integrated circuit according to claim 1, It is characterized in that The high-k dielectrics and the metal gate electrodes of the metal gates have multiple compositions and multiple structures, so that the gate voltages of the metal gates are changed by a 5-second thermal treatment at 1000° C.

6. The integrated circuit according to claim 1, It is characterized in that The polysilicon gates have a dielectric thickness suitable for operation at a gate voltage of 10V or higher.

7. An integrated circuit, It is characterized in that include: A semiconductor substrate including a memory region and a peripheral region; a memory element formed in the memory region; A high-k metal gate is formed in the peripheral region; and a polysilicon gate formed in the peripheral region; The polysilicon gate has an area that is larger than an area of ​​the high dielectric constant metal gate; A top surface of the polysilicon gate is flush with a top surface of the high dielectric constant metal gate.

8. The integrated circuit according to claim 7, It is characterized in that The polysilicon gate has an area that is larger than a design limit of the high-k metal gate.

9. The integrated circuit according to claim 7, Features: The semiconductor substrate is implanted with dopants in a source and drain region, the source and drain regions being operatively associated with the high-k metal gate; The source and drain regions have physical structures produced by annealing after implanting the dopant; as well as The high-k metal gate has a structure that would not be possible if the high-k metal gate had been subjected to the annealing step.

10. The integrated circuit according to claim 7, Features: The polysilicon gate includes a polysilicon electrode, a channel region, and one or more dielectrics extending from the channel region to the polysilicon electrode; and Each of the one or more dielectrics of the polysilicon gate has a dielectric constant that is lower than a dielectric constant of any high-k dielectric.

11. The integrated circuit according to claim 7, It is characterized in that The polysilicon gate has a thickness greater than 1 μm 2 An area of ​​.

12. A method of forming an integrated circuit, It is characterized in that The following steps are involved: A semiconductor substrate is provided, the semiconductor substrate comprises a memory region and a peripheral region, the peripheral region comprises a first region and a second region; forming a gate oxide layer in the first region; forming a polysilicon layer over the first region and the second region, thereby forming the polysilicon layer over the gate oxide layer; forming a protective layer on the polysilicon layer; masking the first area; selectively removing the protective layer and the polysilicon layer from the second region while masking the first region; forming a high-k dielectric layer over the first region and the second region; forming a dummy electrode layer above the high-k dielectric layer; patterning the dummy electrode layer and the high-k dielectric layer to form a plurality of dummy gates in the second region and removing the dummy electrode layer and the high-k dielectric layer from the first region; patterning the protection layer and the polysilicon layer to define a plurality of polysilicon gates in the first region; forming a plurality of spacers adjacent to the dummy gates; filling an area adjacent to the spacers; planarizing the first region and the second region; removing the dummy electrode layer from the dummy gates to form a plurality of void regions; Depositing metal over the first region and the second region, whereby the metal fills the gap regions to form a plurality of high dielectric constant metal gates; as well as planarizing the first region and the second region to remove excess metal; wherein the first region and the second region are planarized to remove excess metal so that multiple top surfaces of the high-k metal gates are flush with multiple top surfaces of the polysilicon gates; Areas of the polysilicon gates are larger than surfaces of the high-k metal gates; and A memory device is formed in the memory area.

13. The method according to claim 12, It is characterized in that Further comprising the steps of: Before patterning the dummy electrode layer and the high-k dielectric layer to form a dummy gate, a hard mask is formed over the dummy electrode layer.

14. The method according to claim 12, It is characterized in that Further comprising the steps of: After planarizing the first region and the second region to remove excess metal, a silicide process is performed on the polysilicon gates.

15. The method according to claim 12, It is characterized in that Each of the polysilicon gates has a thickness greater than 1 μm 2 An area of ​​.

16. The method according to claim 12, It is characterized in that The polysilicon gates may operate as high voltage gates.

17. The method according to claim 12, It is characterized in that The gate oxide has a thickness suitable for a gate voltage of 10V or higher.

18. The method according to claim 12, It is characterized in that The memory device is a flash memory element.

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