Memory and reference signal generating circuit thereof

Abstract

The present invention provides a memory data reading sensing circuit, the memory comprises a plurality of memory cells arranged in an array and reference cells arranged in an array, wherein the reference cells comprise a first reference cell and a second reference cell, the data reading sensing circuit comprises an integrated operational amplifier, the bit lines of the first reference cell and the second reference cell are commonly connected to an input end of the integrated operational amplifier, the output end of the integrated operational amplifier is connected to another input end of the operational amplifier, the output end of the integrated operational amplifier and the bit line of a column of the memory cell to be read are respectively input into a voltage comparator to judge the data stored in the memory cell through the output signal of the voltage comparator.

Description

Technical Field

[0001] The invention relates to the field of memory, in particular to a reference signal generating circuit of a read-write control circuit of the memory. Background Art

[0002] There are various types of existing memories, such as DRAM memory, Flash memory, magnetic memory, RRAM memory, and ferroelectric memory, etc. Among them, ferroelectric memory is a non-volatile memory that uses ferroelectric materials as storage media, which has the advantages of low power consumption, fast writing performance, and high maximum read / write endurance.

[0003] The existing ferroelectric memory cells usually have 2T2C structure and 1T1C structure. The 2T2C structure is that each memory cell includes two paired memory cells composed of transistors and capacitors, and the two memory cells store two opposite data as reference signals. The 1T1C structure is that each memory cell includes a memory cell composed of a transistor and a capacitor, and the data stored in each memory cell is compared with an additional reference signal to determine the data stored in the memory cell.

[0004] like Figure 1 As shown, the existing 1T1C structured ferroelectric memory includes a ferroelectric memory cell and a reference cell, wherein the reference cell includes a column of reference cells storing data "1" and a column of reference cells storing data "0". Figure 2 As shown, it shows the reference signal generating circuit of the existing 1T1C structure memory. As shown in the figure, the bit line BLref1 of the reference cell storing data "1" and the bit line BLref0 of the reference cell storing data "0" are connected to the node nb through transistors T1 and T0 respectively, and the node nb is connected to one input end of the voltage comparator. The bit line BLx of the storage cell to be read is connected to the node na through a transistor Tx, and the node na is connected to the other input end of the voltage comparator. The data stored in the read storage cell is judged by comparing the voltage of the node na with the voltage of the reference cell nb node. In this read data comparison circuit, the bit line BLx of the storage cell to be read is not directly input into the voltage comparator, but is input into the voltage comparator through the node na of the circuit composed of transistors Tx. This increases the complexity of the circuit, and the voltage of the node na may not match the bit line voltage, which will cause the loss of read capacity. Moreover, the existing reference signal generating circuit cannot obtain the equivalent average value of BL1 and BL0, and because the bit line of the storage cell is only connected to the input end of one voltage comparator, and the reference signal generating circuit needs to be connected to the input ends of multiple voltage comparators, the bit line voltage of the storage cell cannot match the bit line voltage of the reference cell, so the comparison result may be biased.

[0005] Therefore, it is necessary to propose a new reference signal generating circuit and a read sensing circuit to overcome the above-mentioned defects of the prior art. Summary of the invention

[0006] The object of the present invention is to provide a reference signal generating circuit which can generate an accurate and stable reference signal.

[0007] Another object of the present invention is to provide a memory read sensing circuit, which can improve the accuracy of sensing

[0008] Another object of the present invention is to provide a memory having a stable reference signal and a more reliable read sensing circuit.

[0009] Another object of the present invention is to provide an input voltage averaging circuit, which can calculate the average value of any input voltage.

[0010] To achieve the above-mentioned object, the present invention provides a memory reference voltage generating circuit, which comprises:

[0011] a first reference unit storing first data;

[0012] a second reference unit storing second data;

[0013] An integrated operational amplifier comprising a first input terminal, a second input terminal and an output terminal;

[0014] The bit line of the first reference unit and the bit line of the second reference unit are connected to the first input terminal of the integrated operational amplifier, the output terminal of the integrated operational amplifier is connected to the second input terminal to form a follower circuit, and the output signal of the integrated operational amplifier is the average value of the input signal of the first input terminal.

[0015] According to an embodiment of the present invention, a memory reference voltage generating circuit, wherein the integrated operational amplifier circuit comprises: a plurality of first input terminals, each of which is connected to an input transistor, and the input voltage is connected to the input electrode of the input transistor; a plurality of second input terminals, each of which is connected to an output transistor; the input transistors are connected in parallel with the output transistors, and the input electrodes of the output transistors are connected to the output terminals of the integrated operational amplifier circuit.

[0016] According to an embodiment of the present invention, a memory reference voltage generating circuit is provided, wherein the integrated operational amplifier comprises a first Pmos transistor (P0), (P1) connected to a first input terminal, a second Pmos transistor (P2), (P3) connected to a second input terminal, one end of the first Pmos transistor and the second Pmos transistor are commonly connected to a first node (J1), a third PMOS transistor (P4) is connected between the first node and a power supply voltage, the other end of the first Pmos transistor is grounded via a first Nmos transistor (N0), the other end of the second Pmos transistor is grounded via a second Nmos transistor (N1), the gates of the first Nmos transistor and the second Nmos transistor are commonly connected to the same node (J4), a third NMOS transistor (N2) is connected between the node where the first Pmos transistor and the first Nmos transistor are connected and an output terminal, the output node is connected to the gate of the second PMOS transistor, and a fourth PMOS transistor (P5) is connected between the output node and the power supply voltage.

[0017] According to a memory reference voltage generating circuit of one embodiment of the present invention, the first PMOS transistor includes two, the gate of each transistor is respectively connected to the bit line of the first reference unit and the bit line of the second reference unit, and the second PMOS transistor includes two, the gate of each transistor is commonly connected to the output node.

[0018] To achieve the aforementioned another object, the present invention provides a memory read sensing circuit, which comprises:

[0019] An integrated operational amplifier having a plurality of first input terminals, a plurality of second input terminals and an output terminal, wherein the first input terminal is connected to a reference signal, and the output terminal is connected to the second input terminal to form a follower circuit, and the output signal of the integrated operational amplifier is an average value of the input signal of the first input terminal;

[0020] The voltage comparator comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a bit line signal of a memory storage unit, and the second input terminal is connected to the output terminal of an operational amplifier.

[0021] According to one embodiment of the present invention, a memory read sensing circuit further includes a reference signal generating circuit, wherein the reference signal generating circuit includes a reference unit, the reference unit includes a first reference unit storing first data and a second reference unit storing second data, wherein a bit line of the first reference unit and a bit line of the second reference unit are connected to a first input terminal of the integrated operational amplifier.

[0022] According to an embodiment of the present invention, a memory reference voltage generating circuit is provided, wherein the integrated operational amplifier comprises a first Pmos transistor (P0), (P1) connected to a first input terminal, a second Pmos transistor (P2), (P3) connected to a second input terminal, one end of the first Pmos transistor and the second Pmos transistor are commonly connected to a first node (J1), a third PMOS transistor (P4) is connected between the first node and a power supply voltage, the other end of the first Pmos transistor is grounded via a first Nmos transistor (N0), the other end of the second Pmos transistor is grounded via a second Nmos transistor (N1), the gates of the first Nmos transistor and the second Nmos transistor are commonly connected to the same node (J4), a third NMOS transistor (N2) is connected between the node where the first Pmos transistor and the first Nmos transistor are connected and an output terminal, the output node is connected to the gate of the second PMOS transistor, and a fourth PMOS transistor (P5) is connected between the output node and the power supply voltage.

[0023] According to a memory reference voltage generating circuit of one embodiment of the present invention, the first PMOS transistor includes two, the gate of each transistor is respectively connected to the bit line of the first reference unit and the bit line of the second reference unit, and the second PMOS transistor includes two, the gate of each transistor is commonly connected to the output node.

[0024] To achieve the aforementioned further object, the present invention provides a memory, comprising:

[0025] A plurality of storage units arranged in an array, each storage unit being used to store data;

[0026] Reference cells arranged in an array, wherein the reference cells include a first reference cell and a second reference cell;

[0027] The data reading sensing circuit includes an integrated operational amplifier and a voltage comparator. The bit lines of the first reference unit and the second reference unit are commonly connected to an input terminal of the integrated operational amplifier. The output terminal of the integrated operational amplifier is connected to another input terminal of the integrated operational amplifier. The output signal of the integrated operational amplifier is the average value of the input signal of the first input terminal. The output terminal of the integrated operational amplifier and the bit line of the storage unit are respectively input to the input terminal of the voltage comparator. The data stored in the storage unit can be judged by the output signal of the voltage comparator.

[0028] In a memory according to an embodiment of the present invention, a plate line of a memory cell and a plate line of a reference cell are connected to the same plate line.

[0029] In a memory according to an embodiment of the present invention, a plate line of a memory cell and a plate line of a reference cell are connected to different plate lines.

[0030] To achieve the aforementioned further object, the present invention provides an input voltage averaging integrated operational amplifier circuit, which comprises:

[0031] A plurality of positive input terminals, each of which is connected to an input transistor, and an input voltage is connected to an input electrode of the input transistor;

[0032] A plurality of negative input terminals, each of which is connected to an output transistor;

[0033] The input transistor and the output transistor are connected in parallel correspondingly, and the input electrode of the output transistor is connected to the output end of the integrated operational amplifier circuit.

[0034] According to an embodiment of the present invention, an input voltage averaging integrated operational amplifier circuit comprises a first Pmos transistor (P0), (P1) connected to a first input terminal, a second Pmos transistor (P2), (P3) connected to a second input terminal, one end of the first Pmos transistor and the second Pmos transistor are commonly connected to a first node (J1), a third PMOS transistor (P4) is connected between the first node and a power supply voltage, the other end of the first Pmos transistor is grounded via a first Nmos transistor (N0), the other end of the second Pmos transistor is grounded via a second Nmos transistor (N1), the gates of the first Nmos transistor and the second Nmos transistor are commonly connected to the same node (J4), a third NMOS transistor (N2) is connected between the node where the first Pmos transistor and the first Nmos transistor are connected and an output terminal, the output node is connected to the gate of the second PMOS transistor, and a fourth PMOS transistor (P5) is connected between the output node and the power supply voltage.

[0035] The input voltage averaging circuit of the present invention can calculate the average value of any input voltage. The reference signal generating circuit of the present invention can obtain a stable average value of two or more input reference signals. In the read sensing circuit of the present invention, the bit line of the storage unit read is directly connected to the input end of the voltage comparator, which can reduce the voltage loss of the bit line voltage sensing and improve the accuracy of detection. Because the reference signal generating circuit can generate a stable reference signal, there is no situation where the voltage of the bit line of the storage unit and the bit line of the reference unit do not match, so the reference signal can be connected to the voltage comparators of any number of storage units. In addition, the word line and plate line of the reference unit of the present invention are separated from the word line and bit line of the storage unit and are separately set, so that the reference signal can be generated earlier than the signal read from the storage unit, which can avoid the delay during comparison and read the data stored in the storage unit more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1It is a circuit structure diagram of a memory with a 1T1C structure.

[0037] Figure 2 The invention is a schematic diagram of the structure of an existing memory reference signal generating circuit and a read sensing circuit.

[0038] Figure 3 FIG. 4 is a schematic diagram of a circuit structure of a memory according to an embodiment of the present invention.

[0039] Figure 4 4 is a schematic diagram of the structure of a reference signal generating circuit according to an embodiment of the present invention.

[0040] Figure 5 FIG. 4 is a schematic diagram comparing a single input signal circuit and two input signal circuits of a reference signal generating circuit according to an embodiment of the present invention.

[0041] Figure 6 The diagram is a comparison diagram of a single input signal circuit and multiple input signal circuits of a reference signal generating circuit according to an embodiment of the present invention.

[0042] Figure 7 It is a schematic diagram of the circuit structure of a memory according to an embodiment of the present invention, wherein the word lines and plate lines of the storage unit and the reference unit are separately arranged. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments may be implemented without one or more of the specific details or with other alternative and / or additional methods or components. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0045] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0046] The present invention may be related to memory, in particular to ferroelectric memory. Figure 3 As shown, it is a circuit diagram showing a partial structure of the ferroelectric memory of the present invention. According to one embodiment of the present invention, the ferroelectric memory includes a storage unit for storing data and a reference unit for generating a reference signal, and the specific data stored in the storage unit is determined by comparing the reference signal with the data stored in the storage unit.

[0047] According to an embodiment of the present invention, the memory may include a plurality of storage areas, each storage area includes a plurality of storage blocks, and each storage block may include a plurality of identical storage cells arranged in an array. To simplify the description, the figure only shows two rows and two columns of storage cells in the storage cell area by way of example. In actual products, storage cells in different rows and columns may be provided according to the capacity of the memory.

[0048] like Figure 3 As shown, according to one embodiment of the present invention, each memory cell of the memory of the present invention includes a transistor and a ferroelectric capacitor, wherein the transistor is a CMOS transistor, which includes a gate, a source and a drain, and the source or drain of the transistor is connected to a plate of the ferroelectric capacitor. The gates of the transistors of the memory cells in the same horizontal row are connected to the same word line wl. As shown in the figure, the gates of the transistors T0 of the memory cell Cell0 and the transistor T1 of the memory cell Cell1 of the two memory cells in the first row are connected to the word line wl0. The gates of the transistors T2 of the memory cell Cell2 and the transistor T3 of the memory cell Cell3 of the two memory cells in the second row are connected to the word line wl1. The sources of the transistors of the memory cells in the same vertical column are connected to the same bit line bl. As shown in the figure, the sources of the transistors of the memory cells Cell0 and the memory cell Cell2 of the two memory cells in the first column are connected to the bit line bl0. The sources of the transistors of the memory cells Cell1 and Cell3 of the two memory cells in the second column are connected to the bit line bl1. As shown in the figure, in this embodiment, the plates of the ferroelectric capacitors Ccell0 , Ccell1 , Ccell2 , and Ccell3 of the memory cells that are away from the transistors are commonly connected to the same common plate line PL.

[0049] Continue reading Figure 3As shown, each storage unit area of ​​the memory of the present invention also includes a reference unit area corresponding to the storage unit and providing a reference signal. In this embodiment, the reference unit area includes two columns, one of which is a reference unit storing data "1", and the other is a reference unit storing data "0". Each reference unit also includes a transistor and a ferroelectric capacitor, wherein the transistor is a CMOS transistor, which includes a gate, a source and a drain, and the source or drain of the transistor is connected to a plate of the ferroelectric capacitor. The gates of the transistors of the reference units in the same horizontal row and the gates of the transistors of the storage units in the same row are connected to the same word line wl. As shown in the figure, the gates of the transistors T4 and T5 of the two reference units Cellr1 and Cellr0 in the first row are connected to the word line wl0, and the gates of the transistors T6 and T7 of the two reference units Cellr2 and Cellr3 in the second row are connected to the word line wl1. The sources of the transistors of the reference cells in the same vertical column are connected to the same bit line bl. As shown in the figure, the sources of the transistors of the two reference cells Cellr1 and Cellr2 in the first column are connected to the bit line blref1, which is used to store data "1". The sources of the transistors of the two reference cells Cellr0 and Cellr3 in the second column are connected to the bit line blref0, which is used to store data "0". As shown in the figure, in this embodiment, the plates of the ferroelectric capacitors Cref1 and Cref0 of the reference cells away from the transistors are connected to the same common plate line PL.

[0050] Please continue reading Figure 3 As shown, the memory of the present invention also includes a reference signal generating circuit, and the reference signal generating circuit includes an integrated operational amplifier OA. The integrated operational amplifier OA includes a first input terminal (Vino, Vin1), a second input terminal (D0, D1) and an output terminal Vout. The specific structure of the integrated operational amplifier OA will be described in detail later. The bit lines blref1 and blref0 of the reference unit are respectively input to the first input terminals Vin1 and Vin0 of the integrated operational amplifier, and the output terminal Vout of the integrated operational amplifier is connected to the second input terminals D0 and D1 of the integrated operational amplifier.

[0051] The memory of the present invention further includes a voltage comparator, and each column of storage cells is provided with a corresponding voltage comparator, wherein the bit line of each column of storage cells is connected to an input terminal of the voltage comparator, and the output terminal of the integrated operational amplifier of the reference signal generating circuit is connected to the other input terminal of the voltage comparator corresponding to each column of storage cells. Figure 3As shown, the bit line bl0 of the first column of memory cells is connected to one input terminal of the voltage comparator comp0, and the bit line bl1 of the second column of memory cells is connected to one input terminal of the voltage comparator comp1. The output terminal Vout of the integrated operational amplifier OA of the reference signal generation circuit is respectively connected to the other input terminals of the voltage comparators comp0 and comp1.

[0052] When reading the data stored in the memory cells, the row decoder (not shown) and the column decoder (not shown) of the memory respectively output decoding signals to determine the address of the memory cells to be read. For example, when reading the data stored in the memory cell Cell0, the control circuit (not shown) of the memory controls the word line wl0 to input a high level according to the selected memory cell. The gate of the transistor T0 of the memory cell Cell0 is turned on, while the word lines wl1 of the rows of the unselected memory cells are at a low level. Therefore, the transistors T2 and T3 of the memory cells in the first row are not turned on. Then the control circuit controls the plate line PL connected to the plate of the capacitor Ccell0 of the memory cell Cell0 to input a high level Vpl. Since the transistor T0 of the selected memory cell Ccell0 is turned on, the bit line bl0 connected to the transistor T0 of the memory cell Ccell0 is equivalent to being connected to one plate of the capacitor Ccell0 of the memory cell. When a high level Vpl is input to the other plate PL of the capacitor, the bit line voltage Vbl0 of the bit line bl0 = Vpl*Ccell0 / (Ccell0 + Cbl0), where Ccell0 is the capacitance value of the capacitor Ccell0, and Cbl0 is the parasitic capacitance of the entire bit line bl0.

[0053] Then, the bit line voltage Vbl0 is compared with the reference voltage Vref through the voltage comparator SA0, and the data value stored in the memory cell is judged according to the signal output by the voltage comparator. Since the memory cell stores two-bit data of "1" or "0", when the data stored in the memory cell Ccell0 is "1", Vbl0 is a value, assumed to be V1, when reading. When the data stored in the memory cell Ccell0 is "0", Vblo is another value, assumed to be V0, when reading. In this way, when judging whether the value stored in the memory cell Ccell0 is "1" or "0", an intermediate value can be taken. For example, Vref = (V1 + V0) / 2. In this way, when the data stored in the memory cell Ccell0 is "1", the bit line voltage of the bit line bl0 connected to it is Vbl0 = V1 > Vref, and it can be judged that the data stored in the memory cell Ccell0 is "1" through the output signal SA0 of the voltage comparator comp0; when the data stored in the memory cell Ccell0 is "0", the bit line voltage Vbl0 of the bit line bl0 connected to it is Vbl0 = V0 < Vref, and it can be judged that the data stored in the memory cell Ccell0 is "0" through the output signal SA0 of the voltage comparator comp0.

[0054] The reference voltage generating circuit of the present invention will be specifically described below. As mentioned above, the memory of the present invention includes reference cells, wherein the transistors and capacitors of each reference cell have the same structure as the transistors and capacitors of the storage cells. In this embodiment, the word lines of the storage cells and reference cells in the same row are connected to the same word line, for example, the gates of the transistors of the reference cells Cellr1 and Cellr0 in the first row and the gates of the transistors of the storage cells Ccell0 and Ccell1 are connected to the same word line wl0, and one plate of the capacitors of the reference cells Cellr1 and Cellr0 and one plate of the capacitors of the storage cells Ccell0 and Ccell1 are connected to the same plate line PL. The data stored in the reference cell Ccellr1 is the data "1" written during writing, and the data stored in the reference cell Ccellr0 is the data "0" written during writing. When reading the data of the storage cell Ccell0, the word line wl0 inputs a high level, then when the plate line PL is high, the voltage of the bit line blref1 connected to the reference cell Cellr1 is Vblref1=Vpl*Cref1 / (Cref1+Cblref1), where Cref1 is the capacitance value of the capacitor Cref1, and Cblref1 is the parasitic capacitance of the entire bit line blref1; the voltage of the bit line blref0 connected to the reference cell Cellr0 is Vblref0=Vpl*Cref0 / (Cref0+Cblref0), where Cref0 is the capacitance value of the capacitor Cref0, and Cblref0 is the parasitic capacitance of the entire bit line blref0. Vblref1 and Vblref0 are input to the same input terminal of the operational amplifier, and the output voltage Vout of the integrated operational amplifier is Vblref0=(Vblref0+Vblref1) / 2, and the output voltage Vout of the integrated operational amplifier is the reference voltage Vref.

[0055] See also Figure 4 As shown, it shows a schematic diagram of the structure of the integrated operational amplifier OA of the reference signal generating circuit of the present invention, wherein the figure shows two embodiments of the integrated operational amplifier with a single signal input and a dual signal input respectively. Figure 4 As shown, the reference signal generating circuit of the present invention includes a first input terminal, a second input terminal and an output terminal. When a single signal is input, the input signal Vin is input to the first input terminal of the integrated operational amplifier, and the output terminal of the integrated operational amplifier is connected to the second input terminal to form a follower circuit, wherein the output signal Vout of the integrated operational amplifier is equal to Vin. When there are two input signals Vin1 and Vin0, if Vin1 is equal to Vin0, then Vout is equal to Vin1 and Vin0 is equal to (Vin1+Vin0) / 2. Therefore, in Figure 4 As shown in, the voltages of the bit lines blref1 and blref0 of the reference unit of the present invention are simultaneously input to the first input terminal of the integrated operational amplifier, and the output terminal of the integrated operational amplifier is connected to the second input terminal of the integrated operational amplifier, so that the output signal Vout of the integrated operational amplifier is Vout=(Vblref0+Vblerf1) / 2=Vref.

[0056] See also Figure 5 As shown, it shows a specific circuit structure schematic diagram of the integrated operational amplifier of the reference signal generating circuit of the memory of the present invention. Figure 4 and Figure 5 As shown, the integrated operational amplifier circuit of the present invention includes two first input terminals Vin1 and Vin0, one of which is connected to the bit line blref1 of the reference unit storing data "1", and the other first input terminal Vin0 is connected to the bit line blref0 of the reference unit storing data "0". The integrated operational amplifier circuit of the present invention includes two second input terminals D0 and D1, wherein the two second input terminals D0 and D1 are connected to the output terminal Vout of the integrated operational amplifier.

[0057] Please continue reading Figure 5 As shown, the integrated operational amplifier includes a PMOS transistor P1 connected to a first input terminal Vin1, and a first PMOS transistor P0 connected to a first input terminal Vin0, wherein the first input terminal Vin1 is connected to a gate of the first PMOS transistor P1, a source of the first PMOS transistor P1 is connected to a first node J1, and a drain of the first PMOS transistor P1 is connected to a second node J2. The first input terminal Vin0 is connected to a gate of the first PMOS transistor P0, a source of the first PMOS transistor P0 is connected to a first node J1, and a drain of the first PMOS transistor P0 is connected to a second node J2.

[0058] A first NMOS transistor N0 is connected between the second node J2 and the ground. A source of the first NMOS transistor N0 is connected to the second node J2, and a gate of the first NMOS transistor N0 is connected to a fourth node J4.

[0059] The integrated operational amplifier includes a second PMOS transistor P2 connected to a second input terminal D0, and a second PMOS transistor P3 connected to a second input terminal D1. The second input terminal D0 is connected to the gate of the second PMOS transistor P2, the source of the second PMOS transistor P2 is connected to the first node J1, and the drain of the second PMOS transistor P2 is connected to the third node J3. The second input terminal D1 is connected to the gate of the second PMOS transistor P3, the source of the second PMOS transistor P3 is connected to the first node J1, and the drain of the second PMOS transistor P3 is connected to the third node J3.

[0060] A second NMOS transistor N1 is connected between the third node J3 and the ground, the source of the second NMOS transistor N1 is connected to the third node J3, the gate of the second NMOS transistor N1 is connected to the fourth node J4, and the source and gate of the second NMOS transistor N1 are connected.

[0061] A third NMOS transistor N2 is connected between the second node J2 and the output terminal Vout, a gate of the third NMOS transistor N2 is connected to the second node J2, a source of the third NMOS transistor N2 is connected to the output terminal Vout, and a drain of the third NMOS transistor N2 is grounded.

[0062] A third PMOS transistor P4 is connected between the first node J1 and the power supply Vcc, the source of the third PMOS transistor P4 is connected to the power supply Vcc, the gate of the third PMOS transistor P4 is connected to the control signal pbias, and the drain of the third PMOS transistor P4 is connected to the first node J1.

[0063] A fourth PMOS transistor P5 is connected between the power supply Vcc and the output terminal Vout, the source of the fourth PMOS transistor P5 is connected to the power supply Vcc, the gate of the fourth PMOS transistor P4 is connected to the control signal pbias, and the drain of the fourth PMOS transistor P4 is connected to the output terminal Vout.

[0064] according to Figure 5 The integrated operational amplifier circuit combines Figure 3 and Figure 4 As shown, the voltage Vblref1 of the bit line blref1 connected to the reference cell Cellr1 and the voltage Vblref0 of the bit line blref0 connected to the reference cell Cellr0 are respectively input to the first input terminals Vin1 and Vin0 of the integrated operational amplifier, and the output terminal Vout of the integrated operational amplifier is connected to the second input terminals D0 and D1 of the integrated operational amplifier. In this way, the output signal Vout of the integrated operational amplifier = (Vblref0 + Vblerf1) / 2 = Vref.

[0065] As described above, the bit line voltage Vbl0 is compared with the reference voltage Vref by the voltage comparator comp0, and the data value stored in the memory cell is determined according to the signal SA0 output by the voltage comparator. When the data stored in the memory cell Ccell0 is "1", the bit line voltage of the bit line bl0 connected thereto is Vbl0 = V1 > Vref, and it can be determined that the data stored in the memory cell Ccell0 is "1" through the output signal SA0 of the voltage comparator comp0; when the data stored in the memory cell Ccell0 is "0", the bit line voltage Vbl0 = V0 < Vref of the bit line bl0 connected thereto, and it can be determined that the data stored in the memory cell Ccell0 is "0" through the output signal SA0 of the voltage comparator comp0.

[0066] The above is an illustration with reading the data of the memory cell Ccell0 as an example. As Figure 3 shown, a voltage comparator such as comp1... compn is provided for each column of memory cells. Similarly, when reading other memory cells, the bit line voltage connected to the cell to be read and the value of the reference voltage are compared by the voltage comparator corresponding to the memory cell to output a comparison signal to determine the data stored in the memory cell to be read.

[0067] In the foregoing embodiment, two columns of reference signal units are used to generate the input signals of two input integrated operational amplifiers to generate the reference signal. In other embodiments, multiple columns of reference signal units can also be used to generate the input signals of multiple input integrated operational amplifiers. As Figure 6 shown, a total of N + 1 input signals from Vin0 to VinN can be input to the first input terminal of the integrated operational amplifier. Similarly, the output terminal of the integrated operational amplifier is connected to the second input terminal of the integrated operational amplifier, so that the output signal Vout of the integrated operational amplifier = Sum(Vin0, Vin1,..., VinN) / N. The specific internal circuit of the integrated operational amplifier can refer to Figure 4 shown, each first input terminal is connected to multiple input signals through the gates of multiple first PMOS transistors, and each second input terminal is respectively connected to the gates of multiple second PMOS transistors, where the first PMOS transistors and the second PMOS transistors are connected in parallel, and the output terminal of the integrated operational amplifier is connected to the second PMOS transistor of each second input terminal. Through Figure 5 and Figure 6 embodiments, it can be seen that for the integrated operational amplifier circuit and method of the present invention, the average value of multiple input values can be calculated regardless of the values of the multiple input values. Although the specific integrated operational amplifier circuit shown in Figure 4 is adopted in the foregoing specific embodiment, it is not limited to Figure 4The specific circuit in the circuit may also adopt other forms of integrated operational amplifier circuits, as long as the transistors at the first input terminal and the second input terminal are connected in parallel, the input voltage is connected to the input electrode of the transistor at the first input terminal, and the input electrode of the transistor at the second input terminal is connected to the output terminal, it is possible to realize that the output signal is the average value of multiple input signals. Figure 5 In the embodiment shown, the input voltage connected to the first input terminal is the bit line voltage of two reference cells, and the average value is used as the reference voltage. Figure 6 The integrated operational amplifier circuit for averaging multiple input voltages in the illustrated embodiment may be used in any other circuits.

[0068] See also Figure 7 As shown, it shows a schematic diagram of the structure of another embodiment of the present invention. In this embodiment, Figure 3 The difference between the illustrated embodiment is that the plate line PL connected to the storage unit and the plate line PLref connected to the reference unit are not connected to a common plate line PL, but are separately set. In this way, during the read operation, the plate line voltage Vpl can be applied to the reference unit separately through the separate plate line PLref. In this way, relative to the storage unit, the plate line voltage Vpl can be applied to the reference unit a little earlier, and the voltage Vblref1 or Vblref0 generated by the bit line blref1 or blref0 connected to the reference unit can be obtained in advance, and the reference voltage Vref signal can be obtained in advance, so that the delay caused by the transmission of the reference circuit signal can be avoided, and the input signals of the voltage comparator can be input at the same time as much as possible to avoid sensing errors.

[0069] According to an embodiment of the present invention, the bit line bl of each storage unit is directly connected to the input end of a voltage comparator, so that the voltage of the bit line bl is directly collected, which can more accurately reflect the real voltage of the bit line bl, and there is no loss of the bit line voltage of the storage unit in the reading circuit of the prior art. The integrated operational amplifier of the reference voltage generating circuit of the present invention can accurately obtain the reference voltage signal Vref = (Vblref0 + Vblref0) / 2, and there is no loss of the reference unit bit line voltage of the reference signal generating circuit of the prior art. Moreover, the reference voltage generating circuit of the present invention, its reference voltage signal is only related to the bit line voltage of the reference unit, so that the reference voltage signal is the same when input into any number of voltage comparators, which can solve the problem of the prior art that if the reference voltage is connected to different numbers of voltage comparators, the reference voltage signal will change due to the different numbers of connected comparators. Furthermore, according to an embodiment of the present invention, by separately setting up independent storage cell plate lines and reference cell plate lines, and by loading a control signal to the plate line of the reference cell a certain time in advance relative to the storage cell, data reading of the reference cell can be started in advance, and a reference voltage signal can be generated in advance. This can avoid delays in data transmission in the reference voltage generating circuit, and try to ensure that the storage cell bit line voltage and the reference voltage are input into the voltage comparator at the same time, thereby ensuring the accuracy of the data reading operation.

[0070] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims of the present invention.

Claims

1. A memory reference signal generating circuit, comprising: An integrated operational amplifier circuit comprises a first input terminal, a second input terminal and an output terminal, wherein the integrated operational amplifier circuit comprises a first PMOS transistor connected to the first input terminal, a second PMOS transistor connected to the second input terminal, sources of the first PMOS transistor and the second PMOS transistor are commonly connected to a first node J1, a third PMOS transistor P4 is connected between the first node and a power supply voltage, a drain of the first PMOS transistor is grounded via a first NMOS transistor N0, a drain of the second PMOS transistor is grounded via a second NMOS transistor N1, gates of the first NMOS transistor and the second NMOS transistor are commonly connected to a fourth node J4, a third NMOS transistor N2 is connected between the node where the first PMOS transistor and the first NMOS transistor are connected and the output terminal, the output terminal is connected to the gate of the second PMOS transistor, a fourth PMOS transistor P5 is connected between the output terminal and the power supply voltage, The bit line of the first reference unit and the bit line of the second reference unit are respectively connected to the first input terminal Vin0 and the first input terminal Vin1 of the integrated operational amplifier circuit, the first reference unit stores the first data, the second reference unit stores the second data, the first PMOS transistor includes a first parallel PMOS transistor and a second parallel PMOS transistor, the first input terminal Vin1 is connected to the gate of the first parallel PMOS transistor, the source of the first parallel PMOS transistor is connected to the first node, and the drain of the first parallel PMOS transistor is connected to the second node; the first input terminal Vin0 is connected to the gate of the second parallel PMOS transistor, the source of the second parallel PMOS transistor is connected to the first node, and the drain of the second parallel PMOS transistor is connected to the second node, The second PMOS transistor includes a third parallel PMOS transistor and a fourth parallel PMOS transistor, the source of the third parallel PMOS transistor is connected to the first node J1, the gate of the third parallel PMOS transistor is connected to the second input terminal D1, the drain of the third parallel PMOS transistor is connected to the third node J3, the source of the fourth parallel PMOS transistor is connected to the first node J1, the gate of the fourth parallel PMOS transistor is connected to the second input terminal D0, the drain of the fourth parallel PMOS transistor is connected to the third node J3, the second input terminals D1 and D0 are connected to the output terminal, The source of the second NMOS transistor N1 is connected to the third node J3, the gate of the second NMOS transistor N1 is connected to the fourth node J4, and the source and gate of the second NMOS transistor N1 are connected. The gate of the third NMOS transistor N2 is connected to the second node J2, the source of the third NMOS transistor N2 is connected to the output terminal Vout, and the drain of the third NMOS transistor N2 is grounded. The source of the third PMOS transistor P4 is connected to the power supply Vcc, the gate of the third PMOS transistor P4 is connected to the control signal pbias, and the drain of the third PMOS transistor P4 is connected to the first node J1. The source of the fourth PMOS transistor P5 is connected to the power supply Vcc, the gate of the fourth PMOS transistor P5 is connected to the control signal pbias, and the drain of the fourth PMOS transistor P5 is connected to the output terminal Vout. The output end of the integrated operational amplifier circuit is connected to the second input end to form a follower circuit, and the output signal of the integrated operational amplifier circuit is the average value of the input signal of the first input end, wherein the bit line of the storage unit and the output end of the integrated operational amplifier circuit are directly connected to the corresponding input ends of the comparator respectively.

2. A memory read sensing circuit, comprising a reference signal generating circuit, the reference signal generating circuit comprising: An integrated operational amplifier circuit has a plurality of first input terminals, a plurality of second input terminals and an output terminal, wherein the first input terminal is connected to a reference signal, and the output terminal is connected to the second input terminal to form a follower circuit, and the output signal of the integrated operational amplifier circuit is the average value of the input signal of the first input terminal, wherein the integrated operational amplifier circuit comprises a first PMOS transistor connected to the first input terminal, a second PMOS transistor connected to the second input terminal, the sources of the first PMOS transistor and the second PMOS transistor are commonly connected to a first node J1, a third PMOS transistor P4 is connected between the first node and a power supply voltage, the drain of the first PMOS transistor is grounded through a first NMOS transistor N0, the drain of the second PMOS transistor is grounded through a second NMOS transistor N1, and the gates of the first NMOS transistor and the second NMOS transistor are connected to the ground. Commonly connected to a fourth node J4, a third NMOS transistor N2 is connected between the node where the first PMOS transistor and the first NMOS transistor are connected and the output terminal, the output terminal is connected to the gate of the second PMOS transistor, a fourth PMOS transistor P5 is connected between the output terminal and the power supply voltage, the first PMOS transistor includes a first parallel PMOS transistor and a second parallel PMOS transistor, the first input terminal Vin1 is connected to the gate of the first parallel PMOS transistor, the source of the first parallel PMOS transistor is connected to the first node, and the drain of the first parallel PMOS transistor is connected to the second node; the first input terminal Vin0 is connected to the gate of the second parallel PMOS transistor, the source of the second parallel PMOS transistor is connected to the first node, and the drain of the second parallel PMOS transistor is connected to the second node; The second PMOS transistor includes a third parallel PMOS transistor and a fourth parallel PMOS transistor, the source of the third parallel PMOS transistor is connected to the first node J1, the gate of the third parallel PMOS transistor is connected to the second input terminal D1, the drain of the third parallel PMOS transistor is connected to the third node J3, the source of the fourth parallel PMOS transistor is connected to the first node J1, the gate of the fourth parallel PMOS transistor is connected to the second input terminal D0, the drain of the fourth parallel PMOS transistor is connected to the third node J3, the second input terminals D1 and D0 are connected to the output terminal, The source of the second NMOS transistor N1 is connected to the third node J3, the gate of the second NMOS transistor N1 is connected to the fourth node J4, and the source and gate of the second NMOS transistor N1 are connected. The gate of the third NMOS transistor N2 is connected to the second node J2, the source of the third NMOS transistor N2 is connected to the output terminal Vout, and the drain of the third NMOS transistor N2 is grounded. The source of the third PMOS transistor P4 is connected to the power supply Vcc, the gate of the third PMOS transistor P4 is connected to the control signal pbias, and the drain of the third PMOS transistor P4 is connected to the first node J1. The source of the fourth PMOS transistor P5 is connected to the power supply Vcc, the gate of the fourth PMOS transistor P5 is connected to the control signal pbias, and the drain of the fourth PMOS transistor P5 is connected to the output terminal Vout. The voltage comparator comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a bit line signal of a memory storage unit, and the second input terminal is connected to the output terminal of an integrated operational amplifier circuit.

3. The memory read sensing circuit according to claim 2, wherein: The bit line of the first reference unit and the bit line of the second reference unit are respectively connected to the first input terminal Vin0 and the first input terminal Vin1 of the integrated operational amplifier circuit. The first reference unit stores first data, and the second reference unit stores second data.

4. A memory comprising: A plurality of storage units arranged in an array, each storage unit being used to store data; Reference cells arranged in an array, wherein the reference cells include a first reference cell and a second reference cell; A data reading sensing circuit includes an integrated operational amplifier circuit and a voltage comparator, wherein the bit line of a first reference unit and the bit line of a second reference unit are respectively connected to the first input terminal Vin0 and the first input terminal Vin1 of the integrated operational amplifier circuit, the output terminal of the integrated operational amplifier circuit is connected to the second input terminal of the integrated operational amplifier circuit, the output signal of the integrated operational amplifier circuit is the average value of the input signal of the first input terminal, the output terminal of the integrated operational amplifier circuit and the bit line of the storage unit are respectively input to the input terminal of the voltage comparator, and the data stored in the storage unit can be judged by the signal output by the voltage comparator, wherein the integrated operational amplifier circuit includes a first PMOS transistor connected to the first input terminal, a second PMOS transistor connected to the second input terminal, the sources of the first PMOS transistor and the second PMOS transistor are commonly connected to a first node J1, a third PMOS transistor P4 is connected between the first node and the power supply voltage, the drain of the first PMOS transistor is grounded through a first NMOS transistor N0, and the second The drain of the PMOS transistor is grounded through the second NMOS transistor N1, the gates of the first NMOS transistor and the second NMOS transistor are commonly connected to a fourth node J4, a third NMOS transistor N2 is connected between the node where the first PMOS transistor and the first NMOS transistor are connected and the output terminal, the output terminal is connected to the gate of the second PMOS transistor, and a fourth PMOS transistor P5 is connected between the output terminal and the power supply voltage, the first PMOS transistor includes a first parallel PMOS transistor and a second parallel PMOS transistor, the first input terminal Vin1 is connected to the gate of the first parallel PMOS transistor, the source of the first parallel PMOS transistor is connected to the first node, and the drain of the first parallel PMOS transistor is connected to the second node; the first input terminal Vin0 is connected to the gate of the second parallel PMOS transistor, the source of the second parallel PMOS transistor is connected to the first node, and the drain of the second parallel PMOS transistor is connected to the second node, The second PMOS transistor includes a third parallel PMOS transistor and a fourth parallel PMOS transistor, the source of the third parallel PMOS transistor is connected to the first node J1, the gate of the third parallel PMOS transistor is connected to the second input terminal D1, the drain of the third parallel PMOS transistor is connected to the third node J3, the source of the fourth parallel PMOS transistor is connected to the first node J1, the gate of the fourth parallel PMOS transistor is connected to the second input terminal D0, the drain of the fourth parallel PMOS transistor is connected to the third node J3, the second input terminals D1 and D0 are connected to the output terminal, The source of the second NMOS transistor N1 is connected to the third node J3, the gate of the second NMOS transistor N1 is connected to the fourth node J4, and the source and gate of the second NMOS transistor N1 are connected. The gate of the third NMOS transistor N2 is connected to the second node J2, the source of the third NMOS transistor N2 is connected to the output terminal Vout, and the drain of the third NMOS transistor N2 is grounded. The source of the third PMOS transistor P4 is connected to the power supply Vcc, the gate of the third PMOS transistor P4 is connected to the control signal pbias, and the drain of the third PMOS transistor P4 is connected to the first node J1. A source of the fourth PMOS transistor P5 is connected to the power source Vcc, a gate of the fourth PMOS transistor P5 is connected to the control signal pbias, and a drain of the fourth PMOS transistor P5 is connected to the output terminal Vout.

5. The memory of claim 4, wherein the plate line of the memory cell and the plate line of the reference cell are connected to the same plate line.

6. The memory as claimed in claim 4, wherein the plate line of the memory cell and the plate line of the reference cell are connected to different plate lines.

7. An input voltage averaging integrated operational amplifier circuit for a memory, comprising: A first PMOS transistor connected to the first input terminal, a second PMOS transistor connected to the second input terminal, sources of the first PMOS transistor and the second PMOS transistor are commonly connected to a first node J1, a third PMOS transistor P4 is connected between the first node and the power supply voltage, a drain of the first PMOS transistor is grounded via a first NMOS transistor N0, a drain of the second PMOS transistor is grounded via a second NMOS transistor N1, gates of the first NMOS transistor and the second NMOS transistor are commonly connected to a fourth node J4, and a third NMOS transistor is connected between the node where the first PMOS transistor and the first NMOS transistor are connected and the output terminal. The OS transistor N2 has an output terminal connected to the gate of the second PMOS transistor, and a fourth PMOS transistor P5 is connected between the output terminal and the power supply voltage. The first PMOS transistor includes a first parallel PMOS transistor and a second parallel PMOS transistor. The first input terminal Vin1 is connected to the gate of the first parallel PMOS transistor, the source of the first parallel PMOS transistor is connected to the first node, and the drain of the first parallel PMOS transistor is connected to the second node; the first input terminal Vin0 is connected to the gate of the second parallel PMOS transistor, the source of the second parallel PMOS transistor is connected to the first node, and the drain of the second parallel PMOS transistor is connected to the second node. The second PMOS transistor includes a third parallel PMOS transistor and a fourth parallel PMOS transistor, the source of the third parallel PMOS transistor is connected to the first node J1, the gate of the third parallel PMOS transistor is connected to the second input terminal D1, the drain of the third parallel PMOS transistor is connected to the third node J3, the source of the fourth parallel PMOS transistor is connected to the first node J1, the gate of the fourth parallel PMOS transistor is connected to the second input terminal D0, the drain of the fourth parallel PMOS transistor is connected to the third node J3, the second input terminals D1 and D0 are connected to the output terminal, The source of the second NMOS transistor N1 is connected to the third node J3, the gate of the second NMOS transistor N1 is connected to the fourth node J4, and the source and gate of the second NMOS transistor N1 are connected. The gate of the third NMOS transistor N2 is connected to the second node J2, the source of the third NMOS transistor N2 is connected to the output terminal Vout, and the drain of the third NMOS transistor N2 is grounded. The source of the third PMOS transistor P4 is connected to the power supply Vcc, the gate of the third PMOS transistor P4 is connected to the control signal pbias, and the drain of the third PMOS transistor P4 is connected to the first node J1. The source of the fourth PMOS transistor P5 is connected to the power supply Vcc, the gate of the fourth PMOS transistor P5 is connected to the control signal pbias, and the drain of the fourth PMOS transistor P5 is connected to the output terminal Vout. The bit lines of the storage units of the memory and the output ends of the integrated operational amplifier circuit are directly connected to the corresponding input ends of the comparator respectively.

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