Semiconductor devices

Abstract

The semiconductor device (1) comprises: a semiconductor layer (40) having a main surface (40a and 40b); a metal layer (31) having a main surface (31a and 31b), the main surface (31a) being in contact with the main surface (40b), being thicker than the semiconductor layer (40), and being made of a first metal material; and a metal layer (30) having a main surface (30a and 30b), the main surface (30a) being in contact with the main surface (31b), being thicker than the semiconductor layer (40), and being made of a Young's modulus greater than that of the first metal material. The present invention relates to a semiconductor device comprising a semiconductor layer (40) and a semiconductor material; the semiconductor device (40) is composed of a metal material having a large metal material; and transistors (10 and 20); the transistor (10) has a source electrode (11) and a gate electrode (19) on the main surface (40a) side of the semiconductor layer (40); the transistor (20) has a source electrode (21) and a gate electrode (29) on the main surface (40a) side of the semiconductor layer (40), and a bidirectional path from the source electrode (11) through the metal layer (31) to the source electrode (21) is used as a main current path.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a flip-chip package type semiconductor device. Background Art

[0002] Conventionally, a semiconductor device has been proposed, comprising: a semiconductor layer having a first main surface and a second main surface, two vertical field effect transistors arranged from the first main surface to the second main surface, and a metal layer formed on the second main surface. In this structure, as a current path flowing from the first transistor to the second transistor, not only a horizontal path inside the semiconductor substrate but also a horizontal path in the metal layer having a low on-resistance can be used, so that the on-resistance of the semiconductor device can be reduced.

[0003] Patent Document 1 proposes a semiconductor device in which a conductive layer is formed on the metal layer opposite to the semiconductor substrate in addition to the above structure. This conductive layer can suppress the occurrence of burrs on the metal layer during the chip singulation process.

[0004] Patent Document 2 proposes a semiconductor device having an insulating film formed on the metal layer opposite to the semiconductor substrate in addition to the above structure. The insulating film can maintain the thickness of the semiconductor device and prevent damage such as scratches and defects.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2016-86006

[0008] Patent Document 2: Japanese Patent Application Publication No. 2012-182238 Summary of the invention

[0009] Problems to be solved by the invention

[0010] However, in the semiconductor devices disclosed in Patent Documents 1 and 2, since the thermal expansion coefficient of the metal layer is larger than the thermal expansion coefficient of the semiconductor substrate, warping of the semiconductor device occurs due to temperature changes.

[0011] In Patent Document 1, a conductive layer is formed on the side of the metal layer opposite to the semiconductor substrate, but the main material of the conductive layer is the same type of metal as the metal layer, so it is not easy to form a conductive layer with a thickness sufficient to reduce the warping of the semiconductor device caused by temperature changes in manufacturing.

[0012] In Patent Document 2, an insulating coating is formed on the side of the metal layer opposite to the semiconductor substrate to achieve thinning of the semiconductor device and prevent damage. However, when the thickness of the metal layer is the thickness required to ensure low on-resistance, stress sufficient to reduce warping of the semiconductor device does not occur in the insulating coating.

[0013] That is, in the semiconductor devices disclosed in Patent Documents 1 and 2, it is not possible to achieve both reduction in on-resistance and suppression of warpage of the semiconductor device.

[0014] Therefore, an object of the present invention is to provide a chip size package type semiconductor device that achieves both reduction of on-resistance and suppression of warpage.

[0015] Means used to solve problems

[0016] In order to solve the above-mentioned problems, a technical solution of the semiconductor device of the present invention is a semiconductor device of chip size packaging type capable of flip-chip mounting, comprising: a semiconductor layer, having a first main surface and a second main surface facing each other, and composed of silicon, gallium nitride or silicon carbide; a first metal layer, having a third main surface and a fourth main surface facing each other, the third main surface being formed in contact with the second main surface, the first metal layer being thicker than the semiconductor layer, and composed of a first metal material; a second metal layer, having a fifth main surface and a sixth main surface facing each other, the fifth main surface being formed in contact with the fourth main surface, the second metal layer being thicker than the semiconductor layer, and composed of a second metal material having a Young's modulus greater than that of the first metal material; a first vertical field effect transistor , formed in the first region of the above-mentioned semiconductor layer; and a second vertical field effect transistor, in the above-mentioned semiconductor layer, formed in the second region adjacent to the above-mentioned first region in the direction along the above-mentioned first main surface; the above-mentioned first vertical field effect transistor has a first source electrode and a first gate electrode on the above-mentioned first main surface side of the above-mentioned semiconductor layer; the above-mentioned second vertical field effect transistor has a second source electrode and a second gate electrode on the above-mentioned first main surface side of the above-mentioned semiconductor layer; the above-mentioned first metal layer functions as a common drain electrode of the above-mentioned first vertical field effect transistor and the above-mentioned second vertical field effect transistor; and a bidirectional path from the above-mentioned first source electrode via the above-mentioned common drain electrode to the above-mentioned second source electrode is used as a main current path.

[0017] According to this structure, since the first metal layer having a thickness for ensuring low on-resistance contacts the second metal layer having a larger Young's modulus than the first metal layer and thicker than the semiconductor layer, warping of the semiconductor device caused by the contact between the semiconductor layer and the first metal layer can be suppressed. Therefore, a chip-size package type semiconductor device that achieves both reduction of on-resistance and suppression of warping can be provided.

[0018] Effects of the Invention

[0019] According to the semiconductor device according to the present invention, it is possible to provide a flip-chip-size package semiconductor device that achieves both reduction in on-resistance and suppression of warping of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment.

[0021] Figure 2 A plan view showing an example of an electrode structure of a semiconductor device according to an embodiment and a schematic cross-sectional view showing the flow of a bidirectional current.

[0022] Figure 3 This is a circuit diagram showing an example of application of the semiconductor device according to the embodiment to a charge and discharge circuit.

[0023] Figure 4A This is a graph showing the warpage amount and on-resistance corresponding to the Ag layer thickness / Si layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer.

[0024] Figure 4B This is a graph showing the results of confirming the warpage amount corresponding to the Ni layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer through a prototype experiment.

[0025] Figure 5A This is a graph showing the results of confirming the on-resistance corresponding to the Si layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer or Si layer / Ag layer through a trial production experiment.

[0026] Figure 5B This is a graph showing the results of confirming the on-resistance corresponding to the Ni layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer through a trial production experiment.

[0027] Figure 6 (a) is an electron microscope photograph of the main surface of the Ni layer in the semiconductor device according to the embodiment. Figure 6 (b) is an electron microscope photograph of a cross section of a Ni layer in the semiconductor device according to the embodiment.

[0028] Figure 7 This is an electron microscope photograph of a cross section of a Ni layer / Ag layer in a semiconductor device according to an embodiment.

[0029] Figure 8 This is a graph comparing the measured value and the predicted value of the warpage amount corresponding to the Ni layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer.

[0030] Fig. 9 1 is a schematic cross-sectional view of a semiconductor device having a Ni layer composed of a plurality of layers having different crystal grain sizes.

[0031] Fig.10 This is a diagram showing the temperature dependency of the warpage amount of a semiconductor device having a two-layer Ni layer formed by different plating methods.

[0032] Fig.11 It is a schematic cross-sectional view showing the relationship between the concavo-convex cycle and the marking pattern width on the main surface of the Ni layer and the marking visibility.

[0033] Fig.12 This is a schematic cross-sectional view showing the relationship between the maximum height roughness of the main surface of the Ni layer, the marking depth, and the marking visibility.

[0034] Fig.13A is a cross-sectional view of a semiconductor device according to an embodiment.

[0035] Fig. 13B is a cross-sectional view of a semiconductor device according to an embodiment.

[0036] Fig. 13C is a cross-sectional view of a semiconductor device according to an embodiment.

[0037] Fig.13D is a cross-sectional view of a semiconductor device according to an embodiment.

[0038] Fig.13E is a cross-sectional view of a semiconductor device according to an embodiment.

[0039] Fig.13F is a cross-sectional view of a semiconductor device according to an embodiment.

[0040] Fig.14 is a cross-sectional view of a semiconductor device according to an embodiment.

[0041] Fig.15 It is a diagram for explaining the retreat distance of the Si layer in the semiconductor device according to the embodiment.

[0042] Fig.16 This is an electron microscope photograph of the side surface of the Si layer in the semiconductor device according to the embodiment.

[0043] Fig.17 It is a diagram for explaining the relationship between the side surface shape of the Si layer and the manufacturing method in the semiconductor device according to the embodiment.

[0044] Fig.18 This is an electron microscope photograph of the side surface of the Si layer / Ag layer in the semiconductor device according to the embodiment.

[0045] Fig.19is a cross-sectional view of a semiconductor device according to an embodiment.

[0046] Fig. 20 It is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0047] Fig.21 It is a schematic cross-sectional view of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0048] The embodiments described below all represent a specific example of the present invention. The numerical values, shapes, materials, components, configurations of components, and connection forms, etc., shown in the following embodiments are examples and do not limit the meaning of the present invention. In addition, among the components of the following embodiments, the components that are not described in the independent claims representing the highest concept are described as arbitrary components.

[0049] (Implementation Method)

[0050] [1. Structure of semiconductor device]

[0051] The structure of the semiconductor device 1 according to the present embodiment is described below. The semiconductor device 1 according to the present invention is a flip-chip CSP (Chip Size Package) type multi-transistor chip having two vertical MOS (Metal Oxide Semiconductor) transistors formed on a semiconductor substrate. The two vertical MOS transistors are power transistors, so-called trench MOS FETs (Field Effect Transistors). However, the semiconductor device 1 according to the present embodiment is not suitable for devices classified as optoelectronic devices such as solid-state imaging devices.

[0052] Figure 1 1 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the embodiment. Figure 2 A plan view showing an example of an electrode structure of a semiconductor device according to an embodiment and a schematic cross-sectional view showing the flow of a bidirectional current. Figure 1 The cross-sectional view is to observe Figure 2 (a) is a diagram of the cross section taken along line I-I.

[0053] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor layer 40, metal layers 30 and 31, a first vertical MOS transistor 10 (hereinafter referred to as transistor 10), and a second vertical MOS transistor 20 (hereinafter referred to as transistor 20).

[0054] The semiconductor layer 40 has a main surface 40a (first main surface) and a main surface 40b (second main surface) facing each other, and is composed of silicon. The semiconductor layer 40 is a structure in which a semiconductor substrate 32 and a low-concentration impurity layer 33 are stacked. The semiconductor substrate 32 is arranged on the main surface 40b side of the semiconductor layer 40, and the low-concentration impurity layer 33 is arranged on the main surface 40a side of the semiconductor layer 40.

[0055] The metal layer 31 is a first metal layer composed of a first metal material and having a main surface 31a (third main surface) and a main surface 31b (fourth main surface) facing each other, the main surface 31a is formed in contact with the main surface 40b, and is thicker than the semiconductor layer 40. Examples of the first metal material include silver (Ag), copper (Cu) or gold (Au).

[0056] The metal layer 30 is a second metal layer having a main surface 30a (fifth main surface) and a main surface 30b (sixth main surface) facing each other, the main surface 30a is formed in contact with the main surface 31b, is thicker than the semiconductor layer 40, and is composed of a second metal material having a Young's modulus greater than that of the first metal material. Examples of the second metal material include nickel (Ni), platinum (Pt), iridium (Ir), rhodium (Rh), or chromium (Cr).

[0057] In addition, if Figure 1 and Figure 2 As shown in (a) and (b), when the semiconductor layer 40 is viewed in a planar manner, the transistor 10 formed in the first region A1 has four source electrodes 11a, 11b, 11c and 11d (corresponding to the source electrode 11, respectively) and one gate electrode 19 (first gate electrode) on the main surface 40a side of the semiconductor layer 40. In addition, the transistor 20 formed in the second region A2 adjacent to the first region A1 in the direction along the main surface 40a has four source electrodes 21a, 21b, 21c and 21d (corresponding to the source electrode 21, respectively) and one gate electrode 29 (second gate electrode). In addition, the number and arrangement relationship of the source electrodes and gate electrodes constituting one transistor 10 and 20 are not limited to Figure 2 shown.

[0058] like Figure 2 As shown in (b) and (c), the metal layer 31 functions as a common drain electrode of the transistors 10 and 20, with a bidirectional path from the source electrode 11 (first source electrode) through the metal layer 31 to the source electrode 21 (second source electrode) as a main current path.

[0059] According to the above structure, the metal layer 31 having a thickness for ensuring low on-resistance is in contact with the metal layer 30 having a larger Young's modulus than the metal layer 31 and thicker than the semiconductor layer 40, so that warping of the semiconductor device 1 caused by the contact between the semiconductor layer 40 and the metal layer 31 can be suppressed. Therefore, a chip size package type semiconductor device 1 that achieves both reduction of on-resistance and suppression of warping can be provided.

[0060] Hereinafter, the structure and operation of the semiconductor device 1 will be described in detail.

[0061] The semiconductor substrate 32 contains impurities of the first conductivity type and is made of silicon. The semiconductor substrate 32 is, for example, an N-type silicon substrate.

[0062] The low concentration impurity layer 33 and the upper surface of the semiconductor substrate 32 ( Figure 1 The low-concentration impurity layer 33 is formed in contact with the main surface on the positive z-axis direction side of the semiconductor substrate 32, and contains first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the semiconductor substrate 32. The low-concentration impurity layer 33 may also be formed on the semiconductor substrate 32 by epitaxial growth, for example.

[0063] In the first region A1 of the low-concentration impurity layer 33, a body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed. In the body region 18, a source region 14 containing impurities of the first conductivity type, a gate conductor 15, and a gate insulating film 16 are formed. The source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the source region 14 and the body region 18 via the portion 13. The gate conductor 15 is connected to the gate electrode 19.

[0064] The portion 12 of the source electrode 11 is a layer that exhibits good bonding properties with a conductive bonding material such as solder during installation, and may be composed of one or more metal materials including nickel, titanium, tungsten, and palladium as an example without limitation. The surface of the portion 12 may also be plated with gold or the like.

[0065] The portion 13 of the source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as an example but not limited thereto.

[0066] In the second region A2 of the low-concentration impurity layer 33, a body region 28 containing impurities of a second conductivity type different from the first conductivity type is formed. In the body region 28, a source region 24 containing impurities of the first conductivity type, a gate conductor 25, and a gate insulating film 26 are formed. The source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the source region 24 and the body region 28 via the portion 23. The gate conductor 25 is connected to the gate electrode 29.

[0067] The portion 22 of the source electrode 21 is a layer that exhibits good bonding properties with a conductive bonding material such as solder during installation, and may be composed of a metal material containing one or more of nickel, titanium, tungsten, and palladium as an example without limitation. The surface of the portion 22 may also be plated with gold or the like.

[0068] The portion 23 of the source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be formed of a metal material including one or more of aluminum, copper, gold, and silver as an example but not limited thereto.

[0069] The body region 18 and the body region 28 are covered by an interlayer insulating layer 34 having an opening, and portions 13 and 23 of the source electrode are provided which pass through the opening of the interlayer insulating layer 34 and are connected to the source region 14 and the source region 24. The interlayer insulating layer 34 and portions 13 and 23 of the source electrode are covered by a passivation layer 35 having an opening, and portions 12 and 22 are provided which pass through the opening of the passivation layer 35 and are connected to portions 13 and 23 of the source electrode, respectively.

[0070] [2. Operation of semiconductor device]

[0071] exist Figure 1 In the semiconductor device 1 shown, for example, the first conductivity type can be set to N type, the second conductivity type can be set to P type, the source region 14, the source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are N-type semiconductors, and the body region 18 and the body region 28 are P-type semiconductors.

[0072] In addition, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the source region 14, the source region 24, the semiconductor substrate 32 and the low concentration impurity layer 33 are P type semiconductors, and the body region 18 and the body region 28 are N type semiconductors.

[0073] Hereinafter, the on-state operation of the semiconductor device 1 will be described assuming a so-called N-channel transistor in which the first conductivity type is an N-type and the second conductivity type is a P-type.

[0074] exist Figure 1In the semiconductor device 1 shown, if a high voltage is applied to the source electrode 11 and a low voltage is applied to the source electrode 21, and a voltage above the threshold is applied to the gate electrode 29 (gate conductor 25) with reference to the source electrode 21, a conduction channel is formed near the gate insulating film 26 in the body region 28. As a result, a conduction current flows through the path of source electrode 11-body region 18-low concentration impurity layer 33-semiconductor substrate 32-metal layer 31-semiconductor substrate 32-low concentration impurity layer 33-conduction channel formed in the body region 28-source region 24-source electrode 21, and the semiconductor device 1 is in an on state. In addition, there is a PN junction at the contact surface between the body region 18 and the low concentration impurity layer 33 in the conduction path, which functions as a body diode. In addition, since the conduction current flows through the metal layer 31, by thickening the metal layer 31 and expanding the cross-sectional area of ​​the conduction current path, the on-resistance of the semiconductor device 1 can be reduced. This conduction state is described later. Figure 3 The charging status of the device.

[0075] [3. Structure that achieves both reduced warpage and low on-resistance of semiconductor device]

[0076] Figure 3 This is a circuit diagram showing an application example of a semiconductor device 1 to a charging and discharging circuit of a smartphone or tablet computer. The semiconductor device 1 controls the discharge operation from a battery 3 to a load 4 and the charging operation from a load 4 to a battery 3 according to a control signal given from a control IC 2. When the semiconductor device 1 is applied as a charging and discharging circuit of a smartphone or tablet computer, the on-resistance is required to be 2.2 to 2.4 mΩ or less as a 20V withstand voltage specification due to the constraints of shortening the charging time and realizing rapid charging.

[0077] Furthermore, when the semiconductor device 1 is mounted on a mounting substrate, the source electrode 11, the gate electrode 19, the source electrode 21, and the gate electrode 29 are bonded to electrodes provided on the mounting substrate in a flip-chip manner via a conductive bonding material such as solder. In this case, the greater the warpage of the semiconductor device 1, the more unstable the electrical connection between the source electrode 11, the gate electrode 19, the source electrode 21, and the gate electrode 29 and the electrodes provided on the mounting substrate. That is, in order to stabilize the bonding with the electrodes on the mounting substrate of the semiconductor device 1, the warpage of the semiconductor device 1 needs to be reduced.

[0078] Figure 4A The graph is a result of confirming the warpage amount and on-resistance corresponding to the Ag layer thickness / Si layer thickness (the value obtained by dividing the Ag layer thickness by the Si layer thickness) in a semiconductor device having a stacked structure of a semiconductor layer 40 (hereinafter referred to as a Si layer) / metal layer 31 (hereinafter referred to as an Ag layer) through a trial production experiment. More specifically, the graph shows a long side length of 3.40 mm ( Figure 2 L1) and the short side length is 1.96mm( Figure 2 The warpage amount and on-resistance of the semiconductor device L2 at 250°C. According to the figure, the on-resistance is required to meet the Ag layer thickness / Si layer thickness ratio of 1.0 or greater, which is less than 2.4 mΩ. On the other hand, in the range where the Ag layer thickness / Si layer thickness ratio is greater than 1.0, the warpage amount at 250°C does not become less than 60 μm, which is the industry standard.

[0079] In contrast, the metal layer 30 (hereinafter referred to as the Ni layer) is configured to suppress warping in the semiconductor device 1 while ensuring low on-resistance of the semiconductor device 1. This is a structure in which the metal layer 31 is sandwiched between the semiconductor layer 40 and the metal layer 30. From the perspective of stress balance on both sides of the metal layer 31, in order to suppress the amount of warping, it is preferred that the metal layer 30 has the same material properties and the same thickness as the semiconductor layer 40. However, since such a metal material does not exist, the metal layer 30 at least needs to have a material property value that is closer to the material property value of the semiconductor layer 40 than the material property value of the metal layer 31, and the thickness of the metal layer 30 is thicker than the thickness of the semiconductor layer 40.

[0080] Table 1 shows typical film thicknesses and physical property values ​​of each layer of Si layer / Ag layer / Ni layer as an example of semiconductor layer 40 / metal layer 31 / metal layer 30.

[0081] [Table 1]

[0082]

[0083] As shown in Table 1, the Young's modulus of the second metal material constituting the Ni layer is greater than the Young's modulus of the first metal material constituting the Ag layer. In addition, the thickness of the Ni layer is thicker than the Si layer, and the thickness of the Ag layer is thicker than the thickness of the Si layer. Furthermore, the linear expansion coefficient of the second metal material constituting the Ni layer is smaller than the linear expansion coefficient of the first metal material constituting the Ag layer. By making the linear expansion coefficient of the Ni layer smaller than the linear expansion coefficient of the Ag layer, the warping of the semiconductor device 1 can be further suppressed.

[0084] Figure 4B The graph is a result of confirming the warpage amount corresponding to the Ni layer thickness in the semiconductor device 1 having a stacked structure of Si layer / Ag layer / Ni layer through a trial production experiment. More specifically, Figure 4B 3 is a graph showing the result of predicting the warpage amount at 250° C. corresponding to the Ni layer thickness when the Si layer thickness is 20 μm and the Ag layer thickness is 50 μm by a computer simulator.

[0085] As shown in the figure, in the state without Ni layer (Ni layer thickness = 0 μm), the warpage is about 67 μm, but the warpage decreases as the Ni layer thickness increases. Here, in order to completely suppress the installation problem of warpage, the warpage needs to be reduced to about 30 μm. For this purpose, the Ni layer needs to be thicker than the Si layer.

[0086] according to Figure 4A and Figure 4B As a result, in order to achieve both reduced warpage and low on-resistance, in the semiconductor device 1 having a stacked structure of Si layer / Ag layer / Ni layer, the Ag layer needs to be thicker than the Si layer, and the Ni layer needs to be thicker than the Si layer.

[0087] Next, a stacked structure that can achieve both reduction in warpage and low on-resistance will be described.

[0088] Figure 5A This is a graph showing the results of on-resistance corresponding to the thickness of the Si layer in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer or Si layer / Ag layer, which was confirmed through trial production experiments. More specifically, the figure shows a graph showing on-resistance corresponding to the thickness of the Si layer when the Ag layer thickness is 30μm and 50μm in a semiconductor device having a stacked structure of Si layer / Ag layer. At the same time, the figure shows a graph showing on-resistance corresponding to the thickness of the Si layer when the Ag layer thickness is 30μm and the Ni layer thickness is 30μm, and when the Ag layer thickness is 50μm and the Ni layer thickness is 30μm in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer.

[0089] like Figure 5A As shown in FIG. 1 , as the Si layer is made thinner, the on-resistance of the semiconductor device becomes lower. However, although the on-resistance can be reduced by thinning the Si layer, problems in the manufacturing process such as uneven film thickness increase and local cracking or cracking within the semiconductor substrate wafer surface become prominent, so it is difficult to achieve stable thin filming below 20 μm. In addition, the thicker the Ag layer, the lower the on-resistance. If a Ni layer is added, the on-resistance tends to decrease.

[0090] Figure 5BThis is a graph of the results of the on-resistance corresponding to the Ni layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer, which was confirmed through trial production experiments. More specifically, in this figure, a graph of the on-resistance corresponding to the Ni layer thickness is shown for Si layer (20μm) / Ag layer (30μm) and Si layer (20μm) / Ag layer (50μm). It can be seen from the figure that as the Ni layer thickness becomes thicker, the on-resistance of the semiconductor device decreases slightly, so by adding a Ni layer, the on-resistance of the semiconductor device will not increase. In particular, when the Si layer thickness is 20μm, the Ag layer thickness is 30μm, and the Ni layer thickness is 30μm, the on-resistance is reduced to about 2.3mΩ.

[0091] according to Figure 5A and Figure 5B It can also be seen that in the semiconductor device 1 having the stacked structure of Si layer / Ag layer / Ni layer, since the Ag layer is thicker than the Si layer and the Ni layer is thicker than the Si layer, both the reduction in warpage and the low on-resistance can be achieved.

[0092] [4. Microstructure of semiconductor devices]

[0093] In the semiconductor device 1 related to the present embodiment, it is preferred that the Ni layer is thicker than the Si layer, and the Si layer is thicker than 20μm, so the Ni layer needs to be a layer with a thickness of several tens of μm. According to this viewpoint, the Ni layer is formed, for example, by a wet plating method. The wet plating method is generally divided into an electroplating method and a chemical plating method, but the electroplating method has the characteristics of less restrictions on film thickness, can be formed at low temperature, and has less thermal impact on the equipment. Therefore, as a method for making the Ni layer of the semiconductor device 1, the electroplating method is preferred. As a method for forming the Ni layer, dry methods such as evaporation can also be cited, but because its crystal particles are on the order of several tens of nm and the film formation rate is low, it is unrealistic as a method for making a thick film with a film thickness of more than 10μm.

[0094] Electroplating is a method in which ionized metal species in a solution migrate toward the cathode due to a potential gradient, and the metal species chemically bonds with the atoms of the substrate at the cathode to form a metal film. Therefore, the crystal particles of the formed metal film tend to grow and become larger.

[0095] Figure 6 1 is a diagram showing the crystal state of the Ni layer of the semiconductor device 1 according to the embodiment. Figure 6 (a) is an electron microscope photograph of the main surface 30b of the Ni layer of the semiconductor device 1. Figure 6 (b) is an electron microscope photograph of a cross section of the Ni layer of the semiconductor device 1 .

[0096] exist Figure 6 In (a), the primary surface 30b of the Ni layer presents a concavo-convex structure of particles that are aggregates of a plurality of crystals, and the period of the concavo-convex structure is, for example, 10 to 20 μm. Figure 6 In (b), in the cross-sectional structure of the Ni layer, a plurality of crystals having a size of 1 μm or more that grow in a direction substantially perpendicular to the primary surface 30 b are present.

[0097] according to Figure 6 (a) and (b) are characteristics of a thick metal layer 30 (Ni layer) formed by electroplating, in which the period of projections and depressions in the horizontal direction (x-axis direction) of the main surface 30b of the metal layer 30 (Ni layer) is larger than the grain size in the horizontal direction (x-axis direction) of the crystals constituting the metal layer 30 (Ni layer).

[0098] This shows that electroplating is effective as a method for forming a Ni layer thicker than a Si layer.

[0099] Figure 7 1 is an electron microscope photograph showing a cross section of a Ni layer / Ag layer of a semiconductor device 1 according to an embodiment. Figure 7 (a), (b) and (c) show cross sections of an Ag layer and a Ni layer formed by electroplating when the plating current is 2.1 A, 4.5 A and 8.0 A, respectively.

[0100] As a characteristic of a metal film, it is known that there is a relationship between the crystallinity of the metal film and the hardness of the metal film. The metal film composed of finer crystal particles is harder (the Young's modulus is larger). In addition, in the electroplating method, the crystal grains become larger as the film is formed. In other words, the crystal grains become larger as the film thickness increases.

[0101] In the semiconductor device 1 according to the present embodiment, the Ni layer / Ag layer forms an Ag layer on the main surface 40b of the Si layer, and then forms a Ni layer on the main surface 31b of the Ag layer. Figure 7 As shown, regardless of the plating current, the crystal grain size of the metal layer 30 (Ni layer) near the main surface 30a is smaller than the crystal grain size of the metal layer 30 (Ni layer) near the main surface 30b. In addition, the crystal grain size of the metal layer 30 (Ni layer) near the main surface 30a is smaller than the crystal grain size of the metal layer 31 (Ag layer) near the main surface 31b.

[0102] Therefore, in addition to the Ni layer with a relatively small linear expansion coefficient being in contact with the Ag layer with a relatively large linear expansion coefficient, the Ni layer with a relatively small crystal grain size is in contact with the Ag layer with a relatively large crystal grain size, so the Ag layer is not easy to extend when the temperature rises, and the effect of suppressing the warping of the semiconductor device 1 becomes higher.

[0103] Figure 8 This is a graph comparing the measured value and predicted value of the warpage amount corresponding to the Ni layer thickness in a semiconductor device having a stacked structure of Si layer / Ag layer / Ni layer. In this figure, the measured value of the trial production experiment and the predicted value of the computer simulator are shown for the warpage amount caused by the increase in Ni layer thickness when the Si layer thickness is 20μm and the Ag layer thickness is 50μm in the stacked structure of Si layer / Ag layer / Ni layer. It can be seen that in the area where the Ni layer thickness is more than 20μm, the measured value of the warpage amount deviates from the predicted value, and the effect of warpage suppression caused by the increase in Ni layer thickness decreases in the measured value.

[0104] In addition, the warpage suppression effect of the semiconductor device 1 is improved by increasing the thickness of the Ni layer, but the time required for the formation of the plated film of the Ni layer is prolonged, and the manufacturing cost is increased. In addition, the cutting load in the dicing process of singulating the semiconductor device 1 is increased, and there is a possibility that the manufacturing cost is increased due to the reduction in cutting speed, the dicing blade is damaged, and other undesirable conditions may occur.

[0105] Therefore, from the perspective of effective warpage suppression effect brought about by increasing the thickness of the Ni layer and the manufacturing process, the Ni layer thickness is preferably 30 μm or less. That is, the thickness of the metal layer 30 (Ni layer) is preferably thicker than the semiconductor layer 40 (Si layer) and 30 μm or less. In this way, an effective warpage suppression effect can be obtained, and the manufacturing process can be shortened and the cost can be reduced.

[0106] Fig. 9 1 is a schematic cross-sectional view of a semiconductor device having a Ni layer composed of a plurality of layers having different crystal grain sizes.

[0107] Fig. 9 (a) shows a state where the crystal grains of the first layer 70A having the main surface 30a are smaller than the crystal grains of the second layer 70B having the main surface 30b. In this structure, the first layer 70A is a harder layer than the second layer 70B. Therefore, as a tendency of warping in the Ni layer, the softer second layer 70B is easier to extend than the harder first layer 70A, and the main surface 30b side of the Ni layer is convexly warped, which is in the same direction as the warping direction between the Si layer and the Ag layer. That is, by stacking the Ni layer, although the warping amount of the semiconductor device 1 is reduced, the warping suppression effect of the semiconductor device is reduced according to the above-mentioned crystal grain size distribution in the Ni layer.

[0108] Fig. 9 The distribution of the crystal grain size of the Ni layer shown in (a) is the result of forming the Ni layer without changing the film forming conditions of the electroplating method. Fig. 9The structure of the Ni layer shown in (a) can suppress the warping of the semiconductor device while forming the Ni layer by a simplified electroplating method in which the plating current condition is kept constant.

[0109] Fig. 9 (b) shows that the crystal grain size of the first layer 70C having the main surface 30a and the crystal grain size of the second layer 70D having the main surface 30b are approximately the same. Furthermore, the crystal grain size of the metal layer 30 (Ni layer) is smaller than the crystal grain size on the main surface 31b side of the metal layer 31 (Ag layer). In this structure, the Ni layer has a uniform hardness, and the Ni layer is harder than the Ag layer, so the warping of the semiconductor device 1 can be suppressed. In addition, since the Ni layer that can serve as the outer surface of the semiconductor device 1 is harder than the Ag layer, the damage of the cutting blade can be suppressed in the cutting process by cutting, and the manufacturing process can be simplified.

[0110] Fig. 9 (c) represents a state in which the crystal grains of the first layer 70E having the main surface 30a are larger than the crystal grains of the second layer 70F having the main surface 30b. In this structure, the first layer 70E is a softer layer than the second layer 70F. Therefore, as the tendency of the warping in the Ni layer, the softer first layer 70E is easier to extend than the harder second layer 70F, and the main surface 30a side of the Ni layer is convexly warped, which is in the opposite direction to the warping direction between the Si layer and the Ag layer. That is, according to the above-mentioned crystal grain size distribution in the Ni layer, the warping suppression effect of the semiconductor device 1 is enhanced. In addition, since the main surface 30b side of the Ni layer that can become the outer surface of the semiconductor device 1 is harder, the cutting process by cutting becomes easy, and the simplification of the manufacturing process can be achieved.

[0111] In addition, if Fig. 9 To realize the crystalline state of the first layer and the crystalline state of the second layer as in (b) and (c), it is sufficient to perform control such as setting separate plating current conditions between the first layer and the second layer.

[0112] Next, the relationship between the crystal orientation and hardness of the metal layer 30 will be described.

[0113] Generally, the physical property values ​​of a crystal with atoms arranged correctly according to known rules vary depending on the direction of the crystal. The same is true for Ni, where the physical property values ​​vary depending on the crystal orientation. The Young's modulus of a Ni single crystal in the crystal growth direction is <110> In the case of orientation, it is 2.04×10 12 (dyn / cm 2 ), in the crystal growth direction <100> In the case of orientation, it is 1.21×10 12 (dyn / cm 2).Right now, <110> The Ni layer with preferential orientation <100> The Ni layer in the preferred orientation has a larger Young's modulus and is harder.

[0114] In addition, when the Ni layer is formed by electroplating, it is known that the crystal orientation of the Ni layer varies depending on the solution. For example, in the case of a Ni layer using a sulfuric acid bath or a watts bath, the crystal growth direction is <110> The preferred orientation is that the Ni layer using the aminosulfonic acid bath becomes a crystal growth direction <100> Preferred orientation of crystals.

[0115] Fig.10 1 is a diagram showing the temperature dependence of the warpage of a semiconductor device having a Ni layer composed of two layers formed by different plating methods. (a) of the figure is a cross-sectional view of a stacked structure in which the first layer (film thickness 15 μm) using an aminosulfonic acid bath and the second layer (film thickness 15 μm) using a sulfuric acid bath are sequentially formed from the main surface 31b of the Ag layer (film thickness 50 μm). In addition, (b) of the figure shows the temperature dependence of the warpage in the stacked structure of the Ag layer (film thickness 50 μm) and the first layer (film thickness 30 μm), the temperature dependence of the warpage in the stacked structure of the Ag layer (film thickness 50 μm) and the second layer (film thickness 15 μm), and the temperature dependence of the warpage in the stacked structure of the Ag layer (film thickness 50 μm), the first layer (film thickness 15 μm) and the second layer (film thickness 15 μm).

[0116] According to the above understanding, since the crystal growth direction of the first layer (Ni sulfamic acid) (negative direction of z axis) is <100> Preferred orientation, the crystal growth direction of the second layer (Ni sulfate) (negative direction of z axis) is <110> The preferred orientation makes the second layer have a higher Young's modulus than the first layer. As a result, the second layer tends to have a smaller warpage than the first layer, and the upper limit of the warpage in the high temperature region becomes smaller. However, since the lower limit of the warpage in the low temperature region tends to decrease and reaches the negative region, the upper and lower limits of the warpage of the first layer are narrower. Here, by stacking the first layer and the second layer having different characteristics for the warpage, the upper limit of the warpage in the high temperature region can be made smaller than that of the first layer, and the lower limit value of the warpage in the low temperature region (the value in the negative region) can be made larger than that of the second layer.

[0117] In addition, the "preferred crystal orientation" is also called <110> The preferred orientation (or {110} plane preferred orientation) etc. indicates that the proportion of crystals having a specified crystal orientation (or crystal plane) is the largest among all crystals in a unit volume or unit area, and can be confirmed using X-ray diffraction or backscattered electron diffraction.

[0118] According to the above structure, the metal layer 30 (Ni layer) includes a first layer having a main surface 30a and a second layer having a main surface 30b. In the horizontal direction of the main surface 30b, the metal crystals constituting the first layer and the metal crystals constituting the second layer have different preferential orientation planes.

[0119] This makes it easier to control the warpage amount (absolute value and range) and the like of the semiconductor device 1 .

[0120] Alternatively, in the horizontal direction of the principal surface 30 b , metal crystals constituting one of the first and second layers may be preferentially oriented in the {100} plane, and metal crystals constituting the other of the first and second layers may be preferentially oriented in the {110} plane.

[0121] This makes it easier to control the warpage amount (absolute value and range) and the like of the semiconductor device 1 .

[0122] Furthermore, regardless of whether the metal layer 30 (Ni layer) is composed of a plurality of layers having different crystal orientations or a single layer, the metal crystals constituting the metal layer 30 (Ni layer) may be preferentially oriented in the {100} plane on the primary surface 30 b .

[0123] Thus, since the Young's modulus of the {100} plane is smaller than that of the {110} plane, laser marking in the marking step becomes easy.

[0124] Furthermore, regardless of whether the metal layer 30 (Ni layer) is composed of a plurality of layers having different crystal orientations or a single layer, the metal crystals constituting the metal layer 30 (Ni layer) may be preferentially oriented in the {110} plane on the primary surface 30 b .

[0125] Thus, since the Young's modulus of the {110} plane is larger than that of the {100} plane, the warping of the semiconductor device 1 can be suppressed more effectively.

[0126] [5. Marking Identification of Semiconductor Devices]

[0127] The semiconductor device 1 of this embodiment further has a marking formed on the main surface 30b of the metal layer 30 (Ni layer). The above-mentioned marking is, for example, a mark including identification information such as a product name and a manufacturing date. In the semiconductor device 1, for example, the main surface 30b is marked by laser irradiation so that it becomes easy to identify from the outside even after flipping. Among the lasers used for the above-mentioned laser irradiation, YAG laser is often used. YAG laser is a laser that can perform fine marking on metal materials including resin materials.

[0128] The recognizability of the engraving formed on the main surface 30b of the Ni layer greatly affects the surface state of the Ni layer. By irradiating the main surface 30b of the Ni layer with laser, the grain boundaries of the laser irradiated area in the main surface 30b are reconstructed and the surface state changes. The recognizability of the engraving is determined by the relationship between the width (engraved pattern width) and depth (engraving depth) of the linear area after the surface state change and the surface state of the area of ​​the main surface 30b outside the linear area. As an example of the deterioration of the recognizability of the engraving, there can be cited the situation where the identification of the engraving becomes difficult due to the disappearance and blurring of the engraved characters and lines.

[0129] Fig.11 It is a schematic cross-sectional view of a semiconductor device showing the relationship between the concavo-convex cycle of the main surface 30b of the Ni layer and the width of the engraved pattern and the engraving recognizability. As shown in the figure, when the pattern width (in the x-axis direction) of the linear region where the surface state changes due to laser irradiation is smaller than the concavo-convex cycle of the main surface 30b of the Ni layer, the engraving cannot be recognized and is judged as unqualified. In contrast, when the pattern width of the above-mentioned linear region is larger than the concavo-convex cycle of the main surface 30b of the Ni layer, the engraving can be recognized and is judged as good.

[0130] Fig.12 : is a diagram showing the relationship between the maximum height roughness of the main surface 30b of the Ni layer and the marking depth and the marking recognition. As shown in the figure, when the marking depth (in the z-axis direction) of the linear region where the surface state changes due to laser irradiation is smaller than the maximum height roughness Rz of the main surface 30b of the Ni layer, the marking cannot be recognized and is judged as defective. In contrast, when the marking depth of the linear region is greater than the maximum height roughness Rz of the main surface 30b of the Ni layer, the marking can be recognized and is judged as good.

[0131] [6. End structure of semiconductor device]

[0132] Fig.13A 1 is a cross-sectional view of a semiconductor device 1A according to an embodiment. As shown in the figure, the semiconductor device 1A includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), transistors 10 and 20, and protrusions 36A, 36B, 37A, and 37B. The semiconductor device 1A differs from the semiconductor device 1 according to the embodiment in that it includes protrusions 36A, 36B, 37A, and 37B, and that the periphery of the Si layer is retreated toward the center of the semiconductor device 1A relative to the periphery of the Ni layer and the Ag layer when the Si layer is viewed in a plane. Hereinafter, regarding the semiconductor device 1A, description of the same points as the semiconductor device 1 will be omitted, and the description will be centered on the different points.

[0133] When the semiconductor layer 40 (Si layer) is viewed in a planar manner, the periphery of the semiconductor layer 40 (Si layer) is retreated from the peripheries of the metal layers 30 (Ni layer) and 31 (Ag layer) toward the center of the semiconductor device 1A. This is because the process of singulating the semiconductor device 1A is performed through a two-stage cutting process (a cutting process of the Si layer, and a cutting process of the Ni layer and the Ag layer). In addition, in the semiconductor device 1A, a structure in which the periphery of the Si layer is retreated from the peripheries of the Ni layer and the Ag layer is not essential.

[0134] The protrusions 36A and 36B are first protrusions protruding from the main surface 30b in the direction from the main surface 30a toward the main surface 30b (negative direction of the z-axis) at the periphery of the Ni layer when the metal layer 30 (Ni layer) is viewed from the main surface 30b in a planar manner. The protrusions 36A and 36B include at least one of the first metal material included in the metal layer 31 and the second metal material included in the metal layer 30. In the semiconductor device 1A, the protrusions 36A and 36B include at least one of Ag and Ni.

[0135] This can enhance the mechanical strength and hardness of the outer periphery of the Ni layer, thereby enhancing the suppression of warping of the semiconductor device 1A.

[0136] Furthermore, the protrusions 36A and 36B may be formed on two opposing sides or all sides of the sides constituting the outer periphery of the metal layer 30 (Ni layer) in the above-mentioned plan view.

[0137] This can enhance the suppression of warping of the semiconductor device 1A in a direction perpendicular to the direction in which the protrusions 36A and 36B are formed.

[0138] In addition, the protrusion height of the protrusions 36A and 36B is, for example, 1 / 3 or more of the thickness of the metal layer 30 (Ni layer).

[0139] Thereby, the mechanical strength and hardness of the outer periphery of the Ni layer can be further enhanced.

[0140] Furthermore, the protrusion width of the protrusions 36A and 36B is, for example, 4 μm or more.

[0141] This can further enhance the mechanical strength and hardness of the periphery of the Ni layer. In addition, it can suppress the protrusions 36A and 36B from detaching from the semiconductor device 1A during the cleaning process, thereby suppressing the occurrence of short circuit failures in the semiconductor device 1A due to detached conductive materials.

[0142] Furthermore, in the protrusions 36A and 36B, the content of the second metal material is higher than the content of the first metal material. In the semiconductor device 1A, in the protrusions 36A and 36B, the content of Ni is higher than the content of Ag.

[0143] Thus, the protrusions 36A and 36B contain more Ni having a larger Young's modulus than Ag having a smaller Young's modulus, and thus become relatively hard protrusions. Therefore, the mechanical strength and hardness of the periphery of the metal layer 30 can be further enhanced, and in addition, since the protrusions 36A and 36B can be prevented from detaching from the semiconductor device 1A during the cleaning process, the semiconductor device 1A can be prevented from short-circuiting due to the detached conductive material.

[0144] In addition, in the semiconductor device 1A, the structures of the protrusions 36A and 36B are not essential.

[0145] When the semiconductor layer 40 (Si layer) is viewed in a plan view, the outer periphery of the semiconductor layer 40 (Si layer) is formed inside the outer periphery of the metal layer 31 (Ag layer) with a gap therebetween.

[0146] The protrusions 37A and 37B are second protrusions protruding from the main surface 31a in the direction from the main surface 31b toward the main surface 31a (z-axis positive direction) at the periphery of the metal layer 31 (Ag layer) when the metal layer 31 (Ag layer) is viewed from the main surface 31a. The protrusions 37A and 37B include at least one of the first metal material included in the metal layer 31 (Ag layer) and the second metal material included in the metal layer 30 (Ni layer). In the semiconductor device 1A, the protrusions 37A and 37B include at least one of Ag and Ni.

[0147] This can enhance the mechanical strength and hardness of the outer periphery of the Ag layer, thereby enhancing the suppression of warping of the semiconductor device 1A.

[0148] Furthermore, the protrusions 37A and 37B may be formed on two opposing sides or all sides of the sides constituting the outer periphery of the metal layer 31 (Ag layer) in the plan view.

[0149] This can enhance the suppression of warping of the semiconductor device 1A in a direction perpendicular to the direction in which the protrusions 37A and 37B are formed.

[0150] In addition, in the semiconductor device 1A, the structures of the protrusions 37A and 37B are not essential.

[0151] In addition, in the semiconductor device 1A, the protrusions 36A, 36B, 37A and 37B are formed by extending the components of the metal layers 30 (Ni layer) and 31 (Ag layer) from the outer periphery of the metal layers 30 (Ni layer) and 31 (Ag layer) through the singulation process of the semiconductor device 1A.

[0152] In the singulation process of the semiconductor device 1A, for example, blade cutting is used. This is a process of cutting the Si layer, Ni layer and Ag layer by rotating at high speed using a circular blade with a width of about tens of μm attached with a diamond grindstone. At this time, the circular blade cuts from the Si layer side to the Ni layer side, but the material of about the width of the circular blade (tens of μm) is cut off. Therefore, the ductile Ni layer and Ag layer are stretched in the cutting direction of the circular blade to form a protrusion (burr). The protrusion forms a new roughly flat surface in a direction perpendicular to the surface of the Ni layer and the Ag layer, and acts as a reinforcement for the Ni layer and the Ag layer. In this way, the warping suppression of the semiconductor device 1A can be strengthened.

[0153] Fig. 13B 1 is a cross-sectional view of a semiconductor device 1B according to an embodiment. As shown in the figure, the semiconductor device 1B includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), and protrusions 36B, 37B, and 38. The semiconductor device 1B is different from the semiconductor device 1A in that it includes a protrusion 38. Hereinafter, the description of the semiconductor device 1B will be omitted for the same points as the semiconductor device 1A, and the description will focus on the different points.

[0154] The protrusion 38 is a third protrusion formed on the outer peripheral side surface of the metal layer 31 (Ag layer) in the direction from the center of the metal layer 31 (Ag layer) toward the outer periphery when the metal layer 31 (Ag layer) is viewed in a plane (the positive direction of the x-axis). In addition, the protrusion 38 can also be formed on the outer peripheral side surface of the Ni layer in the direction from the center of the Ni layer toward the outer periphery when the Ni layer is viewed in a plane (the positive direction of the x-axis).

[0155] This can enhance the mechanical strength and hardness of the outer periphery of the Ni layer, thereby suppressing the warping of the semiconductor device 1B.

[0156] Fig. 13C 1 is a cross-sectional view of a semiconductor device 1C according to an embodiment. As shown in the figure, the semiconductor device 1C includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), a cover layer 50, and protrusions 37A (not shown) and 37B. The semiconductor device 1C is different from the semiconductor device 1A in that it does not have protrusions 36A and 36B but includes a cover layer 50. Hereinafter, the description of the semiconductor device 1C will be omitted for the same points as the semiconductor device 1A, and the description will focus on the different points.

[0157] The covering layer 50 is a first covering layer made of ceramic material or plastic material and has a main surface 50a (7th main surface) and a main surface 50b (8th main surface) facing each other, and the main surface 50a is formed by directly contacting the main surface 30b of the Ni layer or sandwiching a bonding material.

[0158] In addition, the cover layer 50 is disposed before the singulation step of the semiconductor device 1C. Thus, it is possible to avoid the generation of protrusions (burrs) on the main surface 30b of the Ni layer in the singulation step using a blade dicing.

[0159] Fig.13D 1 is a cross-sectional view of a semiconductor device 1D according to an embodiment. As shown in the figure, the semiconductor device 1D includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), and capping layers 50 and 51. The semiconductor device 1D is different from the semiconductor device 1C in that it does not have protrusions 37A and 37B but includes a capping layer 51. Hereinafter, the description of the semiconductor device 1D will be omitted for the same points as the semiconductor device 1C, and the description will focus on the different points.

[0160] The covering layer 51 is a second covering layer made of ceramic material or plastic material, and has a main surface 51a (9th main surface) and a main surface 51b (10th main surface) facing each other at the outer edge of the metal layer 31 (Ag layer) when the metal layer 31 (Ag layer) is viewed in a plane. The main surface 51b is formed by directly contacting the main surface 31a of the metal layer 31 (Ag layer) or sandwiching a bonding material.

[0161] In addition, the cover layer 51 is disposed before the singulation step of the semiconductor device 1D. Thus, it is possible to avoid the generation of protrusions (burrs) on the main surface 31a of the Ag layer in the singulation step using a blade dicing.

[0162] Fig.13E 1 is a cross-sectional view of a semiconductor device 1E according to an embodiment. As shown in the figure, the semiconductor device 1E includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), a cap layer 50, and a groove portion 60. The semiconductor device 1E is different from the semiconductor device 1D in that it does not have a cap layer 51 but has a groove portion 60 that separates the Si layer. Hereinafter, the description of the semiconductor device 1E will be omitted for the same points as the semiconductor device 1D, and the description will focus on the different points.

[0163] The groove portion 60 is a groove formed along the outer periphery of the semiconductor layer 40 (Si layer) at the outer edge portion of the semiconductor layer 40 (Si layer) and having the main surface 31 a as the bottom surface.

[0164] Furthermore, the grooves 60 are formed before the singulation step of the semiconductor device 1E. Thus, in the singulation step using a blade dicing, it is possible to avoid generation of Si layer fragments that reach the body region 18 or the body region 28.

[0165] Fig.13F1 is a cross-sectional view of a semiconductor device 1F according to an embodiment. As shown in the figure, the semiconductor device 1F includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), and a composite 39. The semiconductor device 1F is different from the semiconductor device 1 in that it includes the composite 39. Hereinafter, the description of the semiconductor device 1F will be omitted for the same points as the semiconductor device 1, and the description will focus on the different points.

[0166] The composite material 39 is a composite material of the first metal material and the second metal material formed on the outer peripheral side surface of the metal layer 30 (Ni layer). In the present embodiment, the composite material 39 is a composite material of Ag and Ni.

[0167] Thus, the mechanical strength and hardness of the periphery of the Ni layer can be enhanced, so the warpage suppression of the semiconductor device 1F can be strengthened. In addition, the composite 39 can also be formed on the peripheral side of the Ag layer. In this case, the mechanical strength and hardness of the periphery of the Ag layer can be enhanced, so the warpage suppression of the semiconductor device 1F can be strengthened.

[0168] In the singulation process of the semiconductor device 1F, laser dicing is used as a method of cutting the Ni layer and the Ag layer, for example. Therefore, a composite of the first metal material and the second metal material melted by the laser is attached to the outer peripheral side surfaces of the Ni layer and the Ag layer.

[0169] In addition, when the metal layers 30 (Ni layer) and 31 (Ag layer) are viewed in a plan view, the composite 39 may be formed on the outer peripheral side surface of at least one of the metal layers 30 (Ni layer) and 31 (Ag layer) over the entire circumference of the semiconductor device 1F.

[0170] Thereby, the mechanical strength and hardness of the periphery of the Ni layer or the Ag layer can be further enhanced.

[0171] In addition, if Fig.13F As shown, for example, in the direction from the main surface 31a toward the main surface 30b (negative z-axis direction), the center position of the composite 39 is between the position of half the distance from the main surface 31a to the main surface 30b and the position of the main surface 30b.

[0172] Thus, in the singulation process by laser cutting, it is possible to suppress the loose bodies (hereinafter referred to as debris) of the components of the Ni layer and the Ag layer from being attached to the surface (z-axis positive direction side) of the semiconductor device 1F. For example, when cutting the composite layer of the Ni layer and the Ag layer, the generation of debris can be suppressed by cutting the remaining thin composite layer from the main surface 31a side or from the main surface 30b side with a laser output of weaker intensity after the thickness of more than half of the distance from the main surface 31a to the main surface 30b is cut with a blade from the main surface 31a side.

[0173] In addition, it can be confirmed that the protrusions 36A, 36B, 37A, 37B, 38 and the composite 39 are continuously formed over a distance of more than 1 / 3 of each side of the outer periphery of the semiconductor device 1A. The structure in which the protrusions or the composite are continuously formed on the outer periphery of the semiconductor device 1A further enhances the warpage suppression of the semiconductor device 1A. In addition, depending on the conditions of the singulation process, the protrusions or the composite may be continuously formed over a distance of more than 1 / 2 or more than 2 / 3 of each side of the outer periphery of the semiconductor device 1A, in which case the warpage suppression of the semiconductor device 1A can be further enhanced.

[0174] Fig.14 1 is a cross-sectional view of a semiconductor device 1G according to an embodiment. As shown in the figure, the semiconductor device 1G includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), and transistors 10 and 20. The semiconductor device 1G is different from the semiconductor device 1 in that the periphery of the semiconductor layer 40 (Si layer) is retreated toward the center of the semiconductor device 1G relative to the periphery of the metal layers 30 (Ni layer) and 31 (Ag layer) when the semiconductor layer 40 (Si layer) is viewed in a plan view. Hereinafter, for the semiconductor device 1G, descriptions of the same points as the semiconductor device 1 are omitted, and the description will be centered on the different points.

[0175] When the semiconductor layer 40 (Si layer) is viewed in a plane, the outer periphery of the semiconductor layer 40 (Si layer) is spaced apart from the outer periphery of the metal layer 31 (Ag layer) and formed on the inner side. Furthermore, the outer periphery of the semiconductor layer 40 (Si layer) may be spaced apart from the outer periphery of the metal layer 31 (Ag layer) and formed on the inner side over the entire periphery.

[0176] In addition, the above structure has been formed before the Ni layer and the Ag layer are cut in the singulation process. As a result, it is possible to suppress the attachment of fragments and debris of the Si layer to the side of the Si layer when the Ni layer and the Ag layer are cut by cutting. In addition, when the blade cuts the Ni layer and the Ag layer, it is also possible not to cut the Si layer at the same time, so the cutting load of the blade cutting can be reduced, and the selection of the cutting blade used in the cutting becomes easy. This is because the types of cutting blades suitable for cutting are different in the Si layer of ceramic material and the Ni layer and the Ag layer of metal material.

[0177] Furthermore, the distance (length of the gap) between the periphery of the semiconductor layer 40 (Si layer) and the periphery of the metal layer 31 (Ag layer) in the planar direction of the semiconductor layer 40 (Si layer) and the metal layer 31 (Ag layer) is, for example, 15 μm or more.

[0178] Fig.151 is a diagram for explaining the retreat distance of the Si layer in the semiconductor device 1G according to the embodiment. This figure shows a cross-sectional view of the boundary region between two adjacent semiconductor devices 1G during the manufacturing process.

[0179] In the singulation process of the semiconductor device 1G, when the Si layer is cut by a blade, there is a case where fragments are generated in the Si layer. In order to avoid this, it is effective to use not only blade cutting but also plasma cutting to perform singulation in the semiconductor device 1G. Plasma cutting can perform cutting without generating fragments on the cut surface of the Si layer by dry etching method that chemically removes the Si layer by plasma reaction.

[0180] In the process of singulating the semiconductor device 1G, by plasma dicing, the area to be subsequently diced by blade or laser is cut to a width (in Fig.15 The cutting width is the laser processing width or blade processing width) plus the excess width (in Fig.15 The Si layer is removed by an amount equal to the plasma processing width. Then, the Ag layer and the Ni layer are cut by blade cutting or laser cutting. Thus, the semiconductor device 1G can be singulated without generating fragments on the periphery of the Si layer.

[0181] When the Ag layer and the Ni layer are cut, in order to prevent the Si layer from being damaged by blade cutting or laser cutting, the interval between the Si layers of the adjacent semiconductor devices 1G needs to be ensured to be larger than the laser processing width or the blade processing width. Thus, the outer periphery of the Si layer is spaced apart from the outer periphery of the Ag layer and formed on the inner side.

[0182] like Fig.15 As shown, when the laser processing width or the blade processing width is set to 30 to 35 μm, for example, and the processing width based on plasma cutting is set to 65 μm, for example, the distance between the outer periphery of the Si layer and the outer periphery of the Ag layer ( Fig.15 The retreat distance LB) is, for example, 15 to 17 μm.

[0183] Thus, when the Si layer is processed by plasma dicing and the Ag layer and the Ni layer are processed by blade dicing or laser dicing as the singulation step of the semiconductor device 1G, singulation can be easily achieved without generating fragments on the periphery of the Si layer.

[0184] Fig.16This is an electron microscope photograph of the side surface of the Si layer in the semiconductor device 1G of the embodiment. As shown in the figure, the maximum height roughness Rz of the concavo-convex side surface of the end side surface on the main surface 40b side in contact with the main surface 31a in the peripheral side surface of the semiconductor layer 40 (Si layer) is approximately equal to the maximum height roughness Rz of the concavo-convex side surface on the main surface 40a side in the peripheral side surface of the semiconductor layer 40 (Si layer). In addition, in the plan view of the semiconductor layer 40 (Si layer), the end side surface on the main surface 40b side in contact with the main surface 31a in the peripheral side surface of the semiconductor layer 40 (Si layer) is not formed further outward than the maximum outer periphery of the side surface on the main surface 40a side in the peripheral side surface of the semiconductor layer 40 (Si layer). That is, no residue of the semiconductor layer 40 is formed on the main surface 31a of the Ag layer.

[0185] Thereby, when the Ag layer and the Ni layer are laser cut, it is possible to suppress the metal constituting the Ag layer and the Ni layer from being attached to the side surface of the Si layer.

[0186] In addition, if Fig.16 As shown, the outer peripheral side surface of the semiconductor layer 40 (Si layer) may have a concavo-convex shape including an acute-angle vertex.

[0187] Thus, the concavo-convex shape including the acute-angle apex promotes heat dissipation from the outer peripheral side surface of the Si layer, thereby improving the heat dissipation performance of the semiconductor device 1G.

[0188] Fig.17 It is a figure for explaining the relationship between the side shape of the Si layer in the semiconductor device 1G of the embodiment and the manufacturing method. In (a) of the figure, a concave-convex shape including an acute-angle vertex based on the shape of the plasma cutting mask is shown when the Si layer is viewed in a plane. In addition, in (b) of the figure, the processing state during plasma cutting when the Si layer is viewed in section is shown. In the plasma cutting process here, since the plasma cutting process is performed in multiple stages, the side of the Si layer is formed with concave-convex including an acute-angle vertex in both the y-axis direction (or the x-axis direction) and the z-axis direction. In addition, as shown in (b) of the figure, the maximum height roughness Rz of the concave-convex side of the end side in contact with the Ag layer in the peripheral side of the Si layer is approximately equal to the maximum height roughness Rz of the concave-convex side located on the side opposite to the Ag layer in the peripheral side of the Si layer. In addition, in the plane view of the Si layer, the end side in contact with the Ag layer in the peripheral side of the Si layer is not formed more outside than the maximum periphery of the side located on the opposite side of the Ag layer in the peripheral side of the Si layer.

[0189] Fig.18This is an electron microscope photograph of the side surface of the Si layer and the Ag layer in the semiconductor device 1H of the embodiment. As shown in the figure, the semiconductor device 1H includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), transistors 10 and 20, and an amorphous semiconductor 44. The semiconductor device 1H is different from the semiconductor device 1G in that it includes an amorphous semiconductor 44. Hereinafter, the description of the semiconductor device 1H will be omitted for the same points as the semiconductor device 1G, and the description will focus on the different points.

[0190] The amorphous semiconductor 44 is formed on the outer peripheral side surface of the semiconductor layer 40 (Si layer) so as to cover the semiconductor layer 40 (Si layer).

[0191] In addition, the amorphous semiconductor 44 is formed by melting and solidifying Si constituting the Si layer when the Si layer is cut by laser cutting in the singulation process of the semiconductor device 1H and adhering to the side surface of the Si layer. Thus, when the Ag layer and the Ni layer are cut by blade cutting later, cracks in the Si layer or partial peeling of the Si layer is suppressed.

[0192] Fig.19 1 is a cross-sectional view of a semiconductor device 1J according to an embodiment. As shown in the figure, the semiconductor device 1J includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), transistors 10 and 20, and grooves 43A and 43B. The semiconductor device 1J is different from the semiconductor device 1G in that it includes grooves 43A and 43B. Hereinafter, the description of the semiconductor device 1J will be omitted for the same points as the semiconductor device 1G, and the description will focus on the different points.

[0193] The transistor 10 has a plurality of grooves 41 (first plurality of grooves, main body trenches) filled with solid members serving as the gate conductor 15 and the gate insulating film 16 on the main surface 40 a of the Si layer.

[0194] The transistor 20 has a plurality of grooves 42 (second plurality of grooves, main body trenches) filled with solid members serving as the gate conductor 25 and the gate insulating film 26 on the main surface 40 a of the Si layer.

[0195] The plurality of grooves 43A and the plurality of grooves 43B are third plurality of grooves (pseudo-grooves) formed along the outer periphery of the semiconductor layer 40 (Si layer) at the outer edge of the main surface 40a of the semiconductor layer 40 (Si layer) and filled with a solid member containing silicon. The plurality of grooves 43A are arranged at the outer edge of the main surface 40a on the side of the transistor 10. In addition, the plurality of grooves 43B are arranged at the outer edge of the main surface 40a on the side of the transistor 20.

[0196] Furthermore, the solid member filled in the plurality of grooves 43A and the plurality of grooves 43B may be made of the same material as the solid member filled in the plurality of grooves 41 and the plurality of grooves 42. In this case, the plurality of grooves 43A and the plurality of grooves 43B can be formed by the same process as the process for forming the plurality of grooves 41 and the plurality of grooves 42. This simplifies the manufacturing process.

[0197] Thus, in the singulation process of the semiconductor device 1J, cracks and partial peeling of the Si layer that occur during blade dicing can be suppressed from reaching the body regions 18 and 28 .

[0198] In addition, the interval LgA between multiple grooves 41 and multiple grooves 43A, and the interval LgB between multiple grooves 42 and multiple grooves 43B can also be larger than the interval Pg1 between adjacent grooves in multiple grooves 41, and larger than the interval Pg2 between adjacent grooves in multiple grooves 42.

[0199] Thus, since the intervals LgA and LgB are larger than the intervals Pg1 and Pg2 of the groove portions of the main body portion, the mask pattern occupancy rate in manufacturing the semiconductor device 1J can be reduced to a range that allows stable manufacturing.

[0200] In addition, the semiconductor device 1J has a passivation layer 35 (protective layer) formed in a manner partially overlapping the source electrode 11 or the source electrode 21. Here, when the semiconductor layer 40 (Si layer) is viewed in a plan view, the periphery of the passivation layer 35 is formed on the inner side with a gap relative to the periphery of the semiconductor layer 40 (Si layer), and the plurality of grooves 43A and the plurality of grooves 43B are formed in the interval from the periphery of the semiconductor layer 40 (Si layer) to the periphery of the passivation layer 35 in the above plan view.

[0201] Thus, the resistance to cracking and partial peeling of the Si layer can be improved even at the outer edge portion of the main surface 40a of the Si layer where the passivation layer 35 is not formed and the resistance to cracking and partial peeling of the Si layer during blade dicing is relatively weak.

[0202] In addition, the pitch of the grooves in the plurality of grooves 43A and the plurality of grooves 43B may be the same as the pitch of the grooves in the plurality of grooves 41 and the plurality of grooves 42 .

[0203] Thus, the plurality of grooves 43A and the plurality of grooves 43B can be formed simultaneously in the process of forming the plurality of grooves 41 and the plurality of grooves 42 , so that the design and manufacture of the semiconductor device 1J can be simplified.

[0204] (Other embodiments)

[0205] The semiconductor device of one or more technical solutions of the present invention has been described above based on the embodiments, but the present invention is not limited to the embodiments. As long as it does not deviate from the gist of the present invention, various modified forms that can be thought of by those skilled in the art are implemented on the present embodiment, or forms constructed by combining some constituent elements of different embodiments are also included in the scope of one or more technical solutions of the present invention.

[0206] In this embodiment, the semiconductor device 1 in which two vertical MOS transistors are formed on a semiconductor substrate made of silicon is exemplified. However, the semiconductor device according to the present invention includes a semiconductor device having the following structure.

[0207] Fig. 20 1 is a schematic cross-sectional view of a vertical III-nitride semiconductor transistor constituting a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 is a flip-chip package type III-nitride semiconductor transistor. Fig. 20 As shown, the vertical III-nitride semiconductor transistor constituting the semiconductor device 100 includes a substrate 132 composed of an n-type III-nitride semiconductor, an n-type III-nitride semiconductor layer 133 (and 143), a p-type III-nitride semiconductor layer 134 (and 144), and metal layers 130 and 131. In addition, a recessed portion is provided which penetrates a portion of the III-nitride semiconductor layer 134 and whose bottom reaches the III-nitride semiconductor layer 133. In addition, a recessed portion is provided which penetrates a portion of the III-nitride semiconductor layer 144 and whose bottom reaches the III-nitride semiconductor layer 143. Furthermore, a III-nitride semiconductor layer 137 and a III-nitride semiconductor layer 135 having a larger band gap than the III-nitride semiconductor layer 137 are sequentially formed so as to cover the bottom, the side, and a portion of the surface of the III-nitride semiconductor layer 134 of the recessed portion. In addition, a group III nitride semiconductor layer 147 and a group III nitride semiconductor layer 145 having a larger band gap than the group III nitride semiconductor layer 147 are sequentially formed so as to cover the bottom and side of the recess and a part of the surface of the group III nitride semiconductor layer 144. Furthermore, a gate conductor 119 is formed on the surface of the group III nitride semiconductor layer 134, and a source electrode 111 is formed on the upper layer of the group III nitride semiconductor layer 135. In addition, a gate conductor 129 is formed on the surface of the group III nitride semiconductor layer 144, and a source electrode 121 is formed on the upper layer of the group III nitride semiconductor layer 145. A two-dimensional electron gas 136 is generated near the boundary between the group III nitride semiconductor layer 137 and the group III nitride semiconductor layer 135. In addition, a two-dimensional electron gas 146 is generated near the boundary between the group III nitride semiconductor layer 147 and the group III nitride semiconductor layer 145.

[0208] The semiconductor layer 140, which is a stack of the group III nitride semiconductor layer 134, the group III nitride semiconductor layer 133, and the substrate 132, has a first main surface and a second main surface facing each other. In addition, the semiconductor layer 150, which is a stack of the group III nitride semiconductor layer 144, the group III nitride semiconductor layer 143, and the substrate 132, has a first main surface and a second main surface facing each other.

[0209] The metal layer 131 has a third main surface and a fourth main surface facing each other, the third main surface is formed in contact with the second main surface, is thicker than the semiconductor layers 140 and 150 , and is a first metal layer made of a first metal material.

[0210] The metal layer 130 has a fifth main surface and a sixth main surface facing each other, the fifth main surface is formed in contact with the fourth main surface, is thicker than the semiconductor layers 140 and 150, and is a second metal layer made of a second metal material having a larger Young's modulus than the first metal material.

[0211] In addition, in the first region of the semiconductor layer 140, a first vertical III-nitride semiconductor transistor consisting of a substrate 132, III-nitride semiconductor layers 133, 134, 135 and 137, metal layers 130 and 131, a gate conductor 119, and a source electrode 111 is formed, and in the second region adjacent to the first region in the direction along the first main surface, a second vertical III-nitride semiconductor transistor consisting of a substrate 132, III-nitride semiconductor layers 143, 144, 145 and 147, metal layers 130 and 131, a gate conductor 129, and a source electrode 121 is formed.

[0212] The metal layer 131 functions as a common drain electrode of the first vertical group III nitride semiconductor transistor and the second vertical group III nitride semiconductor transistor.

[0213] In addition, the group III nitride semiconductor layers 133 and 143 may be a continuous layer. In addition, the group III nitride semiconductor layers 135 and 145 may be a continuous layer. In addition, the group III nitride semiconductor layers 137 and 147 may be a continuous layer. In addition, the two-dimensional electron gases 136 and 146 may be continuous. In addition, the group III element constituting the group III nitride semiconductor layers 133, 134, 135, 137, 143, 144, 145 and 147 may be Al, Ga or In alone, or a combination thereof.

[0214] According to the above structure, since the metal layer 131 having a thickness for ensuring low on-resistance is in contact with the metal layer 130 having a Young's modulus greater than that of the metal layer 131 and thicker than the semiconductor layers 140 and 150, it is possible to suppress warping of the semiconductor device 100 caused by the contact between the semiconductor layers 140 and 150 and the metal layer 131. Therefore, it is possible to provide a chip size package type semiconductor device 100 that achieves both reduction of on-resistance and suppression of warping.

[0215] Fig.21 FIG. 2 is a schematic cross-sectional view of a vertical SiC transistor constituting a semiconductor device 200 according to an embodiment of the present invention. The semiconductor device 200 is a SiC (silicon carbide) power transistor in a chip-size package that can be flipped. Fig.21 As shown, the SiC transistor constituting the semiconductor device 200 includes a SiC substrate 232 containing high-concentration n-type impurities, a low-concentration n-type impurity layer 233, and metal layers 230 and 231. A p-type impurity layer having a high-concentration n-type impurity layer inside is provided in the low-concentration n-type impurity layer 233. In addition, a source electrode 211 (and 221) is provided in contact with the surface of the high-concentration n-type impurity layer inside the p-type impurity layer and the surface of the p-type impurity layer, and a gate conductor 219 (and 229) is provided via an insulating film 216 at a position facing the p-type impurity layer between the high-concentration n-type impurity layer inside the p-type impurity layer and the low-concentration n-type impurity layer 233.

[0216] The semiconductor layer 240 , which is a stacked body of the low-concentration n-type impurity layer 233 and the SiC substrate 232 , has a first main surface and a second main surface that face each other.

[0217] The metal layer 231 has a third main surface and a fourth main surface facing each other, the third main surface is formed in contact with the second main surface, is thicker than the semiconductor layer 240 , and is a first metal layer made of a first metal material.

[0218] The metal layer 230 is a second metal layer having a fifth main surface and a sixth main surface facing each other, the fifth main surface being formed in contact with the fourth main surface, being thicker than the semiconductor layer 240 , and being made of a second metal material having a Young's modulus greater than that of the first metal material.

[0219] In addition, in the first region of the semiconductor layer 240, a first vertical SiC transistor consisting of a SiC substrate 232, a low-concentration n-type impurity layer 233, metal layers 230 and 231, a gate conductor 219, and a source electrode 211 is formed, and in the second region adjacent to the first region in the direction along the first main surface, a second vertical SiC transistor consisting of a SiC substrate 232, a low-concentration n-type impurity layer 233, metal layers 230 and 231, a gate conductor 229, and a source electrode 221 is formed.

[0220] The metal layer 231 functions as a common drain electrode of the first vertical SiC transistor and the second vertical SiC transistor.

[0221] According to the above structure, since the metal layer 231 having a thickness for ensuring low on-resistance is in contact with the metal layer 230 having a larger Young's modulus than the metal layer 231 and thicker than the semiconductor layer 40B, it is possible to suppress the warping of the semiconductor device 200 caused by the contact between the semiconductor layer 40B and the metal layer 231. Therefore, it is possible to provide a chip size package type semiconductor device 200 that achieves both reduction of on-resistance and suppression of warping.

[0222] Industrial Applicability

[0223] The semiconductor device according to the present invention can be widely used as a CSP type semiconductor device in various semiconductor devices such as bidirectional transistors.

[0224] Description of symbols

[0225] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1J, 100, 200 Semiconductor devices

[0226] 2 Control IC

[0227] 3 Batteries

[0228] 4 Load

[0229] 10 Transistor (1st vertical MOS transistor)

[0230] 11, 11a, 11A, 11b, 11B, 11c, 11d, 21, 21a, 21A, 21b, 21B, 21c, 21d, 111, 121, 211, 221 source electrode

[0231] Parts 12, 13, 22, 23

[0232] 14, 24 Source region

[0233] 15, 25, 119, 129, 219, 229 Gate conductor

[0234] 16, 26 Gate insulation film

[0235] 18, 28 body area

[0236] 19, 19A, 19B, 29, 29A, 29B Gate electrode

[0237] 20 transistor (second vertical MOS transistor)

[0238] 30, 31, 130, 131, 230, 231 metal layer

[0239] 30a, 30b, 31a, 31b, 40a, 40b, 50a, 50b, 51a, 51b main surface

[0240] 32 Semiconductor substrate

[0241] 33 Low concentration impurity layer

[0242] 34 Interlayer insulation layer

[0243] 35 Passivation layer

[0244] 36A, 36B, 37A, 37B, 38 protrusions

[0245] 39 Synthetic

[0246] 40, 140, 150, 240 Semiconductor layer

[0247] 41, 42, 43A, 43B, 60 grooves

[0248] 44 Amorphous semiconductor

[0249] 50, 51 Covering layer

[0250] 70A, 70C, 70E 1st floor

[0251] 70B, 70D, 70F 2nd floor

[0252] 132 substrate

[0253] 133, 134, 135, 137, 143, 144, 145, 147 Group III nitride semiconductor layer

[0254] 136, 146 Two-dimensional electron gas

[0255] 216 Insulation film

[0256] 232 SiC substrate

[0257] 233 Low concentration n-type impurity layer

Claims

1. A semiconductor device, which is a flip-chip chip size package type semiconductor device, wherein: have: The semiconductor layer has a first main surface and a second main surface facing each other, and is composed of silicon, gallium nitride or silicon carbide; a first metal layer having a third main surface and a fourth main surface facing each other, the third main surface being formed in contact with the second main surface, the first metal layer being thicker than the semiconductor layer and being made of a first metal material; a second metal layer having a fifth main surface and a sixth main surface facing each other, the fifth main surface being formed in contact with the fourth main surface, the second metal layer being thicker than the semiconductor layer and being composed of a second metal material having a Young's modulus greater than that of the first metal material; A first vertical field effect transistor is formed in the first region of the semiconductor layer; as well as a second vertical field effect transistor formed in the semiconductor layer in a second region adjacent to the first region in a direction along the first main surface; The first vertical field effect transistor has a first source electrode and a first gate electrode on the first main surface side of the semiconductor layer; The second vertical field effect transistor has a second source electrode and a second gate electrode on the first main surface side of the semiconductor layer; The first metal layer functions as a common drain electrode of the first vertical field effect transistor and the second vertical field effect transistor; A bidirectional path from the first source electrode to the second source electrode via the common drain electrode is used as a main current path.

2. The semiconductor device according to claim 1, wherein: The period of unevenness in the horizontal direction of the sixth main surface is larger than the crystal grain size in the horizontal direction of the crystal grains constituting the second metal layer.

3. The semiconductor device according to claim 1, wherein: The crystal grain size of the second metal layer on the fifth main surface is smaller than the crystal grain size of the first metal layer on the fourth main surface.

4. The semiconductor device according to claim 1, wherein: The linear expansion coefficient of the second metal material is smaller than the linear expansion coefficient of the first metal material.

5. The semiconductor device according to claim 1, wherein: The thickness of the second metal layer is 30 μm or less.

6. The semiconductor device according to claim 1, wherein: The second metal layer includes: a first layer having the fifth main surface; and a second layer having the sixth principal surface; The crystal grain size of the second layer is larger than the crystal grain size of the first layer.

7. The semiconductor device according to claim 1, wherein: The second metal layer includes: a first layer having the fifth main surface; and a second layer having the sixth principal surface; The crystal grain size of the second layer is smaller than the crystal grain size of the first layer.

8. The semiconductor device according to claim 1, wherein: The second metal layer includes: a first layer having the fifth main surface; and a second layer having the sixth principal surface; The crystal grain size of the first layer is substantially the same as that of the second layer, and the crystal grain size of the second metal layer is smaller than that of the first metal layer.

9. The semiconductor device according to claim 1, wherein: The second metal layer includes: a first layer having the fifth main surface; and a second layer having the sixth principal surface; In the horizontal direction of the sixth principal surface, the metal crystals constituting the first layer and the metal crystals constituting the second layer have different preferential orientation planes.

10. The semiconductor device according to claim 9, wherein: In the horizontal direction of the sixth main surface, The metal crystals constituting one of the first layer and the second layer are preferentially oriented in the {100} plane; The metal crystals constituting the other of the first layer and the second layer are preferentially oriented in the {110} plane.

11. The semiconductor device according to claim 1, wherein: The metal crystals constituting the second metal layer are preferentially oriented in the {100} plane on the sixth principal surface.

12. The semiconductor device according to claim 1, wherein: The metal crystals constituting the second metal layer are preferentially oriented in the {110} plane on the sixth principal surface.

13. The semiconductor device according to claim 1, wherein: Also having an imprint formed on the sixth main surface of the second metal layer; The pattern width of the imprint is larger than the concavo-convex period in the horizontal direction of the sixth main surface.

14. The semiconductor device according to claim 13, wherein: The depth of the pattern of the imprint is greater than the maximum height roughness of the concavities and convexities of the sixth main surface.

15. The semiconductor device according to claim 1, wherein: further comprising a first protrusion, the first protrusion protruding from the sixth main surface in a direction from the fifth main surface toward the sixth main surface at the outer periphery of the second metal layer when the second metal layer is viewed in a plan view; The first protrusion includes at least one of the first metal material and the second metal material.

16. The semiconductor device according to claim 15, wherein: The first protrusion is formed on two opposing sides of the outer periphery of the second metal layer in the plan view.

17. The semiconductor device according to claim 15, wherein: The protrusion height of the first protrusion is equal to or greater than 1 / 3 of the thickness of the second metal layer.

18. The semiconductor device according to claim 15, wherein: The protrusion width of the first protrusion is 4 μm or more.

19. The semiconductor device according to claim 15, wherein: A content of the second metal material in the first protrusion is greater than a content of the first metal material in the first protrusion.

20. The semiconductor device according to claim 1, wherein When the semiconductor layer is viewed in a plan view, the outer periphery of the semiconductor layer is spaced apart from the outer periphery of the first metal layer and is formed on the inner side; further comprising a second protrusion, the second protrusion protruding from the third main surface in a direction from the fourth main surface toward the third main surface at the outer periphery of the first metal layer when the first metal layer is viewed in a planar manner; The second protrusion includes at least one of the first metal material and the second metal material.

21. The semiconductor device according to claim 20, wherein: The second protrusion is formed on two opposing sides of the outer periphery of the first metal layer in the plan view.

22. The semiconductor device according to claim 1, wherein: A third protrusion is further provided on an outer peripheral side surface of at least one of the first metal layer and the second metal layer in a direction from the center of the first metal layer toward the outer periphery of the first metal layer when the first metal layer is viewed in a plan view.

23. The semiconductor device according to claim 1, wherein: The invention further comprises a first covering layer having a seventh main surface and an eighth main surface facing each other, wherein the seventh main surface is formed in contact with the sixth main surface, and the first covering layer is made of a ceramic material or a plastic material.

24. The semiconductor device according to claim 1, wherein: The outer edge portion of the above-mentioned first metal layer when the above-mentioned first metal layer is viewed in a plane has a second covering layer, and the second covering layer has a 9th main surface and a 10th main surface facing each other, and the above-mentioned 10th main surface is formed in contact with the above-mentioned 3rd main surface. The second covering layer is composed of ceramic material or plastic material.

25. The semiconductor device according to claim 24, wherein: A groove portion having the third main surface as a bottom surface is formed at an outer edge portion of the semiconductor layer along an outer periphery of the semiconductor layer.

26. The semiconductor device according to claim 1, wherein: A composite of the first metal material and the second metal material is formed on an outer peripheral side surface of at least one of the first metal layer and the second metal layer.

27. The semiconductor device according to claim 26, wherein: The composite is formed on the outer peripheral side surface over the entire circumference of the semiconductor device when the first metal layer and the second metal layer are viewed in a plan view.

28. The semiconductor device according to claim 26, wherein: In the direction from the third main surface toward the sixth main surface, the center position of the composite is between a position that is half the distance from the third main surface to the sixth main surface and a position of the sixth main surface.

29. The semiconductor device according to claim 1, wherein: When the semiconductor layer is viewed in a plan view, the outer periphery of the semiconductor layer is formed inside the outer periphery of the first metal layer with a gap therebetween.

30. The semiconductor device according to claim 29, wherein: In the plan view, the outer periphery of the semiconductor layer is formed inside the outer periphery of the first metal layer at a distance from the outer periphery over the entire periphery.

31. The semiconductor device according to claim 29, wherein: The length of the above-mentioned space is 15 μm or more.

32. The semiconductor device according to claim 29, wherein: The maximum height roughness of the unevenness on the end side of the outer peripheral side of the semiconductor layer on the second main surface side contacting the third main surface is substantially equal to the maximum height roughness of the unevenness on the side of the outer peripheral side of the semiconductor layer on the first main surface side.

33. The semiconductor device according to claim 29, wherein: The semiconductor layer has an outer peripheral side surface having a concavo-convex shape including an acute-angle vertex.

34. The semiconductor device according to claim 29, wherein: The outer peripheral side surface of the semiconductor layer is covered with an amorphous semiconductor.

35. The semiconductor device according to claim 1, wherein: The semiconductor layer has: a semiconductor substrate formed on the second main surface side and made of silicon; and a low-concentration impurity layer formed on the first main surface side and containing the first conductive type impurity at a concentration lower than the first conductive type impurity contained in the semiconductor substrate; The first vertical field effect transistor has a first plurality of grooves on the surface of the semiconductor layer, and the first plurality of grooves are filled with a solid member including a first gate conductor; The second vertical field effect transistor has a second plurality of grooves on the surface of the semiconductor layer, and the second plurality of grooves are filled with a solid member including a second gate conductor; The semiconductor device further includes a third plurality of grooves formed along an outer periphery of the semiconductor layer on an outer edge surface of the semiconductor layer, and the third plurality of grooves are filled with a solid member containing silicon.

36. The semiconductor device according to claim 35, wherein: The intervals between the first plurality of grooves and the third plurality of grooves, and the intervals between the second plurality of grooves and the third plurality of grooves are larger than the intervals between adjacent grooves of the first plurality of grooves, and larger than the intervals between adjacent grooves of the second plurality of grooves.

37. The semiconductor device according to claim 35, wherein: further comprising a protective layer formed in a manner partially overlapping with the first source electrode or the second source electrode; When the semiconductor layer is viewed in a plan view, the outer periphery of the protective layer is spaced apart from the outer periphery of the semiconductor layer and is formed on the inner side; The third plurality of grooves are formed from the outer periphery of the semiconductor layer to the outer periphery of the protective layer in the plan view.

38. The semiconductor device according to claim 35, wherein: A pitch of the grooves in the third plurality of grooves is the same as a pitch of the grooves in the first plurality of grooves and a pitch of the grooves in the second plurality of grooves.

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