Devices including conductive contacts and related systems and methods

Abstract

The present application relates to devices including conductive contacts and related systems and methods. A device includes an array region, a dummy region, and pillars of electrically insulating material in the array region and the dummy region. The device further includes a conductive contact between adjacent pillars of the electrically insulating material in the array region, another electrically insulating material between adjacent pillars of the electrically insulating material in the dummy region, a conductive material above the conductive contact in the array region and above the electrically insulating material in the dummy region, and an oxide between the conductive material in the dummy region and the electrically insulating material in the dummy region. Related devices, systems and methods are also disclosed.

Description

[0001] Priority claim

[0002] This application claims the benefit of U.S. patent application Ser. No. 16 / 038,387, filed Jul. 18, 2018, entitled “Semiconductor Devices Including Electrically Conductive Contacts, and Related Systems and Methods.” Technical Field

[0003] Embodiments disclosed herein relate to the field of semiconductor device design and manufacturing. More specifically, embodiments of the present disclosure relate to methods of forming conductive contacts in an array region of a semiconductor device and related semiconductor devices and systems. Background Art

[0004] A semiconductor device may include a number of conductive interconnects between its various components. For example, a semiconductor device may include an active surface, include active components such as transistors, capacitors, electrodes, diodes, other access devices, or other components. During fabrication of a semiconductor device, electrical connections may be formed between the active surface of the semiconductor device and other portions thereof to form electrical connections to circuitry remote from the active surface.

[0005] A conventional semiconductor device may include an array region (which may also be referred to as a "memory array region", "active region" or "array region") and a peripheral region surrounding at least a portion of the array region. The array region may include memory cells arranged, for example, in rows and columns. The peripheral region may include peripheral circuits for operating the semiconductor device, such as sense amplifiers, decoder circuits, control circuits, multiplexers, column decoders, row decoders, word line drivers, or other control logic devices and circuits for operating the semiconductor device.

[0006] The semiconductor device may also include a dummy region located between the peripheral region and the array region. The dummy region may provide a buffer between relatively closely spaced memory cells in the array region and relatively far spaced components in the peripheral region. The dummy region may include dummy word lines, dummy bit lines, and dummy memory cells. The dummy region may provide a transition region between relatively smaller critical dimensions of components in the array region (e.g., word line width, bit line depth, and other components of the memory cell) and relatively larger critical dimensions of components in the peripheral region (e.g., conductive traces, conductive pads, etc.).

[0007] However, during conventional semiconductor device fabrication, patterning of conductive contact openings in the array region may undesirably form openings in the dummy region and the peripheral region. For example, in some cases, a wet etchant used to form openings in the array region may penetrate (e.g., wet) under the photoresist material and enter the dummy region and the peripheral region, thereby removing electrically insulating material within the dummy region and the peripheral region. When the openings in the array region are filled with conductive material, undesirable openings in the peripheral region of the dummy region may be filled with conductive material, which may cause short circuits between conductive components undesirably formed in the dummy region and one or more components within the peripheral region and the array region. For example, during operation of the semiconductor device, short circuits may occur in the dummy region and the peripheral region. Summary of the invention

[0008] Embodiments disclosed herein include a semiconductor device including a conductive contact in an array region, and related methods of forming a semiconductor device. For example, according to one embodiment, a semiconductor device includes an array region, a dummy region, pillars of electrically insulating material in the array region and the dummy region, a conductive contact between adjacent pillars of the electrically insulating material in the array region, another electrically insulating material between adjacent pillars of the electrically insulating material in the dummy region, a conductive material above the conductive contact in the array region and above the electrically insulating material in the dummy region, and an oxide between the conductive material in the dummy region and the electrically insulating material in the dummy region.

[0009] In an additional embodiment, a semiconductor device includes a semiconductor structure; a first insulating material located above the semiconductor structure, the first insulating material including a first opening and a second opening; a conductive material filling the first opening; a second insulating material filling the second opening, the second insulating material having a material composition different from that of the first insulating material; and a conductive contact located above the second insulating material and above the conductive material, the conductive contact above the conductive material being separated from the conductive material by a silicide material.

[0010] In another embodiment, a method of forming a semiconductor device includes: forming an opening in a first electrically insulating material; filling the opening with a second electrically insulating material; removing a portion of the second electrically insulating material so that an upper surface of the second electrically insulating material is recessed relative to an upper surface of the first electrically insulating material; oxidizing an exposed surface of the first electrically insulating material; forming a mask material on the oxidized surface of the first electrically insulating material in a dummy area of ​​the semiconductor device; removing the second electrically insulating material from an array area of ​​the semiconductor device; removing the mask material; and forming a conductive material above the semiconductor device.

[0011] In yet additional embodiments, a system includes: at least one processor device operably coupled to at least one input device and at least one output device; and a semiconductor device operably coupled to the at least one processor device, the semiconductor device including: pillars of a first electrically insulating material extending from a base structure; a conductive material between adjacent pillars of the first electrically insulating material in an array region; a second electrically insulating material between adjacent pillars of the first electrically insulating material in a dummy region; another conductive material above the conductive material in the array region and above the second electrically insulating material in the dummy region; an oxide between the conductive material and the second electrically insulating material; and a memory storage element connected to the another conductive material in the array region and in the dummy region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1J is a simplified cross-sectional view illustrating a method of forming a conductive contact opening in a semiconductor device and forming a semiconductor device according to an embodiment of the present disclosure; and

[0013] Figure 2 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The drawings included herewith are not intended to be actual views of any particular system or semiconductor structure, but are merely idealized representations used to describe the embodiments herein. Elements and features that are common between the figures may retain the same numerical designations, but for ease of the following description, in most cases, the reference number begins with the number of the figure on which the element is introduced or most fully described.

[0015] The following description provides specific details, such as material type, material thickness, and processing conditions, in order to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without adopting these specific details. In fact, the embodiments can be practiced in combination with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete description of a semiconductor device including a conductive contact or a complete description of a process flow for manufacturing such a conductive contact or semiconductor device. The structure described below does not form a complete semiconductor device structure. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete semiconductor device or conductive contact can be performed by conventional techniques.

[0016] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to a major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration) in or on which one or more structures and / or features are formed and are not necessarily defined by the earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. A major plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0017] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, characteristic, or condition meets a degree of variance (e.g., within an acceptable tolerance). By way of example, depending on a particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition may be met by at least 90.0%, may be met by at least 95.0%, may be met by at least 99.0%, may be met by at least 99.9%, or even by 100.0%.

[0018] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes numerical values ​​and degrees of variation of numerical values ​​that one of ordinary skill in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the 90.0% to 110.0% range of the numerical value, such as within the 95.0% to 105.0% range of the numerical value, within the 97.5% to 102.5% range of the numerical value, within the 99.0% to 101.0% range of the numerical value, within the 99.5% to 100.5% range of the numerical value, or within the 99.9% to 100.1% range of the numerical value.

[0019] As used herein, spatially relative terms such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like may be used herein for ease of description purposes to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the drawings is inverted, an element described as being "below" or "below" or "under" or "bottom" other elements or features would be oriented "above" or "on top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] According to embodiments described herein, a semiconductor device includes an active region, a peripheral region, and a dummy region between the active region and the peripheral region. A first electrically insulating material includes different portions (e.g., pillars) in the active region and in the dummy region. In the active region, a conductive contact is located between adjacent pillars of the first electrically insulating material. The conductive contact is electrically connected to the active surface of the substrate below. A second electrically insulating material different from the first electrically insulating material may be located above the substrate in the peripheral region. In the dummy region, the second electrically insulating material may be located between adjacent pillars of the first electrically insulating material. The upper surface of the first electrically insulating material may be located farther away from the substrate (e.g., higher, above) than the upper surface of the second electrically insulating material. The upper portion of the first electrically insulating material in the dummy region may be oxidized. Conductive material may be patterned above the active region, the dummy region, and the peripheral region. In the active region, the conductive material may form an electrical connection to the conductive contact. The conductive material above the dummy region may be electrically isolated from the conductive material above the array region and the conductive material above the peripheral region. A memory storage element (e.g., a capacitor) may be located above the conductive material in the array region and in the dummy region. In the array region, the memory storage elements may be electrically connected to the active surface of the substrate through the conductive material and the conductive contacts. Since the dummy region may not include conductive contacts (and include the second electrically insulating material), the memory storage elements in the dummy region may not be electrically connected to the active surface of the substrate.

[0021] A semiconductor device may be formed by forming a second electrically insulating material over a substrate and forming openings therein in an active region and a dummy region. A first electrically insulating material may be formed in the opening. A portion of the second electrically insulating material may be removed so that the upper surface of the second electrically insulating material is located below the upper surface of the first electrically insulating material. During the removal of the portion of the second electrically insulating material, an upper portion (e.g., an oxidized portion) of the first electrically insulating material may be removed, leaving a dangling bond on the exposed surface of the first electrically insulating material. The upper portion of the first electrically insulating material containing a dangling bond may be oxidized to form an oxide on its exposed portion. After oxidizing the exposed portion of the first electrically insulating material, a mask material (e.g., a photoresist material) may be formed and bonded to the oxidized portion of the second electrically insulating material over the dummy region and in the peripheral region. The second electrically insulating material is removed from the active region to form an opening between the pillars of the first electrically insulating material. The opening is filled with a conductive material to form a conductive contact electrically connected to the active surface in the active region. Conductive material is formed and patterned over the active region, the dummy region, and the peripheral region. In some embodiments, a memory storage element electrically connected to the conductive material in the active region is formed. The memory storage elements may be in electrical communication with the active surface because the conductive material is in electrical communication with the conductive contacts in the array region.

[0022] Oxidation of the exposed portion of the first electrically insulating material can reduce the amount of dangling bonds of the first electrically insulating material. Since the exposed portion of the first electrically insulating material is substantially free of dangling bonds, the mask material can be directly bonded (e.g., chemically bonded) to the oxidized portion. The boundary between the array region and the dummy region can be defined by the edge of the mask material, which can be chemically bonded to the oxidized portion of the first electrically insulating material. Since the mask material is chemically bonded to the oxidized portion, an etchant (e.g., a wet etchant) used to remove the second electrically insulating material from the array region may not penetrate into the dummy region or the peripheral region. Therefore, during subsequent processing of the semiconductor device, the conductive contact and the conductive material in the array region may not form a short circuit to the conductive material in the dummy region. In addition, the conductive material in the dummy region may not be shorted to the conductive material in the peripheral region. Therefore, a contact opening can be formed in the array region, and substantially no opening is formed in the dummy region or the peripheral region.

[0023] Figures 1A to 1J A method of forming a conductive contact opening in a semiconductor device and forming a semiconductor device according to an embodiment of the present disclosure is described. Figure 1A , the semiconductor device 100 may include a substrate 102 on which or in which components of the semiconductor device 100 are formed. The substrate 102 may be a base material (e.g., a structure) or a structure with additional materials formed thereon. The substrate 102 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate on which one or more layers, structures, or regions are formed. The substrate 102 may be a conventional silicon substrate or other bulk substrate including a layer of a semiconducting material. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate 102 may be doped or undoped.

[0024] The upper portion of substrate 102 may include an active region 114, which may include, for example, a portion of a memory cell. By way of non-limiting example, active region 114 may include a portion of a transistor (e.g., a source region, a drain region), a portion of a capacitor structure, a gate electrode, a diode, another access device, another material, or a combination thereof. In some embodiments, active region 114 includes a source region or a drain region of a transistor. In other embodiments, some portions of active region 114 include source regions and other portions of active region 114 include drain regions. As will be described herein, conductive contacts may be formed in electrical communication with active region 114 to electrically connect active region 114 to other circuits or components of semiconductor device 100. Contact region 103 may be located above substrate 102 and may be a region whereby conductive contacts are formed from the upper surface of semiconductor device 100 to active region 114 of substrate 102.

[0025] The etch stop material 105 may be located between the substrate 102 and the contact region 103. In some embodiments, the etch stop material 105 includes silicon nitride. However, the present disclosure is not limited thereto and the etch stop material 105 may include other materials, such as aluminum nitride, aluminum oxide, silicon nitride carbon (SiCN), another material, or a combination thereof.

[0026] The semiconductor device 100 may include an active region 104, a peripheral region 108, and a dummy region 106 between the active region 104 and the peripheral region 108. The active region 104 may include memory cells or components thereof (e.g., transistors) patterned, for example, in rows extending along a first direction and in columns extending along a second direction that may be perpendicular to the first direction. In other embodiments, the memory cells may be arranged in different configurations, such as in a hexagonal close-packed orientation for increasing the density of memory elements (e.g., memory cells).

[0027] The active regions 104 may include isolation regions 112 formed within the substrate 102, the isolation regions 112 isolating the active regions 114 from each other. The isolation regions 112 may be referred to herein as shallow trench isolation (STI) structures. The isolation regions 112 may include, for example, an electrically insulating material. The electrically insulating material may include a dielectric material, such as silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In some embodiments, the isolation regions 112 include silicon dioxide.

[0028] The active region 104 may further include the first electrically insulating material 116 located between the distinct portions 120 of the second electrically insulating material 118. The width W of the distinct portions 120 is1 The width W may be in a range from about 20 nanometers (nm) to about 40 nm, such as from about 20 nm to about 25 nm, from about 25 nm to about 30 nm, from about 30 nm to about 35 nm, or from about 35 nm to about 40 nm. 1 It is from about 27nm to about 30nm.

[0029] The lower portion of the second electrically insulating material 118 may be generally aligned with the active region 114 of the substrate 102 (e.g., at Figure 1A 1 ). In some such embodiments, second electrically insulating material 118 may be offset from isolation region 112. First electrically insulating material 116 may include a portion located above and aligned with isolation region 112.

[0030] The second electrically insulating material 118 may include a sacrificial material that may be replaced with a conductive material to form a conductive contact, as will be described herein. The second electrically insulating material 118 may include, for example, silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride, another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In other embodiments, the second electrically insulating material 118 may include silicon dioxide.

[0031] First electrically insulating material 116 between distinct portions 120 of second electrically insulating material 118 may include a material that exhibits an etch selectivity relative to second electrically insulating material 118. In other words, first electrically insulating material 116 may include a material that may be patterned or removed without substantially removing second electrically insulating material 118. Similarly, second electrically insulating material 118 may include a material that may be removed without substantially removing first electrically insulating material 116. In some embodiments, first electrically insulating material 116 includes a nitride material, such as silicon nitride. In some such embodiments, second electrically insulating material 118 may include an oxide material, such as silicon dioxide.

[0032] Continue to refer Figure 1A , dummy region 106 may include at least some distinct portions 120 of second electrically insulating material 118 and first electrically insulating material 116 located between adjacent portions of second electrically insulating material 118. Figure 1AThe dummy region 106 is illustrated to include two distinct portions 120 , but the disclosure is not limited thereto and the dummy region 106 may include only one distinct portion 120 , or may include more than two distinct portions 120 , such as three distinct portions 120 , four distinct portions 120 , five distinct portions 120 , or another number of distinct portions 120 .

[0033] The peripheral region 108 may include a second electrically insulating material 118 over the etch stop material 105. The second electrically insulating material 118 may include a substantially continuous material over the substrate 102 in the peripheral region 108. The first electrically insulating material 116 may be over the second electrically insulating material 118 in the peripheral region 108.

[0034] Figure 1A The semiconductor device 100 may be formed by forming a second electrically insulating material 118 over a surface of the substrate 102. The second electrically insulating material 118 may be patterned to form openings (e.g., pores) between adjacent distinct portions 120. By way of non-limiting example, the openings may be formed by forming a mask material (e.g., a photoresist material) over the second electrically insulating material 118, exposing and removing portions of the mask material, and transferring the pattern of the mask material to the second electrically insulating material 118. The openings in the second electrically insulating material 118 may be formed by exposing the second electrically insulating material 118 to wet etching conditions, such as exposing the second electrically insulating material 118 to a solution comprising hydrofluoric acid (HF), potassium hydroxide (KOH), a solution comprising hydrofluoric acid and ammonium fluoride (NH4F4). 4 F), a solution containing sulfuric acid and hydrogen peroxide (also referred to as piranha solution), another wet etchant, or a combination thereof. In other embodiments, the openings in second electrically insulating material 118 may be formed by exposing second electrically insulating material 118 to a dry etching process, such as a reactive ion etching (RIE) process. In some such embodiments, the dry etchant may contain SF 6 NH 3 CF 4 / O 2 CF 4 / H 2 CF 4 , CHF 3 / O 2 , C 2 F 6 , C 3 F 8 , C 5 F 8 / CO / O 2 / Ar, other etch chemistries, or combinations thereof.

[0035] The opening may be filled with a first electrically insulating material 116. The first electrically insulating material 116 may be formed by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), another deposition method, or a combination thereof.

[0036] refer to Figure 1B , portions of first electrically insulating material 116 located above the surface of second electrically insulating material 118 may be removed to form isolated pillars 121 of first electrically insulating material 116 and expose upper portions of second electrically insulating material 118. Thus, second electrically insulating material 118 may extend further away from substrate 102 than remaining portions of first electrically insulating material 116.

[0037] In some embodiments, the first electrically insulating material 116 is removed, for example, by exposing the first electrically insulating material to a dry etching process (eg, a RIE process). By way of non-limiting example, the first electrically insulating material 116 may be removed by exposing the first electrically insulating material 116 to, for example, a CF 4 / H 2 CF 4 / O 2 / N 2 NF 3 / O 2 , SF 6 / O 2 / N 2 , SF 6 / CH 4 / N 2 , another material, or a combination thereof. In some embodiments, the first electrically insulating material 116 is removed by exposure to CF 4 / H 2 to remove the first electrically insulating material 116 .

[0038] Removing portions of first electrically insulating material 116 may form recessed portions 117 of first electrically insulating material 116. In some such embodiments, an upper surface of first electrically insulating material 116 may be lower than an upper surface of a distinct portion 120 of second electrically insulating material 118 in active region 104 (e.g., located closer to a major surface of substrate 102). In some embodiments, an upper surface of first electrically insulating material 116 may be lower than an upper surface of second electrically insulating material 118 in peripheral region 108.

[0039] refer to Figure 1C After removing portions of the first electrically insulating material 116, portions of the second electrically insulating material 118 between the distinct portions 120 may be removed ( Figure 1B) to form a recessed portion 119 of the second electrically insulating material 118. An upper surface of the second electrically insulating material 118 may be located closer to the substrate 102 than an upper surface of the first electrically insulating material 116.

[0040] In some embodiments, portions of second electrically insulating material 118 are removed by, for example, wet etching. In some such embodiments, second electrically insulating material 118 may be exposed to a solution comprising hydrofluoric acid, potassium hydroxide, a solution comprising hydrofluoric acid and ammonium fluoride, a solution comprising sulfuric acid and hydrogen peroxide, another wet etchant, or a combination thereof. In some embodiments, exposing second electrically insulating material 118 to a wet etchant may remove oxidized portions of first electrically insulating material 116 and may leave dangling bonds (e.g., exposed hydrogen (H)) on the exposed surface of first electrically insulating material 116. + )atom).

[0041] In some embodiments, the distance D between the upper surface of first electrically insulating material 116 and the upper surface of second electrically insulating material 118 may be from about 1 nanometer to about 10 nm, for example, from about 1 nm to about 5 nm, or from about 5 nm to about 10 nm, although the present disclosure is not limited thereto. In some embodiments, distance D is from about 1 nm to about 5 nm, for example, about 2 nm, which may help remove first electrically insulating material 116 that may be located on the surface of second electrically insulating material 118.

[0042] Forming recessed portion 119 may expose at least an upper portion (e.g., an upper portion of a sidewall) of first electrically insulating material 116. At least a portion of sidewall 122 of first electrically insulating material 116 and an upper surface of first electrically insulating material 116 may be exposed (e.g., not in contact with second electrically insulating material 118).

[0043] refer to Figure 1D , semiconductor device 100 may be exposed to an oxidizing condition, as indicated at arrow 123, to oxidize at least some of the exposed surfaces of first electrically insulating material 116 and form oxide 124 above the surface of first electrically insulating material 116. For example, exposed portions of sidewalls 122 and the upper surface of first electrically insulating material 116 may be oxidized. In some embodiments, exposing semiconductor device 100 to the oxidizing condition may significantly remove dangling bonds from the exposed surface of first electrically insulating material 116.

[0044] In some embodiments, exposing the semiconductor device 100 to an oxidizing condition may include exposing the exposed portion of the first electrically insulating material 116 ( Figure 1C) is exposed to a rapid thermal annealing (RTA) process. For example, the semiconductor device 100 may be exposed to an oxidizing environment (e.g., air, oxygen, ozone, water vapor, an oxygen-containing plasma (e.g., a plasma including oxygen radicals), another oxidizing agent, or a combination thereof) at an elevated temperature (e.g., a temperature greater than about 20° C.). In some embodiments, the semiconductor device 100 may be exposed to a temperature greater than about 300° C., e.g., greater than about 400° C., greater than about 600° C., greater than about 800° C., greater than about 1,000° C., or greater than about 1,200° C. during oxidation of the exposed portion of the first electrically insulating material 116. In some embodiments, the semiconductor device 100 is exposed to the oxidizing condition for a duration in a range from about 30 seconds to about 10 minutes, e.g., from about 30 seconds to about 1 minute, from about 1 minute to about 3 minutes, from about 3 minutes to about 5 minutes, or from about 5 minutes to about 10 minutes.

[0045] Oxide 124 may include an oxide of first electrically insulating material 116. In some embodiments, such as where first electrically insulating material 116 includes silicon nitride, oxide 124 includes silicon oxide (SiO x ), where x is between about 1.0 and about 2.0. In other embodiments, oxide 124 includes silicon oxynitride (eg, SiON).

[0046] The thickness T of the oxide 124 may range from about To date For example, from about To date From about To date From about To date Or from about However, the present disclosure is not limited thereto and the thickness T of the oxide 124 may be greater than the thickness described above.

[0047] Oxidation of the exposed portion of the first electrically insulating material 116 may thin the exposed portion. For example, the width W of the upper portion of the first electrically insulating material 116 may be 2 The width W of the first electrically insulating material 116 may be smaller than the width W of other portions of the first electrically insulating material 116 that are not exposed to the oxidizing conditions (eg, portions of the first electrically insulating material 116 that are buried within the second electrically insulating material 118). 3 .

[0048] Oxidation of exposed portions of first electrically insulating material 116 may form exposed surfaces 125 of oxide 124 having hydrophobic properties, such that masking material (eg, masking material including photoresist material) formed thereon adheres to the oxidized portions of first electrically insulating material 116 .

[0049] refer to Figure 1E, a mask material 126, which may include a photoresist material, may be formed over the peripheral region 108 and the dummy region 106 of the semiconductor device 100. The mask material 126 may be located over and contact the second electrically insulating material 118 in the peripheral region 108. The mask material 126 may be located over and contact the oxide 124 in the dummy region 106 and may be directly bonded (e.g., chemically bonded) to the oxide 124. Since the second electrically insulating material 118 is removed and the first electrically insulating material 116 (e.g., the oxide 124 thereof) is located higher than the second electrically insulating material 118, the mask material 126 may be directly located over and bonded to the first electrically insulating material 116. In some such embodiments, the edges 130 of the mask material 126 may form so-called partition walls, which may significantly reduce or prevent exposure of material of the dummy region 106 and the peripheral region 108 beneath the mask material 126 to one or more etching chemistries to which the semiconductor device 100 (e.g., the active region 104) is exposed.

[0050] In some embodiments, oxide 124 exhibits hydrophobic properties and mask material 126 substantially adheres to oxide 124. Improved adhesion of mask material 126 to oxide 124 can reduce or prevent the etching solution from undercutting or etching undesirable portions of semiconductor device 100, such as portions of semiconductor device 100 located within dummy region 106 or peripheral region 108.

[0051] In some embodiments, gaps 128 may remain between the surface of mask material 126 and the upper surface of second electrically insulating material 118 in dummy region 106. Without wishing to be bound by any particular theory, it is believed that due to the relatively high viscosity of mask material 126, the relatively small width of second electrically insulating material 118 (e.g., W 1 ( Figure 1A )), or both, the gap 128 is not filled with the mask material 126.

[0052] The mask material 126 may include a photosensitive polymer. In some embodiments, the mask material 126 includes a photoacid generator (PAG) or a photoacid (PAH). In some such embodiments, in response to exposure to electromagnetic radiation (e.g., light), incoming photons may generate acid molecules that diffuse into the mask material 126 and catalytically cause chemical changes in the mask material 126, thereby causing image formation. In other words, the mask material 126 may include a photoacid generator that converts into an acid in response to exposure to electromagnetic radiation. The generated acid may catalyze a reaction of a polymer composition of the mask material 126 so that such portions of the mask material 126 are soluble in a developer. In other embodiments, the mask material 126 may include a photosensitive compound that is formulated and configured to generate an acid (e.g., a free radical (e.g., a proton, H+)) that catalyzes the development of the mask material 126 (e.g., polymerization of a selected portion thereof) in response to exposure to electromagnetic radiation.

[0053] As non-limiting examples, the mask material 126 may include a phenol-formaldehyde polymer (novolak resin), an epoxy polymer, a polyisoprene resist, a polymethyl methacrylate resist, a polymethyl isopropyl ketone resist, a polybutene-1-sulfone resist, a polytrifluoroethyl chloroacetate resist, a copoly(α-cyanoethyl acrylate-α-amidoethyl acrylate) resist, a poly(2-methylpentene-1-sulfone) resist, or another resist material. However, the present disclosure is not limited to the specific materials described above and the mask material 126 may include materials other than those described.

[0054] Without wishing to be bound by any particular theory, it is believed that because first electrically insulating material 116 is exposed to oxidizing conditions to form oxide 124, oxide 124 does not include a significant amount of dangling bonds (e.g., H + ). It is believed that the dangling bonds may interfere with the development of the mask material 126, for example, by consuming protons (H+) within the mask material 126. However, the protons may facilitate the development of the mask material 126. Therefore, the formation of the oxide 124 may significantly hinder the consumption of protons in the mask material 126. By way of comparison, where the semiconductor device 100 does not include the oxide 124, in some embodiments, the mask material 126 is not fully developed, leaving undeveloped portions of the mask material 126 above the semiconductor device 100, resulting in no conductive contacts being formed in locations where the mask material 126 is not developed.

[0055] refer to Figure 1FAfter forming the mask material 126 in the dummy region 106 and the peripheral region 108, the semiconductor device 100 may be exposed to etching conditions to remove portions of the second electrically insulating material 118 from the active region 104 and form openings (e.g., apertures) 132 between the pillars 121 of the first electrically insulating material 116. By way of non-limiting example, the semiconductor device 100 may be exposed to one or more wet etchants that are formulated and configured to substantially remove the exposed portions of the second electrically insulating material 118 (e.g., the apertures 132). Figure 1E ). The wet etchant may include, for example, a solution including hydrofluoric acid, potassium hydroxide, a solution including hydrofluoric acid and ammonium fluoride, a solution including sulfuric acid and hydrogen peroxide, another wet etchant, or a combination thereof.

[0056] In some embodiments, oxide 124 may also be removed during removal of second electrically insulating material 118. In some embodiments, portions of oxide 124 in dummy regions 106 that are not in contact with mask material 126 may be removed while portions of oxide 124 directly beneath mask material 126 are not significantly removed.

[0057] Since the mask material 126 is bonded to the surface of the oxide 124 in the dummy region 106, there may be no gap between the mask material 126 and the oxide 124. Without wishing to be bound by any particular theory, it is believed that since the oxide 124 has a relatively low thickness T ( Figure 1D ), so that with the oxide 124 removed, the wet etchant does not significantly flow into the dummy region 106, for example through any space that may be formed between the mask material 126 and the first electrically insulating material 116.

[0058] In some embodiments, the etch stop material 105 may be exposed at a bottom portion of the opening 132. Figure 1G After the etch stop material 105 is exposed, the etch stop material 105 within the opening 132 may be removed, for example, by exposing the etch stop material to a reactive ion etching process. The removal of the etch stop material 105 may expose the active region 114 between the isolation regions 112 within the substrate 102.

[0059] Continue to refer Figure 1G , the conductive material 134 may be formed above the surface of the semiconductor device 100 and within the opening 132 ( Figure 1F ). Conductive material 134 may be formed above and in contact with active region 114. Thus, conductive material 134 may be in electrical communication with active region 114. In some embodiments, a lower surface of conductive material 134 may not be coplanar with an upper surface of substrate 102. Conductive material 134 may be formed by ALD, PVD, CVD, LPCVD, PECVD, another deposition method, or a combination thereof.

[0060] The conductive material 134 may include a material exhibiting suitable electrical conductivity, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold, metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), materials including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAIN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of an alloy thereof, a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped, silicon germanium, etc.), polysilicon, other materials exhibiting electrical conductivity, or a combination thereof. In some embodiments, conductive material 134 includes polysilicon.

[0061] refer to Figure 1H Conductive material 134 may be removed from the surface of semiconductor device 100 , such as by chemical mechanical planarization (CMP), to form conductive contacts 136 between adjacent portions of first electrically insulating material 116 . Conductive contacts 136 may be in electrical communication with active region 114 .

[0062] In some embodiments, the conductive contact 136 is recessed relative to a portion of the first electrically insulating material 116. In other words, an upper surface of the conductive contact 136 can be lower than an upper surface of the first electrically insulating material 116.

[0063] Continue to refer Figure 1H , a silicide material 138 may be formed over the conductive contact 136. The silicide material 138 may include, for example, a metal silicide, such as cobalt silicide (CoSi 2 ), tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), Tantalum silicide (TaSi 2 ), Molybdenum silicide (MoSi 2 ), nickel silicide (NiSi 2 ), another silicide, or a combination thereof. In some embodiments, the silicide material 138 includes cobalt silicide.

[0064] In some embodiments, an upper surface of the first electrically insulating material 116 may be located further away from the substrate 102 than an upper surface of the silicide material 138 .

[0065] refer to Fig. 1I, conductive contacts 140 (also referred to herein as “conductive plugs” or “interconnects”) may be formed and patterned over the semiconductor device 100. The conductive contacts 140 may be in electrical communication with the conductive contacts 136 in the active region 104, for example, through the silicide material 138. The spaces 142 between the conductive contacts 140 in the active region 104 may correspond to the first electrically insulating material 116 and be substantially laterally aligned with the first electrically insulating material 116.

[0066] The conductive contact 140 may be substantially continuous over the dummy region 106. In other words, the conductive contact 140 over the dummy region 106 may be substantially unitary. In other embodiments, the conductive contact 140 in the dummy region 106 may include a plurality of conductive contacts 140, such as a conductive contact 140 over and corresponding to the isolated first electrically insulating material 116 in the dummy region 106.

[0067] One or more conductive contacts 140 may be formed over the peripheral region 108 .

[0068] The conductive contact 140 may include a conductive material such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold, a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAIN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of an alloy thereof, a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped, silicon germanium, etc.), polysilicon, other materials exhibiting electrical conductivity, or a combination thereof. In some embodiments, the conductive contact 140 includes tungsten.

[0069] refer to Figure 1J , the memory storage element 144 may be formed to be in electrical communication with the conductive contact 140. In some embodiments, the memory storage element 144 includes a capacitor. The memory storage element 144 may be formed within an insulating material 152. The insulating material 152 may include, for example, silicon dioxide, silicon nitride, phosphosilicate glass borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride, another dielectric material, a dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof.

[0070] The memory storage element 144 may include, for example, a lower electrode 146 , an upper electrode 150 , and a dielectric material 148 between the lower electrode 146 and the upper electrode 150 .

[0071] The lower electrode 146 can be in electrical communication with the conductive contact 140. The lower electrode 146 can include a suitable conductive material, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold, a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAIN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of its alloys, a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped, silicon germanium, etc.), polysilicon, other materials exhibiting electrical conductivity, or a combination thereof. In some embodiments, lower electrode 146 includes titanium nitride.

[0072] The upper electrode 150 may include a conductive material, such as one or more of the materials described above with reference to the lower electrode 146 .

[0073] The dielectric material 148 may be configured to store a charge or other property associated with the logic state of the memory storage element 144. Therefore, the memory storage element 144 may be referred to as a "cell capacitor" or a "storage capacitor". The dielectric material 148 may include silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO 3 )(STO), barium titanate (BaTiO 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), ferroelectric materials (eg, ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), high-k dielectric materials, or combinations thereof. In some embodiments, dielectric material 148 includes zirconium oxide.

[0074] In some embodiments, the conductive contacts 140 may arrange the memory storage elements 144 in a different configuration than the conductive contacts 136 and may be referred to as a so-called "redistribution layer." In some embodiments, the conductive contacts 136 are arranged in a generally vertical orientation with rows and columns extending in mutually perpendicular directions, and the conductive contacts 140 are arranged in a hexagonal close-packed orientation.

[0075] Therefore, in at least some embodiments, a semiconductor device includes a semiconductor structure; a first insulating material, which is above the semiconductor structure, the first insulating material includes a first opening and a second opening; a conductive material, which fills the first opening; a second insulating material, which fills the second opening, the second insulating material has a material composition different from that of the first insulating material; and a conductive contact, which is above the second insulating material and above the conductive material, the conductive contact above the conductive material being separated from the conductive material by a silicide material.

[0076] Therefore, in at least some embodiments, a semiconductor device comprises an array region, a dummy region, pillars of electrically insulating material in the array region and the dummy region, a conductive contact between adjacent pillars of the electrically insulating material in the array region, another electrically insulating material between adjacent pillars of the electrically insulating material in the dummy region, a conductive material above the conductive contact in the array region and above the electrically insulating material in the dummy region, and an oxide between the conductive material in the dummy region and the electrically insulating material in the dummy region.

[0077] Therefore, in at least some embodiments, a method of forming a semiconductor device includes: forming an opening in a first electrically insulating material; filling the opening with a second electrically insulating material; removing a portion of the second electrically insulating material so that an upper surface of the second electrically insulating material is recessed relative to an upper surface of the first electrically insulating material; oxidizing the exposed surface of the first electrically insulating material; forming a mask material on the oxidized surface of the first electrically insulating material in a dummy area of ​​the semiconductor device; removing the second electrically insulating material from an array area of ​​the semiconductor device; removing the mask material; and forming a conductive material above the semiconductor device.

[0078] A semiconductor device (eg, semiconductor device 100 ) including a conductive contact (eg, conductive contact 136 ) according to an embodiment of the present disclosure may be used in an embodiment of an electronic system of the present disclosure. For example, Figure 2 203 may include, for example, a computer or computer hardware component, a server or other network connection hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or The electronic system 203 includes at least one memory device 205. The memory device 205 may include an embodiment of a semiconductor device (e.g., semiconductor device 100) including a conductive contact (e.g., conductive contact 136) such as previously described herein.

[0079] The electronic system 203 may additionally include at least one electronic signal processor device 207 (commonly referred to as a "microprocessor"). The electronic signal processor device 207 may optionally include an embodiment of a semiconductor device (e.g., semiconductor device 100) previously described herein. The electronic system 203 may additionally include one or more input devices 209 for inputting information into the electronic system 203 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 203 may additionally include one or more output devices 211 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 209 and the output device 211 may include a single touch screen device that can be used to input information to the electronic system 203 and output visual information to the user. The input device 209 and the output device 211 may be in electrical communication with one or more of the memory device 205 and the electronic signal processor device 207. In some embodiments, more than one function may be performed by a single semiconductor die, such as in the case of a system on a chip (SoC), where processor and memory functions are incorporated into a single die.

[0080] Therefore, according to an embodiment of the present disclosure, a system includes: at least one processor device operably coupled to at least one input device and at least one output device; and a semiconductor device operably coupled to the at least one processor device. The semiconductor device includes pillars of a first electrically insulating material extending from a base structure, a conductive material between adjacent pillars of the first electrically insulating material in an array region, a second electrically insulating material between adjacent pillars of the first electrically insulating material in a dummy region, another conductive material above the conductive material in the array region and above the second electrically insulating material in the dummy region, an oxide between the conductive material and the second electrically insulating material, and a memory storage element connected to the another conductive material in the array region and in the dummy region.

[0081] Additional non-limiting example embodiments of the present disclosure are described below.

[0082] Embodiment 1: A semiconductor device comprises: an array region; a dummy region; pillars of electrically insulating material, which are located in the array region and the dummy region; a conductive contact, which is located between adjacent pillars of the electrically insulating material in the array region; another electrically insulating material, which is located between adjacent pillars of the electrically insulating material in the dummy region; a conductive material, which is located above the conductive contact in the array region and above the electrically insulating material in the dummy region; and an oxide, which is located between the conductive material in the dummy region and the electrically insulating material in the dummy region.

[0083] Embodiment 2: The semiconductor device of Embodiment 1, wherein the electrically insulating material comprises silicon nitride.

[0084] Embodiment 3: The semiconductor device of Embodiment 1 or Embodiment 2, wherein the conductive contact comprises polysilicon.

[0085] Embodiment 4: The semiconductor device of any one of embodiments 1 to 3, wherein the oxide comprises silicon dioxide.

[0086] Embodiment 5: The semiconductor device of any one of embodiments 1 to 4, wherein the conductive material comprises tungsten.

[0087] Embodiment 6: The semiconductor device of any one of Embodiments 1 to 5, further comprising a capacitor in electrical communication with the conductive material over the conductive contact.

[0088] Embodiment 7: The semiconductor device of any one of Embodiments 1 to 6, wherein uppermost surfaces of the electrically insulating material in the array region and the dummy region are higher than an uppermost surface of the another electrically insulating material.

[0089] Embodiment 8: The semiconductor device of any one of Embodiments 1 to 7, wherein a width of an upper portion of the electrically insulating material is smaller than a width of a lower portion of the electrically insulating material.

[0090] Embodiment 9: The semiconductor device of any one of embodiments 1 to 6, wherein an upper surface of the electrically insulating material is located further from an underlying substrate than an upper surface of the another electrically insulating material.

[0091] Embodiment 10: A semiconductor device comprises: a semiconductor structure; a first insulating material located above the semiconductor structure, the first insulating material comprising a first opening and a second opening; a conductive material filling the first opening; a second insulating material filling the second opening, the second insulating material having a material composition different from that of the first insulating material; and a conductive contact located above the second insulating material and above the conductive material, the conductive contact above the conductive material being separated from the conductive material by a silicide material.

[0092] Embodiment 11: The semiconductor device according to Embodiment 10, wherein the first insulating material comprises silicon nitride.

[0093] Embodiment 12: The semiconductor device according to Embodiment 10 or Embodiment 11, wherein the second insulating material comprises silicon dioxide.

[0094] Embodiment 13: The semiconductor device of any one of Embodiments 10 to 12, wherein the first aperture is located within an array region of the semiconductor device.

[0095] Embodiment 14: The semiconductor device of any one of Embodiments 10 to 13, wherein the second aperture is located within a dummy region of the semiconductor device.

[0096] Embodiment 15: The semiconductor device according to any one of Embodiments 10 to 14, wherein an upper surface of the first insulating material is higher than an upper surface of the second insulating material.

[0097] Embodiment 16: The semiconductor device of any one of Embodiments 10 to 15, further comprising an oxide between the conductive contact and the second insulating material.

[0098] Embodiment 17: A method for forming a semiconductor device, the method comprising: forming an opening in a first electrically insulating material; filling the opening with a second electrically insulating material; removing a portion of the second electrically insulating material so that an upper surface of the second electrically insulating material is recessed relative to an upper surface of the first electrically insulating material; oxidizing an exposed surface of the first electrically insulating material; forming a mask material on the oxidized surface of the first electrically insulating material in a dummy area of ​​the semiconductor device; removing the second electrically insulating material from an array area of ​​the semiconductor device; removing the mask material; and forming a conductive material above the semiconductor device.

[0099] Embodiment 18: The method of Embodiment 17, wherein forming a mask material on the oxidized surface of the first electrically insulating material comprises bonding the mask material to the oxidized surface of the first electrically insulating material.

[0100] Embodiment 19: The method of Embodiment 17 or Embodiment 18, wherein forming a mask material comprises forming a photoresist material.

[0101] Embodiment 20: A method according to any one of embodiments 17 to 19, wherein forming a conductive material above the semiconductor device includes forming the conductive material above the first electrically insulating material in the array region and above the oxidized surface of the first electrically insulating material in the dummy region and in contact with the oxidized surface.

[0102] Embodiment 21: The method of any of Embodiments 17 to 20, wherein oxidizing the exposed surface of the first electrically insulating material comprises oxidizing the exposed surface of the first electrically insulating material comprising silicon nitride.

[0103] Embodiment 22: A system comprising: at least one processor device operably coupled to at least one input device and at least one output device; and a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising: pillars of a first electrically insulating material extending from a base structure; a conductive material between adjacent pillars of the first electrically insulating material in an array region; a second electrically insulating material between adjacent pillars of the first electrically insulating material in a dummy region; another conductive material above the conductive material in the array region and above the second electrically insulating material in the dummy region; an oxide between the conductive material and the second electrically insulating material; and a memory storage element connected to the another conductive material in the array region and in the dummy region.

[0104] Although certain illustrative embodiments have been described in conjunction with the drawings, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Specifically, various additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure (such as those claimed herein, including legal equivalents). Additionally, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: Array area; fictitious area; pillars of electrically insulating material, which are located in the array region and the dummy region; an electrically conductive contact between adjacent pillars of said electrically insulating material in said array region; another electrically insulating material between adjacent pillars of the electrically insulating material in the dummy region; a conductive material over the conductive contacts in the array region and over the electrically insulating material in the dummy region; and An oxide directly between and contacting the conductive material in the dummy region and the electrically insulating material in the dummy region, the oxide being on at least a portion of a sidewall of the electrically insulating material in the dummy region. The semiconductor device according to claim 1 , wherein the oxide comprises silicon dioxide. The semiconductor device of claim 1 , wherein the electrically insulating material comprises silicon nitride. The semiconductor device according to claim 1 , wherein the conductive contact comprises polysilicon. The semiconductor device according to claim 1 , wherein the conductive material comprises tungsten.

6. The semiconductor device of any one of claims 1-5, further comprising a capacitor in electrical communication with the conductive material over the conductive contact.

7. The semiconductor device of any one of claims 1 to 5, wherein a width of an upper portion of the electrically insulating material is less than a width of a lower portion of the electrically insulating material.

8. The semiconductor device of any one of claims 1 to 5, wherein an upper surface of the electrically insulating material is located further from an underlying substrate than an upper surface of the further electrically insulating material. 9 . The semiconductor device according to claim 8 , wherein a distance between the upper surface of the electrically insulating material and the upper surface of the another electrically insulating material is in the range of 1 nm to 5 nm.

10. The semiconductor device of any one of claims 1-5, further comprising a silicide material between the conductive contact and the conductive material in the array region. The semiconductor device according to claim 10 , wherein the dummy region does not contain the silicide material.

12. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the oxide is from arrive within the range.

13. The semiconductor device of claim 1, further comprising a memory storage element in communication with the conductive material in the array region and in the dummy region.

14. A system comprising: The semiconductor device of claim 1 operatively coupled to at least one processor device operatively coupled to at least one input device and at least one output device.

15. A method of forming a semiconductor device, the method comprising: removing a portion of a first electrically insulating material so that an upper surface of the first electrically insulating material is recessed relative to an upper surface of a second electrically insulating material; oxidizing an exposed surface of the first electrically insulating material to form an oxide material over the first electrically insulating material in an array region and a dummy region of the device; bonding a masking material to the oxide material over the first electrically insulating material in the dummy region of the device; removing the second electrically insulating material from the array region of the device; forming an electrically conductive contact between pillars of the first electrically insulating material over the device and in the array region; and A conductive material is formed over the conductive contacts in the array region and over the oxide material in the dummy region, the oxide material being directly between and contacting the conductive material in the dummy region and the first electrically insulating material. The method of claim 15 , wherein forming a mask material comprises forming a photoresist material.

17. The method of any of claims 15-16, wherein oxidizing an exposed surface of the first electrically insulating material comprises oxidizing an exposed surface of the first electrically insulating material comprising silicon nitride.

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