IC layout tile with internal channels for signal distribution

Abstract

A modular layout design unit having internal channels for multi-directional distribution of shared signals is provided. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each having an internal channel for signal distribution. The internal channel has: an edge connection on each edge of the modular unit; a hub node coupled to each edge connection through a corresponding bidirectional buffer, the bidirectional buffer having an input and an output buffer and at least one of the input and output buffers being disabled, the bidirectional buffers cooperating to divert a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap providing a signal for use by an internal circuit of the modular unit.

Description

Background Art

[0001] Most integrated circuit devices have become so complex that it is impractical for electronic device designers to design integrated circuit devices from scratch. Instead, electronic device designers rely on pre-defined modular units of integrated circuit layout design, arranging and joining them as needed to achieve various functions of the desired device. Each modular unit has a defined interface and behavior that has been verified by its creator. Although each modular unit may require a lot of time and investment to create, its reuse and availability for further development greatly shorten the product cycle time and make the product better. The pre-defined units can be organized hierarchically, with a given unit containing one or more low-level units and being included in the high-level unit. Many organizations have libraries of such pre-defined modular units for sale or licensing, including, for example: embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, etc. Pre-defined modular units are also called units, boxes, cores, and macros, which have different meanings and variations ("IP cores", "soft macros"), but are often used interchangeably.

[0002] Modular cells can be expressed in different ways, for example, in the form of a hardware description language (HDL) file, or in the form of a fully routed design that can be printed directly onto a range of manufacturing process masks. Fully routed design files are typically process specific, which means that additional design work may often be required to migrate modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but are process independent, which means that different manufacturers can apply their preferred automatic synthesis, placement, and routing processes to implement the cells using various manufacturing processes. Due to the high-level representation of HDL cells, they can be easier to modify and easy to use variable design parameters, while fully routed cells can provide better predictability in terms of area requirements, reliability, and performance. Although there are no fixed rules, digital module design is usually specified in HDL form, while analog and mixed-signal cells are usually specified as low-level physical descriptions.

[0003] When modular units have compatible interfaces, electronic device designers are able to route their interface signals together using short, simple conductors, or even in some cases by abutting the modular units together so that their interface signal input and output nodes are connected together. More commonly, however, electronic device designers desire to "stitch" modular units together using buffers and latches to pass interface signals from one unit to the next. As more units are combined and signal frequencies increase, stitching becomes increasingly complex, particularly with respect to distributing shared signals to multiple units without sacrificing quality. Summary of the invention

[0004] Accordingly, disclosed herein is a tileable layout design unit with built-in channels for multi-directional distribution of shared signals. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each modular unit having an internal channel for signal distribution. The internal channel has: an edge connection, the edge connection being on each edge of the modular unit; a hub node, the hub node being coupled to each edge connection through a corresponding bidirectional buffer, the bidirectional buffer having an input buffer and an output buffer, wherein at least one of the input buffer and the output buffer is disabled, the bidirectional buffers cooperating to divert a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap, the tap providing a signal for use by an internal circuit of the modular unit.

[0005] In another illustrative embodiment, a method for manufacturing an integrated circuit includes: arranging a plurality of modular units to form an array, each modular unit in the array having an internal channel for distributing signals to adjacent modular units via edge connections on each edge of the modular unit, the internal channel including a hub node coupled to each edge connection through a corresponding bidirectional buffer, the bidirectional buffer having an input buffer and an output buffer; coupling a source of a signal to one of the edge connections; and selectively disabling the input buffer and the output buffer of the bidirectional buffer to provide a signal distribution path from the source to each of the plurality of modular units.

[0006] In yet another illustrative embodiment, a method for distributing a clock signal includes providing a plurality of modular units, each modular unit having an internal channel; electrically connecting each of the plurality of modular units to one or more of the other plurality of modular units via an edge connection of the internal channel to extend the internal channel over each of the plurality of modular units; coupling a clock signal to the edge connection of one of the plurality of modular units; and disabling an output buffer and selected ones of an input buffer of the internal channel to configure the internal channel as a clock distribution tree that transmits the clock signal to each of the plurality of modular units.

[0007] Each of the foregoing embodiments may be implemented individually or in combination, and may be implemented with one or more of the following features in any suitable combination: 1. The modular unit has four edges. 2. A bidirectional buffer diverts a signal from a selectable one of the edge connections to each of the other edge connections. 3. One or more modular units include a plurality of modular units abutting each other to form an array, the abutting electrically connecting the edge connections of adjacent modular units. 4. Some of the bidirectional buffers are disabled to prevent loops and / or conflicts within the signal distribution path. 5. The signal is a clock signal. 6. The internal circuitry of the modular unit includes a deserializer that derives a sampling clock from the clock signal. 7. The tap includes a buffer that connects the hub node to the internal circuitry. 8. Each connection between one of the bidirectional buffers and a corresponding edge connection is an arm segment. 9. The tap is one of a plurality of taps from a given arm segment. 10. One or more arm segments are tapped to provide a signal for use by the internal circuitry of the modular unit. 11. The bidirectional buffers in each of the plurality of modular units cooperate to divert a signal from a selected one of the edge connections to one or more of the other edge connections. 12. The arrangement includes abutting a plurality of modular units to electrically connect edge connections of adjacent modular units. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a plan view of a wafer patterned with integrated circuit devices.

[0009] Figure 1B is a block diagram of an illustrative application specific integrated circuit.

[0010] Figure 1C is a block diagram of multiple deserializer instances sharing a clock.

[0011] Figure 2A is a schematic diagram of a first illustrative modular block.

[0012] Figure 2B is a schematic diagram of a second illustrative modular block.

[0013] Figure 2C is a schematic diagram of a third illustrative modular block.

[0014] Figure 2D is a schematic diagram of a fourth illustrative modular block.

[0015] Figure 3 is a schematic diagram of an illustrative allocation tree implemented by adjacency- and locally-connected modular boxes. DETAILED DESCRIPTION

[0016] Although specific embodiments are presented in the drawings and the following description, it is noted that they do not limit the present disclosure. Instead, they provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are included within the scope of the appended claims.

[0017] Figure 1A A plan view of a semiconductor wafer 100 is shown which is patterned to form an array of integrated circuits 102 which can be segmented into IC chips and packaged as components for assembly in electronic devices. The IC chips can be packaged individually or combined into multi-chip modules using interposers and / or packaging substrates, in either case using a ball grid array or lead frame to provide external contacts for electrical connection with other circuit components, typically via a printed circuit board. Each IC chip can implement digital logic, analog functions, and / or mixed signal circuits.

[0018] The patterning of wafers is performed by a semiconductor fabrication facility ("fab") using a series of cleaning, alignment, deposition, patterning, etching, implantation, and related processes. The "recipe" (sequence of patterns and process steps) employed determines the functionality of the resulting integrated circuit. The recipe to be used is specified by the electronic device designer working for the fab customer or for the company that owns the fab. As described in the background, the designer facilitates the design process by relying on modular layout design units to implement the elements of the desired integrated circuit. These modular units can be pre-defined units obtained from an existing library or from a supplier that specializes in designing components of the desired type.

[0019] Figure 1BAn illustrative high-speed serializer / deserializer ("SerDes") retimer chip 110 is shown, which serves as an example of an integrated circuit device here. Chip 110 includes: a SerDes module with contacts 111 for receiving and transmitting a high-speed serial bit stream in four lines in one direction; an additional SerDes module with contacts 112 for receiving and transmitting a high-speed serial bit stream in four lines in the other direction; and core logic 113 for handling channel communication protocols while buffering the interconnection between the two directions. Chip 110 also includes: support modules and contacts 114, 115, such as power regulation and distribution, clock generation, digital input / output lines for control, and a JTAG module for built-in self-test. A chip designer can design a device by placing pre-defined modular units of serializers, deserializers, power supplies, clock generators, I / O cells, and JTAG and using some support logic to route the interconnections between the modular units.

[0020] The retimer chip uses an instance of eight deserializer modules 120, and the eight deserializer modules 120 can share a common clock source, such as Figure 1C 120. Each instance 120 uses an analog-to-digital converter 122 to digitize a received signal 121 to obtain a digital received signal, which is then processed by a demodulator 123 to extract a represented bit stream 124. A phase-locked loop 125 obtains a clock signal from a shared oscillator 126, multiplies it as needed to generate a channel clock signal having a frequency associated with the symbol rate of the received signal 121. A phase interpolator 127 adjusts the phase of the channel clock signal as needed to provide a sampling clock signal to the ADC 122. The phase interpolator 127 can also be used to provide a smaller frequency offset to the sampling clock as needed to compensate for frequency drift. The phase and frequency offsets are determined by a feedback loop filter 128 or an error processor operating on a timing error signal from a timing error sensor 129. The feedback loop operates to minimize the timing error so that the sampling clock can track any reasonable changes in the phase and frequency of the received signal. Not shown, but also likely included, are channel symbol decoders, serial-to-parallel converters, frame alignment modules, demultiplexers, FEC decoders, and other such elements that implement the desired channel traffic protocol and enable reliable extraction of communicated data.

[0021] Although the above summary of the deserializer operation may seem easy, the actual implementation may be very challenging, especially at very high channel symbol rates (e.g., symbol rates above 5 GHz) where jitter and noise need to be strictly controlled. Accordingly, chip designers may strongly prefer to use pre-defined modular units provided by professional suppliers for this purpose. However, in order to ensure that the predetermined modular units work as expected, designers need to provide high-quality clock signals with minimal jitter and noise for the pre-defined modules, because any jitter on the clock channel accumulates and translates into a loss of performance margin of the modular units. It is very challenging for chip designers to distribute low-noise clock signals at the die, package substrate or PCB level, especially when multiple instances of modular units whose performance depends on a low-noise clock source are integrated. Care must be taken to isolate the clock tree from noise sources and ensure that the clock tree has sufficient buffering in the chain to prevent unnecessary jitter due to slowed conversion rates. To the greatest extent practicable, experts (in this case the designers of the predefined modules) preferably handle clock signal distribution rather than relying on chip designers to attempt to route the clock signals while taking the necessary stringent measures to prevent accidental sources of jitter and noise.

[0022] Accordingly, a clock channel grid implemented in a predefined modular unit is provided herein, which has a configurable allocation direction, so that multiple instances of a modular layout design unit can receive and / or send reference clock signals only by adjacency or, if necessary, via short interconnect traces that do not require additional buffering. The clock channel grid includes all necessary noise isolation and buffering within the layout design box, thereby facilitating the designer's work. Implementing the clock channel in this manner can also provide the potential benefit of reducing the number of identical clock sources entering the package, thereby reducing the overall bill of materials (BOM) cost.

[0023] This "distribution-by-abutment" feature enables multiple instances of a selected modular unit to be assembled in a space-filling abutment manner, i.e., "tiled," as discussed further below. Modular units having this feature may accordingly be referred to as "tiles," and may be designed with 2-fold (rectangular or parallelogram), 3-fold (triangular), 4-fold (square), or 6-fold (hexagonal) symmetry in the arrangement of clock distribution ports, although in the absence of such symmetry, mirroring may be selectively employed to provide abutment connectivity.

[0024] Figure 2Ais a schematic diagram of an illustrative modular unit having an internal channel for distributing a shared signal (such as a low-jitter clock signal). The modular unit includes one or more subunits (labeled as layout design units x in FIG. 2 and Figure 3 The modular unit is provided with a "central" node C that is coupled to a channel connection on each edge of the modular unit through a bidirectional buffer. In the illustrated embodiment, a modular unit having a rectangular shape is provided, with a channel connection on each of the four edges of the rectangular shape. The four connections are labeled W, N, E, and S in the figure. The bidirectional buffers that couple each channel connection to the node include an "outgoing" buffer that buffers a signal from the central node C to a channel connection on one of the edges; and an "incoming" buffer that buffers a signal from an edge connection to the central node C. One of the output buffer or the input buffer is enabled, but not both. For the edge at which the channel connection is desired to be terminated, the input and output buffers can be disabled.

[0025] exist Figure 2A In , four logic signals are used to indicate edge connections through which signals enter the modular unit: Win, Nin, Ein, Sin. Although some system embodiments may allow more than one of these signals to be true, it is generally preferred that the signal distribution path has the structure of a tree graph, such as each node has exactly one parent (i.e., only one signal source). In this case, exactly one of the four signals is true, making it possible to use two bits B1B0 to represent four options. Although different binary code assignments are possible, one possible encoding uses 00, 01, 11, and 10 to indicate that S, E, N, and W are the incoming edges of the signal, respectively. In this example, the logic signal Sin can be expressed as -(B1+B0) and can be expressed as Figure 2B The southern bidirectional buffer is realized as shown in FIG. Other signals can be expressed as Ein=(-B1)*(B0), Nin=(B1)*(B0), Win=(B1)*(-B0).

[0026] Since the distribution paths are established during the layout phase and do not need to be changed thereafter, the enable nodes of each of the logic signals or equivalent input and output buffers can be tied high or low as part of the manufacturing process to create the appropriate steering paths for distributing shared signals. Alternatively, the enable nodes of each of the input and output buffers can be tied to programmable register bits, thereby providing the user with complete flexibility at power-up under the only constraint that the programmed bit states do not cause any signal conflicts that could damage the device. The signal paths can be implemented differentially or in a single-ended manner, with appropriate buffer gain, routing size, and / or shielded conductors as needed to minimize signal noise and environmental sources of jitter.

[0027] exist Figure 2A In , the clock signal is provided to the functional sub-unit(s) by one or more signal buffers from a central node C, but additional bidirectional buffers may be included to prevent capacitive loading from slowing down the signal conversion rate. Figure 2C An embodiment is shown in which the central node C is used only for signal steering and an additional bidirectional buffer is provided to create an additional segment in the "west" channel arm for providing signals to (multiple) functional subunits and bidirectional buffers near edge connections or providing signals from bidirectional buffers near edge connections. This principle can be as follows Figure 2D , to provide additional segments along the distribution channel as needed to support an indefinite number N of functional subunits. As a practical matter, the number of functional subunits may be limited by the inherent jitter of each buffer stage, which, when accumulated, should still meet the signal specification requirement for total random jitter. Note that the segments need not be concentrated on one arm of the channel, but can be provided along any or all channel arms as needed.

[0028] Figure 31 is a schematic diagram showing a plurality of modular units closely adjacent or placed to enable the use of short interconnects and an illustrative signal distribution tree formed by internal channels. The enable node of each of the input and output buffers is shown as being bound to a high (enabled) voltage rail or a low (disabled) voltage rail, and the disabled buffer is shown with a reduced line width to help understand how the distribution channel adopts a tree structure. The differential comparator at the bottom left converts the differential clock signal (CXP, CXN) into a single-ended signal, which is then provided to the lower edge connection of the modular unit at the bottom left. In the modular unit at the bottom left, the clock signal is used locally and distributed to each of the other three edges, although only adjacent connections are shown at the upper edge and the right edge. The signal passing through the upper edge is used by the middle left modular unit and distributed to the upper edge and the left edge. The dual-phase buffer at the right edge is disabled to avoid forming a loop in the distribution path via the adjacent center modular unit. Similarly, the upper left modular unit uses the signal locally and avoids distributing the signal to the right to prevent the formation of a loop in the distribution path via the adjacent middle upper unit. Connections for further distribution are available on the upper edge as well as on the left edge.

[0029] The lower middle modular cell receives a signal from its left edge connection, uses the signal locally, and distributes it from each of the other edges of the modular cell. The center modular cell abuts the lower middle cell to receive the signal, and abuts the upper middle cell to distribute the clock signal via its upper edge. The lower right modular cell is placed adjacent to the lower middle cell, with a conductive interconnect connecting the right edge connection of the lower middle cell to the left edge connection of the lower right cell. The middle right cell abuts the upper edge of the lower right cell to receive the signal, and abuts the lower edge of the upper right cell to pass the signal via the upper edge connection. In this way, a device designer can instantiate multiple modular cells with internal channels to provide distribution of shared signals.

[0030] Note that Figure 3 In the embodiment of the present invention, a mirror image of the modular cell is used to ensure the alignment of the edge connections. This can be done because almost all integrated circuits are functionally equivalent when mirrored to each other. Although such mirroring is often convenient, it is not required if the connections have the desired symmetry. Other signals used by the modular cell can be provided via different layers in the device design and / or via pad connections inside the outline of the modular cell. In the specific case of a SerDes device, external signals can be provided via ball grid array pads.

[0031] The above-described embodiments and principles may provide at least the following potential advantages: simplification of clock tree routing in high macro instances, built-in noise suppression of the clock tree, built-in buffering of the clock tree for long-distance routing, and highly flexible design.

[0032] Numerous alternatives, equivalents and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the claims be interpreted as covering all such alternatives, equivalents and modifications that are included within the scope of the appended claims.

Claims

1. An integrated circuit, comprising: One or more modular units, each modular unit having an internal channel for signal distribution, the internal channel comprising: an edge connection, the edge connection being on each edge of the modular unit; a hub node coupled to each edge connection via a respective bidirectional buffer, the bidirectional buffer having an input buffer and an output buffer, at least one of the input buffer and the output buffer being disabled, the bidirectional buffers cooperating to divert signals from a selectable one of the edge connections to one or more of the other edge connections; and A tap provides the signal for use by internal circuitry of the modular unit.

2. The integrated circuit according to claim 1, characterized in that The modular unit has four edges, and wherein the bidirectional buffer diverts the signal from the selectable one of the edge connections to each of the other edge connections.

3. The integrated circuit according to claim 1, characterized in that The one or more modular units include a plurality of modular units abutting each other to form an array, the abutting electrically connecting edge connections of adjacent modular units.

4. The integrated circuit according to claim 3, characterized in that Some of the bidirectional buffers are disabled to prevent signal distribution path loops.

5. The integrated circuit according to claim 1, characterized in that The signal is a clock signal.

6. The integrated circuit according to claim 5, characterized in that The internal circuitry of the modular unit includes a deserializer that derives a sampling clock from the clock signal.

7. The integrated circuit according to claim 1, characterized in that The tap includes a buffer that connects the hub node to the internal circuit.

8. The integrated circuit according to claim 1, characterized in that Each connection between one of the bidirectional buffers and the corresponding edge connection is an arm segment, and wherein the tap is one of a plurality of taps from a given arm segment.

9. The integrated circuit according to claim 1, characterized in that: Each connection between one of the bidirectional buffers and the corresponding edge connection is an arm segment, and wherein a plurality of such segments are tapped out to provide the signal for use by internal circuitry of the modular unit.

10. A method of manufacturing an integrated circuit, the method comprising: Arranging a plurality of modular units to form an array, each modular unit in the array having an internal channel for distributing signals to adjacent modular units via edge connections on each edge of the modular unit, the internal channel including a hub node coupled to each edge connection via a corresponding bidirectional buffer, the bidirectional buffer having an input buffer and an output buffer; coupling a source of a signal to one of the edge connections; and An input buffer and an output buffer of the bidirectional buffer are selectively disabled to provide a signal distribution path from the source to each of the plurality of modular units.

11. The method according to claim 10, characterized in that The bidirectional buffers in each of the plurality of modular units cooperate to divert a signal from a selected one of the edge connections to one or more of the other edge connections, and wherein each of the modular units further comprises a tap that provides the signal for use by the modular internal circuitry.

12. The method according to claim 10, characterized in that The arranging includes abutting the plurality of modular units to electrically connect the edge connections of adjacent modular units.

13. The method according to claim 12, characterized in that Some of the bidirectional buffers are completely disabled to prevent loops within the signal distribution path.

14. The method according to claim 10, characterized in that The signal is a clock signal.

15. The method according to claim 14, characterized in that Internal circuitry in each of the modular units includes a deserializer that derives a sampling clock from the clock signal.

16. A method for distributing a clock signal, the method comprising: A plurality of modular units are provided, each of the plurality of modular units having an internal channel, the internal channel comprising: an edge connection, the edge connection being on each edge of the modular unit; a hub node coupled to each edge connection via a corresponding bidirectional buffer having an input buffer and an output buffer; and a tap, the tap providing the clock signal for use by internal circuitry of the modular unit; electrically connecting each of the plurality of modular units to one or more of the other plurality of modular units via the edge connection to extend the internal channel on each of the plurality of modular units; coupling a clock signal source to an edge connection of one of the plurality of modular units; and The output buffer and selected ones of the input buffers are disabled to configure the internal channel as a clock distribution tree that transmits the clock signal to each of the plurality of modular units.

17. The method according to claim 16, characterized in that The tap includes a buffer that connects the hub node to the internal circuit.

18. The method according to claim 16, characterized in that Each connection between one of the bidirectional buffers and the corresponding edge connection is an arm segment, and wherein the tap is one of a plurality of taps from a given arm segment.

19. The method according to claim 16, characterized in that Each of the plurality of modular units has four edges.

20. The method according to claim 16, characterized in that The electrically connecting includes abutting at least some of the plurality of modular units to form an array, the abutting electrically connecting edge connections of adjacent modular units.

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