Electrostatic discharge protection circuit

Abstract

An electrostatic discharge (ESD) protection circuit includes: a plurality of transistors, each transistor including a gate terminal, a drain terminal, and a source terminal; a first connection line connected to the drain terminals of the plurality of transistors; a second connection line connected to the source terminals of the plurality of transistors; a third connection line connected to the gate terminals of the plurality of transistors; an external resistor connected to the third connection line; and a ground terminal connected to the external resistor. The external resistor includes a first resistor and a second resistor connected in parallel with each other.

Description

Technical Field

[0001] The present disclosure relates to an electrostatic discharge protection circuit, and more particularly, to an ESD protection circuit including a gate-coupled transistor. Background Art

[0002] When a semiconductor circuit comes into contact with a charged human body or machine, the static electricity carried by the human body or machine may be released into the semiconductor circuit through the input / output (I / O) pads, causing transient current to flow in the semiconductor's internal circuit, thereby potentially damaging the semiconductor circuit.

[0003] Therefore, to prevent the internal semiconductor circuit from being damaged by static electricity, the semiconductor circuit includes an ESD protection circuit between the I / O pad and the internal semiconductor circuit. When static electricity with an overvoltage flows into the I / O pad, the ESD protection circuit limits the voltage level of the node between the I / O pad and the internal semiconductor circuit to a certain range, thereby protecting the internal semiconductor circuit.

[0004] In the prior art, bipolar junction transistors (BJTs) or diodes are primarily used as ESD protection circuits. However, grounded-gate NMOS (GGNMOS) transistors have recently gained widespread use. GGNMOS transistors are transistors with grounded gates. Due to static-induced breakdown, the NMOS transistor's npn structure behaves like a BJT transistor, releasing a large amount of current. However, with the advancement of semiconductor technology, the thickness of the gate insulating layer has become significantly thinner, increasing the likelihood of the gate insulating layer being damaged by ESD pulses.

[0005] Therefore, a gate-coupled NMOS (GCNMOS) transistor has been proposed, which is designed so that the gate of the NMOS transistor is turned on based on a relatively low voltage to reduce damage to a gate insulating layer.

[0006] In particular, when configuring an ESD protection circuit by connecting multiple GCNMOS transistors, damage to the gate insulating layer can be reduced, and an ESD effect can be effectively achieved. However, in this case, the resistance value varies depending on the position of the ESD protection circuit, and therefore, the resistance value varies depending on the position of the gate bias, resulting in a decrease in the uniformity of the discharge current. Summary of the Invention

[0007] Accordingly, the present disclosure is directed to an ESD protection circuit that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0008] An aspect of the present disclosure is to provide an ESD protection circuit that reduces a deviation in a resistance value to enhance uniformity of a discharge current based on a position.

[0009] Other advantages and features of the present disclosure will be partially described in the following description and will become apparent to those skilled in the art after reading the following or may be learned from the practice of the present disclosure. The objectives and other advantages of the present disclosure may be realized and obtained through the structure particularly pointed out in the written description and claims and the accompanying drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, there is provided an electrostatic discharge (ESD) protection circuit comprising: a plurality of transistors, each transistor comprising a gate terminal, a drain terminal, and a source terminal; a first connection line connected to the drain terminals of the plurality of transistors; a second connection line connected to the source terminals of the plurality of transistors; a third connection line connected to the gate terminals of the plurality of transistors; an external resistor connected to the third connection line; and a ground terminal connected to the external resistor, wherein the external resistor comprises a first resistor and a second resistor connected in parallel with each other.

[0011] In another aspect of the present disclosure, an electrostatic discharge (ESD) protection circuit is provided, which includes: a plurality of transistors, each transistor including a gate terminal arranged on a substrate; an external resistor, the external resistor including a first resistor and a second resistor connected in parallel to each other on the substrate; a connecting line connecting the external resistor to the gate terminal; a grounding line connected to the external resistor; a first insulating layer, the first insulating layer being arranged in the bottom surface of the gate terminal; a second insulating layer, the second insulating layer being arranged in the top surface of the gate terminal; and a third insulating layer, the third insulating layer being arranged in the top surface of the grounding line, wherein the connecting line includes a first connecting portion connected to the gate terminal and a second connecting portion connecting the first connecting portion to the first resistor.

[0012] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is a diagram showing unit elements constituting an ESD protection circuit according to one embodiment of the present disclosure;

[0015] Figure 2 is a diagram showing an ESD protection circuit according to one embodiment of the present disclosure;

[0016] Figure 3 is a schematic plan view of an ESD protection circuit according to one embodiment of the present disclosure;

[0017] Figure 4 is a diagram showing a schematic cross-sectional shape of an ESD protection circuit according to one embodiment of the present disclosure;

[0018] Figure 5 is a plan view of an ESD protection circuit according to another embodiment of the present disclosure; and

[0019] Figure 6 is a cross-sectional view of an ESD protection circuit according to another embodiment of the present disclosure, and is taken along Figure 5 A cross-sectional view taken along line I-II in FIG. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0021] The advantages and features of the present disclosure and their implementation methods will be explained through the embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0022] The shapes, sizes, ratios, angles and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the text, the same reference numerals represent the same elements. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted. Where "comprising", "having" and "including" described in this specification are used, another component may be added unless "only" is used. Unless otherwise indicated, a term in the singular may include a plural form.

[0023] Although not explicitly described, when an element is constructed, the element is constructed to include a range of error.

[0024] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "above," "below," and "next," unless "just" or "directly" is used, one or more other components may be disposed between the two components.

[0025] When describing a time relationship, for example, when a time sequence is described as "after," "followed," "next," and "before," discontinuous cases may be included unless "immediately" or "directly" is used.

[0026] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0027] When describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. can be used. Such terms are only used to distinguish corresponding elements from other elements, and corresponding elements are not restricted by these terms in their essence, order or priority. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to other elements or layers, or there can be an intermediate element or layer. In addition, it should be understood that when an element is arranged on or below another element, this can represent that the element is set to be in direct contact with each other, but can also represent that the element is set to not be in direct contact with each other.

[0028] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" refers to all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0029] As will be fully appreciated by those skilled in the art, the features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be driven technically in different ways. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 11 is a diagram showing unit elements constituting the ESD protection circuit 3 according to one embodiment of the present disclosure.

[0032] like Figure 1 As shown, a unit element of an ESD protection circuit 3 according to an embodiment of the present disclosure may be provided between an input / output (I / O) pad 1 and a semiconductor internal circuit 2 .

[0033] The I / O pad 1 and the semiconductor internal circuit 2 may be connected to each other through a first connection wire 10 , and unit elements of the ESD protection circuit 3 may be connected to the first connection wire 10 .

[0034] The unit elements of the ESD protection circuit 3 may include a transistor Tr, a capacitor C, and an external resistor R.

[0035] The transistor Tr may include a gate-coupled MOS (GCMOS) transistor in which its gate terminal G is connected to the I / O pad 1 , and more specifically, may include a gate-coupled NMOS (GCNMOS) transistor in which its gate terminal G is coupled to the I / O pad 1 .

[0036] The drain terminal D of transistor Tr can be connected to the I / O pad 1 through a first connection line 10, the source terminal S of transistor Tr can be connected to the ground terminal GND through a second connection line 20, and the gate terminal G of transistor Tr can be connected to a node N connected in series to the capacitor C and the resistor R.

[0037] The capacitor C may be provided between the gate terminal G and the drain terminal D of the transistor Tr. The capacitor C may be implemented as a separate capacitor element, or may be implemented as a parasitic capacitor between the gate terminal G and the drain terminal D. That is, the gate terminal G may overlap with the drain terminal D with an insulating layer therebetween, and thus, a parasitic capacitor may be formed therebetween, and the parasitic capacitor may be used as a unit element of the ESD protection circuit 3.

[0038] The external resistor R may be connected to the capacitor C and the gate terminal G at the node N and may be connected to the ground terminal GND through the second connection line 20. The external resistor R may include a semiconductor material such as polysilicon, but is not limited thereto and may include various materials such as metal.

[0039] Next, the operation of the ESD protection circuit 3 will be described.

[0040] When an ESD event occurs from I / O pad 1, ESD protection circuit 3 can direct the ESD current to ground terminal GND to prevent damage to semiconductor internal circuit 2. Specifically, when a high-frequency ESD pulse is applied to I / O pad 1, the current generated by the ESD pulse may flow through capacitor C and external resistor R to ground terminal GND. At this time, the current flowing through external resistor R may cause a voltage drop, thereby increasing the gate voltage to turn on transistor Tr. In other words, when the gate voltage at gate terminal G, which is normally grounded, increases due to the voltage drop, transistor Tr can be turned on. As a result, the current caused by static electricity can flow through the channel of transistor Tr to ground terminal GND, thereby preventing damage to semiconductor internal circuit 2.

[0041] Figure 2 is a diagram illustrating an ESD protection circuit 3 according to one embodiment of the present disclosure.

[0042] like Figure 2 As shown, the ESD protection circuit 3 according to one embodiment of the present disclosure may be provided between the I / O pad 1 and the semiconductor internal circuit 2 .

[0043] The I / O pad 1 and the semiconductor internal circuit 2 may be connected to each other through a first connection wire 10 , and a drain terminal D of the transistor Tr constituting the ESD protection circuit 3 may be connected to the first connection wire 10 .

[0044] The ESD protection circuit 3 may include a plurality of transistors Tr, a plurality of capacitors C, and a plurality of external resistors R1 and R2 .

[0045] Each of the plurality of transistors Tr may include a GCMOS transistor in which a gate terminal G thereof is coupled to the I / O pad 1, and two adjacent transistors Tr may be arranged to share a source terminal S or a drain terminal D. For example, the source terminal S of the first transistor Tr may be used as the source terminal S of the second transistor Tr disposed adjacent thereto on its right side, and the drain terminal D of the second transistor Tr may be used as the drain terminal D of the third transistor Tr disposed adjacent thereto on its right side.

[0046] Similar to the above-described embodiment, the drain terminal D of each of the transistors Tr may be connected to the I / O pad 1 through the first connection line 10, and the source terminal S of each of the transistors Tr may be connected to the ground terminal GND through the second connection line 20. In addition, the gate terminal G of each of the transistors Tr may be connected to the external resistors R1 and R2 through the third connection line 30.

[0047] Each of the plurality of capacitors C may be provided between the gate terminal G and the drain terminal D of a corresponding transistor Tr among the plurality of transistors Tr. Each of the plurality of capacitors C may be implemented as an individual capacitor element or as a parasitic capacitor between the gate terminal G and the drain terminal D.

[0048] The external resistors R1 and R2 may include a first resistor R1 and a second resistor R2, and the first resistor R1 and the second resistor R2 may be connected in parallel to each other. One end of each of the first resistor R1 and the second resistor R2 may be connected to the gate terminal G via a third connection line 30, and the other end of each of the first resistor R1 and the second resistor R2 may be connected to the ground terminal GND. In addition, the first resistor R1 and the second resistor R2 may be connected to a second connection line 20. The external resistors R1 and R2 may include a semiconductor material such as polysilicon, but are not limited thereto, and may include various materials such as metal.

[0049] As described above, the ESD protection circuit 3 according to an embodiment of the present disclosure may include a plurality of transistors Tr, a plurality of capacitors C, and a plurality of resistors R1 and R2, thereby further enhancing the ESD protection effect.

[0050] When the ESD protection circuit 3 includes a plurality of transistors Tr, a deviation in resistance value may occur for each position of the ESD protection circuit 3, and according to one embodiment of the present disclosure, the position-based resistance deviation can be reduced by using a configuration in which a first resistor R1 and a second resistor R2 are provided in parallel. Figure 3 Describe this.

[0051] Figure 3 is a schematic plan view of an ESD protection circuit according to one embodiment of the present disclosure.

[0052] like Figure 3 As shown, a plurality of transistors Tr each including a gate terminal G, a drain terminal D, and a source terminal S can be arranged in a plurality of rows. Specifically, each of the gate terminal G, the drain terminal D, and the source terminal S can be configured as a straight line structure extending in one direction (e.g., a vertical direction). Specifically, two adjacent transistors Tr can share the drain terminal D or the source terminal S, thereby reducing the area occupied by the plurality of transistors Tr.

[0053] The gate terminal G may have an internal resistor Rg, and the gate terminal G may be formed of a semiconductor material such as polysilicon, wherein the internal resistor Rg has a high resistance value. A capacitor C such as a parasitic capacitor may be provided between the gate terminal G and the drain terminal D.

[0054] The plurality of gate terminals G may be connected to the first resistor R1 via the third connection line 31 on one side (e.g., the upper side), and may be connected to the second resistor R2 via the third connection line 32 on the other side (e.g., the lower side). Specifically, the upper ends of the plurality of gate terminals G may be connected to the third connection line 31 on one side via the contact portion x, the third connection line 31 on one side may be connected to the first resistor R1 via the contact portion x, and the first resistor R1 may be connected to the ground terminal GND. In addition, the lower ends of the plurality of gate terminals G may be connected to the third connection line 32 on the other side via the contact portion x, the third connection line 32 on the other side may be connected to the second resistor R2 via the contact portion x, and the second resistor R2 may be connected to the ground terminal GND. In this specification, the contact portion x may refer to a configuration in which two layers (e.g., a lower layer and an upper layer) spaced apart from each other have an insulating layer therebetween, and the two layers are directly connected to each other via a contact hole passing through the insulating layer, or are connected to each other via an interconnect (via) filled in the contact hole.

[0055] The third connection line 31 on one side and the third connection line 32 on the other side may extend in a direction (e.g., horizontal direction) intersecting the extension direction of each of the gate terminal G, the drain terminal D, and the source terminal S. In addition, the first resistor R1 and the second resistor R2 may extend in the same direction (e.g., vertical direction) as the extension direction of each of the gate terminal G, the drain terminal D, and the source terminal S. The first resistor R1 may be provided on one side (e.g., the left outer side) of each of the plurality of transistors Tr, and the second resistor R2 may be provided on the other side (e.g., the right outer side) of each of the plurality of transistors Tr.

[0056] For example, when one of the first resistor R1 and the second resistor R2 is omitted, a large difference may occur between the resistance values ​​depending on the position. For example, a large difference may occur between the resistance value of region A at the upper left end and the resistance value of region B at the lower right end. More specifically, when the number of columns of the plurality of transistors Tr increases or the distance from the upper end to the lower end of each transistor Tr increases, the resistance deviation depending on the position may increase. As described above, when the resistance deviation depending on the position increases, the gate bias may vary for each position, and due to this, the uniformity of the discharge constant current may decrease.

[0057] However, according to one embodiment of the present disclosure, since the first resistor R1 is configured to be electrically connected to one end (e.g., the upper end) of each of the multiple gate terminals G, and the second resistor R2 is configured to be electrically connected to the other end of each of the multiple gate terminals G, the position-based resistance deviation can be reduced, thereby enhancing the uniformity of the discharge current.

[0058] Figure 4 is a diagram illustrating a schematic cross-sectional shape of an ESD protection circuit according to one embodiment of the present disclosure.

[0059] like Figure 4 As shown, the drain terminal D and the source terminal S may be alternately arranged on the upper end of the semiconductor substrate 100, the first insulating layer 210 may be provided on the top surface of the semiconductor substrate 100 and between the drain terminal D and the source terminal S, and the gate terminal G may be provided on the first insulating layer 210. In this case, a specific region of the gate terminal G may overlap with a specific region of the drain terminal D, and therefore, a parasitic capacitor C may be provided therebetween.

[0060] As shown in the figure, a plurality of transistors Tr may be arranged such that two adjacent transistors Tr share a source terminal S or a drain terminal D.

[0061] A first resistor R1 may be disposed at a left outer portion of each of the plurality of transistors Tr on the semiconductor substrate 100 , and a second resistor R2 may be disposed at a right outer portion of each of the plurality of transistors Tr on the semiconductor substrate 100 .

[0062] The drain terminals D of the plurality of transistors Tr may be connected to the first connection line 10 between the I / O pad 1 and the semiconductor internal circuit 2. The source terminals S of the plurality of transistors Tr may be connected to the ground terminal GND through the second connection line 20, and the gate terminals G of the plurality of transistors Tr may be connected to the first resistor R1 and the second resistor R2 through the third connection line 30. For reference, in Figure 4 , the first connection line 10 , the second connection line 20 , and the third connection line 30 conceptually illustrate electrical connections between elements.

[0063] Figure 5 is a plan view of an ESD protection circuit according to another embodiment of the present disclosure.

[0064] like Figure 5 As shown, an ESD protection circuit according to another embodiment of the present disclosure may include multiple transistors Tr, multiple external resistors R1 and R2, a first connection line 10, a second connection line 20, multiple third connection lines 31 and 32, multiple fourth connection lines 41 and 42, and a ground line 50.

[0065] The plurality of transistors Tr may be arranged in a plurality of rows. Each of the plurality of transistors Tr may include a gate terminal G, a drain terminal D, and a source terminal S extending in one direction (eg, a vertical direction). Two adjacent transistors Tr may share the drain terminal D or the source terminal S.

[0066] One end portion (eg, an upper end portion) of each of the plurality of gate terminals G may be connected to the first resistor R1 through a third connection line 31 on one side (eg, an upper side).

[0067] The third connection line 31 on the upper side may include a first connection portion 31a and a second connection portion 31b, which extend in a direction different from the extending direction of each of the gate terminal G, the drain terminal D, and the source terminal S (e.g., a horizontal direction). The first connection portion 31a may be connected to each of the plurality of gate terminals G via a plurality of contact portions x. The second connection portion 31b may connect the first connection portion 31a to the first resistor R1. Therefore, one end of the second connection portion 31b may be connected to the first connection portion 31a via the contact portion x, and the other end of the second connection portion 31b may be connected to the first resistor R1 via the contact portion x.

[0068] The first resistor R1 may include a first electrode E1, a second electrode E2, and a resistance component R. The first electrode E1 and the second electrode E2 may include a metal material, and the resistance component R may include a material having high resistance, such as polysilicon.

[0069] The first electrode E1 may be connected to one end of the resistance component R, and the second electrode E2 may be connected to the other end of the resistance component R. The resistance component R may extend in the same vertical direction as the extension direction of each of the gate terminal G, the drain terminal D, and the source terminal S. Therefore, the first electrode E1 may be connected to the upper end of the resistance component R, and the second electrode E2 may be connected to the lower end of the resistance component R. The first resistor R1 may include a plurality of first electrodes E1, a plurality of second electrodes E2, and a plurality of resistance components R, and thus, may be designed to have an appropriate resistance value.

[0070] The first electrode E1 of the first resistor R1 may be connected to the second connection portion 31 b of the third connection line 31 on the upper side through the contact portion x, and the second electrode E2 of the first resistor R1 may be connected to the fourth connection line 41 on one side through the contact portion x.

[0071] The fourth connection line 41 on one side may connect the first resistor R1 to the ground line 50. Therefore, one end of the fourth connection line 41 on one side may be connected to the second electrode E2 of the first resistor R1 through the contact portion x, and the other end of the fourth connection line 41 on one side may be connected to the ground line 50 through the contact portion x.

[0072] The other end portion (eg, lower end portion) of each of the plurality of gate terminals G may be connected to the second resistor R2 through a third connection line 32 on the other side (eg, lower side).

[0073] The third connection line 32 on the lower side may include a first connection portion 32a and a second connection portion 32b, which extend in a direction different from the extending direction of each of the gate terminal G, the drain terminal D, and the source terminal S (e.g., a horizontal direction). The first connection portion 31a may be connected to each of the plurality of gate terminals G via a plurality of contact portions x. The second connection portion 32b may connect the first connection portion 32a to the second resistor R2. Thus, one end of the second connection portion 32b may be connected to the first connection portion 32a via the contact portion x, and the other end of the second connection portion 32b may be connected to the second resistor R2 via the contact portion x.

[0074] Similar to the first resistor R1 described above, the second resistor R2 may include a first electrode E1, a second electrode E2, and a resistance component R, and the resistance component R may extend in the same vertical direction as the extension direction of each of the gate terminal G, the drain terminal D, and the source terminal S. However, the first electrode E1 of the second resistor R2 may be connected to the lower end of the resistance component R, and the second electrode E2 of the second resistor R2 may be connected to the upper end of the resistance component R. Similar to the first resistor R1, the second resistor R2 may also include a plurality of first electrodes E1, a plurality of second electrodes E2, and a plurality of resistance components R.

[0075] The first electrode E1 of the second resistor R2 may be connected to the second connection portion 32 b of the third connection line 32 on the lower side through the contact portion x, and the second electrode E2 of the second resistor R2 may be connected to the fourth connection line 42 on the other side through the contact portion x.

[0076] The fourth connection line 42 on the other side can connect the second resistor R2 to the ground line 50. Therefore, one end of the fourth connection line 42 on the other side can be connected to the second electrode E2 of the second resistor R2 through the contact portion x, and the other end of the fourth connection line 42 on the other side can be connected to the ground line 50 through the contact portion x.

[0077] The first connection line 10 may include a plurality of first connection portions 10a and a second connection portion 10b connecting the plurality of first connection portions 10a. The plurality of first connection portions 10a may be arranged to extend in the same direction as the plurality of drain terminals D and overlap with the plurality of drain terminals D. Furthermore, the plurality of first connection portions 10a may be connected to the plurality of drain terminals D, respectively, via contact portions x. The second connection portion 10b may connect the upper ends of the plurality of first connection portions 10a. Although not shown, the second connection portion 10b of the first connection line 10 may be connected to an I / O pad.

[0078] The first connection line 10 may intersect the first connection portion 31a of the third connection line 31 and the ground line 50 on one side. Therefore, in order to prevent a short circuit, the first connection line 10 is provided on a different layer from the first connection portion 31a of the third connection line 31 and the ground line 50 on one side. Specifically, the first connection line 10 may be provided on a layer higher than the first connection portion 31a of the third connection line 31 and the ground line 50 on one side. The first connection line 10 may be provided on the same layer as the second connection portion 31b of the third connection line 31 on one side. The plurality of first connection portions 10a and second connection portions 10b constituting the first connection line 10 may be formed of the same conductive material and may be provided integrally.

[0079] The second connection line 20 may include a plurality of first connection portions 20 a and a second connection portion 20 b connecting the plurality of first connection portions 20 a. The plurality of first connection portions 20 a may be arranged to extend in the same direction as the plurality of source terminals S and overlap with the plurality of source terminals S. Furthermore, the plurality of first connection portions 20 a may be connected to the plurality of source terminals S, respectively, via contact portions x. The second connection portion 20 b may connect the lower ends of the plurality of first connection portions 20 a.

[0080] The second connection line 20 may intersect with the first connection portion 32a of the third connection line 32 on the other side. Therefore, to prevent a short circuit, the second connection line 20 and the first connection portion 32a of the third connection line 32 on the other side may be arranged on different layers. Specifically, the second connection line 20 may be arranged on a layer higher than the first connection portion 32a of the third connection line 32 on the other side. The second connection line 20 may be arranged on the same layer as the second connection portion 32b of the third connection line 32 on the other side. The multiple first connection portions 20a and second connection portions 20b constituting the second connection line 20 may be formed of the same conductive material and may be arranged as a whole. The second connection line 20 and the first connection line 10 may be formed of the same material on the same layer.

[0081] In addition, the second connection line 20 may be connected to the ground line 50 through the contact portion x. Although an example is shown in which the plurality of first connection portions 20 a of the second connection line 20 are connected to the ground line 50 through the plurality of contact portions x, the second connection portion 20 b of the second connection line 20 may be connected to the ground line 50 through the plurality of contact portions x.

[0082] As described above, the third connection lines 31 and 32 may include a third connection line 31 on one side and a third connection line 32 on the other side. The first connection portion 31a of the third connection line 31 on one side and the first connection portion 32a of the third connection line 32 on the other side may be formed on the same layer and made of the same material. In addition, the second connection portion 31b of the third connection line 31 on one side and the second connection portion 32b of the third connection line 32 on the other side may be formed on the same layer and made of the same material. The second connection portion 31b of the third connection line 31 on one side may obliquely face the second connection portion 32b of the third connection line 32 on the other side.

[0083] As described above, the fourth connection lines 41 and 42 may include a fourth connection line 41 on one side and a fourth connection line 42 on the other side. The fourth connection line 41 on one side and the fourth connection line 42 on the other side may be formed of the same material on the same layer. The fourth connection line 41 on one side may face the fourth connection line 42 on the other side at an angle.

[0084] The fourth connection lines 41 and 42 , the first connection line 10 , the second connection line 20 , and the second connection portions 31 b and 32 b of the third connection lines 31 and 32 may be formed of the same material on the same layer.

[0085] The ground line 50 may be provided outside each of the plurality of transistors Tr, and more specifically, may be provided to surround the plurality of transistors Tr. For example, the ground line 50 may be formed into a quadrilateral frame structure. In addition, the ground line 50 may be provided outside each of the first resistor R1, the second resistor R2, and the third connection lines 31 and 32.

[0086] The ground line 50 and the first connection portions 31 a and 32 a of the third connection lines 31 and 32 may be formed of the same material on the same layer.

[0087] Figure 6 is a cross-sectional view of an ESD protection circuit according to another embodiment of the present disclosure, and is taken along Figure 5 A cross-sectional view taken along line I-II.

[0088] like Figure 6 As shown, a first insulating layer 210 may be formed on a substrate 100, and a resistance component R of a first resistor R1 and a gate terminal G of a transistor may be formed separately from each other on the first insulating layer 210. The resistance component R and the gate terminal G may be formed of the same material on the same layer and, for example, may include a semiconductor material such as polysilicon.

[0089] A second insulating layer 220 may be formed on the resistance component R and the gate terminal G, and the ground line 50 , the first and second electrodes E1 and E2 of the first resistor R1 , and the first connection portion 31 a of the third connection line 31 on one side may be formed separately from each other on the second insulating layer 220 .

[0090] The ground line 50 , the first and second electrodes E1 and E2 of the first resistor R1 , and the first connection portion 31 a of the third connection line 31 on one side may be formed of the same conductive material on the same layer.

[0091] The first electrode E1 and the second electrode E2 of the first resistor R1 may be connected to one end and the other end of the resistance component R, respectively, through contact holes provided in the second insulating layer 220, but are not limited thereto, and may be connected thereto through interconnections filled in the contact holes. The first connection portion 31a of the third connection line 31 on one side may be connected to one end of the gate terminal G through a contact hole provided in the second insulating layer 220, but are not limited thereto, and may be connected thereto through an interconnection filled in the contact hole.

[0092] The third insulating layer 230 can be formed on the ground line 50, the first electrode E1 and the second electrode E2 of the first resistor R1, and the first connection portion 31a of the third connection line 31 on one side, and the fourth connection line 41 on one side, the second connection portion 31b of the third connection line 31 on one side, and the first connection portion 10a of the first connection line 10 can be formed separately from each other on the third insulating layer 230.

[0093] The fourth connection line 41 on one side, the second connection portion 31 b of the third connection line 31 on one side, and the first connection portion 10 a of the first connection line may be formed of the same conductive material on the same layer.

[0094] One end of the fourth connection line 41 on one side may be connected to the ground line 50 through an interconnection provided in the third insulating layer 230, and the other end of the fourth connection line 41 on one side may be connected to the second electrode E2 of the first resistor R1 through an interconnection provided in the third insulating layer 230. Alternatively, the fourth connection line 41 on one side may be directly connected to the ground line 50 and the second electrode E2 of the first resistor R1 through a contact hole provided in the third insulating layer 230.

[0095] One end of the second connection portion 31b of the third connection line 31 on one side may be connected to the first electrode E1 of the first resistor R1 through an interconnection provided in the third insulating layer 230, and the other end of the second connection portion 31b of the third connection line 31 on one side may be connected to the first connection portion 31a of the third connection line 31 on one side through an interconnection provided in the third insulating layer 230. Alternatively, the second connection portion 31b of the third connection line 31 on one side may be directly connected to the first electrode E1 of the first resistor R1 and the first connection portion 31a of the third connection line 31 on one side through a contact hole provided in the third insulating layer 230.

[0096] In the above, Figure 6 Shows the Figure 5 The cross section is taken along a line intersecting each of the ground line 50, the fourth connection line 41 on one side, the first resistor R1, the third connection line 31 on one side, the first connection line 10, and the gate terminal G shown in FIG. Figure 5 The cross section taken by the line intersecting each of the ground line 50, the fourth connection line 42 on the other side, the second resistor R2, the third connection line 32 on the other side, the second connection line 20 and the gate terminal G shown may have the same value as Figure 6 Same structure.

[0097] According to one embodiment of the present disclosure, since the first resistor is set to be electrically connected to one end of each of the gate terminals of a plurality of transistors, and the second resistor is set to be electrically connected to the other end of each of the gate terminals of the plurality of transistors, position-based resistance deviation can be reduced, thereby enhancing the uniformity of the discharge current.

[0098] The above-mentioned features, structures and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. In addition, those skilled in the art can realize the features, structures and effects described in at least one embodiment of the present disclosure by combining or modifying other embodiments. Therefore, the contents associated with the combination and modification should be interpreted as being within the scope of the present disclosure.

[0099] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

[0100] CROSS-REFERENCE TO RELATED APPLICATIONS

[0101] This application claims the benefit of Korean Patent Application No. 10-2019-0100332, filed on August 16, 2019, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. An electrostatic discharge (ESD) protection circuit, the ESD protection circuit comprising: a plurality of transistors, each transistor including a gate terminal, a drain terminal, and a source terminal; a first connection line connected to the drain terminals of the plurality of transistors; a second connection line connected to the source terminals of the plurality of transistors; a third connection line connected to the gate terminals of the plurality of transistors; an external resistor connected to the third connection line; as well as A ground terminal connected to the external resistor, wherein the external resistor includes a first resistor and a second resistor connected in parallel to each other, The third connection line includes a third connection line on one side connected to one end of each of the gate terminals and a third connection line on the other side connected to the other end of each of the gate terminals, and The first resistor is connected to the third connection line on the one side, and the second resistor is connected to the third connection line on the other side.

2. The ESD protection circuit according to claim 1, wherein: The first resistor is provided outside one side of each of the plurality of transistors, and the second resistor is provided outside the other side of each of the plurality of transistors, and The first resistor and the second resistor extend in the same direction as an extending direction of the gate terminal.

3. The ESD protection circuit according to claim 1, wherein: The third connection line on the one side includes a first connection portion connected to the one end of each of the gate terminals and a second connection portion connecting the first connection portion to one end of the first resistor, and The third connection line on the other side includes a first connection portion and a second connection portion, the first connection portion of the third connection line on the other side is connected to the other end of each of the gate terminals, and the second connection portion of the third connection line on the other side connects the first connection portion of the third connection line on the other side to one end of the second resistor.

4. The ESD protection circuit according to claim 3, wherein: The first connection portion of the third connection line on the one side intersects with the first connection line, and The first connection portion of the third connection line on the other side intersects with the second connection line.

5. The ESD protection circuit according to claim 3, wherein: The second connection portion of the third connection line on the one side, the second connection portion of the third connection line on the other side, the first connection line, and the second connection line are disposed on the same layer and include the same conductive material.

6. The ESD protection circuit according to claim 1 , further comprising: a ground line, the ground line being arranged outside the plurality of transistors; a fourth connecting line on one side, the fourth connecting line on the one side connecting the ground line to the first resistor; as well as The fourth connecting line on the other side connects the ground line to the second resistor.

7. The ESD protection circuit according to claim 6, wherein: The fourth connection line on the one side, the fourth connection line on the other side, the first connection line, and the second connection line are disposed on the same layer and include the same conductive material.

8. The ESD protection circuit according to claim 1, wherein: Each of the first resistor and the second resistor includes a resistance component, a first electrode connected to one end of the resistance component, and a second electrode connected to the other end of the resistance component, and The resistance component is provided on the same layer as the gate terminal and includes the same material as that of the gate terminal.

9. The ESD protection circuit according to claim 1, wherein: The first connection line includes a plurality of first connection portions connected to the drain terminal to extend in the same direction as an extending direction of the drain terminal, and a second connection portion connecting the plurality of first connection portions.

10. The ESD protection circuit according to claim 1, wherein: The plurality of transistors include two adjacent transistors sharing the source terminal or the drain terminal.

11. An electrostatic discharge (ESD) protection circuit, the ESD protection circuit comprising: a plurality of transistors, each transistor including a gate terminal disposed on the substrate; an external resistor including a first resistor and a second resistor connected in parallel to each other on the substrate; a connecting line connecting the external resistor to the gate terminal; a ground line connected to the external resistor; a first insulating layer disposed in a bottom surface of the gate terminal; a second insulating layer disposed in a top surface of the gate terminal; as well as a third insulating layer provided in a top surface of the ground line, wherein the connection line includes a first connection portion connected to the gate terminal and a second connection portion connecting the first connection portion to the first resistor, The gate terminal is connected to the ground line through the first resistor and the second resistor.

12. The ESD protection circuit according to claim 11, wherein: The first connection portion is provided in a top surface of the second insulating layer, and the second connection portion is provided in a top surface of the third insulating layer, and The first connection portion and the ground line are provided on the same layer and include the same material.

13. The ESD protection circuit according to claim 11, wherein: The first resistor includes a resistance component provided on the same layer as the gate terminal, a first electrode connected to one end of the resistance component and provided on the same layer as the ground line, and a second electrode connected to the other end of the resistance component and provided on the same layer as the ground line, and The first electrode is connected to the second connection portion. 14 . The ESD protection circuit according to claim 11 , further comprising an additional connection line provided on the third insulating layer to connect the ground line to the first resistor.

15. The ESD protection circuit according to claim 14, wherein: The first resistor includes a resistance component provided on the same layer as the gate terminal, a first electrode connected to one end of the resistance component and provided on the same layer as the ground line, and a second electrode connected to the other end of the resistance component and provided on the same layer as the ground line, and The second electrode is connected to the additional connection line.

16. The ESD protection circuit according to claim 14, further comprising another additional connection line disposed on the third insulating layer and connected to drain terminals of the plurality of transistors, in, The additional connection line and the further additional connection line are provided on the same layer and include the same material.

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