An adaptive chip power switch network circuit with fast wake-up capability

Abstract

This invention discloses an adaptive chip power switch network circuit with fast wake-up capability, comprising: N parallel cascaded chains; when all cascaded chains are turned on and the signal is transmitted to the last stage of each cascaded chain, the sleep wake-up is completed; an embedded voltage sensor for real-time sampling of the power network VDD; and a comparator for comparing the sampled value output by the embedded voltage sensor with a preset IR drop threshold, thereby enabling real-time observation of the IR drop of VDD, reducing the latency of the power switch network, and adaptively maximizing the wake-up response speed.

Description

Technical Field

[0001] This invention belongs to the field of chip design, and in particular relates to an adaptive chip power switch network circuit that can be quickly woken up. Background Technology

[0002] Existing power switching network technology is used for wake-up control of the internal power supply of a chip. The specific structure is as follows: Figure 1 As shown:

[0003] Among them, VDD is a normally open power network that is never turned off, while Virtual VDD is a power network that can be turned off; the PMOS transistor acts as a power switch, connecting VDD and Virtual VDD to realize the switching control of the Virtual VDD power network.

[0004] The cascading of delay buffers forms a delay buffer daisy chain. The wake-up signal (WAKEUP_N) is transmitted sequentially along the delay buffer daisy chain to each PMOS power switch. Each delay buffer delays the wake-up signal's arrival time at that PMOS switch. The PMOS power switches on the daisy chain turn on one by one with a certain time delay, avoiding the problem of excessive in-rush current caused by all switches turning on simultaneously. In-rush current refers to the peak current flowing into the switching power supply at the moment of power-on. The sequential turn-on of the PMOS power switches avoids excessive IR voltage drop on VDD during wake-up, thus ensuring the integrity of the data stored on VDD during wake-up.

[0005] Existing power switching networks suffer from significant latency, making them unsuitable for applications requiring rapid wake-up. The time interval between the activation of the wake-up signal (WAKEUP_N transitioning from '1' to '0') and the activation of the response signal (ACK_N transitioning from '1' to '0') is the time required for chip wake-up, which is determined by the total delay of the cascaded chain. For large-scale integrated circuit (SoC) chips, the power-down region typically contains a large number of transistors, necessitating a large number of PMOS power switches. Therefore, existing power switching network structures require relatively long wake-up times. Summary of the Invention

[0006] For the application scenario of a fast wake-up power switch network, the present invention provides an adaptive chip power switch network circuit that can be quickly awakened, including:

[0007] N parallel cascaded chains; when all cascaded chains are turned on and transmitted to the last stage of each cascaded chain, the sleep wake-up is completed;

[0008] An embedded voltage sensor for real-time sampling of the power network VDD;

[0009] A comparator for comparing the sampled value output by the embedded voltage sensor with a preset IR voltage drop threshold. When the sampled value output by the embedded voltage sensor is less than the IR voltage drop threshold, the output signal of the comparator becomes valid, realizing real-time observation of the IR voltage drop of VDD.

[0010] The N parallel cascaded chains include: a first cascaded chain and N - 1 cascaded chains;

[0011] Except for the first cascaded chain, each of the N - 1 cascaded chains includes an OR gate, which ORs the input signal of each of the N - 1 cascaded chains with the output signal of the comparator;

[0012] Except for the first cascaded chain, each of the N - 1 cascaded chains includes an AND gate, which ANDs the output signal of the OR gate of each of the N - 1 cascaded chains with the output signal of the previous stage cascaded chain.

[0013] For the first cascaded chain, the wake-up signal WAKEUP_N is directly driven to the input control end of the first cascaded chain;

[0014] The input wake-up signal WAKEUP_N of the entire power switch network circuit is the input signal of the N cascaded chains;

[0015] The wake-up response signal ACK_N is obtained by ORing the outputs of the N cascaded chains.

[0016] The value N = total number of PMOS in the circuit / number of PMOS in each cascaded chain,

[0017] where the total number of PMOS required is determined through power integrity and reliability analysis based on the number of transistors in the power-down area;

[0018] The maximum delay of the system wake-up response required by the function is T1, and the delay of each daisy chain is T2, T2 < T1; the number of PMOS in each daisy chain needs to consider meeting the condition of T2 < T1 and is determined in combination with the specific chip backend layout design.

[0019] Compared with the closest existing technology, the technical solution provided by the present invention has the following beneficial effects:

[0020] 1. This invention proposes an adaptive chip power switch network circuit that can be quickly woken up. Compared with the wake-up circuit in the prior art, it can minimize the delay of the power switch network while ensuring effective control of the in-rush current, and adaptively maximize the wake-up response speed, making it suitable for high-speed wake-up application scenarios.

[0021] 2. The power switch network circuit in this invention can be quickly woken up by adding an embedded voltage sensor and comparator. By observing the IR voltage drop of VDD in real time and adjusting the circuit, the power switch network has a self-protection function, ensuring the reliability of the function.

[0022] For the foregoing and related purposes, one or more embodiments include features that will be described in detail below and particularly pointed out in the claims. The following description and accompanying drawings detail certain exemplary aspects and indicate only a few of the various ways in which the principles of the various embodiments can be utilized. Other benefits and novel features will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents.

[0023] Instruction manual illustrations

[0024] Figure 1 This is a diagram of the wake-up control circuit of the chip power switch network in the prior art provided by the present invention;

[0025] Figure 2 This is a circuit diagram of an adaptive chip power switch network that can be quickly woken up, provided by an embodiment of the present invention. Detailed Implementation

[0026] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments. The scope of embodiments of the invention includes the entire scope of the claims and all available equivalents thereof. In this document, these embodiments of the invention may be referred to individually or collectively with the term "invention," which is merely for convenience and is not intended to automatically limit the scope of the application to any single invention or inventive concept if more than one invention is disclosed.

[0027] The PMOS transistor acts as a power switch, connecting the normally open power network VDD and the turn-off power network VirtualVDD, thereby enabling switching control of the VirtualVDD power network. When the gate (G) terminal of the PMOS transistor is 1, the PMOS transistor is turned off; when its gate (G) terminal is 0, the PMOS transistor is turned on.

[0028] The wake-up signal WAKEUP_N, '0' is valid, indicating wake-up. WAKEUP_N is transmitted step by step along the delay buffer daisy chain to each PMOS power switch.

[0029] This invention provides an adaptive chip power switch network circuit with fast wake-up capability, comprising:

[0030] N parallel cascaded chains; the N parallel cascaded chains include: the first cascaded chain and N-1 cascaded chains;

[0031] An embedded voltage sensor is used to sample VDD in real time.

[0032] The comparator is used to compare the sampled value of the output of the embedded voltage sensor with a preset IR drop threshold to realize real-time observation of the IR drop of VDD; when the sampled value of the output of the embedded voltage sensor is less than the IR drop threshold, the comparator output signal becomes valid.

[0033] Furthermore, in addition to the first cascade chain, each of the N-1 cascade chains includes an OR gate that ORs the input signal of each of the N-1 cascade chains with the output signal of the comparator.

[0034] Except for the first cascade chain, each of the N-1 cascade chains includes an AND gate, which ANDs the output signal of each cascade chain OR gate with the output signal of the previous cascade chain.

[0035] The wake-up signal (WAKEUP_N) directly drives the input control terminal of the first cascade chain;

[0036] Connect an OR gate to the output of N cascaded chains, and the wake-up response signal (ACK_N) is obtained by ORing the outputs of the N cascaded chains.

[0037] Once all cascading chains are activated and the signal is passed to the last stage of each cascading chain, the sleep / awakening process is complete.

[0038] N = Total number of PMOS required / Number of PMOS per daisy chain;

[0039] Among them, the total number of PMOSs required is determined through power integrity and reliability analysis based on the number scale of transistors included in the power-down area;

[0040] The maximum delay of the system wake-up response required by the function is T1, and the delay of each daisy chain is T2, where T2 < T1; the number of PMOSs in each daisy chain needs to consider the condition of T2 < T1 and be determined in combination with the specific chip backend layout design.

[0041] Embodiment

[0042] This embodiment provides a self-adaptive chip power switch network circuit that can be quickly awakened. As Figure 2 shown, taking N = 4 as an example, it includes:

[0043] 4 parallel cascaded chains of daisy chain; the wake-up signal (WAKEUP_N) is directly driven to the input control terminal of the first daisy chain;

[0044] Each of the second daisy chain, the third daisy chain, and the fourth daisy chain includes an OR gate to OR the input signals of the second, third, and fourth daisy chains with the output signal of the comparator;

[0045] The second, third, and fourth daisy chains respectively include an AND gate to AND the output signal of the OR gate of each daisy chain with the output signal of the previous cascaded chain, and the output of the AND gate of each daisy chain is connected to the PMOS transistor of the corresponding daisy chain.

[0046] The embedded voltage sensor voltage sensor is input-connected to the VDD power rail;

[0047] The output of the embedded voltage sensor is connected to the input of the comparator, and the output of the comparator comparator is connected to the input of the OR gate of the second, third, and fourth cascaded chains;

[0048] The comparator compares the output VDD Sample Value of the voltage sensor with the preset IR voltage drop threshold IRDrop Margin; when the chip wakes up, the wake-up signal WAKEUP_N jumps to '0', enabling each daisy chain and starting to transmit along the 4 daisy chains. When VDD Sample Value is greater than the IR voltage drop threshold IR Drop Margin, the output signal is 0;

[0049] When the VDD Sample Value is less than the VDD IR Drop Margin, the comparator output signal VDD Shutoff becomes valid (jumps to '1');

[0050] During the daisy chain startup process, if the current between VDD and Virtual VDD is too large, it will cause a large IR drop in VDD; by continuously sampling VDD with a voltage sensor, the IR drop of VDD can be observed in real time.

[0051] When the IR drop of VDD approaches the IR drop threshold IR drop margin, the comparator's output signal VDDShutoff jumps to 1, and the comparator's output effectively shields the wake-up enable signal through the OR gate, thereby shutting down the parallel daisychain.

[0052] In this scenario, the four daisy chains are automatically restored to a single series chain via AND gates; on this series chain, the power switches that the wake-up signal did not reach are automatically turned off, the current decreases, and VDD automatically returns to normal.

[0053] When VDD returns to normal, the comparator output signal VDD Shutoff returns to 0, the comparator output signal becomes invalid, the OR gate is opened, and the daisy chain automatically returns to parallel acceleration state.

[0054] The wake-up response signal ACK_N is connected to the last stage of the Delay Buffer daisy chain. When it is '0', ACK_N jumps to '0' when all chains are turned on and the wake-up has been passed to the last stage of each chain, indicating that WAKEUP_N has been passed along the daisy chain to the last stage; at this time, all PMOS switches are turned on, and the wake-up operation is complete.

[0055] Thus, based on the improved power switch network, the present invention divides a single serial daisy chain in the prior art into N parallel daisy chains, which can adaptively and safely achieve the fastest chip wake-up response.

[0056] Unless otherwise specifically stated, terms such as processing, calculation, operation, determination, display, etc., may refer to the actions and / or processes of one or more processing or computing systems or similar devices that represent the manipulation and conversion of data representing physical (e.g., electronic) quantities within the registers or memory of the processing system into other data similarly representing physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0057] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0058] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features in a single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of the invention.

[0059] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments herein can be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0060] The steps of the methods or algorithms described in conjunction with the embodiments herein can be directly embodied in hardware, software modules executed by a processor, or a combination thereof. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor and storage medium can exist as discrete components in the user terminal.

[0061] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. This software code can be stored in memory units and executed by a processor. The memory units can be implemented within the processor or outside the processor; in the latter case, they are communicatively coupled to the processor via various means, as is well known in the art.

[0062] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. An adaptive chip power switch network circuit with fast wake-up capability, characterized in that, include: N parallel cascaded chains; when all cascaded chains are activated and the process is passed to the last stage of each cascaded chain, the sleep / wake cycle is complete. An embedded voltage sensor for real-time sampling of the power network VDD; A comparator is used to compare the sampled value of the output of the embedded voltage sensor with a preset IR drop threshold, so as to realize real-time observation of the IR drop of VDD; Specifically, for the first cascade chain, the wake-up signal WAKEUP_N directly drives the input control terminal of the first cascade chain; The input wake-up signal WAKEUP_N of the entire power switch network circuit is the input signal of the N cascaded chains; The wake-up response signal ACK_N is obtained by ORing the outputs of N cascaded chains.

2. The chip power switch network circuit as described in claim 1, characterized in that, The N parallel cascaded chains include: the first cascaded chain and N-1 cascaded chains; Except for the first cascade chain, each of the N-1 cascade chains includes an OR gate that ORs the input signal of each of the N-1 cascade chains with the output signal of the comparator.

3. The chip power switch network circuit as described in claim 1, characterized in that, Except for the first cascade chain, each of the N-1 cascade chains includes an AND gate, which ANDs the output signal of each of the N-1 cascade chains with the output signal of the preceding cascade chain.

4. The chip power switch network circuit as described in claim 1, characterized in that, The value N = total number of PMOS in the circuit / number of PMOS in each cascaded chain.

5. The chip power switch network circuit as described in claim 1, characterized in that, When the sampled value of the output of the embedded voltage sensor is less than the IR drop threshold, the comparator output signal becomes valid.

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