System, computing device and method using multiplier-accumulator circuit

Abstract

A system, a computing device, and a method using a multiplier-accumulator circuit are provided. A multiplier-accumulator (MAC) system includes a MAC circuit, the MAC circuit including: a plurality of resistors having respective resistances; a capacitor connected to the plurality of resistors, the capacitor charged with electric charge in response to a plurality of input signals; and a time-to-digital converter (TDC) configured to convert information of a charging time of the capacitor due to the electric charge into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0109173 filed on September 3, 2019, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0046244 filed on April 16, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference for all purposes. Technical Field

[0002] The following description relates to the technology of multiplier-accumulator (MAC) circuits. Background Art

[0003] Vector-matrix multiplication operations (also called multiply and accumulate (MAC) operations) affect the performance of devices in various fields. For example, MAC operations may be performed in machine learning and authentication operations of devices including a neural network of multiple layers. The input signal may be considered to form an input vector and may be data about an image, a byte stream, or other data set. The input signal may be multiplied by each weight, an output vector may be obtained from the result of the accumulation operation for the multiplication, and the output vector may be provided as an input vector for a subsequent layer of the neural network. Since the MAC operation as above is repeated for multiple layers, the neural network processing performance is mainly determined by the performance of the MAC operation. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In one general aspect, a multiplier-accumulator (MAC) system includes a MAC circuit, the MAC circuit comprising: a plurality of resistors having respective resistances; capacitors connected to the plurality of resistors, the capacitors being charged with charges in response to a plurality of input signals; and a time-to-digital converter (TDC) configured to convert information of charging times of the capacitors due to the charges into digital values, wherein the digital values ​​are accumulation results of the MAC circuit.

[0006] In one general aspect, a MAC computing device includes one or more MAC circuits, the one or more MAC circuits respectively including: a memory array including a plurality of input lines respectively intersecting a plurality of output lines, wherein each of the output lines includes a respective capacitor, the capacitor being configured to be charged or discharged in response to input signals being respectively provided to two or more of the plurality of input lines; and a time-to-digital converter (TDC) including a single global counter, the single global counter being configured to generate respective output values ​​indicating a time that has elapsed from a start time, the TDC being configured to determine a selection output from the respective output values ​​at a time corresponding to a respective charging or discharging time of the respective capacitor for charging or discharging, and converting each of the determined selection outputs into respective digital value results for the output lines of the MAC circuit.

[0007] In one general aspect, a computation method performed by a multiplier-accumulator (MAC) circuit includes: receiving an input signal; charging a capacitor connected to a plurality of resistors with an electric charge according to corresponding voltages applied to the plurality of resistors in response to the input signal; and converting a charging time of the capacitor into a digital value according to the input signal, the plurality of resistors, and the capacitor.

[0008] In one general aspect, a multiplier-accumulator (MAC) circuit includes: a plurality of resistors to which a voltage is applied in response to an input signal; a capacitor connected to the plurality of resistors and configured to be charged with an electric charge in response to the application of the voltage; and a time-to-digital converter (TDC) configured to convert a charging time of the capacitor into a digital value based on a combination of the input signal, the plurality of resistors, and the capacitor.

[0009] The MAC circuit may further include: a plurality of output lines, each including the plurality of resistors and capacitors, wherein the respective capacitors of the output lines may have the same capacitance.

[0010] The MAC circuit may further include: a comparator connected to the plurality of resistors and capacitors and configured to: output a comparison result obtained by comparing a target voltage corresponding to the amount of charge in the capacitor with a reference voltage, wherein the TDC may be configured to: convert time information indicating a charging time into a digital value based on the comparison result of the comparator.

[0011] The time information may include information indicating a time at which the comparison result is output.

[0012] The comparator may be configured to output a comparison result in response to the target voltage exceeding the reference voltage as the capacitor is charged according to the voltage of the input signal.

[0013] The input signal may include a series of input voltage signals corresponding to input data and to be input to a plurality of input lines.

[0014] The plurality of resistors may be connected in parallel to each other, and one end of each of the plurality of resistors may be configured to receive a voltage through a switch, and the other end of each of the plurality of resistors may be connected to a capacitor and a comparator.

[0015] One or more resistors to which a voltage is applied by an input signal among the plurality of resistors may form a composite resistance, and the TDC may be configured to convert a charging time corresponding to a combination of the composite resistance and a capacitance of the capacitor into a digital value.

[0016] The TDC may be configured to output a charging time corresponding to time information regarding a time elapsed from a start time when an input signal is received to an output time when a comparison result is output, as a digital value.

[0017] The TDC may include: a single global counter configured to output a digital value indicating a time elapsed from a start time; and a referencer configured to refer to the digital value output by the single global counter at a time of outputting a comparison result.

[0018] The plurality of output lines may each include a plurality of resistors, capacitors and comparators, a single global counter may be connected to the comparators of the plurality of output lines, the reference device may include a plurality of holding circuits, the plurality of holding circuits being configured to reference comparison results of the comparators of the plurality of output lines, and each of the plurality of holding circuits may be configured to reference a moment when the comparison result is output from a comparator included in a corresponding output line among the plurality of output lines.

[0019] Each of the plurality of holding circuits may be configured as a flip-flop circuit.

[0020] The plurality of resistors may have resistance values ​​corresponding to connection weights of edges connecting a plurality of nodes in a neural network including a layer including the plurality of nodes.

[0021] The MAC circuit may further include: an outputter configured to output a value mapped to the digital value generated by the TDC as an output value of each output line.

[0022] The MAC circuit may be configured to discharge the capacitor to a threshold voltage or less after all output lines output digital output values ​​for input signals until a subsequent input signal is received.

[0023] The MAC circuit may be configured to reset the count of the single global counter in response to the start signal.

[0024] The MAC circuit may be configured to apply an input signal to a resistor corresponding to an input line indicated by the input data among the plurality of resistors in response to a start signal, and the TDC may be configured to start counting an elapsed time in response to the start signal.

[0025] The MAC circuit may further include a switch connected to one of the plurality of resistors and configured to transmit an input voltage signal according to the input data to the connected resistor upon receiving the start signal in response to the input data indicating an input line including the connected resistor.

[0026] The MAC circuit may further include: a switch connected to one end of each of the plurality of resistors, wherein the switch may be configured to: transmit a power supply voltage to a corresponding resistor in response to an input voltage signal being a closing signal, and disconnect one end of the corresponding resistor in response to the input voltage signal being a disconnecting signal, wherein the input voltage signal is received from an input line provided with the corresponding resistor.

[0027] The MAC circuit may further include a switch connected to one of the plurality of resistors and configured to apply a power supply voltage to the connected resistor in response to an input voltage signal during a charging period.

[0028] The switch may be configured to apply a reset voltage to the connected resistor in response to an input voltage signal during a discharge period, and the MAC circuit may further include a comparator configured to output a comparison result in response to a target voltage exceeding a first reference voltage when the capacitor is charged with charge by the power supply voltage, and to output a comparison result in response to the target voltage being less than a second reference voltage when the charge is released from the capacitor by the reset voltage, wherein the target voltage corresponds to the charge in the capacitor.

[0029] In another general aspect, a computing method performed by a MAC circuit includes: receiving an input signal; charging a capacitor connected to a plurality of resistors with an electric charge according to a voltage applied to the plurality of resistors in response to the input signal; and converting a charging time of the capacitor into a digital value according to a combination of the input signal, the plurality of resistors, and the capacitor.

[0030] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 An example of a multiplier-accumulator (MAC) circuit is shown.

[0032] Figure 2 An example of the mapping relationship between the composite resistance and the operation result in the MAC circuit is shown.

[0033] Figure 3 An example of a MAC circuit including a plurality of input lines and a plurality of output lines is shown.

[0034] Figure 4 An example of a time-to-digital converter (TDC) is shown.

[0035] Figure 5 An example of a reference for a TDC is shown.

[0036] Figure 6 An example of the switching operation of the TDC is shown.

[0037] Figure 7 An example of a calculation method using a MAC circuit of an example calculation device is shown.

[0038] Figure 8 An example of a computing method of an example computing device is shown.

[0039] Fig. 9 An example of a MAC circuit to which a power supply voltage is applied by switching is shown.

[0040] Figures 10 to 12 Show Fig. 9 An example of a charge period operation and a discharge period operation of a MAC circuit.

[0041] Fig.13 An example of a neural network operation implemented by a MAC circuit of an example computing device is shown.

[0042] Fig.14 An example of a computing device is shown.

[0043] Throughout the drawings and detailed description, unless otherwise described or provided, the same figure reference numerals will be understood to refer to the same elements, features and structures. The drawings may not be to scale, and the relative sizes, proportions and depictions of the elements in the drawings may be exaggerated for clarity, illustration and convenience. DETAILED DESCRIPTION

[0044] Hereinafter, examples will be described in detail with reference to the accompanying drawings. However, various changes and modifications may be made to the examples. Here, the examples are not to be construed as limiting the disclosure. The examples should be understood to include all changes, equivalents, and substitutes within the disclosed concept and technical scope.

[0045] The terms used herein are for the purpose of describing specific examples only and do not limit the examples. Unless the context clearly indicates otherwise, as used herein, the singular form is also intended to include the plural form. It will also be understood that the terms "comprise" and / or "include" when used herein specify the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the examples belong. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0047] When describing examples with reference to the accompanying drawings, the same reference numerals represent the same constituent elements, and repeated descriptions related thereto will be omitted. In the description of the examples, when it is considered that a detailed description of a well-known related structure or function will lead to an obscure interpretation of the present disclosure, such description will be omitted.

[0048] Figure 1 An example of a multiplier-accumulator (MAC) circuit is shown. Figure 2 MAC circuits (eg, Figure 1 An example of the mapping relationship between the composite resistance and the operation result in a MAC circuit).

[0049] The MAC circuit 100 may be a circuit that outputs an accumulated value of a multiplication result. The MAC circuit 100 may include, for example, a plurality of resistors 110, a capacitor C, and a time digital converter (TDC) 140. The MAC circuit 100 may also include a comparator 130 to generate time information to be sent to the TDC 140.

[0050] In response to the input signal, a corresponding voltage may be applied to the plurality of resistors 110. The plurality of resistors 110 may be connected in parallel to each other, and the resistors to which the voltage is applied may form a composite resistor. One end of each of the plurality of resistors 110 may receive a voltage through a switch, and the other end thereof may be connected to a capacitor C (e.g., one or more capacitors) and a comparator 130. An input voltage signal of the input signal may be directly applied to the plurality of resistors 110, or a power supply voltage may be applied to the plurality of resistors 110 according to the input signal.

[0051] A plurality of resistors 110 connected in parallel to each other may form a composite resistor in response to an input signal, and the composite resistance value may correspond to the value of the product accumulation result between the input data and the weight data. For example, among the plurality of resistors 110, the resistor to which voltage is applied may participate in the formation of the composite resistor, and the resistor to which voltage is not applied may be excluded from the formation of the composite resistor. For example, the resistor to which voltage is applied may represent the first resistance value (e.g., 100 kilo-ohms) of the corresponding resistor, and the different resistors to which voltage is not applied may represent a second resistance value (e.g., 10 megohms) that is sufficiently larger than the natural or set resistance value of the corresponding resistor due to one end being open circuited. If the resistor representing the first resistance value and the resistor representing the second resistance value are connected in parallel to form a composite resistor, and the second resistance value is sufficiently larger than the first resistance value, the second resistance value may be substantially ignored in the composite resistance value, or the second resistance value may have little influence on the composite resistance value. Therefore, the resistors involved in forming the composite resistance may correspond to the bitwise multiplication result of the voltage value of the input voltage signal and the resistance value of the resistor, and for example, if the voltage value of the input voltage signal is binary, the composite resistance value may correspond to the sum of the bitwise multiplication results. Figure 1 As shown in , it can be connected to a capacitor, so the time constant of the MAC circuit 100 can be determined by the composite resistance value and the capacitance. Since the charging time of the capacitor is determined by the time constant, the composite resistance value can be inferred from the charging time of the capacitor. Therefore, the sum of the bitwise multiplication results can be inferred from the charging time of the capacitor according to the time constant. An example of the charging time will be described in more detail below in conjunction with the operation of the comparator 130.

[0052] In addition, the composite resistance value is not limited to indicating only the bit-by-bit multiplication result. If the voltage value of the input voltage signal is not binary but indicates multiple states (e.g., multiple bits), the resistors involved in forming the composite resistance may correspond to the multiplication result of the voltage value of the input voltage signal and the resistance value of the resistor, and the composite resistance value may correspond to the sum of the multiplication results.

[0053] For reference, in Figure 1 An example of applying an input voltage signal of an input signal to a resistor in response to a start signal START is described in FIG. The MAC circuit 100 may further include a plurality of switches 101 connected to one end of each of the plurality of resistors 110. For example, the first switch SW 1 Can be connected to the first resistor R 1 One end of the jth switch SW j Can be connected to the jth resistor R j one end, and the mth switch SW m Can be connected to the mth resistor R mHere, m may be an integer greater than or equal to "1", and j may be an integer between "1" and "m" (including "1" and "m"). The other end of the plurality of switches 101 may receive an input voltage signal V 1 To V m For example, the jth switch SW j The other end can receive the jth input voltage signal V j .

[0054] The input signal is a signal corresponding to input data and may include a series of input voltage signals V input to a plurality of input lines. 1 To V m For example, the jth input voltage signal may be switched through the jth switch SW in response to the start signal START. j Applied to the jth resistor R j However, the input voltage signal V 1 To V m It is not always applied to all resistors, and the input voltage signal may be applied to a part of the resistors but not to another part of the resistors according to input data.

[0055] For example, in response to one of the input data indicating an input line including a resistor connected to a corresponding switch, the corresponding switch may send an input voltage signal according to the input data to the resistor connected to the switch when a start signal (START) is received. On the contrary, when another one of the input data does not indicate the corresponding input line, even when the switch of the input line is closed in response to receiving the start signal START (for example, in a non-limiting example, all switches may be closed when the start signal START is received), the voltage will not be provided to the resistor. Here, since the other input data of the input signal does not include the input voltage signal to be applied to the corresponding input line, the voltage will not be provided to the resistor of the corresponding input line. Therefore, one end of the resistor of the corresponding input line can be floated and excluded from the formation of the composite resistor. As described above, a resistor with one end open indicates a resistance value much greater than its own natural or set resistance value, or the natural or set resistance value of other resistors providing the corresponding input voltage signal, so the resistor with an effectively relatively high resistance can be ignored in the composite resistance value or has a small effect on the composite resistance.

[0056] The capacitor C may be connected to the plurality of resistors 110 and charged with electric charge in response to voltage being applied. For example, the capacitor C may be charged with electric charge by respective currents flowing through the plurality of resistors 110 to which voltage is applied by input voltage signals or by switching. Figure 1, an example in which the capacitor C is charged with electric charge by an input voltage signal applied to the plurality of resistors 110 is described.

[0057] The comparator 130 may be connected to the plurality of resistors 110 and the capacitor C. The comparator 130 may output a target voltage V corresponding to the amount of charge in the capacitor C. o With reference voltage V ref In one example, the comparator 130 may be configured as an operational amplifier (OP amp), and the other ends of the plurality of resistors 110 and one end of the capacitor C may be connected to one input node of the operational amplifier. The other input node of the operational amplifier may receive a reference voltage V ref . Target voltage V o is a voltage corresponding to the amount of charge in the capacitor C, and may vary with time according to a time constant determined by the capacitance of the capacitor C and a composite resistance formed by the input signal and the plurality of resistors 110. ref It can be a voltage used as a standard for measuring voltage change time (eg, charging time or discharging time). For example, in response to the target voltage V o Exceeds the reference voltage V ref , the comparator 130 can output the comparison result. Figure 1 The comparison result can indicate the target voltage V o Exceeds the reference voltage V ref , and the time when the comparison result is output may be referred to as the output time. The comparator 130 may generate a count end signal STOP as the comparison result.

[0058] As discussed, the TDC 140 may convert the charging time of the capacitor C according to the combination of the input signal, the plurality of resistors 110, and the capacitor C into a digital value. The TDC 140 may convert the charging time into a digital value based on the comparison result of the comparator 130. For example, the charging time may be a time difference between the output time of the comparison result of the output comparator 130 and the start time when the start signal START is given. The time information is information indicating the charging time, and may be information indicating the number of clocks counted by the counter from the start time to the output time, which will be referred to below. Figure 4 and Figure 5 Described in more detail. In addition, the reference to a clock count may refer to a count of clock cycles, or other forms of clock count.

[0059] For reference, Figure 1The plurality of resistors 110, the comparator 130, and the TDC 140 shown in the figure may correspond to one output line. In response to the start signal START, the MAC circuit 100 may apply an input voltage signal to the plurality of resistors 110. As described above, among the plurality of resistors, the resistors to which the input voltage signal is applied may form a composite resistor. In response to the input signal being applied, the natural response between these resistors and the capacitor C may increase the target voltage V of the capacitor C. o For example, after the start signal START is given, the operation of the circuit including the resistor and the capacitor C can be expressed by Equation 1, for example.

[0060] [Equation 1]

[0061]

[0062] In Equation 1, j may represent an integer between "1" and "m" (inclusive). j can be the jth input voltage signal applied to the jth input line, R j It may be the resistance value of the jth resistor set in the jth input line, C may be the capacitance value of the capacitor C, and t represents time. For reference, if the input data is an input bit sequence including a series of binary values, each of the multiple input lines in the MAC circuit 100 may correspond to each bit position (bitposition) of the bit sequence. If the bit value of the bit position is "1", an input voltage signal having a voltage value may be applied to the input line corresponding to the bit position. On the contrary, if the bit value of the bit position is "0", the input voltage signal will not be applied to the input line corresponding to the bit position. In addition, the resistance values ​​of the plurality of resistors 110 may correspond to the bit value multiplied by each bit of the input bit sequence. For example, among the plurality of resistors 110, the resistor corresponding to the bit value "1" has a first resistance value, and the resistor corresponding to the bit value "0" has a second resistance value much larger than the first resistance value, which has no significant effect on the composite resistance value. As described above, in a composite resistor formed by a resistor having a first resistance value and a resistor having a second resistance value, the magnitude of the second resistance value much larger than the first resistance value can be ignored since it has little or no significant effect on the composite resistance value.

[0063] The boundary condition regarding the above equation 1 can be expressed by equation 2, for example.

[0064] [Equation 2]

[0065]

[0066] In Equation 2, V o (0 +) can be the target voltage V o The initial value, V o (∞) can be the target voltage V o For example, as shown in Equation 3, the target voltage V o It can be derived from Equation 1 and Equation 2.

[0067] [Equation 3]

[0068]

[0069] In Equation 3, the composite resistance R o It is formed by resistors connected in parallel to each other, and the resistance value of the composite resistor can be expressed by Equation 4, for example.

[0070] [Equation 4]

[0071]

[0072] In Equation 4, if the jth resistor corresponds to a bit value of “0”, or one end of the jth resistor is open (for example, if the input voltage signal is not applied to the jth resistor), then R j can be effectively a second resistance value greater than the first resistance value. If the jth resistor corresponds to a bit value of "1" and an input voltage signal is applied to one end of the jth resistor, then R j It can be a first resistance value.

[0073] When the target voltage V of the capacitor C is charged after the input signal is applied o exceeds the preset reference voltage V ref When the target voltage V o becomes equal to the preset reference voltage V ref Charging time T out , Equation 3 can be expressed as Equation 5, for example.

[0074] [Equation 5]

[0075]

[0076] For example, as shown in Equation 6, Equation 5 can be used for the charging time T out Rearrange.

[0077] [Equation 6]

[0078]

[0079] As shown in Equation 6, the charging time T out It can be a composite resistor R o is a linear function of the composite resistance Ro As mentioned above, the composite resistance R o Each R j The value may correspond to the bitwise multiplication result between the bit value of the input data and the bit value indicated by the resistor in the j-th input line. For example, if the bit value "1" corresponds to a low resistance value (e.g., 100 kilo-ohms) and the bit value "0" corresponds to a high resistance value (e.g., 10 megohms), the composite resistance R o The number of bits that are "1" in the product-accumulation result can be expressed as Figure 2 The inverse proportional relationship shown in the graph 200. Figure 2 In the graph 200 of FIG. 1 , the x-axis may represent the number of bits as the total number of resistors corresponding to the bit value “1”, and the y-axis may represent the composite resistance value normalized to “1” with 100 kilo-ohms. Based on the inverse proportional relationship, the MAC circuit may calculate the composite resistance R from the estimated composite resistance R o Estimate the number of bits based on the result of the bit-by-bit multiplication.

[0080] In short, if Figure 2 As shown in the graph, the charging time T out Can be combined with the composite resistor R o proportional to the composite resistance R o The multiplication-accumulation result may be mapped to the value of the plurality of resistors 110 or the value indicated by the plurality of resistors 110 and the value of the input data. In binary operation, the multiplication-accumulation result may correspond only to the number of bit values ​​"1" used for summation.

[0081] As described above, the MAC circuit 100 may output a charging time T corresponding to the multiplication and accumulation result. out For example, the TDC 140 of the MAC circuit 100 may count a time difference (eg, charging time) between the start signal START and the count end signal STOP as the number of reference clocks CLK and output the counted number of reference clocks CLK as a digital value.

[0082] Unlike a von Neumann architecture in which a memory and an arithmetic unit are separated, the MAC circuit 100 can improve data transmission rate and power consumption. In addition, unlike a structure in which an analog-to-digital converter (ADC) is used to perform quantization into a digital signal and the signal is used as an input of an activation function in an in-memory computing architecture in which a memory and an arithmetic unit are integrated, the MAC circuit 100 may not need to configure independent ADCs in all columns, and therefore, power consumption and occupied area in the circuit can be reduced.

[0083] For reference, in the above Figure 1 and Figure 2In the example, it is assumed that the voltage value of the input voltage signal and the resistance value of the resistor have binary values ​​(e.g., a value corresponding to conduction (ON) and a value corresponding to cutoff (OFF)). However, the example is not limited to this. The voltage value of the input voltage signal and the resistance value of the resistor may have values ​​that are distinguished into multiple states. For example, if a 2-bit value is input to an input line, the input voltage signal may float for "00", the first voltage value may be assigned to the input voltage signal for "01", the second voltage value greater than the first voltage value may be assigned to the input voltage signal for "10", and the third voltage value greater than the second voltage value may be assigned to the input voltage signal for "11". If each resistor indicates a 2-bit value, the first resistance value may be assigned to the resistor for "00", the second resistance value greater than the first resistance value may be assigned to the resistor for "01", the third resistance value may be assigned to the resistor for "10", and the fourth resistance value may be assigned to the resistor for "11". The signal received in each input line and each resistor is not limited to indicating a plurality of states of 2 bits, but may indicate a plurality of states corresponding to more bits, or may be assigned a value according to a system other than binary.

[0084] Figure 3 An example of a MAC circuit including a plurality of input lines and a plurality of output lines is shown.

[0085] The MAC circuit 300 may include a plurality of input lines for respectively receiving input signals and a plurality of output lines for respectively outputting output signals (eg, a specific T out Each of the plurality of output lines may include a plurality of resistors, a capacitor 320, and a comparator 330. Each of the plurality of input lines may intersect with the plurality of output lines. Figure 3 The MAC circuit 300 may include m input lines and n output lines. Although the input lines and the output lines are shown to intersect each other perpendicularly, the example is not limited thereto. The MAC circuit 300 may include a plurality of resistors, a plurality of capacitors, a plurality of comparators, a single TDC 340, and an output stage 350.

[0086] like Figure 3 As shown in , a plurality of resistors may be arranged along a plurality of output lines and a plurality of input lines. For example, a plurality of resistors may be arranged in each of a plurality of input lines along the output lines. Each of the plurality of resistors may be configured to receive a voltage through an input line in which a corresponding resistor 310 is arranged among the plurality of input lines. For example, a resistor arranged along the j-th input line 391 may be configured to receive a j-th input voltage signal b in response to a start signal. j .exist Figure 3 As an example, the input voltage signal b 1 To b mThe input voltage signal indicating the bit value "1" may indicate a certain voltage, and the input voltage signal indicating the bit value "0" may indicate a floating voltage. The structure in which multiple resistors are arranged for such multiple input voltage signals and multiple output lines may also be referred to as a memory array 390.

[0087] A plurality of capacitors may be arranged in each of a plurality of output lines, respectively. Each of a plurality of capacitors may be connected to the other end of a resistor arranged along an output line in which a corresponding capacitor 320 is arranged among a plurality of output lines and a respective comparator 330. Each of a plurality of capacitors may be charged with an electric charge in response to a voltage received by a corresponding resistor. For example, a capacitor 320 arranged in the i-th output line 392 may be charged with an electric charge according to a voltage applied to a resistor arranged in the i-th output line 392. For reference, a plurality of capacitors may have the same capacitance. This is because each output line should have a charging time or a discharging time of the same scale due to the output of a single global counter shared by a plurality of output lines. The charging time and the discharging time may represent a scale proportional to a time constant corresponding to a composite resistance value and a capacitance.

[0088] A plurality of comparators may be provided in a plurality of output lines, respectively. Each of the plurality of comparators may be connected to the other end of a resistor and a capacitor 320 arranged along an output line in which a corresponding comparator 330 is provided among the plurality of output lines, and outputs a result of comparing a target voltage of the corresponding capacitor 320 with a reference voltage. For example, the comparator 330 provided in the i-th output line 392 may compare a target voltage of a capacitor 320 provided in the i-th output line 392 with a reference voltage, and output an i-th count end signal STOP in response to the target voltage exceeding the reference voltage. i .

[0089] The TDC 340 may receive count end signals for a plurality of output lines and convert respective time information into digital values. For example, the TDC 340 may output digital values ​​corresponding to the time information of n output lines, respectively. The TDC 340 may output n digital values ​​corresponding to the time information. For example, in response to receiving the i-th count end signal STOP i , TDC 340 can generate the i-th time information T out,i , the i-th time information T out,i Indicates the start time corresponding to the start signal START and the count end signal STOP i The time difference between the output moments. The i-th time information T out,i It may also be referred to as the i-th charging time.

[0090] The output stage 350 may output a value mapped to the digital value generated by the TDC as an output value OUTs of the output line. As described above, the output value OUTs may be a value in which the digital value indicating the time information is mapped to a number corresponding to the product-accumulation result. For example, the MAC circuit may output the value mapped to the i-th time information T through a mapping table (e.g., a lookup table). out,i The i-th output value OUT i Since the output values ​​are output for the output lines respectively, the output stage 350 can output n output values ​​for n output lines.

[0091] Hereinafter, a single global counter included in the TDC 340 will be described.

[0092] Figure 4 An example of TDC is shown. Figure 5 An example of a referrer of a TDC is shown.

[0093] Will refer to Figure 4 describe Figure 3 An example of a configuration of a TDC. The TDC may include a single global counter 441 and a reference 442.

[0094] The single global counter 441 may output a digital value indicating the time elapsed from the start time. The single global counter 441 may be connected to multiple output lines ( Figure 3 For example, a single global counter 441 may count the number of reference clocks CLK generated from the start time. Therefore, an additional synchronization operation may not be used, and the single global counter 441 may count the corresponding elapsed time (e.g., charging time or discharging time) for each individual output line in units of the reference clock based on the same start time.

[0095] The reference device 442 may refer to or observe a digital value output from the single global counter 441 at the time of outputting a comparison result. The reference device 442 may include a plurality of holding circuits to refer to the comparison results of the comparators of the plurality of output lines. Each of the plurality of holding circuits may refer to the time at which the comparison result is output from the comparator included in the corresponding output line among the plurality of output lines. For example, each holding circuit may hold the number of reference clocks CLK counted by the single global counter 441 at the output time of receiving the count end signal. The number of reference clocks CLK held at the output time may correspond to time information (e.g., charging time or discharging time), and may be output as time information T out .

[0096] Regardless of whether the plurality of holding circuits are holding or not, the single global counter 441 can count the reference clock CLK, and each holding circuit can operate independently of the other holding circuits. For example, even when the corresponding holding circuit holds the time information corresponding to the moment when the count end signal is received, the single global counter 441 can continue to count the reference clock CLK.

[0097] like Figure 5 As shown in , each of the plurality of holding circuits may be configured as a flip-flop circuit. The single global counter 441 may receive a reference clock (e.g., a clock cycle) from a clock generator 544, and count the number of reference clocks in response to a start signal START, wherein the start signal START may be input to an enable terminal EN of the single global counter 441, and the counted number of reference clocks may be output from an output terminal OUT of the single global counter 441 to each flip-flop circuit FF. In response to receiving a count end signal STOPs from a comparator of a corresponding output line, each flip-flop circuit may hold a digital value indicating the number of reference clocks counted from the start moment to the output moment of outputting the count end signal STOPs. The digital value held by the flip-flop circuit 543 may indicate time information T outs Time information T outs Information indicating a time to output a comparison result of the comparator may be included.

[0098] Therefore, the plurality of holding circuits in the MAC circuit can count the number of reference clocks of the single global counter 441 independently and in parallel. In this example, since the holding circuit is implemented with a simple flip-flop structure, the area occupied in the circuit and the power consumption can be minimized. In addition, since there is no need to arrange a plurality of counters for a plurality of output lines, the MAC circuit can be implemented with simpler elements.

[0099] For reference, in one example, refer to Fig.13 Some operations of the neural network described, or another neural network or other machine learning model can be performed by Figure 5 For example, the connection weight value W of the neural network j,i can be stored in the resistor corresponding to the internal memory. Similar to the above description, the input signal b 1 to b m The start time being input applies the start signal START to the TDC 340. The single global counter 441 starts counting in response to the start signal START. 1 to b m The connection weight value W of each resistor j,iThe resistance corresponding to the bitwise multiplication (e.g., XNOR) operation between the capacitors can be determined. As described above, the resistance of the resistor can vary depending on whether the input voltage signal is applied and the internal resistance value of the resistor. At the input of the comparator, a transient behavior corresponding to all the bitwise multiplication results determined by the combination of the capacitor and the composite resistor can be observed. In response to the target voltage of the capacitor reaching the predetermined reference voltage V due to the transient behavior ref , the comparator may send a count end signal STOP to the TDC 340, and the TDC may output the time value as a digital value.

[0100] Figure 6 An example of the switching operation of the TDC is shown.

[0101] like Figure 6 As shown in , the target voltage 639 of the capacitor set in the output line can gradually increase according to the natural response corresponding to the corresponding time constant of the capacitor. That is because the charge in the capacitor gradually increases. In this example, Figure 5 The clock generator described in the above may generate a reference clock, and a single global counter may count the number of reference clocks from the start time START. Even when the target voltage 639 becomes equal to the reference voltage V ref The single global counter may also continue to count the number of reference clocks after the output time STOP of the reference clock. The holding circuit of the reference clock may hold a digital value indicating the number of reference clocks counted from the start time START to the output time STOP. For example, Figure 6 In the example of , from the start time START to the output time STOP, 6 reference clocks may be generated, and the holding circuit may output a digital value "6".

[0102] Figure 7 An example of a calculation method using a MAC circuit is shown.

[0103] First, in operation 710, the MAC circuit may receive an input signal. For example, the MAC circuit may receive the input signal through each input line. Depending on the input signal, a voltage may be applied to a resistor of each individual input line or no voltage may be applied.

[0104] In operation 720 , the MAC circuit may charge capacitors connected to the plurality of resistors with charges according to voltages applied to the plurality of resistors in response to an input signal.

[0105] Then, in operation 730 , the TDC may convert the charging time of the capacitor into a digital value according to a combination of the input signal, the plurality of resistors, and the capacitor.

[0106] Figure 8 A detailed example of the calculation method is shown.

[0107] First, in operation 801, the MAC circuit may refresh the capacitor. For example, after all output lines have output digital output values ​​for previous input signals, the MAC circuit may discharge the capacitor to a threshold voltage or lower until a subsequent input signal is received. The MAC circuit may release charge from the capacitor until a voltage applied across the capacitor becomes less than a threshold voltage (e.g., 0 volts (V)).

[0108] In operation 810, the MAC circuit may determine whether to start a MAC operation. For example, the MAC circuit may perform the following operations in response to a start signal being generated. The MAC circuit may generate a start signal in response to an input signal being received.

[0109] In operation 815, the single global counter may reset the count in response to the start signal. For example, the single global counter may reset the number of reference clocks to "0".

[0110] In operation 820, the MAC circuit may apply a voltage to the resistor and the capacitor according to the input signal. For example, the MAC circuit may apply the input signal to a resistor corresponding to an input line indicated by the input data among the plurality of resistors in response to the start signal. When a voltage is applied through the input line, the target voltage of the capacitor may gradually increase according to a natural response to the applied voltage.

[0111] In operation 831, a single global counter may count the charging time. For example, the single global counter may count the number of reference clocks from the start time of generating the start signal. Therefore, the TDC may start counting the elapsed time in response to the start signal.

[0112] In operation 832, the comparator may determine whether or when the target voltage of the capacitor exceeds the reference voltage. The comparator may output a comparison result in response to the target voltage exceeding the reference voltage. If the target voltage is less than or equal to the reference voltage, the MAC circuit may return to operation 831 so that the single global counter may continue to count the number of reference clocks. In addition, the single global counter may continue to count the number of reference clocks after the target voltage exceeds the reference voltage.

[0113] The TDC may output a digital value corresponding to the charging time in operation 833. The TDC may output the charging time corresponding to time information about the time elapsed from the start time when the input signal is received to the output time when the comparison result is output as a digital value.

[0114] Fig. 9 An example of a MAC circuit to which a power supply voltage is applied by switching is shown.

[0115] The MAC circuit 900 may include switches connected to the plurality of resistors 110, respectively. Fig. 9 Medium, SW' 1 To SW' m The plurality of switches 901 are respectively arranged in the plurality of input lines.

[0116] The plurality of switches 901 may be opened or closed in response to a start signal. The plurality of switches 901 may connect or disconnect the power supply voltage V based on a switching signal provided after the start signal is generated. DD and a corresponding resistor. The input voltage signal may be received as a switching signal. When the input voltage signal has a first voltage value corresponding to the ON state, the switch may be closed and the power supply voltage V DD When the input voltage signal has a second voltage value corresponding to the OFF state, the switch can be opened and the power supply voltage V DD The switches are disconnected from the corresponding resistors. In one example, the switches may be implemented as metal oxide semiconductor field effect transistors (MOSFETs), and each switch may receive a corresponding switching signal at a gate node. For example, each gate node of each switch may receive a respective input voltage signal. The operation of the switches according to the input voltage signal is similar to the above description of Figure 1 For example, in the case where the input data of the input signal does not include an input voltage signal to be applied to the corresponding input line, one end of the corresponding resistor may float, and the corresponding resistance of the resistor has a large value, thus having a small influence on the composite resistance. Fig. 9 In the example of FIG. 1 , if the input voltage signal has a voltage value corresponding to the OFF state (eg, a zero voltage value), the switch may be turned off and disconnected, or remain off and maintain the power supply voltage V DD The corresponding resistor is disconnected and prevented from affecting the composite resistance.

[0117] Each of the plurality of switches 901 may switch the power supply voltage V DD The input voltage signal is transmitted to the corresponding resistor (wherein the input voltage signal is received in an input line provided with a resistor connected to the corresponding switch), and one end of the corresponding resistor is disconnected in response to the input voltage signal being a disconnection signal. For example, if the j-th input voltage signal V j is a closed signal, then the jth switch SW' j The two ends can be connected or left connected to receive the supply voltage V at the other end. DD transmitted to the jth resistor R connected to one end j , but if the jth input voltage signal V j is a disconnect signal, then the jth switch SW' jThe two ends can be disconnected or kept disconnected to make the jth resistor R j One end is floating.

[0118] As reference Fig. 9 If the power supply voltage V DD is applied to the resistor, the MAC circuit 900 can operate not only in a charging period but also in a discharging period, which will be described below.

[0119] Figures 10 to 12 Show Fig. 9 An example of a charge period operation and a discharge period operation of a MAC circuit.

[0120] In the MAC circuit, the capacitance of the capacitor is limited, so the capacitor needs to be discharged after being charged. Fig.10 As shown, the MAC circuit may repeat the charging period 1010 and the discharging period 1020. Here, the MAC circuit may calculate the MAC result not only during the charging period 1010 but also during the discharging period 1020.

[0121] Fig.11 10 is a flowchart illustrating a calculation method using a MAC circuit in a charging period 1010 and a discharging period 1020 .

[0122] First, in operation 1111, the MAC circuit may fully discharge the capacitor. For example, the MAC circuit may provide a ground voltage to a resistor connected to the capacitor. Since one end of the capacitor is connected to the resistor and the other end thereof is connected to the ground, the MAC circuit may discharge the capacitor by providing the ground voltage.

[0123] In operation 1112, the MAC circuit may determine whether to start a MAC operation for a charging period. In operation 1113, the single global counter may reset the count in response to a start signal. Details of operations 1112 and 1113 and reference Figure 8 The details of the described operations 810 and 815 are similar, and thus repeated descriptions will be omitted.

[0124] In operation 1114, the MAC circuit may provide a power supply voltage to the resistor and capacitor according to the input signal. For example, the switch may apply the power supply voltage to the resistor connected thereto in response to the input voltage signal during the charging period. Fig. 9 In the MAC circuit shown in FIG. 1 , when the j-th input voltage signal input to the j-th input line indicates an ON state, the j-th switch SW′ j The two ends of the resistor R j or multiple resistors in the same input line (such as discussed above with respect to Figure 3The j-th input line 391 including a plurality of resistors provides a voltage). Therefore, the power supply voltage can be supplied through the j-th resistor R j The capacitor C is provided to the corresponding output line. In contrast, when the j-th input voltage signal input to the j-th input line indicates an OFF state, the j-th switch SW' j Both ends of the resistor R j Thus, among the plurality of resistors, the resistors in the input line receiving the ON state may form a composite resistor, and the resistors in the input line receiving the OFF state may be excluded from the formation of the composite resistor.

[0125] In operation 1115, a single global counter of the MAC circuit may count. When the power supply voltage is transmitted through the resistor in the ON state as described above in operation 1114, the capacitor may be charged with the charge. As the capacitor is charged with the charge, the target voltage of the capacitor may increase according to the composite resistance formed by the resistor in the ON state and the natural response corresponding to the capacitor. Figure 4 As discussed, the MAC circuit may count the time for charging the capacitor with the electric charge as the number of reference clocks.

[0126] In operation 1116, the comparator can compare the target voltage with the first reference voltage V ref1 When the capacitor is charged by the power supply voltage, the comparator can respond to the target voltage exceeding the first reference voltage V ref1 The comparison result is output, wherein the target voltage corresponds to the charge in the capacitor. When the target voltage reaches the first reference voltage V ref1 When the reference clock is reached, the single global counter may continue to count the number of reference clocks (eg, unless all output line comparators have issued a stop signal).

[0127] In operation 1117, the TDC may output a digital value corresponding to the charging time. For example, the TDC may output a digital value as the charging time, the digital value indicating the number of reference clocks counted from the start time to the output time of outputting the comparison result in the above operation 1116. The charging time may be output as a digital code value. Figures 1 to 8 The discussion of TDC operation with multiple output lines and multiple TDC outputs also applies to Fig.11 .

[0128] In operation 1121 , the MAC circuit may fully charge the capacitor.

[0129] In operation 1122, the MAC circuit may determine whether to start a MAC operation of a discharge period. In one example, in operation 1123, a single global counter may reset the count in response to a start signal. Details of operations 1122 and 1123 are provided in reference to FIG. Figure 8 The details of the described operations 810 and 815 are similar, and thus repeated descriptions will be omitted.

[0130] In operation 1124, the MAC circuit may provide a reset voltage to the resistor and capacitor according to the input signal. The reset voltage may correspond to a ground voltage. For example, the switch may apply the reset voltage to the resistor connected thereto in response to the input voltage signal during the discharge period. Fig. 9 In the MAC circuit shown in FIG. 1 , when the j-th input voltage signal input to the j-th input line indicates an ON state, the j-th switch SW′ j The two ends of the resistor R can be connected, and a reset voltage (eg, ground voltage) can be connected through the jth resistor R j The capacitor C is provided to the corresponding output line. In contrast, when the j-th input voltage signal input to the j-th input line indicates an OFF state, the j-th switch SW' j Both ends of the resistor R j Therefore, similar to the charging period, in the discharging period, among the plurality of resistors, the resistors in the input line receiving the ON state may form a composite resistance, and the resistors in the input line receiving the OFF state may be excluded from the formation of the composite resistance.

[0131] In operation 1125, a single global counter of the MAC circuit may count the discharge time. When the reset voltage is transmitted through the resistor in the ON state as described in the above operation 1124, the charge in the capacitor C may be released therefrom. As the charge is released from the capacitor C, the target voltage of the capacitor C may decrease according to the composite resistance formed by the resistor in the ON state and the natural response corresponding to the capacitor C. The MAC circuit may count the time when the charge is released from the capacitor C as the number of reference clocks.

[0132] In operation 1126, the comparator can compare the target voltage with the second reference voltage V ref2 When the charge is released from the capacitor C by the reset voltage, the comparator can respond to the target voltage according to the charge in the capacitor being less than the second reference voltage V ref2 The comparison result is output. When the target voltage reaches the second reference voltage V ref2 When the reference clock is reached, the single global counter may continue to count the number of reference clocks (eg, unless all output line comparators have issued a stop signal).

[0133] In operation 1127, the TDC may output a digital value corresponding to the discharge time. For example, the TDC may output a digital value indicating the number of reference clocks counted from the start time to the output time when the comparison result is output in the above operation 1126 as the discharge time. The discharge time may be output as a digital code value.

[0134] Reference Fig.12 In the example of , in the first charging period 1211, the comparator may output a comparison result at the time when 4 reference clocks are counted from the start time of the corresponding period, and the TDC may output time information T indicating "4". out In the first discharge period 1222, the comparator may output a comparison result at a time when 5 reference clocks are counted from the start time of the corresponding period, and the TDC may output time information T indicating "5". out In the second charging period 1213, the comparator may output a comparison result at a time when 4 reference clocks are counted from the start time of the corresponding period, and the TDC may output time information T indicating "4". out In the second discharge period 1224, the comparator may output a comparison result at a time when 6 reference clocks are counted from the start time of the corresponding period, and the TDC may output time information T indicating "6". out .

[0135] Therefore, the MAC circuit can reuse power that may be wasted due to simple discharge by alternately performing charging and discharging, thereby minimizing power leakage.

[0136] Fig.13 An example of a neural network operation implemented by a MAC circuit of a computing device is shown.

[0137] The neural network 1300 may be an example of a deep neural network (DNN). The neural network 1300 may be implemented by an example computing device. The DNN may be or may include a fully connected network, a deep convolutional network, and a recurrent neural network. The computing device may implement the neural network 1300 to perform object classification, object recognition, speech recognition, and image recognition by mapping input data and output data in a nonlinear relationship based on deep learning. Deep learning is a machine learning technique for solving problems (such as image recognition or speech recognition) from large data sets, and input data and output data may be mapped to each other through supervised or unsupervised learning.

[0138] Although for ease of description, Fig.13 2 hidden layers are included, but various numbers of hidden layers may be included. In addition, although the neural network 1300 is Fig.131300 as including a separate input layer 1310 for receiving input data, but the input data may be directly input into the hidden layer. In the neural network 1300, artificial nodes of layers other than the output layer may be connected to artificial nodes of subsequent layers through links or connections (for example, only as an example) for transmitting output signals. The number of links or connections may correspond to the number of artificial nodes included in the training of the previous layer, the subsequent layer, and the neural network, for example.

[0139] The output of the artificial node included in the previous input layer may be input to each artificial node included in the hidden layer 1 in a weighted form (e.g., by a connection weight). The input in a weighted form may be referred to as a weighted input, which is obtained by multiplying the weight by the output of the artificial node included in the previous layer and combining the results. The weight may be referred to as a parameter of the neural network 1300. An activation function may be applied to each of the accumulations of the weighted inputs of each node of the hidden layer 1, and, for example, each activation of each node in the hidden layer 1 may be output to the subsequent hidden layer 2. The activation function may include one or more of a sigmoid, a hyperbolic tangent (tanh), and a rectified linear unit (ReLU), and nonlinearity may be formed in the neural network 1300 by the activation function. A similar operation is performed for the hidden layer 2, where the activation output of the hidden layer 2 may be input to each node included in the output layer.

[0140] Refer to above Figures 1 to 12 The MAC circuit described above can be applied to memory computing for driving deep learning algorithms. Figure 5 As discussed, respective calculations of weighted inputs transmitted between nodes 1321 of the neural network 1300 may include MAC operations that repeatedly perform multiplication and accumulation (addition) operations (e.g., in parallel operating MAC circuits and / or in sequential MAC circuit operations). The output of a predetermined node 1321 of the neural network 1300 may be represented by Equation 7, for example.

[0141] [Equation 7]

[0142]

[0143] The above equation 7 may represent the output value y of the i-th node 1321 for m weighted input values ​​in a predetermined layer. i .x j may represent the j-th output value (e.g., node value) of the previous layer, and w j,i w may represent the weight applied to the i-th node 1321 and the j-th output value of the previous layer. j,i x jmay represent the jth weighted input among the m weighted input values ​​in the i-th node 1321 of the corresponding layer, and f() may represent an activation function. As shown in Equation 7, for the activation function, the node value x j and weight w j,i The MAC result of can be used. In other words, load the appropriate node value x at the time of need j and weight w j,i The memory access operations and the MAC operations of multiplying and accumulating them can be repeated.

[0144] In the neural network 1300 including a layer including a plurality of nodes, the plurality of resistors of the MAC circuit may have resistances corresponding to connection weights of edges connecting the plurality of nodes. An input voltage signal provided along an input line provided with the plurality of resistors may indicate a value corresponding to a node value x. j Therefore, the MAC circuit can perform at least a portion of the operations required to implement the neural network 1300. For reference, in the MAC circuit, the resistance value of the resistor is not fixed and can be changed to a resistance value corresponding to the weight value stored in the memory as described above.

[0145] However, the application of the MAC circuit is not limited thereto, and the MAC circuit may be used for a calculation operation that processes a plurality of input data quickly with low power consumption using the characteristics of an analog circuit.

[0146] The MAC circuit may have a low-power structure of an analog addition and digital conversion circuit combined with a memory calculation structure using a TDC. As described above, the MAC circuit can use one TDC (using a single global counter) to calculate multiple columns of data (e.g., data corresponding to multiple output lines). That is because, since the start signal START is synchronized for the global counter and all input lines, only the count value corresponding to the end signal STOP can be independently referenced for each column or each output line. Therefore, the parallel operation of the entire array in the memory can be covered by one TDC. In the case of the existing ADC structure, an ADC is required for each column, and a complex structure is required to improve the bit accuracy, so large power and area are required. However, the TDC structure (such as a MAC circuit) uses a simple counter to digitize the addition value, so it is a simple circuit. In addition, the entire array operation is covered by a single TDC, and power consumption and size can be reduced.

[0147] Fig.14 An example of a computing device is shown. Fig.14, the processing device 1400 includes a processor 1410, a memory 1420, a MAC circuit 1430, and a communication bus 1450. The memory 1420 is connected to the processor 1410 and the MAC circuit 1430, for example, using the communication bus 1450, and stores instructions executable by the processor 1410 and parameters of the neural network, data to be calculated by the processor 1410 or the MAC circuit 1430, or data processed by the processor 1410 or the MAC circuit 1430. For example, as discussed above, the MAC circuit 1430 may be provided with an input signal determined by the processor 1410 (e.g., a resistor resistance value set based on the parameters stored in the memory 1420), and provide outputs corresponding to a plurality of output lines from the MAC circuit 1430. In addition, although an example MAC circuit is described above, the MAC circuit 1430 also represents a plurality of MAC circuits.

[0148] Processor 1410 may execute control and / or start Figures 1 to 13 For example, the processor 1410 may generate input data, or receive input data for the output of a previous layer of a neural network, control the provision of input data to the MAC circuit 1430, and control the reception of output data from the MAC circuit 1430. The processor 1410 may also perform such MAC operations and execute one or more neural networks based on the stored parameters, thereby completing object classification, object recognition, speech recognition, and / or image recognition for the corresponding input.

[0149] The units described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general or special computers (such as, for example, processors, controllers, and arithmetic logic units (ALUs), DSPs, microcomputers, FPGAs, programmable logic units (PLUs), microprocessors, or any other device capable of responding and executing instructions in a limited manner). The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For the purpose of simplicity, the description of the processing device is used as a singular; however, it will be understood by those skilled in the art that the processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. In addition, different processing configurations (such as parallel processors) are feasible.

[0150] Software may include computer programs, code segments, instructions, or some combination thereof, to independently or collectively instruct or configure a processing device to operate as desired. Software and data may be implemented permanently or temporarily in any type of machine, component, physical or virtual device, computer storage medium or device, or in a propagating signal wave capable of providing instructions or data to a processing device or capable of being interpreted by a processing device. Software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored by one or more non-transitory computer-readable recording media.

[0151] According to the method of the above example, it can be recorded in a non-transitory computer-readable medium including program instructions to implement various operations of the above example. The medium can also include data files, data structures, etc., either alone or in combination with program instructions. The program instructions recorded on the medium can be those program instructions specially designed and constructed for the purpose of the example, or they can be types known and available to technicians in the field of computer software. Examples of non-transitory computer-readable media include magnetic media (such as hard disks, floppy disks and tapes), optical media (such as CD-ROM disks, DVDs and / or Blu-ray discs), magneto-optical media (such as optical discs), and hardware devices (such as read-only memory (ROM), random access memory (RAM), flash memory (for example, USB flash drive, memory card, memory stick, etc.)) specially configured to store and execute program instructions. Examples of program instructions include both machine code (such as generated by a compiler) and files containing high-level code that a computer can execute using an interpreter. The above device can be configured to act as one or more software modules to perform the operations of the above example, and vice versa.

[0152] Some examples have been described above. However, it should be understood that various modifications may be made to these examples. For example, suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0153] Accordingly, other implementations are within the scope of the following claims.

Claims

1. A multiplier-accumulator system, comprising: A multiplier-accumulator circuit comprising: a plurality of resistors, each having a respective resistance; a capacitor connected to the plurality of resistors, the capacitor being charged with electric charge in response to a plurality of input signals; and a time-to-digital converter configured to convert information of a charging time of the capacitor due to an electric charge into a digital value, Wherein, the digital value is the accumulated result of the multiplier-accumulator circuit, The time-to-digital converter comprises: a single global counter configured to generate respective output values ​​indicating the time that has elapsed since a start time, the time-to-digital converter being configured to: determine a selected output from the respective output values ​​of the single global counter at a time corresponding to the charging time of the capacitor for charging, and convert the determined selected output into the digital value.

2. The system according to claim 1, in, The plurality of resistors and the capacitor are configured as a first output line, The multiplier-accumulator circuit further comprises: one or more other output lines, each of which comprises a respective other capacitor and a respective plurality of resistors, wherein the respective plurality of resistors have respective resistances and are connected to the corresponding other capacitors, wherein the respective other capacitor of each of the one or more other output lines is configured to be charged with a respective charge in response to the plurality of input signals, and Wherein, the respective other capacitors and the capacitor have the same capacitance.

3. The system according to claim 2, in, The time-to-digital converter is configured to convert respective information of respective charging times of respective other capacitors of the one or more other output lines into respective digital values.

4. The system according to claim 3, in, The first output line further includes: a comparator connected to the capacitor and configured to generate information of a charging time of the capacitor, and The other output lines each further include: a respective other comparator, each of the respective other comparators is respectively connected to a respective other capacitor of the one or more other output lines and is configured to generate respective information of a respective charging time.

5. The system according to claim 4, in, The information of the charging time of the capacitor is an indication of the time when the comparator outputs the comparison result, and The respective information of the respective charging times are respective indications of the times at which the respective other comparators output respective comparison results.

6. The system according to claim 5, wherein: The conversion into the digital value depends on: the corresponding output value of a single global counter at the time corresponding to the moment when the comparator outputs the comparison result, and The conversion into the respective digital values ​​is respectively dependent on: the respective output values ​​of the single global counter at the times corresponding to the moments when the respective other comparators respectively output the respective comparison results.

7. The system according to claim 6, in, The comparator is configured to: output a comparison result in response to the voltage of the capacitor satisfying a reference voltage, and The respective other comparators are respectively configured to: in response to the respective voltages of the respective other capacitors of the one or more other output lines satisfying the reference voltage, respectively output respective comparison results.

8. The system according to claim 4, in, The comparator is configured to: output a comparison result in response to the voltage of the capacitor satisfying a reference voltage, and The respective other comparators are respectively configured to: in response to the respective voltages of the respective other capacitors of the one or more other output lines satisfying the reference voltage, respectively output respective comparison results.

9. The system of claim 3, comprising a computing device, the computing device comprising the multiplier-accumulator circuit, wherein: The multiple input signals are inputs to the neural network layer of the multiplier-accumulator system, as bits of the inputs or as multi-bit states of each input, and the respective resistances and other resistances represent at least one parameter of the neural network layer.

10. The system according to claim 2, wherein: The plurality of input signals are received by the multiplier-accumulator circuit as a plurality of input voltage signals respectively provided to a plurality of input lines of the multiplier-accumulator circuit, wherein, as a first input line of the plurality of input lines, a voltage corresponding to one of the plurality of input signals is supplied to one of the plurality of resistors of the first output line and to one of the plurality of resistors of each of the one or more other output lines, and Wherein, as a second input line of the plurality of input lines, a voltage corresponding to a different one of the plurality of input signals is provided to a different one of the plurality of resistors of the first output line, and to a different one of the plurality of resistors of each of the one or more other output lines.

11. The system according to claim 1, wherein: The multiplier-accumulator circuit also includes: a comparator connected to the plurality of resistors and the capacitor and configured to: output a comparison result obtained by comparing a target voltage corresponding to the amount of charge in the capacitor with a reference voltage, The time-to-digital converter is configured to perform conversion based on the comparison result of the comparator.

12. The system according to claim 11, wherein: The information of the charging time of the capacitor includes information indicating a timing of outputting a comparison result.

13. The system according to claim 12, wherein: The comparator is configured to output a comparison result in response to a target voltage exceeding a reference voltage as the capacitor is charged according to one or more of the plurality of input signals.

14. The system of claim 1, wherein: The plurality of input signals are received by the multiplier-accumulator circuit as a plurality of input voltage signals respectively provided to a plurality of input lines of the multiplier-accumulator circuit.

15. The system of claim 1, wherein: The plurality of resistors are connected in parallel with each other, and One end of each of the plurality of resistors is configured to receive a voltage through a switch, and the other end of each of the plurality of resistors is connected to the capacitor and a comparator, wherein information of a charging time of the capacitor depends on an operation of the comparator.

16. The system of claim 1, wherein: One or more resistors of the plurality of resistors form a composite resistor, and The time-to-digital converter is configured to convert information of charging time into the digital value, wherein the charging time of the capacitor depends on a combination of a composite resistance and a capacitance of the capacitor.

17. The system according to claim 1, in, The plurality of resistors and the capacitor are configured as a first output line, and The information on the charging time of the capacitor is the time that has elapsed from the start time of receiving the plurality of input signals to the output time of outputting the comparison result of the first output line.

18. The system of claim 17, wherein: The time-to-digital converter also includes: The reference device is configured to refer to the output value of the single global counter at the output time.

19. The system of claim 18, wherein The plurality of resistors and the capacitor are configured as a first output line of a plurality of output lines of the multiplier-accumulator circuit, the first output line further comprising a comparator to provide information of a charging time of the capacitor, One or more other output lines of the plurality of output lines each respectively include a respective plurality of resistors and a respective other capacitor, the respective plurality of resistors having a respective resistance, each of the other output lines includes a respective other comparator, the respective other comparator respectively providing information of a charging time of the respective other capacitor, Reference tools include: a holding circuit and a plurality of other holding circuits, the holding circuit being configured to refer to a comparison result of the comparator, and the plurality of other holding circuits being configured to refer to other comparison results of respective other comparators, respectively, and The holding circuit and each of the plurality of other holding circuits are configured to respectively refer to output values ​​of a single global counter at times corresponding to the referenced comparison result and the respectively referenced other comparison results.

20. The system of claim 19, wherein: The holding circuit and each of the plurality of other holding circuits are configured as a flip-flop circuit.

21. The system according to any one of claims 1, 14-17, wherein: The respective resistors are configured to respectively represent connection weights of edges connecting a plurality of nodes in a neural network of the multiplier-accumulator system.

22. The system of claim 1, wherein: The plurality of resistors and capacitors are configured as a first output line of a plurality of output lines, wherein one or more other output lines of the plurality of output lines each respectively include respective plurality of resistors and respective other capacitors, the respective plurality of resistors having respective resistances, and The multiplier-accumulator circuit further includes: an output stage configured to output respective values ​​mapped to the digital values ​​generated by the time-to-digital converter as output values ​​of each of the plurality of output lines.

23. The system according to any one of claims 1, 14-16, in, The plurality of resistors and the capacitor are configured as a first output line, and wherein, after all output lines of the multiplier-accumulator circuit output all digital output values ​​of the time-to-digital converter for a plurality of input signals, the capacitor is discharged to a threshold voltage or lower until subsequent plurality of input signals are received.

24. The system according to any one of claims 1, 14-17, wherein: In response to a start signal corresponding to the receipt of the plurality of input signals, a count of a single global counter used for conversion by the time-to-digital converter is reset.

25. The system according to any one of claims 1, 14-17, wherein: In response to a start signal, corresponding resistors of the plurality of resistors corresponding to respective input lines indicated by input data including the plurality of input signals are applied with each of the plurality of input signals, and The time-to-digital converter is configured to start counting the elapsed time in response to the start signal.

26. The system according to any one of claims 1, 14, 16-17, wherein: The multiplier-accumulator circuit also includes: A switch is connected to a selected one of the plurality of resistors and is configured to, in response to input data including the plurality of input signals indicating a selected input line of a plurality of input lines including the selected one of the resistors, transmit an input voltage signal according to an input signal of the plurality of input signals to the selected one of the resistors upon receiving a start signal.

27. The system according to any one of claims 1, 15-17, wherein: The plurality of input signals are respectively provided to a plurality of input lines of the multiplier-accumulator circuit, the plurality of input lines each including a corresponding resistor among the plurality of resistors, and Wherein, the multiplier-accumulator circuit further includes: a switch connected to one end of each of the plurality of resistors, The switch is configured to transmit the power supply voltage to the corresponding resistor in response to a corresponding input signal of the plurality of input signals being a closed signal, and is configured to disconnect one end of the corresponding resistor in response to a corresponding input signal being an open signal.

28. The system of claim 27, wherein: Each of the switches is a metal oxide semiconductor field effect transistor, and a corresponding input signal is connected to a gate of the metal oxide semiconductor field effect transistor.

29. The system according to any one of claims 1, 14-17, wherein: The multiplier-accumulator circuit also includes: A switch is connected to a selected one of the plurality of resistors and is configured to apply a power supply voltage to the selected one of the resistors in response to an input signal of the plurality of input signals during a charging period of the capacitor.

30. The system of claim 29, wherein: The switch is configured to apply a reset voltage to the selected one of the resistors in response to an input signal during a discharge period of the capacitor.

31. The system of claim 1, wherein: The multiplier-accumulator circuit also includes a comparator, which is configured to output a comparison result in response to a target voltage of the capacitor exceeding a first reference voltage when the capacitor is charged with charge through a power supply voltage, and is configured to output another comparison result in response to a target voltage being less than a second reference voltage when the charge is released from the capacitor through a reset voltage, wherein the target voltage corresponds to the charge.

32. The system of claim 1, wherein: The system includes a computing device, and the multiplier-accumulator circuit is included in the computing device.

33. A multiplier-accumulator computing device, comprising: One or more multiplier-accumulator circuits, each comprising: A memory array comprising a plurality of input lines respectively intersecting a plurality of output lines, wherein each of the output lines comprises a respective capacitor configured to be charged or discharged in response to input signals respectively provided to two or more of the plurality of input lines; and A time-to-digital converter comprising a single global counter configured to generate respective output values ​​indicating the time that has elapsed since a start time, the time-to-digital converter configured to determine selected outputs from the respective output values ​​at times corresponding to respective charging or discharging times of the respective capacitors for charging or discharging, and convert each of the determined selected outputs into respective digital value results for output lines of a multiplier-accumulator circuit.

34. The multiplier-accumulator computing device of claim 33, wherein: The input signals are individual inputs to a neural network layer of a neural network of a multiplier-accumulator computing device, either as bits of the inputs or as multi-bit states of the individual inputs.

35. A method of calculation performed by a multiplier-accumulator circuit, the method of calculation comprising: receiving an input signal; charging capacitors connected to the plurality of resistors with electric charges according to corresponding voltages applied to the plurality of resistors in response to an input signal; and converting the charging time of the capacitor into a digital value by a time-to-digital converter according to the input signal, the plurality of resistors and the capacitor, The step of converting the charging time of the capacitor into the digital value comprises: generating individual output values ​​indicating the time that has elapsed since a starting moment by a single global counter in the time-to-digital converter, At a time corresponding to the charging time of the capacitor, a selected output is determined from the respective output values, and The determined selected output is converted into a digital value for the multiplier-accumulator circuit.

Images