Semiconductor dies and semiconductor wafers

Abstract

Disclosed are a semiconductor die and a semiconductor wafer. The semiconductor die includes a first pad, a switch electrically connected to the first pad, respectively, a test signal generator generating a test signal and transmitting the test signal to the switch, an internal circuit receiving a first signal through the first pad and the switch, performing an operation based on the first signal, and outputting a second signal based on a result of the operation through the switch and the first pad, and a switch controller controlling the switch such that the first pad is communicated with the test signal generator during a test operation, and such that the first pad is communicated with the internal circuit after the test operation is completed.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0107496 filed on August 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concepts described herein relate to a semiconductor device, and more particularly, to a semiconductor die that is easily bonded to another semiconductor die and a semiconductor wafer that is easily bonded to another semiconductor wafer, and a method of manufacturing the semiconductor device. Background Art

[0003] As semiconductor manufacturing technology advances, various processes for manufacturing semiconductor devices are being developed. One of the various processes includes bonding two or more semiconductor dies to realize one semiconductor device or bonding two or more semiconductor wafers to realize multiple semiconductor devices.

[0004] When bonding two or more semiconductor dies or bonding two or more semiconductor wafers, how the semiconductor dies or semiconductor wafers are aligned can determine the yield. If the semiconductor dies or semiconductor wafers are not aligned successfully, communication (or connectivity) between the semiconductor dies or communication between the semiconductor wafers may not be successfully performed.

[0005] If the connection is not successfully performed, one or more semiconductor devices implemented by bonding may have defects, which leads to a decrease in yield. Summary of the Invention

[0006] Embodiments of the inventive concept provide semiconductor dies and semiconductor wafers that facilitate easy bonding.

[0007] According to an exemplary embodiment, a semiconductor die includes: first pads; switches electrically connected to the first pads, respectively; a test signal generator configured to generate a test signal and transmit the test signal to the switch; an internal circuit configured to receive the first signal through the first pad and the switch, perform an operation based on the first signal, and output a second signal through the switch and the first pad based on a result of the operation; and a switch controller configured to control the switch so that the first pad is connected to the test signal generator during a test operation and so that the first pad is connected to the internal circuit after the test operation is completed.

[0008] According to an exemplary embodiment, a semiconductor die includes: a first pad; a switch electrically connected to the first pad; a test signal receiver configured to receive a receive signal through the first pad and the switch; an internal circuit configured to receive the first signal through the first pad and the switch, perform an operation based on the first signal, and output a second signal through the switch and the first pad based on a result of the operation; and a switch controller configured to control the switch so that the first pad is connected to the test signal receiver during a test operation and so that the first pad is connected to the internal circuit after the test operation is completed.

[0009] According to an exemplary embodiment, a semiconductor wafer includes: first pads arranged in rows along a first direction, wherein intervals between the first pads gradually increase or decrease along the first direction; test signal devices electrically connected to the first pads and configured to send or receive test signals through the first pads; and internal circuits, each of the internal circuits being one of a nonvolatile memory cell array and a peripheral device configured to access the nonvolatile memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments of the inventive concept with reference to the attached drawings.

[0011] Figure 1 A first semiconductor wafer and a second semiconductor wafer according to an embodiment of the inventive concept are shown.

[0012] Figure 2 An example is shown in which a first die and a second die are combined.

[0013] Figure 3 An example of an assembly of a first die and a second die is shown.

[0014] Figure 4 An exemplary procedure for a test operation of aligning a first die with a second die is shown.

[0015] Figure 5 Some examples of components of the first die and the second die are shown.

[0016] Figure 6 Some examples of components of the first die and the second die are shown.

[0017] Figure 7 Some examples of components of the first die and the second die are shown.

[0018] Figure 8 Some examples of components of the first die and the second die are shown.

[0019] Figure 9 and Figure 10An example is shown in which a first die and a second die, each including pads arranged at regular intervals, are misaligned.

[0020] Figure 11 and Figure 12 An example is shown in which a first die and a second die, each including pads arranged at increasing or decreasing intervals in a specific direction, are misaligned.

[0021] Figure 13 An example is shown in which pads of semiconductor dies are arranged at gradually increasing or decreasing intervals on a two-dimensional plane.

[0022] Figure 14 An example is shown in which some pads of the semiconductor die are arranged at gradually increasing or decreasing intervals on a two-dimensional plane and the remaining pads of the semiconductor die are arranged at regular intervals.

[0023] Figure 15 An example is shown in which sixth pads for a test operation are provided on horizontal and vertical cutting lines of a semiconductor wafer.

[0024] Figure 16 An example is shown in which the sixth and seventh pads for the test operation are disposed on the horizontal and vertical cutting lines of the semiconductor wafer.

[0025] Figure 17 An example is shown in which the sixth pads are provided at gradually increasing or decreasing intervals at the level of the semiconductor wafer.

[0026] Figure 18 It shows that it can be used Figure 3 Block diagram of a memory cell array implemented by one of a first internal circuit and a second internal circuit.

[0027] Figure 19 It shows Figure 18 A circuit diagram of an example of one memory block in the memory blocks.

[0028] Figure 20 It shows that it can be used Figure 3 A block diagram of a peripheral device implemented by one of a first internal circuit and a second internal circuit. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the inventive concept will be described in such detail and clarity that a person having ordinary skill in the art can easily realize the inventive concept.

[0030] Figure 1 1 and 2 , each having an upper surface and a lower surface extending in a first direction and a second direction, are shown. Figure 1, a first semiconductor die DIE1 can be manufactured on a first semiconductor wafer WAF1 by stacking a plurality of conductor layers and / or insulator layers in a third direction perpendicular to the first and second directions so that the first semiconductor die (also referred to as the "first die") DIE1 is placed within a first boundary line BDL1. The first semiconductor die DIE1 can be separated from the first semiconductor wafer WAF1 by cutting the first semiconductor wafer WAF1 along a first horizontal cutting line CLH1 corresponding to the first direction and a first vertical cutting line CLV1 corresponding to the second direction. For ease of description, spatially relative terms such as "under...", "below...", "below...", "above...", "above", etc. may be used herein to describe the relationship between one element or feature and another (other) element or feature as shown in the accompanying drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" another element or feature would then be positioned "above" the other element or feature. Thus, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0031] The second semiconductor die DIE2 can be manufactured on the second semiconductor wafer WAF2 by stacking a plurality of conductor layers and / or insulator layers in the third direction so that the second semiconductor die (also referred to as the "second die") DIE2 is positioned within the second boundary line BDL2. The second semiconductor die DIE2 can be separated from the second semiconductor wafer WAF2 by cutting the second semiconductor wafer WAF2 along second horizontal cutting lines CLH2 corresponding to the first direction and second vertical cutting lines CLV2 corresponding to the second direction.

[0032] like Figure 1 As shown by the cross CRS, the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 can be bonded / combined with each other to realize multiple semiconductor devices (e.g., non-volatile memory devices). The multiple semiconductor devices in which the first semiconductor die DIE1 and the second semiconductor die DIE2 are bonded can be obtained by bonding the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 and dicing the bonded product (e.g., by dicing the combined product of the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2).

[0033] Figure 2 FIG. 1 shows an example in which a first die DIE1 and a second die DIE2 are combined. Figure 1 and Figure 2In order to combine the first die DIE1 with the second die DIE2, the first die DIE1 may be rotated 180 degrees around the first direction. Therefore, the coordinate system of the first die DIE1 and the coordinate system of the second die DIE2 are shown independently of each other.

[0034] The first die DIE1 may include first pads PAD1 disposed on an upper surface of the first die DIE1 in a third direction. The first pads PAD1 may be disposed at regular intervals along the first direction and the second direction. The first direction, the second direction, and the third direction may be perpendicular to each other.

[0035] The second die DIE2 may include second pads PAD2 disposed on an upper surface of the second die DIE2 in the third direction. The second pads PAD2 may be disposed at regular intervals along the first and second directions.

[0036] When the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 are bonded, the first pad PAD1 of the first die DIE1 and the second pad PAD2 of the second die DIE2 are bonded, respectively. When the positions of the first pad PAD1 and the second pad PAD2 are precisely aligned (e.g., aligned within a tolerance range), bonding is successful. When the positions of the first pad PAD1 and the second pad PAD2 are not precisely aligned (e.g., aligned outside a tolerance range), bonding fails.

[0037] The semiconductor die and semiconductor wafer according to the embodiments of the inventive concept support test operations for determining the accuracy of alignment. For example, the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 can be implemented using circuits and / or patterns configured to test the accuracy of alignment. The semiconductor die and the semiconductor wafer may include pads for test operations. By performing test operations, the semiconductor die and semiconductor wafer according to the embodiments of the inventive concept can be easily and accurately aligned and bonded. For example, a test operation can be performed during the bonding of the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 to enable the first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 to be accurately bonded.

[0038] Figure 3 An example of an assembly of a first die DIE1 and a second die DIE2 is shown. Figure 3 In FIG. 1 , as an embodiment, some components of the first die DIE1 and the second die DIE2 are shown along a plane defined by a first direction and a third direction. For example, Figure 3 A block diagram of certain components of a first die DIE1 and a second die DIE2 is shown, and Figure 3 Some components (eg, pads and dies) shown in FIG. 1 may correspond to cross-sectional views. Figures 1 to 3, the first die DIE1 may include a first internal circuit IC1, a test signal generator TSG, a first switch controller SC1, a plurality of first switches SW1a to SW1d, a plurality of first pads PAD1a to PAD1d, and a third pad PAD3.

[0039] The first internal circuit IC1 may include components for performing operations corresponding to the design purpose of the first die DIE1. For example, the first internal circuit IC1 may include components for referring to Figure 18 and Figure 19 The memory cell array 100 will be described with reference to Figure 20 The peripheral device 200 accessing the memory cell array 100 is described. The first internal circuit IC1 may be electrically connected to the first switches SW1a to SW1d.

[0040] The test signal generator TSG may receive a first test command TC1 from the third pad PAD3. In response to the first test command TC1, the test signal generator TSG may send a test signal TS to the first switches SW1a to SW1d. The test signals TS sent from the test signal generator TSG to the first switches SW1a to SW1d may be voltages of the same level or currents of the same amount. The first test command TC1 may be input to the third pad PAD3 from an external device disposed outside the first die DIE1 and the second die DIE2. The third pad PAD3 may be disposed on a surface of the first die DIE1 that is opposite to a surface on which the first pads PAD1a to PAD1d coupled to the second die DIE2 are disposed. For example, the third pad PAD3 may be disposed on the lower surface of the first die DIE1. For example, the upper and lower surfaces of the first die DIE1 may be flat surfaces extending parallel to each other.

[0041] The first switch controller SC1 can output a first selection signal SEL1 for controlling the first switches SW1a to SW1d. For example, during a test operation for alignment and bonding, the first switch controller SC1 can control the first switches SW1a to SW1d so that the first pads PAD1a to PAD1d are connected to the test signal generator TSG. For example, the first switch controller SC1 can control the first switches SW1a to SW1d to allow the first pads PAD1a to PAD1d to be connected to the test signal generator TSG sequentially. In certain embodiments, the first switch controller SC1 can control the first switches SW1a to SW1d to allow the first pads PAD1a to PAD1d to be connected to the test signal generator TSG simultaneously or randomly.

[0042] After the test operation is completed and the first die DIE1 is aligned and / or bonded to the second die DIE2, the first switch controller SC1 may control the first switches SW1a to SW1d so that the first pads PAD1a to PAD1d are connected to the first internal circuit IC1. The first pads PAD1a to PAD1d may correspond to Figure 2 The first pad is PAD1.

[0043] The second die DIE2 may include a second internal circuit IC2 , a test signal receiver TSR, a second switch controller SC2 , a plurality of second switches SW2 a to SW2 d , a plurality of second pads PAD2 a to PAD2 d , and a fourth pad PAD4 .

[0044] The second internal circuit IC2 may include components for performing operations corresponding to the design purpose of the second die DIE2. For example, the second internal circuit IC2 may include components for Figure 18 and Figure 19 The memory cell array 100 described herein may refer to Figure 20 The peripheral device 200 accessing the memory cell array 100 is described. The second internal circuit IC2 may be electrically connected to the second switches SW2a to SW2d.

[0045] The test signal receiver TSR can receive a second test command TC2 from the fourth pad PAD4. In response to the second test command TC2, the test signal receiver TSR can receive a receive signal RS from the second switches SW2a to SW2d. The second test command TC2 can be input to the fourth pad PAD4 from an external device disposed outside the first die DIE1 and the second die DIE2. The fourth pad PAD4 can be disposed on a surface of the second die DIE2 that is opposite to the surface on which the second pads PAD2a to PAD2d bonded to the first die DIE1 are disposed. For example, the fourth pad PAD4 can be disposed on the lower surface of the second die DIE2. For example, the upper and lower surfaces of the second die DIE2 can be flat surfaces extending parallel to each other.

[0046] When receiving the reception signal RS in response to the second test command TC2 , the test signal receiver TSR may output the reception signal RS to the external device through the fourth pad PAD4 after processing the reception signal RS or without processing the reception signal RS.

[0047] The second switch controller SC2 may output a second selection signal SEL2 for controlling the second switches SW2a to SW2d. For example, in a test operation for alignment and bonding, the second switch controller SC2 may control the second switches SW2a to SW2d so that the second pads PAD2a to PAD2d are connected to the test signal receiver TSR.

[0048] After the test operation is completed and the second die DIE2 is aligned and / or bonded to the first die DIE1, the second switch controller SC2 may control the second switches SW2a to SW2d so that the second pads PAD2a to PAD2d are connected to the second internal circuit IC2. Figure 2 The second pad is PAD2.

[0049] In some embodiments, one or more of the first die DIE1 and the second die DIE2 may be formed as a controller. When one of the first die DIE1 and the second die DIE2 is implemented as a controller, in addition to Figure 3 In addition to the pads shown in FIG, the die corresponding to the controller may include additional pads for communicating with an external host device (e.g., a controller that controls a nonvolatile memory device). In some embodiments, the additional pads may be provided on the surface on which the third pad PAD3 or the fourth pad PAD4 is provided.

[0050] In some embodiments, during a test operation, the die implemented as a controller among the first die DIE1 and the second die DIE2 may receive power through the pad designated to receive power from the external host device among the additional pads described above. The die implemented as a controller may supply the received power to the other die.

[0051] For another example, during a test operation, each of the first die DIE1 and the second die DIE2 may further include an additional pad configured to receive power for the test operation. In this case, power for the test operation may not be supplied to the first internal circuit IC1 and the second internal circuit IC2. The additional pad may be provided on the surface on which the third pad PAD3 or the fourth pad PAD4 is provided.

[0052] In some embodiments, the third pad PAD3, the fourth pad PAD4, or an additional pad for receiving power for the test operation can be used for another purpose after the test operation is completed. For example, the third pad PAD3, the fourth pad PAD4, or an additional pad can be configured to exchange signals with an external host device or a debugging device.

[0053] In this case, similar to the first switch controller SC1 and the first switches SW1a to SW1d or similar to the second switch controller SC2 and the second switches SW2a to SW2d, after the test operation is completed, a switching element that electrically connects the third pad PAD3, the fourth pad PAD4 or an additional pad (e.g., an additional pad) to the first internal circuit IC1 or the second internal circuit IC2 may be added.

[0054] Figure 4An exemplary procedure of a test operation of aligning the first die DIE1 with the second die DIE2 is shown. An external device (eg, a test device or an alignment and bonding device) may play a leading role in the alignment and test operation.

[0055] Reference Figure 3 and Figure 4 In operation S110 , the external device may align the first die DIE1 with the second die DIE2 , and in operation S120 , the external device may send a first test command TC1 to the first die DIE1 and may send a second test command TC2 to the second die DIE2 .

[0056] In operation S130, the first die DIE1 may transmit a test signal TS through the first switches SW1a to SW1d and the first pads PAD1a to PAD1d in response to the first test command TC1. The second die DIE2 may receive a reception signal RS through the second pads PAD2a to PAD2d and the second switches SW2a to SW2d in response to the second test command TC2. For example, with respect to the second die DIE2, the reception signal may begin to change in response to receiving (or transmitting) the first test command TC1.

[0057] In operation S140, the second die DIE2 may output the received signal RS to an external device as a test result TR after processing the received signal RS or without processing the received signal RS. In operation S150, the external device may determine whether the first die DIE1 and the second die DIE2 are accurately aligned (e.g., within an allowable error range).

[0058] In an embodiment, the first die DIE1 may transmit a voltage of a specific level or a current of a specific amount as a test signal TS. When the first pads PAD1a to PAD1d are precisely aligned with the second pads PAD2a to PAD2d, they may receive a voltage of the same specific level (or a level reduced within a tolerance) or a current of the same specific amount (or an amount reduced within a tolerance) as a reception signal RS.

[0059] When the first pads PAD1a to PAD1d are not precisely aligned with the second pads PAD2a to PAD2d, a voltage of a level smaller than a specific level (or a level reduced to a degree exceeding the allowable error) or a current of a bit quantitatively smaller amount (or an amount reduced to a degree exceeding the allowable error) is received as the received signal RS.

[0060] The external device can determine whether the first die DIE1 and the second die DIE2 are accurately aligned (eg, within an allowable error range) by comparing the voltage level or current amount of the reception signal RS with an expected value (eg, the above-mentioned specific level or specific amount).

[0061] When the first die DIE1 and the second die DIE2 are not precisely aligned, an external device may align the first die DIE1 with the second die DIE2 again in operation S110. For example, the external device may calculate an alignment error based on a difference between a voltage level or a current amount of the received signal RS and an expected value, and may align the first die DIE1 with the second die DIE2 again based on the calculated alignment error.

[0062] The external device may repeat operations S110 to S150 until the first die DIE1 and the second die DIE2 are precisely aligned. When determining that the first die DIE1 and the second die DIE2 are precisely aligned, the external device may set the first switch controller SC1 and the second switch controller SC2 to a test completion mode in operation S160.

[0063] For example, the external device may inform the first and second switch controllers SC1 and SC2 of the completion of the test operation by transmitting a test completion command to the third and fourth pads PAD3 and PAD4 .

[0064] As another example, each of the first switch controller SC1 and the second switch controller SC2 may include a laser fuse. An external device may set the first switch controller SC1 and the second switch controller SC2 to a test completion mode by cutting the laser fuse. For example, the laser fuse may be a conductor pattern / wiring designed to be cut / separated by exposure to a laser beam to become an open circuit.

[0065] As another example, each of the first switch controller SC1 and the second switch controller SC2 may include an electrical fuse. An external device may set the first switch controller SC1 and the second switch controller SC2 to the test completion mode by changing the state of the electrical fuse via a method of controlling the electrical fuses of the first die DIE1 and the second die DIE2. For example, the electrical fuse may be a conductor pattern / wiring designed to be cut / separated by flowing a predetermined current through the electrical fuse, thereby opening the electrical fuse, or a storage element that stores a logic value (e.g., a resistance value) that is changed by flowing the predetermined current through the electrical fuse, thereby opening the electrical fuse.

[0066] Before or after operation S160, the first die DIE1 and the second die DIE2 may be bonded after precisely aligning the first die DIE1 and the second die DIE2. For example, the external device may bond the first die DIE1 and the second die DIE2 by bonding the first pads PAD1a to PAD1d and the second pads PAD2a to PAD2d, respectively.

[0067] Figure 5Some examples of components of a first die DIE1a and a second die DIE2a are shown. Figure 5 In FIG. 1 , as an example, certain components of the first die DIE1a and the second die DIE2a are shown along a plane defined by a first direction and a third direction. For example, Figure 5 A block diagram showing certain components of a first die DIE1a and a second die DIE2a is shown, and Figure 5 Some components (e.g., pads and dies) shown in FIG may correspond to cross-sectional views. Figure 3 The first die DIE1 is compared to the Figure 5 In the first die DIE1a, the first pad PAD1d may be directly connected to the first internal circuit IC1. For example, there may be no intermediate component between the first pad PAD1d and the first internal circuit IC1 except for a conductor pattern electrically connecting the first pad PAD1d and the first internal circuit IC1.

[0068] In addition, with Figure 3 Compared with the second die DIE2, Figure 5 In the second bare chip DIE2a, the second pad PAD2d can be directly connected to the second internal circuit IC2. For example, except for the conductor pattern that electrically connects the second pad PAD2d and the second internal circuit IC2, there may be no intermediate components between the second pad PAD2d and the second internal circuit IC2. For example, one or more pads connected to the internal circuit may be used for alignment test operations, while other pads may not be used for alignment test operations.

[0069] In addition to the first pad PAD1d being directly connected to the first internal circuit IC1 and the second pad PAD2d being directly connected to the second internal circuit IC2, Figure 5 The first die DIE1a and the second die DIE2a are Figure 3 The first bare chip DIE1 and the second bare chip DIE2 are identical. Therefore, additional description will be omitted to avoid redundancy. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, the element may be directly connected or directly coupled to the other element or directly on the other element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "in contact with" another element or "in contact with" another element, there is no intermediate element. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent to" versus "directly adjacent to," etc.).

[0070] Figure 6 Some examples of components of a first die DIE1b and a second die DIE2b are shown. Figure 6 In FIG. 1 , as an embodiment, a component of a first die DIE1 b and a second die DIE2 b is shown, which is cut along a plane defined by a first direction and a third direction. For example, Figure 6 A block diagram showing certain components of a first die DIE1b and a second die DIE2b is shown, and Figure 6 Some components (e.g., pads and dies) shown in FIG may correspond to cross-sectional views. Figure 3 The first die DIE1 is compared to the Figure 6 In the first die DIE1b, the first pads PAD1a to PAD1d may be directly connected to the first internal circuit IC1. For example, there may be no intermediate components between the first pads PAD1a to PAD1d and the first internal circuit IC1 except for corresponding conductor patterns electrically connecting the first pads PAD1a to PAD1d to the first internal circuit IC1.

[0071] The first die DIE1b may further include an additional first pad PAD1e for a test operation. A test signal generator TSG of the first die DIE1b may receive a first test command TC1 from the third pad PAD3 and may transmit a test signal TS to the additional first pad PAD1e in response to the first test command TC1.

[0072] and Figure 3 Compared with the second die DIE2, Figure 6 In the second die DIE2b, the second pads PAD2a to PAD2d can be directly connected to the second internal circuit IC2. For example, other than the conductor pattern electrically connecting the second pads PAD2a to PAD2d and the second internal circuit IC2, there may be no intermediate components connected between the second pads PAD2a to PAD2d and the second internal circuit IC2. The second die DIE2b may further include an additional second pad PAD2e for testing operations.

[0073] The test signal receiver TSR of the second die DIE2b may receive the second test command TC2 from the fourth pad PAD4 and may receive a reception signal RS from the additional second pad PAD2e in response to the second test command TC2. The test signal receiver TSR may output a test result TR through the fourth pad PAD4.

[0074] Figure 6 An additional first pad PAD1e and an additional second pad PAD2e are shown for test operations. However, two or more pads may be used for each die for test operations. Furthermore, a pad designated to receive power for test operations may be added to the first die DIE1b or the second die DIE2b.

[0075] Figure 7Some examples of components of a first die DIE1c and a second die DIE2c are shown. Figure 7 In FIG. 1 , as an embodiment, an assembly of a first die DIE1c and a second die DIE2c is shown, taken along a plane defined by a first direction and a third direction. For example, Figure 7 A block diagram showing certain components of a first die DIE1c and a second die DIE2c is shown, and Figure 7 Some components (e.g., pads and dies) shown in FIG may correspond to cross-sectional views. Figure 5 Compared with the first die DIE1a, Figure 7 The first die DIE1c may not include Figure 5 The test signal generator TSG may receive a test command TC through at least one of the first pads PAD1a to PAD1d and at least one switch (eg, SW1c) corresponding to the at least one pad among the first switches SW1a to SW1c.

[0076] and Figure 5 Compared with the second die DIE2a, Figure 7 The test signal receiver TSR of the second die DIE2c can receive the test command TC through the fourth pad PAD4. The test signal receiver TSR can send the test command TC to the first die DIE1c through a switch (e.g., SW2c) among the second switches SW2a to SW2c corresponding to the at least one pad of the first die DIE1c and a pad among the second pads PAD2a to PAD2d corresponding to the at least one pad of the first die DIE1c.

[0077] In an embodiment, the second die DIE2c may receive power for the test operation through a fourth pad PAD4, through another pad designated as receiving power for the test operation, or through a pad for communicating with an external host device. For example, the second die DIE2c may include additional pads designated as receiving power signals from an external device (e.g., an external host device) and / or communicating with an external device (e.g., an external host device). The second die DIE2c may supply power for the test operation received from the external device to the first die DIE1c through at least one of the second pads PAD2a to PAD2d or through a pad designated to a power source (during the test operation or even after the test operation is completed).

[0078] In the examples, as referenced Figure 3 As described, the first die DIE1c and the second die DIE2c may be modified so that all pads connected to the internal circuits are used for the test operation.

[0079] Figure 8Some examples of components of a first die DIE1d and a second die DIE2d are shown. Figure 8 In FIG. 1 , as an example, a component of a first die DIE1d and a second die DIE2d is shown, which is cut along a plane defined by a first direction and a third direction. For example, Figure 8 A block diagram showing certain components of a first die DIE1d and a second die DIE2d is shown, and Figure 8 Some components (e.g., pads and dies) shown in FIG may correspond to cross-sectional views. Figure 6 Compared with the first die DIE1b, Figure 8 The first die DIE1d may not include Figure 6 The test signal generator TSG may receive the test command TC through the additional first pad PAD1e.

[0080] and Figure 6 Compared with the second die DIE2b, Figure 8 The test signal receiver TSR of the second die DIE2d may receive the test command TC through the fourth pad PAD4. The test signal receiver TSR may send the test command TC to the first die DIE1d through the additional second pad PAD2e.

[0081] In an embodiment, the second die DIE2d can receive power for the test operation through a fourth pad PAD4, through another pad designated to receive power for the test operation, or through a pad for communicating with an external host device. For example, the second die DIE2d may include additional pads designated to receive power signals from an external device (e.g., an external host device) and / or communicate with an external device (e.g., an external host device). The second die DIE2d can supply the power for the test operation received from the external device through the pad designated to the power supply to the first die DIE1d (during the test operation or even after the test operation is completed).

[0082] Figure 9 and Figure 10 An example is shown in which a first die DIE1 and a second die DIE2, each including pads arranged at regular intervals, are misaligned. Figure 9 As shown in FIG, in the case where the first pad PAD1 of the first die DIE1 and the second pad PAD2 of the second die DIE2 are not aligned, each reception signal RS (refer to FIG) received at the second die DIE2 Figure 3 and Figures 5 to 8 However, this does not indicate in which direction the first die DIE1 and the second die DIE2 are misaligned.

[0083] like Figure 10As shown in FIG, in the case where the first pad PAD1 of the first die DIE1 and the second pad PAD2 of the second die DIE2 are misaligned, it may be impossible to obtain the misalignment information. For example, the misalignment direction may not be detected. In some cases, the misalignment distance may not be detected. Therefore, when the first die DIE1 is aligned with the second die DIE2 again (when the first die DIE1 is aligned with the second die DIE2 again), the misalignment information may not be obtained. For example, the misalignment direction may not be detected. In some cases, the misalignment distance may not be detected. Figure 4 (When operation S150 in the process proceeds to operation S110), alignment may be repeatedly performed on the external device taking into account all situations regarding the misalignment direction. This results in a decrease in alignment and bonding rate. For example, the lack of misalignment information may delay and / or complicate the realignment process.

[0084] Figure 11 and Figure 12 An example is shown in which a first die DIE1 and a second die DIE2, each including pads arranged at increasing or decreasing intervals along a specific direction, are misaligned. Figure 11 and Figure 12 As shown in FIG, the intervals between the first pads PAD1 of the first die DIE1 may gradually increase along the first direction. The intervals between the second pads PAD2 of the second die DIE2 may gradually increase along the first direction.

[0085] like Figure 11 As shown in FIG, the second die DIE2 can be displaced relative to the first die DIE1 along the first direction. In this case, the first pads PAD1 are connected to the pads of the second pads PAD2 that are adjacent to the pads designed to be connected in the first direction. The remaining pads of the first pads PAD1 and the second pads PAD2 may not be connected to each other.

[0086] like Figure 12 As shown in , the first die DIE1 can be shifted relative to the second die DIE2 along a first direction. In this case, as Figure 12 As shown in FIG, some of the first pads PAD1 may be connected to some of the second pads PAD2. Other first pads PAD1 and second pads PAD2 may not be connected to each other. For example, when the width of the first pad PAD1 and the width of the second pad PAD2 are smaller than the distance between the pads, some of the first pads PAD1 and the second pads PAD2 may not be connected to each other.

[0087] When the first pad PAD1 and the second pad PAD2 are arranged at gradually increasing or decreasing intervals along a specific direction, the reception signal RS can be received through different pads according to the direction in which the first die DIE1 and the second die DIE2 are misaligned. Therefore, directional information for realignment can be obtained from the reception signal RS, and alignment can be easily corrected and bonding can be performed efficiently.

[0088] The external device can store the misalignment direction and realignment distance corresponding to the level or amount of the received signal RS in a table. Referring to the table, the test device or the alignment and bonding device can obtain the misalignment direction and distance and align and bond the semiconductor die and the semiconductor wafer.

[0089] As reference Figure 10 As described above, to prevent the first pads PAD1 and the second pads PAD2 from being completely separated from each other, the interval between at least two closest pads among the first pads PAD1 may be smaller than the width of each first pad PAD1. Similarly, the interval between at least two closest pads among the second pads PAD2 corresponding to the at least two pads may be smaller than the width of each second pad PAD2.

[0090] Figure 13 An example is shown in which the pads of the semiconductor die DIE1 / DIE2 are arranged at gradually increasing or decreasing intervals on a two-dimensional plane. Figure 13 , the first pad PAD1 and the second pad PAD2 may be disposed at gradually increasing intervals along the first direction. In addition, the first pad PAD1 and the second pad PAD2 may be disposed at gradually increasing intervals along the second direction.

[0091] When the first pad PAD1 and the second pad PAD2 are Figure 13 When configured as shown in , the external device can obtain the realignment direction and distance expressed as vectors relative to the coordinate system of the first direction and the second direction. For example, based on the signals transmitted through the first pad PAD1 and the second pad PAD2 and received by the test signal receiver TSR, the external device can calculate the misalignment direction and misalignment distance, respectively, in combination with the position information of the first pad PAD1 and / or the second pad PAD2. For example, the position information of the first pad PAD1 and / or the second pad PAD2 can be the coordinate values ​​of the first pad PAD1 and the second pad PAD2.

[0092] Figure 14 An example is shown in which some pads of the semiconductor die DIE1 / DIE2 (e.g., first pad PAD1 and second pad PAD2) are arranged at gradually increasing or decreasing intervals on a two-dimensional plane and the remaining pads of the semiconductor die DIE1 / DIE2 (e.g., fifth pad PAD5) are arranged at regular intervals.

[0093] For example, the level or amount of the reception signal transmitted through the fifth pad PAD5 arranged at regular intervals can be used by an external device to determine the distance for realignment. For example, the accuracy of the distance for realignment can be improved by combining the level or amount of the reception signal transmitted through the first pad PAD1, the second pad PAD2, and the fifth pad PAD5. For example, the first pad PAD1 and the second pad PAD2 can be arranged at the same level as the distance for realignment. Figure 13The first pad PAD1 and the second pad PAD2 are used in the same manner as explained or in a similar manner.

[0094] Figure 15 An example is shown in which the sixth pad PAD6 for the test operation is arranged on the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2 of the semiconductor wafer WAF1 / WAF2. For example, the cutting lines described herein may include a certain width. For example, the cutting lines may include an extended area between the semiconductor dies arranged in parallel in a direction. For example, the cutting lines may be an extended area along which the cutting / dicing process is performed so that the semiconductor dies are separated from each other. Figure 15 , the sixth pads PAD6 may be disposed between adjacent semiconductor dies DIE1 / DIE2 such that intervals between the sixth pads PAD6 gradually increase along the first direction and gradually increase along the second direction.

[0095] The sixth pad PAD6 may be implemented as a separate device from the semiconductor die DIE1 / DIE2. In an embodiment, the sixth pad PAD6 may correspond to Figure 6 The additional first pad PAD1e or the additional second pad PAD2e may correspond to Figure 8 For example, the sixth pad PAD6 can perform the same Figure 6 and Figure 8 The additional first pad PAD1e and / or the additional second pad PAD2e may have similar functions or the same functions. For example, the components for the test operation corresponding to the sixth pad PAD6 may be implemented on the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2. For example, the sixth pad PAD6 and its related components (e.g., cooperative components) may be formed on the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2. Figure 15 On the horizontal cutting lines CLH1 / CLH2 and vertical cutting lines CLV1 / CLV2 shown in FIG.

[0096] In the process of separating the semiconductor die DIE1 / DIE2 from the semiconductor wafer and / or separating the semiconductor die DIE1 / DIE2 from each other, the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2 can be removed by a dicing process. Therefore, the sixth pad PAD6 used for the test operation and corresponding components can also be removed by the dicing process. For example, some or all components related to the test operation may not remain in the separated semiconductor die DIE1 / DIE2.

[0097] Figure 16An example is shown in which the sixth pad PAD6 and the seventh pad PAD7 for a test operation are disposed on the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2 of the semiconductor wafers WAF1 / WAF2. Figure 16 , the sixth pads PAD6 can be arranged between adjacent semiconductor dies DIE1 / DIE2 so that the intervals between the sixth pads PAD6 gradually increase along the first direction and gradually increase along the second direction. The seventh pads PAD7 can be arranged at regular intervals along the first direction and the second direction. For example, Figure 15 and Figure 16 The sixth pad PAD6 can be used with Figure 13 and Figure 14 The first pad PAD1 and / or the second pad PAD2 described above are similarly used for the test operation, and the seventh pad PAD7 can be used in conjunction with the test operation described above. Figure 14 The fifth pad PAD5 is similarly described for use in a test operation.

[0098] exist Figure 15 and Figure 16 In the example shown in FIG, the sixth pads PAD6 are arranged on the horizontal cutting lines CLH1 / CLH2 and the vertical cutting lines CLV1 / CLV2 between the four adjacent semiconductor dies DIE1 / DIE2, so that the intervals between the sixth pads PAD6 gradually increase or decrease. In some embodiments, the sixth pads PAD6 can be arranged at gradually increasing or decreasing intervals within a large range.

[0099] Figure 17 An example is shown in which the sixth pads PAD6 are arranged at gradually increasing or decreasing intervals at the level of the semiconductor wafers WAF1 / WAF2. Figure 17 , the sixth pad PAD6 can be set in the area of ​​a specific / certain semiconductor die of the semiconductor wafer WAF1 / WAF2. For example, Figure 17 The sixth pad PAD6 may be disposed on certain semiconductor dies or between certain semiconductor dies, as described in the previous embodiments.

[0100] As reference Figure 13 As described above, the sixth pad PAD6 can be arranged on the semiconductor wafer WAF1 / WAF2 along the second direction and the first direction related thereto at intervals that gradually increase or decrease. Figure 15 As described, the sixth pad PAD6 may be repeatedly disposed in two or more regions on the semiconductor wafer WAF1 / WAF2 .

[0101] As reference Figure 16As described, the seventh pad PAD7 may be disposed at regular intervals in regions of specific / certain semiconductor dies of the semiconductor wafer WAF1 / WAF2 . The seventh pad PAD7 may be repeatedly disposed in two or more regions on the semiconductor wafer WAF1 / WAF2 .

[0102] Figure 18 It shows that it can be used Figure 3 A block diagram of a memory cell array 100 implemented by one of a first internal circuit IC1 and a second internal circuit IC2 is shown. Figure 18 , the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz.

[0103] Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to at least one ground select line GSL, a word line WL, and at least one string select line SSL. Some of the word lines WL may serve as dummy word lines. Each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL. Multiple memory blocks BLK1 to BLKz may be commonly connected to a plurality of bit lines BL.

[0104] In an embodiment, each of the plurality of memory blocks BLK1 to BLKz may correspond to a unit of erase operation for information stored in the memory blocks BLK1 to BLKz. For example, information stored in memory cells belonging to each memory block may be erased simultaneously. In certain embodiments, each of the plurality of memory blocks BLK1 to BLKz may include a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of erase operation for information stored in the plurality of sub-blocks. For example, information stored in memory cells of each sub-block may be erased simultaneously.

[0105] The string selection line SSL, word line WL, ground selection line GSL and bit line BL can be connected to another semiconductor die through the pad PAD. For example, all or part of the string selection line SSL, word line WL, ground selection line GSL and bit line BL can be connected to the switch or directly connected to the reference Figure 3 and Figures 5 to 8 Pad as described.

[0106] Figure 19 yes Figure 18 1 to BLKz. Figure 19 , multiple cell strings CS may be arranged in rows and columns along the first direction, the second direction, and the third direction on the substrate SUB. The multiple cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. Figure 19, the position of the substrate SUB and its arrangement direction are shown to help understand the structure of the memory block BLK1.

[0107] Multiple rows of cell strings can be commonly connected to a ground select line GSL, and each row of cell strings can be connected to a corresponding one of the first to fourth upper string select lines SSLu1 to SSLu4 and a corresponding one of the first to fourth lower string select lines SSLl1 to SSLl4. Each column of cell strings can be connected to a corresponding one of the first to fourth bit lines BL1 to BL4. For simplicity and clarity of illustration, cell strings connected to the second and third string select lines SSLl2 and SSLu2 and SSLl3 and SSLu3 are depicted with thin lines.

[0108] Each cell string may include: at least one ground selection transistor GST, connected to a ground selection line GSL; a first dummy memory cell DMC1, connected to a first dummy word line DWL1; a first memory cell MC1 to a tenth memory cell MC10, connected to a first word line WL1 to a tenth word line WL10, respectively; a second dummy memory cell DMC2, connected to a second dummy word line DWL2; and a lower string selection transistor SSTl and an upper string selection transistor SSTu, connected to corresponding lower string selection lines and upper string selection lines, respectively.

[0109] In each cell string, the ground selection transistor GST, the first dummy memory cell DMC1, the first to tenth memory cells MC1 to MC10, the second dummy memory cell DMC2, the lower string selection transistor SSTl and the upper string selection transistor SSTu can be connected in series along a third direction perpendicular to the substrate SUB (or referred to as the "vertical direction") and can be stacked sequentially along the third direction perpendicular to the substrate SUB.

[0110] The memory block BLK1 can be configured as a 3D memory array. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells MC (e.g., MC1-MC10), each of which has an active area disposed on a silicon substrate and circuitry associated with the operation of those memory cells MC. The circuitry associated with the operation of the memory cells MC can be located on or within such a substrate. As used herein, the term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the 3D memory array.

[0111] In an embodiment of the inventive concept, a 3D memory array includes a vertical cell string CS (or NAND string) vertically oriented such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Each cell string may also include at least one select transistor positioned above a memory cell MC. The at least one select transistor may have the same structure as the memory cell MC and may be formed uniformly with the memory cell MC.

[0112] The following patent documents, incorporated herein by reference, describe suitable configurations for a three-dimensional memory array in which the three-dimensional memory array is structured into multiple levels with word lines and / or bit lines shared between levels: U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0113] Figure 20 It shows that it can be used Figure 3 FIG. 1 is a block diagram of a peripheral device 200 implemented by one of a first internal circuit IC1 and a second internal circuit IC2. Figure 20 , the peripheral device 200 may include a row decoder block 210 , a page buffer block 220 , a data input and output block 230 , a buffer block 240 , and a control logic block 250 .

[0114] The row decoder block 210 may be connected to the ground selection line GSL, the word line WL, and the string selection line SSL. The row decoder block 210 may operate under the control of the control logic block 250.

[0115] The row decoder block 210 may decode the row address RA received from the buffer block 240 and may control voltages to be applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded row address.

[0116] The page buffer block 220 may be connected to a plurality of bit lines BL. The page buffer block 220 may be connected to the data input and output block 230 through a plurality of data lines DL. The page buffer block 220 may operate under the control of the control logic block 250.

[0117] In a write operation, the page buffer block 220 may store data to be written. The page buffer block 220 may apply a voltage to a plurality of bit lines BL based on the stored data. In a read operation or a verification read operation performed in a write operation or an erase operation, the page buffer block 220 may sense the voltage of the bit line BL and may store the sensing result.

[0118] The data input and output block 230 may be connected to the page buffer block 220 through a plurality of data lines DL. The data input and output block 230 may receive a column address CA from the buffer block 240. The data input and output block 230 may output data DATA read by the page buffer block 220 to the buffer block 240 according to the column address CA. The data input and output block 230 may provide the data DATA received from the buffer block 240 to the page buffer block 220 based on the column address CA.

[0119] The buffer block 240 may receive a command CMD and an address ADDR from an external device through the first channel CH1 and may exchange data "DATA" with the external device. The buffer block 240 may operate under the control of the control logic block 250. The buffer block 240 may transmit the command CMD to the control logic block 250. The buffer block 240 may transmit the row address RA of the address ADDR to the row decoder block 210 and may transmit the column address CA of the address ADDR to the data input and output block 230. The buffer block 240 may exchange data "DATA" with the data input and output block 230.

[0120] The control logic block 250 may exchange a control signal CTRL with an external device through the second channel CH2. The control logic block 250 may allow the buffer block 240 to route a command CMD, an address ADDR, and data DATA.

[0121] The control logic block 250 may decode the command CMD received from the buffer block 240 and may control the peripheral device 200 according to the decoded command. For example, the control logic block 250 may specify the order of program operations in which the row decoder block 210 and the page buffer block 220 program the memory cells based on differences in the structures and different characteristics of the memory cells.

[0122] The string selection line SSL, the word line WL, the ground selection line GSL, and the bit line BL can be connected to another semiconductor die through the pad PAD. For example, all or part of the string selection line SSL, the word line WL, the ground selection line GSL, and the bit line BL can be connected to the switch or can be directly connected to the reference Figure 3 and Figures 5 to 8 The pad described.

[0123] Including reference Figure 18 and Figure 19 The memory cell array 100 of the semiconductor die and the memory cell array 100 includes reference Figure 20 When the semiconductor die of the peripheral device 200 is combined, a non-volatile memory device (eg, a three-dimensional NAND flash memory device) can be implemented.

[0124] The signal lines of the first channel CH1 and the second channel CH2 can be connected to pads for communicating with an external host device (e.g., a controller for controlling the nonvolatile memory device). When the controller is connected to the nonvolatile memory device combined with the first die DIE1 and the second die DIE2, a memory device such as a memory card or a solid-state drive can be implemented.

[0125] In the above embodiments, the components of the semiconductor wafer and semiconductor die are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc. can be used to distinguish components from each other without limiting the inventive concept. For example, the terms "first," "second," "third," etc. do not imply any form of sequential or numerical meaning.

[0126] In the above embodiments, the components of the embodiments according to the inventive concept are described using blocks. Blocks can be implemented using various hardware devices (such as integrated circuits, application-specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, blocks can include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0127] According to the inventive concept, the semiconductor die and the semiconductor wafer include pads that support alignment during bonding. Therefore, the semiconductor die and the semiconductor wafer provided herein support easy bonding of the semiconductor die and / or the semiconductor wafer.

[0128] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A semiconductor die, comprising: First pad; switches, electrically connected to the first pads respectively; a test signal generator configured to generate a test signal and send the test signal to the switch; an internal circuit configured to receive a first signal through the first pad and the switch, perform an operation based on the first signal, and output a second signal through the switch and the first pad based on a result of the operation; as well as The switch controller is configured to control the switch so that the first pad is connected to the test signal generator during the test operation and the first pad is connected to the internal circuit after the test operation is completed.

2. The semiconductor die according to claim 1, wherein The test signals sent from the test signal generator to the switches are the same level of voltage or the same amount of current.

3. The semiconductor die of claim 1 , further comprising: The second pad is electrically connected to the test signal generator, The test signal generator is configured to send a test signal according to a test command received through the second pad.

4. The semiconductor die of claim 1 , further comprising: The second pad is configured to supply power to the test signal generator and the switch controller in a test operation.

5. The semiconductor die according to claim 1, wherein The switch controller includes laser fuses, Wherein, when the laser fuse is in a connected state, the switch controller controls the switch so that the test signal generator and the first pad are connected to each other; When the laser fuse is in an open state, the switch controller controls the switch so that the internal circuit and the first pad are connected to each other. The semiconductor die according to claim 1 , wherein: The switch controller includes an electric fuse, wherein, when the electrical fuse is in the first state, the switch controller controls the switch so that the test signal generator and the first pad are connected to each other; When the electrical fuse is in the second state, the switch controller controls the switch so that the internal circuit and the first pad are connected to each other.

7. The semiconductor die of claim 1 , further comprising: The second pad is directly connected to the internal circuit.

8. The semiconductor die according to claim 1, wherein The first pads are arranged in a row along a first direction, and intervals between the first pads gradually increase or decrease along the first direction.

9. The semiconductor die according to claim 1, wherein A spacing between at least two closest pads among the first pads is smaller than a width of each of the at least two closest pads.

10. The semiconductor die according to claim 1, wherein The internal circuit includes a memory cell electrically connected to a string selection line, a word line, a ground selection line, and a bit line, and At least some of the string selection lines, the word lines, the ground selection lines, and the bit lines are electrically connected to the first pad through the switch.

11. The semiconductor die of claim 1 , further comprising: The second pad and the third pad are configured to communicate with an external device, and Among them, the internal circuit includes: a buffer block configured to receive a row address, a column address, and a command from an external device through the second pad, and to exchange read data or write data with the external device through the second pad; a row decoder block electrically connected to the string selection line, the word line, and the ground selection line, and configured to receive a row address from the buffer block and adjust voltages of the string selection line, the word line, and the ground selection line based on the row address; a page buffer block electrically connected to the bit lines and configured to adjust voltages of the bit lines based on write data stored in the page buffer block in a write operation and store the voltages of the bit lines therein as read data in a read operation; a data input and output block electrically connected between the page buffer block and the buffer block and configured to receive a column address from the buffer block and exchange write data and read data between the page buffer block and the buffer block based on the column address; and The control logic block is configured to receive a control signal from an external device through a third pad, receive a command from the buffer block, and control a write operation and a read operation based on the command and the control signal.

12. A semiconductor die, comprising: First pad; a switch electrically connected to the first pad; a test signal receiver configured to receive a reception signal through the first pad and the switch; an internal circuit configured to receive a first signal through the first pad and the switch, perform an operation based on the first signal, and output a second signal through the switch and the first pad based on a result of the operation; as well as The switch controller is configured to control the switch so that the first pad is connected to the test signal receiver during the test operation and so that the first pad is connected to the internal circuit after the test operation is completed.

13. The semiconductor die of claim 12, further comprising: The second pad is electrically connected to the test signal receiver, The received signal varies according to a test command received through the second pad.

14. The semiconductor die of claim 12, further comprising: The second pad is configured for a test signal receiver to output a result of a test operation to an external device after receiving a reception signal.

15. The semiconductor die according to claim 12, wherein The first pads are arranged in a row along a first direction, and intervals between the first pads gradually increase or decrease along the first direction.

16. A semiconductor wafer, comprising: first pads arranged in a row along a first direction, wherein intervals between the first pads gradually increase or decrease along the first direction; a test signal device electrically connected to the first pad and configured to send or receive a test signal through the first pad; and The internal circuits are each one of a nonvolatile memory cell array and a peripheral device configured to access the nonvolatile memory cell array.

17. The semiconductor wafer according to claim 16, further comprising: The second pads are arranged in a row along a second direction intersecting the first direction, wherein the intervals between the second pads gradually increase or decrease along the second direction, and The second pad is electrically connected to the test signal device to send or receive a test signal.

18. The semiconductor wafer according to claim 16, further comprising: The switch is configured to perform control so that the first pad is connected to the test signal device during the test operation and the first pad is connected to the internal circuit after the test operation is completed.

19. The semiconductor wafer according to claim 16, wherein The semiconductor wafer includes a plurality of semiconductor dies configured to be divided into individual semiconductor dies, and The first pad and the test signal device are arranged on a cutting line, and the cutting line is arranged between semiconductor bare chips.

20. The semiconductor wafer according to claim 16, further comprising: The second pads are arranged in rows at regular intervals along the first direction.

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