Display module package

Abstract

A display module package includes: a semiconductor chip; a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip; a light-emitting device array disposed on the wiring member and including a plurality of light-emitting devices disposed on one surface, wherein the wiring member is located between the semiconductor chip and the light-emitting device array; and a molding member disposed on the wiring member, sealing a portion of the light-emitting device array, and having an opening for exposing the plurality of light-emitting devices.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0107476 filed on August 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to a display module package. Background Art

[0004] As display panels for electronic devices, display panels in which light-emitting diodes (LEDs) emitting red (R), green (G), and blue (B) light are directly mounted on a substrate have emerged. For small devices such as wearable devices, research has been continuously conducted to develop displays with reduced weight, reduced size, high resolution, and high functionality. Summary of the Invention

[0005] Example embodiments of the inventive concept are to provide a display module package having a reduced thickness and a reduced size.

[0006] Another example embodiment of the present inventive concept is to provide a display module package that can reduce a response delay time of a display.

[0007] According to an example embodiment conceived by the present invention, a display module package includes: a first wiring layer structure having a first wiring layer; a semiconductor chip, which is arranged on the first wiring layer structure and electrically connected to the first wiring layer of the first wiring layer structure; a first molding member, which is arranged on the first wiring layer structure and encapsulates at least a portion of the semiconductor chip; a second wiring layer structure, which is arranged on the semiconductor chip and the first molding member and has a second wiring layer; a vertical connecting electrode, which is arranged between the first wiring layer structure and the second wiring layer structure and electrically connects the first wiring layer to the second wiring layer; a light-emitting device array, which is arranged on the second wiring layer structure, electrically connected to the second wiring layer, has a first surface facing the second wiring layer structure and a second surface opposite to the first surface, and includes a plurality of light-emitting devices arranged on the second surface; and a second molding member, which is arranged on the second wiring layer structure and seals a portion of the light-emitting device array to expose the plurality of light-emitting devices.

[0008] According to an example embodiment conceived in the present invention, a display module package includes: a semiconductor chip; a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip; a light-emitting device array disposed on the wiring member and including a plurality of light-emitting devices disposed on one surface, wherein the wiring member is located between the semiconductor chip and the light-emitting device array; and a molding member disposed on the wiring member, sealing a portion of the light-emitting device array, and having an opening for exposing the plurality of light-emitting devices.

[0009] According to an example embodiment of the present invention, a display module package includes: a first wiring member including a first wiring layer and a connection terminal electrically connected to the first wiring layer; a semiconductor chip disposed on the first wiring member and including a connection member electrically connected to the first wiring layer; an underfill resin disposed between the first wiring member and the semiconductor chip and covering the connection member; a first molding member disposed on the first wiring member and sealing the semiconductor chip and the underfill resin; a second wiring member disposed on the semiconductor chip and the first molding member and including an insulating layer and a second wiring layer disposed on the insulating layer; a vertical connection electrode disposed between the first wiring member and the second wiring member, penetrating the first molding member, and electrically connecting the first wiring member to the second wiring member; a light-emitting device array disposed on the second wiring member, including a plurality of light-emitting devices disposed on one surface, and electrically connected to the second wiring member via bonding wires; an attaching member disposed between the second wiring member and the light-emitting device array; and a second molding member disposed on the second wiring member, encapsulating the bonding wires and a portion of the light-emitting device array, and having an opening for exposing the plurality of light-emitting devices, with the second wiring member contacting the semiconductor chip and the first molding member. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a side sectional view illustrating a display module package according to an example embodiment of the inventive concept;

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken along line II' in FIG.

[0013] Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II';

[0014] Figures 4 to 10 FIG. 1 is a diagram illustrating the manufacturing process of an exemplary embodiment of the present invention. Figure 1A side cross-sectional view of a method for display module packaging is shown in FIG;

[0015] Figure 11 is a side sectional view illustrating a display module package according to an example embodiment of the inventive concept;

[0016] Figures 12 to 15 FIG. 1 is a diagram illustrating the manufacturing process of an exemplary embodiment of the present invention. Figure 11 A side cross-sectional view of a method for display module packaging is shown in FIG;

[0017] Figure 16 is a side sectional view illustrating a display module package according to an example embodiment of the inventive concept;

[0018] Figure 17A and Figure 17B It is along Figure 16 A cross-sectional view taken along line III-III';

[0019] Figure 18 is a side sectional view illustrating a display module package according to an example embodiment of the inventive concept;

[0020] Figure 19 is a side sectional view illustrating a display module package according to an example embodiment of the inventive concept;

[0021] Figures 20 to 25 FIG. 1 is a diagram illustrating the manufacturing process of an exemplary embodiment of the present invention. Figure 19 A side cross-sectional view of the method for display module packaging shown in FIG; and

[0022] Figure 26 is a side-sectional view illustrating a display module package according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings as follows.

[0024] Figure 1 is a side sectional view illustrating a display module package 100A according to example embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line II' in FIG. Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0025] Reference Figures 1 to 3 The display module package 100A may include a first wiring member 110 , a semiconductor chip 120 , an interconnection member 130 , a first molding member 140 , a second wiring member 150 , a light emitting device array 160 , and a second molding member 170 .

[0026] The display module package 100A may include a light emitting device array 160 including a plurality of light emitting devices 166 arranged therein, and a semiconductor chip 120 configured to control the plurality of light emitting devices 166 to be turned on.

[0027] The first wiring member 110 can be configured as a substrate (such as a printed circuit board (PCB), a ceramic substrate, a tape wiring substrate, etc.) for use in a semiconductor package, and can be referred to as a substrate, a wiring substrate, or a package substrate. For example, the first wiring member 110 may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide). For example, the first wiring member 110 may include a prepreg, an Ajinomoto composite film, FR-4, bismaleimide triazine, etc. The first wiring member 110 may also include a photoimagable dielectric resin (PID). In this case, the first wiring member 110 can have a wiring pattern with a fine pitch using a photolithography process.

[0028] The first wiring member 110 may include: a plurality of pads (not shown) respectively arranged on the upper and lower surfaces of the first wiring member 110 relative to each other; and a first wiring layer 112 electrically connecting the plurality of pads to each other. The pads as described herein may be conductive terminals connected to the internal wiring of a device or substrate, and may transmit signals and / or power supply voltages between the internal wiring and / or internal circuits of the device or substrate and an external source. For example, the chip pads of a semiconductor chip may be electrically connected to the integrated circuit of the semiconductor chip and the device to which the semiconductor chip is connected, and transmit power supply voltages and / or signals between the integrated circuit of the semiconductor chip and the device to which the semiconductor chip is connected. The various pads may be arranged on or near the external surface of the device, and may typically have a planar surface area (typically larger than the corresponding surface area of the internal wiring to which they are connected) to facilitate connection to another terminal (such as a bump or solder ball, and / or external wiring).

[0029] The first wiring member 110 may further include connection terminals 114 connected to pads (not shown) provided on the lower surface of the first wiring member 110 in the lower portion of the first wiring member 110. On the lower surface of the first wiring member 110, the connection terminals 114 may be provided in a region overlapping with the semiconductor chip 120 or in a region not overlapping with the semiconductor chip 120 as seen from above. Therefore, at least a portion of the connection terminals 114 may be provided vertically in a region not overlapping with the semiconductor chip 120 as seen from above.

[0030] The connection terminals 114, also described as conductive interconnect terminals or external connection terminals, can be electrically connected to an external device (such as a motherboard, etc.) and can electrically and physically connect the package substrate to the external device. For example, the connection terminals 114 can have a flip-chip connection structure having a grid array such as a solder ball, a conductive bump, a pin grid array, a ball grid array, and a planar grid array.

[0031] The semiconductor chip 120 may be provided on the first wiring member 110 and may be electrically connected to the first wiring layer 112 of the first wiring member 110. For example, the semiconductor chip 120 may be mounted on the first wiring member 110 by a flip-chip bonding method through a connection member 124 provided on an active surface ( Figure 1 The first wiring member 110 is connected to a connection electrode (not shown) on the lower surface of the semiconductor chip 120. The connection member 124 can be a conductive interconnect and can include a solder bump or solder ball, or a copper pillar. An underfill resin 125 including an epoxy resin or the like surrounding the connection member 124 can be provided between the active surface of the semiconductor chip 120 and the upper surface of the first wiring member 110.

[0032] However, example embodiments thereof are not limited to the aforementioned example embodiments, and in example embodiments, the semiconductor chip 120 may be mounted on the first wiring member 110 by a wire bonding method.

[0033] The semiconductor chip 120 may include an integrated circuit IC that transmits lighting signals of the plurality of light-emitting devices 166. For example, the semiconductor chip 120 may include a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, a logic chip (such as an analog-to-digital converter (ADC)), an application-specific integrated circuit (ASIC), etc. However, example embodiments thereof are not limited thereto and may include other types of chip-related components. The semiconductor chip 120 may also include a driver IC configured to control the conduction of the plurality of light-emitting devices 166. The semiconductor chip 120 may include one or more integrated circuit dies to implement these various semiconductor devices.

[0034] The interconnection member 130 (described in the singular, but actually including a plurality of members) can be provided between the first wiring member 110 and the second wiring member 150, and can electrically connect the first wiring layer 112 to the second wiring layer 152. The interconnection member 130 can be formed using a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The interconnection member 130 can have a columnar shape with a cross-sectional surface of various shapes (e.g., circular, square, etc.), or can be configured to form a structure that forms an electrical path upward and downward.

[0035] For example, the interconnection members 130 may be disposed in an outer region of the first wiring member 110 and may surround the semiconductor chip 120 with a predetermined gap between the side surface of the semiconductor chip 120 and each of the first interconnection members 130, and the interconnection members 130 may be configured as conductive pillars penetrating the first molding member 140. Generally, the interconnection members 130 may be described as conductive vias or vertical conductive vias.

[0036] The first molding member 140 can be disposed on the first wiring member 110 and can seal at least a portion of the semiconductor chip 120. The first molding member 140 can be configured to surround and encapsulate at least a portion of the semiconductor chip 120 and can be described as a first encapsulant. For example, the first molding member 140 can surround the side surfaces of the semiconductor chip 120, and the upper surface of the first molding member 140 can be coplanar with the upper surface of the semiconductor chip 120 and the upper surface of the interconnection member 130. Terms such as "same," "equal," "planar," or "coplanar" as used herein include sameness or near sameness, and near sameness includes variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0037] For a configuration in which one surface is coplanar with another surface, the upper surfaces of the first molding member 140, the semiconductor chip 120, and the interconnection member 130 can be planarized and coplanar with each other through a grinding process. In this case, the upper portion of the semiconductor chip 120 can be partially removed through the grinding process, thereby reducing the overall thickness of the display module package.

[0038] However, example embodiments are not limited thereto, and the first molding member 140 may surround the side surfaces and the upper surface of the semiconductor chip 120 , and the upper surface of the first molding member 140 may be disposed at a higher level than the upper surface of the semiconductor chip 120 .

[0039] The first molding member 140 may include an insulating material. For example, the first molding member 140 may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a resin in which a thermosetting resin or a thermoplastic resin is mixed with a core material such as an inorganic filler and / or glass fiber (or glass cloth or glass fabric) (such as prepreg, Ajinomoto composite film (ABF), FR-4, or bismaleimide triazine (BT)). The first molding member 140 may be described as an insulating layer.

[0040] The second wiring member 150 may be disposed on the semiconductor chip 120 and the first molding member 140 and may have a second wiring layer 152. The second wiring member 150 may be electrically connected to the first wiring member 110 through the interconnection member 130. The second wiring member 150 may be referred to as an LED array substrate.

[0041] For example, the second wiring member 150 may include: an insulating layer 151, which is directly disposed on the upper surface of the first semiconductor chip 120 and the first molding member 140; a second wiring layer 152, which is disposed on the upper surface of the insulating layer 151; and a wiring feedthrough 153, which penetrates the insulating layer 151 and electrically connects the second wiring layer 152 to the interconnect member 130. For example, although only one of these components is described, multiple such components may be present at different vertical levels. For example, the insulating layer 151 may be formed by multiple stacked insulating layers (also described as insulating sublayers). The second wiring layer 152 may include multiple wiring layers (also described as wiring sublayers). Each wiring feedthrough 153 may be located at a different vertical level, connect the corresponding wiring layer 152 to other wiring, and pass through the corresponding insulating layer 151. The number of each of the insulating layer 151, the second wiring layer 152, and the wiring feedthrough 153 of the second wiring member 150 may be higher or lower than the example shown in the drawings.

[0042] The insulating layer 151 (e.g., each insulating sublayer) may include an insulating material. When the insulating layer 151 includes a photosensitive resin, the second wiring layer 152 and the wiring feedthrough 153 may be formed to have a fine form through a photolithography process. Thus, the overall thickness of the display module package can be reduced. However, example embodiments thereof are not limited thereto. The second wiring member 150 may be configured as a substrate including a printed circuit board (PCB), a ceramic substrate, a tape wiring substrate, or the like.

[0043] The second wiring layer 152 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Similar to the second wiring layer 152, the wiring feedthrough 153 may include a conductive material. The wiring feedthrough 153 may be completely filled with a conductive material, or a conductive material may be provided along the wall of the feedthrough. The wiring in the second wiring member 150 may be referred to as a wiring layer structure.

[0044] In an example embodiment, the second wiring member 150 may contact at least a portion of the semiconductor chip 120. For example, the upper surface of the semiconductor chip 120 may not be covered by the first molding member 140, and the lower surface of the second wiring member 150 may contact the upper surface of the semiconductor chip 120. Unless the context indicates otherwise, the term "contact" as used herein refers to direct connection (i.e., touching). The lower surface of the second wiring member 150 may be coplanar with the upper surfaces of the semiconductor chip 120, the first wiring member 110, and the interconnection member 130.

[0045] Light-emitting device array 160 may be disposed on second wiring member 150, may be electrically connected to second wiring layer 152, may have a first surface facing second wiring member 150 and a second surface opposite the first surface, and may include a plurality of light-emitting devices 166 disposed on the second surface. Light-emitting device array 160 may include a driver IC configured to drive the plurality of light-emitting devices 166. For example, a driver IC including a thin film transistor (TFT) or the like may be embedded in light-emitting device array 160, and semiconductor chip 120 may control the driver IC to transmit a drive signal to the plurality of light-emitting devices 166, thereby turning on the plurality of light-emitting devices 166.

[0046] The driver IC may be embedded in the semiconductor chip 120 or the second wiring structure 150, and in this case, the light-emitting device array 160 may include an internal circuit (not shown) configured to transmit a driving signal sent from the driver IC to a plurality of light-emitting devices 166 and redistribute electrodes of each of the plurality of light-emitting devices 166.

[0047] The light emitting device array 160 may be attached to the second wiring member 150 by an attachment member 165. The attachment member 165 may be an adhesive film or layer such as a non-conductive film (NCF), an anisotropic conductive film (ACF), a UV-sensitive film, cyanoacrylate, a thermosetting adhesive, a laser-curable adhesive or an ultrasonic-curable adhesive, a non-conductive glue (NCP), or the like.

[0048] The plurality of light emitting devices 166 may be configured as light emitting diodes (LEDs) of various sizes. For example, LEDs having a size (e.g., diameter) of several millimeters (mm) or tens to hundreds of micrometers (μm) may be used. To reduce the size of the display and improve the resolution of the display, micro-LEDs having a size of less than 100 μm may be used.

[0049] In each of the plurality of light emitting devices 166, a red LED chip 166R, a green LED chip 166G, and a blue LED chip 166B may be arranged. The plurality of light emitting devices 166 may be arranged according to a pitch included in a display pixel, etc.

[0050] In an example embodiment, the light emitting device array 160 may include a plurality of connection pads 162 disposed in an outer region of the second surface to surround and electrically connect to the plurality of light emitting devices 166. The plurality of connection pads 162 disposed in the outer region of the second surface may be electrically connected to the second wiring layer 152 of the second wiring member 150 through bonding wires 164, and the plurality of connection pads 162 and the bonding wires 164 may be protected by the second molding member 170.

[0051] The second molding member 170 may be disposed on the second wiring member 150 and may seal a portion of the light emitting device array 160 to expose the plurality of light emitting devices 166. For example, the second molding member 170 may seal exposed conductive components (e.g., pads and bonding wires) of the light emitting device array 160 and may have an opening 171 for exposing the plurality of light emitting devices 166. The opening 171 of the second molding member 170 may have a tapered shape such that the width of the opening 171 decreases in one direction. For example, the opening 171 of the second molding member 170 may have a tapered shape such that the width of the opening 171 decreases toward the surface of the light emitting device array 160 where the plurality of light emitting devices 166 are disposed. The second molding member 170 may include an insulating material. For example, the second molding member 170 may include an epoxy-based resin, a silicone-based resin, or the like.

[0052] Figures 4 to 10 is a diagram illustrating the manufacturing process according to an example embodiment. Figure 1 . A side cross-sectional view of a method for display module packaging is shown in FIG.

[0053] Reference Figure 4, an interconnection member 130 may be provided on the upper surface of the first wiring member 110. The first wiring member 110 may include a printed circuit board (PCB), a ceramic substrate, or the like. The interconnection member 130 may be provided in an outer region of the first wiring member 110. The interconnection member 130 may be configured as a conductive pillar, and may be, for example, a copper (Cu) pillar formed by a known method. The interconnection member 130 may be electrically connected to the first wiring member 110.

[0054] Reference Figure 5 , the semiconductor chip 120 can be mounted on the upper surface of the first wiring member 110. For example, the semiconductor chip 120 can be mounted on the first wiring member 110 by a flip-chip bonding method. The semiconductor chip 120 can be electrically connected to the first wiring member 110 through a connecting member 124. The connecting member 124 can be configured as a solder ball or a solder bump and can be connected to a pad (not shown) provided on the upper surface of the first wiring member 110. An underfill resin 125 that seals and supports the connecting member 124 can be provided between the semiconductor chip 120 and the first wiring member 110.

[0055] Reference Figure 6 , a first molding member 140 may be disposed on the first wiring member 110. The first molding member 140 may be configured to cover the upper surface of the semiconductor chip 120 and the interconnect member 130. The first molding member 140 and the underfill resin 125 may include different materials or may include or be formed of the same material. Therefore, the process for forming the underfill resin 125 and the process for forming the first molding member 140 may not be distinguished from each other.

[0056] Reference Figure 7 , a portion of the upper side of the first molding member 140 can be removed through a grinding process. A portion of the semiconductor chip 120 can also be removed simultaneously with the removal of a portion of the first molding member 140, thereby reducing the thickness of the semiconductor chip 120. The first molding member 140 can be removed to expose the upper surface of each of the semiconductor chip 120 and the interconnect member 130. Therefore, the upper surfaces of the first molding member 140, the semiconductor chip 120, and the interconnect member 130 can be coplanar with each other.

[0057] The connection terminals 114 may be provided at the lower portion of the first wiring member 110. The connection terminals 114 may be connected to pads (not shown) provided on the lower surface of the first wiring member 110. The connection terminals 114 may be configured as solder balls. The connection terminals 114 may be formed while the first molding member 140 and the surface of the semiconductor chip 120 planarized by the grinding process are attached to the carrier. A temporary protective film (not shown) may be used to seal the connection terminals 114.

[0058] Reference Figure 8 , a second wiring member 150 may be disposed on the semiconductor chip 120 and the first molding member 140. If desired, the second wiring member 150 may include a plurality of insulating layers 151a and 151b, a plurality of wiring layers 152a and 152b, and a plurality of wiring feedthroughs 153a and 153b. As described above, by disposing the second wiring member 150 directly on the planarized surface of the first molding member 140 by removing its upper portion, the thickness of the display module can be reduced, and the signal transmission distance between the semiconductor chip and the light-emitting device can be shortened.

[0059] The insulating layers 151a and 151b may be formed by a lamination process and a curing process using a known lamination method, or by coating a precursor using a known coating method and curing the precursor, etc. The wiring layers 152a and 152b and the wiring vias 153a and 153b may be formed using a known electroplating process, and the vias filled with the wiring vias 153a and 153b may be formed by mechanical drilling and / or laser drilling, etc. Each wiring layer 152a or 152b may be integrally formed with its corresponding wiring via 153a or 153b in a single process and using a continuous material.

[0060] When the insulating layers 151 a and 151 b include a photosensitive resin, the wiring layers 152 a and 152 b and the wiring vias 153 a and 153 b may have a finer form through an exposure process and a development process.

[0061] Reference Figure 9 , the light emitting device array 160 is mounted on the upper surface of the second wiring member 150. The light emitting device array 160 can be attached to the second wiring member 150 using an attachment member 165. As the attachment member 165, a non-conductive film (NCF), an anisotropic conductive film (ACF), a UV-sensitive film, cyanoacrylate, a thermosetting adhesive, a laser-curable adhesive or an ultrasonic-curable adhesive, a non-conductive paste (NCP), etc. can be used.

[0062] The light-emitting device array 160 may include a plurality of connection pads 162 electrically connected to the plurality of light-emitting devices 166, and the plurality of connection pads 162 may be electrically connected to the second wiring layer 152 of the second wiring member 150 through bonding wires 164. However, embodiments thereof are not limited thereto, and the plurality of connection pads 162 may be provided on a surface facing the second wiring member 150 and may be electrically connected to the second wiring layer 152 of the second wiring member 150 through a flip-chip bonding method.

[0063] Reference Figure 10, forming a second molding member 170 that partially seals the light-emitting device array 160. The second molding member 170 can be configured to have openings 171 for exposing the plurality of light-emitting devices 166 through a dispensing process, a screen printing process, or the like. For example, silicone paste can be dispensed continuously or multiple times on a portion of the second wiring member 150 to cover the bonding wires 164 and the connection pads 162, thereby forming the second molding member 170 that exposes the plurality of light-emitting devices 166. Epoxy resin, silicone resin, or the like can be used as the second molding member 170.

[0064] Figure 11 is a side sectional view illustrating a display module package 100B according to example embodiments.

[0065] Reference Figure 11 In the display module package 100B in the example embodiment, the first molding member 140 covers the upper surface of the semiconductor chip 120, and the lower surface of the insulating layer 151 of the second wiring member 150 contacts the upper surface of the first molding member 140. For example, the first molding member 140 covering the semiconductor chip 120 and the interconnection member 130 may be provided on the first wiring member 110, and only a portion of the first molding member 140 may be removed to avoid exposing the upper surface of each of the semiconductor chip 120 and the interconnection member 130 in the process of planarizing the upper portion of the first molding member 140.

[0066] The second wiring member 150 may include a connection pattern 155 directly disposed on the planarized upper surface of the first molding member 140 and a connection through-piece 154 that penetrates a portion of the first molding member 140 and electrically connects the connection pattern 155 to the interconnection member 130. Unless otherwise specified, the description of the elements in the example embodiments may be the same as Figure 1 The description of the display module package 100A shown in FIG. 1 is the same as or similar to that of the display module package 100A shown in FIG.

[0067] Figures 12 to 15 is a diagram illustrating the manufacturing process according to an example embodiment. Figure 11 FIG. 1 is a side cross-sectional view of a display module package 100B shown in FIG.

[0068] Reference Figure 12 , through the above Figure 4 and Figure 5 The interconnection member 130 and the semiconductor chip 120 are provided on the first wiring member 110 using a method that is the same as or similar to the method shown in .

[0069] Reference Figure 13A first molding member 140 covering the interconnection member 130 and the semiconductor chip 120 is formed on the first wiring member 110. An upper portion of the first molding member 140 may be ground by a grinding process, etc. The grinding of the first molding member 140 may be performed so as not to expose the upper surface of the semiconductor chip 120 or the interconnection member 130.

[0070] Reference Figure 14 , a connection via 141 exposing the upper surface of the interconnection member 130 is formed on the upper surface of the first molding member 140. The connection via 141 may be formed using mechanical drilling and / or laser drilling, etc. When the first molding member 140 includes a photosensitive resin, the connection via 141 may be formed using a photolithography process.

[0071] Reference Figure 15 , can be achieved by Figure 8 The second wiring member 150 is formed by the same or similar method as the aforementioned manufacturing method shown in FIG. In the figure, the second wiring member 150 may include a single insulating layer 151, a single wiring layer 152 and a single wiring through-piece 153, and if necessary, the second wiring member 150 may include a plurality of insulating layers 151, a plurality of second wiring layers 152 and a plurality of wiring through-pieces 153.

[0072] Figure 16 is a side sectional view illustrating a display module package 100C according to example embodiments. Figure 17A and Figure 17B It is along Figure 16 An alternative cross-sectional view taken along line III-III' in FIG.

[0073] Reference Figure 16 In the display module package 100C in the exemplary embodiment, the interconnection member 130 may include an insulating layer 131 and connection pads 132 respectively provided on the upper and lower surfaces of the insulating layer 131 and electrically connected to each other. The connection pads 132 may be electrically connected to each other through through holes 133 penetrating the insulating layer 131. The insulating layer 131 may include a plurality of layers, and in this case, the connection pads 132 may be provided in the insulating layer 131. The rigidity of the display module package may be improved depending on the material of the insulating layer 131. The insulating layer 131 may include an insulating material, and as the insulating material, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), a thermosetting resin or a resin mixed with a core material such as an inorganic filler and / or glass fiber (or glass cloth or glass fabric) (such as prepreg, Ajinomoto composite film (ABF), FR-4, bismaleimide triazine (BT)) may be used.

[0074] The interconnection member 130 may be attached to the first wiring member 110 by a general conductive attaching member (not shown), or may be manufactured by directly forming the insulating layer 131 , the connection pads 132 , and the through-holes 133 on the wiring pattern of the first wiring member 110 .

[0075] Reference Figure 17A and Figure 17B , the insulating layer 131 of the interconnection member 130 may have a lattice pattern that continuously surrounds the semiconductor chip 120. In this case, the semiconductor chip 120 may be disposed in a space surrounded by the insulating layer 131. Alternatively, the interconnection member 130 may include a plurality of insulating layers 131 separated from each other. In this case, the area between the plurality of separated insulating layers 131 may be filled with the first molding member 140 that seals the semiconductor chip 120. Unless otherwise specified, the description of the elements in this example embodiment may be the same as Figure 1 The descriptions of the elements of the display module package 100A shown in FIG. 1 are the same or similar.

[0076] Figure 18 is a side sectional view illustrating a display module package 100D according to example embodiments.

[0077] Reference Figure 18 In the display module package 100D of the exemplary embodiment, the light-emitting device array 160 may include a plurality of connection pads 162 disposed on the first surface and electrically connected to a plurality of light-emitting devices 166. The plurality of connection pads 162 may be electrically connected to the second wiring layer 152 of the second wiring member 150 via conductive bumps 164. In this case, the second molding member 170 may be formed only in a portion of the area that secures and protects the light-emitting device array 160. Therefore, compared to the exemplary embodiment in which the light-emitting device array 160 is connected to the second wiring member 150 via bonding wires, the area in which the second molding member 170 is formed may be further reduced.

[0078] In the example of the figure, the second molding member 170 may be formed from the side surface to a portion of the upper surface of the light emitting device array 160 to protect the light emitting device array 160, but the embodiment is not limited thereto. The second molding member 170 may be configured to cover only the lower region of the light emitting device array 160 to protect the conductive bumps 164 provided at the lower portion of the light emitting device array 160 and the second wiring layer 152 of the second wiring member 150. Unless otherwise specified, the description of the elements in the example embodiment may be the same as Figure 1 The descriptions of the elements of the display module package 100A shown in FIG. 1 are the same or similar.

[0079] Figure 19 is a side sectional view illustrating a display module package 100E according to example embodiments.

[0080] Reference Figure 19 In the display module package 100E in this example embodiment, the second wiring member 150 may be configured as a plug-in substrate including a printed circuit board (PCB), a ceramic substrate, or the like. The second wiring member 150 may include a plurality of pads 150P disposed on the upper and lower surfaces of the second wiring member 150, which are opposite to each other. The pads 150P disposed on the upper surface of the second wiring member 150 may be electrically connected to the connection pads 162 of the light-emitting device array 160 through bonding wires 164. The pads 150P disposed on the lower surface of the second wiring member 150 may be electrically connected to the interconnection member 130. In the interconnection member 130, the lower connection member 130a and the upper connection member 130b may be coupled to each other. The lower surface of the second wiring member 150 may be spaced apart from the upper surface of the semiconductor chip 120 and the upper surface of the first molding member 140.

[0081] The lower connection member 130a may be electrically and / or physically connected to the first wiring member 110, and the upper connection member 130b may be electrically and / or physically connected to the second wiring member 150. The lower and upper connection members 130a and 130b may be configured as solder balls and may be integrated with each other.

[0082] Unlike the example embodiment shown in the drawings, the space between the second wiring member 150 and the first molding member 140 may be filled with an insulating material having excellent thermal conductivity to protect the semiconductor chip 120 and dissipate heat from the semiconductor chip 120. Unless otherwise specified, the description of the elements in the example embodiment may be the same as Figure 1 The descriptions of the elements of the display module package 100A shown in FIG. 1 are the same or similar.

[0083] Figures 20 to 25 is a side sectional view illustrating a method of manufacturing a display module package 100E according to example embodiments.

[0084] Reference Figure 20 , a lower connection member 130a is provided on the first wiring member 110. For example, the lower connection member 130a may be attached to the outside of the upper surface of the first wiring member 110. The lower connection member 130a may be electrically connected to the first wiring member 110. The lower connection member 130a may be configured as a solder ball and may be attached to the first wiring member 110 using a hot pressing process and / or a reflow process.

[0085] Reference Figure 21, a semiconductor chip 120 is mounted on the first wiring member 110. The semiconductor chip 120 may be positioned surrounded by a plurality of lower connection members 130a. The semiconductor chip 120 may be electrically connected to the lower connection members 130a via the first wiring member 110. The semiconductor chip 120 may be mounted on the first wiring member 110 using a flip-chip bonding method. The lower connection members 130a and the semiconductor chip 120 may be disposed on the first wiring member 110 in a reverse chronological order as in the aforementioned exemplary embodiment, or may be disposed simultaneously on the first wiring member 110.

[0086] Reference Figure 22 , a first molding member 140 sealing the semiconductor chip 120 may be provided on the first wiring member 110. The first molding member 140 may include Figure 6 The underfill resin 125 may be made of a different or the same material as that of the example embodiment shown in FIG. Unlike the example embodiment shown in the drawings, a first molding member 140 may be provided at a lower portion of the semiconductor chip 120 without using the underfill resin 125 .

[0087] Reference Figure 23 The upper surface of the semiconductor chip 120 is exposed by removing a portion of the first molding member 140. A portion of the upper side of the semiconductor chip 120 may be removed, and thus, the thickness of the semiconductor chip 120 may be reduced. The first molding member 140 may be removed by a grinding process or the like.

[0088] An opening 142 (e.g., a plurality of openings) may be formed to expose a portion of the lower connection member 130a (e.g., a plurality of openings to expose a plurality of lower connection members). The opening 142 may be formed using laser drilling or the like. The opening 142 may have a size that exposes only a portion of the lower connection member 130a, or may have a size that exposes the upper surface of each of the lower connection member 130a and the first wiring member 110.

[0089] Reference Figure 24 , an upper connecting member 130b is disposed on the lower surface of the second wiring member 150. The upper connecting member 130b may be disposed in a position contacting the lower connecting member 130a through the opening 142. The upper connecting member 130b may be inserted into the opening 142 and may be electrically and / or physically connected to the lower connecting member 130a. A space may be formed between the upper connecting member 130b and the lower connecting member 130a when the upper connecting member 130b is inserted into the opening 142.

[0090] Reference Figure 25The lower connection member 130a and the upper connection member 130b can be integrated with each other through a hot pressing process and / or a reflow process to form the interconnection member 130 (also described as a vertical connection member or a vertical connection electrode). Therefore, the shapes of the lower connection member 130a and the upper connection member 130b can be changed, and thus, a circuit path connecting the first wiring member 110 and the second wiring member 150 to each other can be formed.

[0091] Figure 26 is a side sectional view illustrating a display module package 100F according to example embodiments.

[0092] Reference Figure 26 In the display module package 100F in the example embodiment, the second wiring member 150 is connected to the interconnection member 130 through the connection terminal 156, and the interconnection member 130 may include an insulating layer 131 and connection pads 132 respectively provided at the upper and lower surfaces of the insulating layer 131 and electrically connected to each other. The description of the interconnection member 130 may be the same as that of the reference Figure 16 、 Figure 17A and Figure 17B The description of the interconnection member 130 in the previously described exemplary embodiment is the same as that in the previous exemplary embodiment. Unless otherwise indicated, the description of the elements in the exemplary embodiment may be the same as that in the previous exemplary embodiment. Figure 1 The descriptions of the elements of the display module package 100A shown in FIG. 1 are the same or similar.

[0093] According to the aforementioned example embodiments, by embedding a light emitting device and a semiconductor chip controlling the light emitting device in a single module package, a display module package having a reduced thickness and a reduced size may be provided.

[0094] In addition, by reducing the signal transmission distance between the light emitting device and the semiconductor chip that controls the light emitting device, a display module package that reduces the response delay time of the display can be provided.

[0095] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention as defined in the appended claims.

Claims

1. A display module package, comprising: a first wiring layer structure having a first wiring layer; a semiconductor chip disposed on the first wiring layer structure and electrically connected to the first wiring layer of the first wiring layer structure; a first molding member disposed on the first wiring layer structure and encapsulating at least a portion of the semiconductor chip; a second wiring layer structure provided on the semiconductor chip and the first molding member and having a second wiring layer; a vertical connection electrode disposed between the first wiring layer structure and the second wiring layer structure and electrically connecting the first wiring layer to the second wiring layer; a light emitting device array disposed on the second wiring layer structure, electrically connected to the second wiring layer, having a first surface facing the second wiring layer structure and a second surface opposite to the first surface, and including a plurality of light emitting devices disposed on the second surface; A second molding member is provided on the second wiring layer structure and seals a portion of the light emitting device array to expose the plurality of light emitting devices.

2. The display module package according to claim 1, wherein: The second wiring layer structure includes an insulating layer, the second wiring layer, and a wiring via, wherein the insulating layer is disposed on the semiconductor chip and the first molding member, the second wiring layer is disposed on the insulating layer, and the wiring via penetrates the insulating layer and electrically connects the second wiring layer to the vertical connection electrode.

3. The display module package according to claim 1, further comprising: a connecting member provided on a lower surface of the semiconductor chip and electrically connected to the first wiring layer; an underfill resin provided between the first wiring layer structure and the semiconductor chip and covering the connection member; and an external connection terminal provided on a lower surface of the first wiring layer structure and electrically connected to the first wiring layer, At least one group of the external connection terminals is arranged in a region that does not overlap with the semiconductor chip when viewed from a top view.

4. The display module package according to claim 1, wherein: A lower surface of the second wiring layer structure contacts an upper surface of the semiconductor chip.

5. The display module package according to claim 4, wherein: The upper surface of the semiconductor chip is coplanar with an upper surface of the first molding member.

6. The display module package according to claim 5, wherein: An upper surface of the vertical connection electrode is coplanar with the upper surface of the first molding member.

7. The display module package according to claim 1, in, The first molding member covers the upper surface of the semiconductor chip, and wherein a lower surface of the second wiring layer structure contacts an upper surface of the first molding member.

8. The display module package according to claim 7, wherein: The second wiring layer structure includes a connection pattern provided on the upper surface of the first molding member and a connection via that penetrates a portion of the first molding member and connects the connection pattern to the vertical connection electrode.

9. The display module package according to claim 1, wherein: A lower surface of the second wiring layer structure is spaced apart from an upper surface of the semiconductor chip and an upper surface of the first molding member.

10. The display module package according to claim 1, in, The light emitting device array includes a plurality of connection pads provided in an outer region of the second surface of the light emitting device array to surround the plurality of light emitting devices and electrically connected to the plurality of light emitting devices, and The plurality of connection pads are electrically connected to the second wiring layer of the second wiring layer structure through bonding wires.

11. The display module package according to claim 10, wherein: The second molding member is configured to cover the plurality of connection pads and the bonding wires.

12. The display module package according to claim 1, in, The light emitting device array includes a plurality of connection pads disposed on the first surface of the light emitting device array and electrically connected to the plurality of light emitting devices, and The plurality of connection pads are electrically connected to the second wiring layer of the second wiring layer structure through conductive bumps.

13. The display module package according to claim 1, wherein: The vertical connection electrode is provided at an outer region of the first wiring layer structure to surround the semiconductor chip, and is configured as a conductive pillar penetrating the first molding member.

14. The display module package according to claim 1, wherein: The vertical connection electrodes pass through the insulating layer and are connected to connection pads, which are respectively provided on the upper and lower surfaces of the insulating layer and are electrically connected to each other.

15. The display module package according to claim 1, wherein: The second molding member includes a silicone-based resin.

16. A display module package, comprising: semiconductor chips; a wiring member provided on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip; a light emitting device array provided on the wiring member and including a plurality of light emitting devices provided on one surface, wherein the wiring member is located between the semiconductor chip and the light emitting device array; and a molding member provided on the wiring member, sealing a portion of the light emitting device array, and having an opening for exposing the plurality of light emitting devices, wherein the light emitting device array has a first surface facing the wiring structure and a second surface opposite to the first surface, and The plurality of light emitting devices are disposed on the second surface.

17. The display module package according to claim 16, wherein: The opening of the molding member has a tapered inner wall such that a width of the opening decreases in a direction toward a surface of the light emitting device array.

18. The display module package according to claim 17, further comprising: bonding wires electrically connecting the light emitting device array to the wiring member, The semiconductor chip includes a chip configured to control the plurality of light-emitting devices.

19. The display module package according to claim 18, wherein: The molding member exposes at least a portion of an end portion of the wiring member.

20. A display module package, comprising: a first wiring member including a first wiring layer and a connection terminal electrically connected to the first wiring layer; a semiconductor chip provided on the first wiring member and including a connection member electrically connected to the first wiring layer; an underfill resin provided between the first wiring member and the semiconductor chip and covering the connection member; a first molding member that is provided on the first wiring member and seals the semiconductor chip and the underfill resin; a second wiring member provided on the semiconductor chip and the first molding member and including an insulating layer and a second wiring layer provided on the insulating layer; a vertical connection electrode disposed between the first wiring member and the second wiring member, penetrating the first molding member, and electrically connecting the first wiring member to the second wiring member; a light emitting device array provided on the second wiring member, including a plurality of light emitting devices provided on one surface and electrically connected to the second wiring member through bonding wires; an attachment member disposed between the second wiring member and the light emitting device array; as well as a second molding member disposed on the second wiring member, encapsulating the bonding wires and a portion of the light emitting device array, and having an opening for exposing the plurality of light emitting devices; wherein the second wiring member contacts the semiconductor chip and the first molding member.

Images