Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device can be provided, including a first chip and a second chip stacked on the first chip. The first chip can include a first base including a first peripheral circuit region and a second peripheral circuit region, first and second contact plugs, and a first passive device located on and electrically connected to the second contact plug. The second chip can include a second base including a cell array region and a contact region vertically stacked with the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip can further include a gate electrode and a cell contact plug disposed on the contact region of the second base and on an end portion of the gate electrode. The first passive device can be vertically located between the gate electrode and the second contact plug and can include a first contact line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0108222, filed on September 2, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a three-dimensional semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device with improved electrical characteristics. Background Technology

[0003] To meet consumer demand for superior performance and low prices, higher integration levels are required in semiconductor devices. For semiconductor devices, increasing integration is particularly advantageous because it is a significant factor determining product price. However, for two-dimensional or planar semiconductor devices, integration is heavily influenced by the level of fine patterning technology, as its degree is primarily determined by the area occupied by a single memory cell. Nevertheless, the extremely expensive processing equipment required to increase pattern fineness sets a practical limit on increasing the integration level of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices incorporating three-dimensionally arranged memory cells have recently been proposed. Summary of the Invention

[0004] Embodiments of the inventive concept provide a three-dimensional semiconductor memory device with improved electrical characteristics.

[0005] According to embodiments of the inventive concept, a three-dimensional semiconductor memory device can be provided, comprising a first chip and a second chip stacked on the first chip. The first chip may include: a first substrate including a first peripheral circuit region and a second peripheral circuit region; a first contact plug located on the first peripheral circuit region of the first substrate; a second contact plug; a second peripheral circuit region located on the first substrate; and a first passive device located on and electrically connected to the second contact plug. The second chip may include a second substrate disposed on the first chip, the second substrate including a cell array region and a contact region respectively vertically stacked with the second peripheral circuit region and the first peripheral circuit region of the first chip. The second chip may further include: a gate electrode stacked on the cell array region and the contact region of the second substrate and disposed between the first chip and the second substrate of the second chip; and a cell contact plug disposed on the contact region of the second substrate and at the end of the gate electrode, and connected to the first contact plug. The first passive device may be vertically located between the gate electrode and the second contact plug and may include a first contact line.

[0006] According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device includes: a first substrate having a first peripheral circuit region and a second peripheral circuit region; a first transistor located on the first peripheral circuit region of the first substrate; a first contact plug connected to the first transistor; a first contact line located on the first contact plug; a second transistor located on the second peripheral circuit region of the first substrate; and a second contact plug connected to the second transistor. The three-dimensional semiconductor memory device may further include: a second substrate disposed on the first contact line, the second substrate including a first region and a second region respectively vertically stacked with respect to the first and second peripheral circuit regions; a gate electrode stacked on the second region of the second substrate and located between the second substrate and the second contact plug; and a cell contact plug disposed on the second region of the second substrate and at the end of the gate electrode, and connected to the second contact plug. The first contact line is electrically disconnectable from the second substrate.

[0007] According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device includes: a first substrate having a first peripheral circuit region and a second peripheral circuit region; a first transistor located on the first peripheral circuit region of the first substrate; an interlayer insulating layer covering the first transistor of the first substrate; and a first contact plug configured to penetrate the interlayer insulating layer and be connected to the first transistor. The three-dimensional semiconductor memory device may further include: a first contact line located on the first contact plug; a second substrate disposed on the interlayer insulating layer, the second substrate including a first region and a second region respectively vertically stacked with respect to the first and second peripheral circuit regions; a gate electrode disposed between the second substrate and the interlayer insulating layer and stacked on the second region of the second substrate; and a vertical channel portion penetrating the gate electrode. Adjacent first contact lines may constitute electrodes of a capacitor. Attached Figure Description

[0008] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0009] Figure 1 This is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0010] Figure 2 This is an oblique projection view showing an embodiment of a three-dimensional semiconductor memory device according to the inventive concept.

[0011] Figure 3 This is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0012] Figure 4 It is along Figure 3The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0013] Figure 5 yes Figure 4 An enlarged sectional view of part "A".

[0014] Figures 6A to 6C This is a plan view illustrating a passive device according to an embodiment of the inventive concept.

[0015] Figure 7 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0016] Figure 8 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0017] Figure 9 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0018] Figure 10 This is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0019] Figure 11 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0020] Figure 12 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0021] Figure 13 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0022] Figure 14 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0023] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in particular exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments, and should not be construed as limiting or restricting the range of values ​​or properties contained in the exemplary embodiments. For example, for clarity, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or exaggerated. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0024] Figure 1 This is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0025] Reference Figure 1 A three-dimensional semiconductor memory device may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTRs disposed between the common source line CSL and the bit lines BL0 to BL2.

[0026] The common-source line (CSL) can be a conductive thin film disposed on a semiconductor substrate or an impurity region formed in the semiconductor substrate. Bit lines BL0 to BL2 can be conductive patterns (e.g., metal lines) disposed on and separated from the semiconductor substrate. Bit lines BL0 to BL2 can be arranged in two dimensions, and multiple cell strings (CSTRs) can be connected in parallel with each of the bit lines BL0 to BL2. Therefore, cell strings (CSTRs) can be arranged in two dimensions on the common-source line (CSL) or the semiconductor substrate.

[0027] Each cell string (CSTR) can consist of a ground select transistor (GST) coupled to the common source line (CSL), a string select transistor (SST) coupled to bit lines BL0 to BL2, and multiple memory cell transistors (MCTs) disposed between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) can be connected in series. Furthermore, the ground select line (GSL), multiple word lines (WL0 to WL3), and multiple string select lines (SSL0 to SSL2) disposed between the common source line (CSL) and the bit lines BL0 to BL2 can be used as the gate electrodes of the ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors (SSTs), respectively.

[0028] The ground select transistor (GST) can be positioned at substantially the same height as the semiconductor substrate, and the gate electrodes of the GST can be connected to the ground select line (GSL) to achieve equipotentiality. For this purpose, the ground select line (GSL) can be positioned between the common source line (CSL) and the adjacent, lowest memory cell transistor (MCT). Similarly, the gate electrodes of the memory cell transistors (MCTs) located at the same height as the common source line (CSL) can be connected to one of the word lines (WL0 to WL3) to achieve equipotentiality. Since each cell string (CSTR) includes memory cell transistors (MCTs) positioned at a different level from the common source line (CSL), word lines (WL0 to WL3) can have a multilayer structure between the common source line (CSL) and the bit lines (BL0 to BL2). Items described as "substantially identical" can be completely identical or equal, or can be identical or equal within acceptable variations that may occur, for example, due to manufacturing processes.

[0029] Ground select transistors (GST), string select transistors (SST), and memory cell transistors (MCT) can be metal-oxide-semiconductor field-effect transistors (MOSFETs) that use a channel structure as their channel region.

[0030] Figure 2 This is an oblique projection view showing an embodiment of a three-dimensional semiconductor memory device according to the inventive concept. Figure 3 This is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 4 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 5 yes Figure 4 An enlarged sectional view of part "A". Figures 6A to 6C This is a plan view illustrating a passive device according to an embodiment of the inventive concept. Ordinal numbers such as "first," "second," "third," etc., may be used merely as designations to distinguish certain elements from one another. Terms not used in the specification such as "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, a term referring to a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0031] Reference Figures 2 to 4The unit chip 1 of the three-dimensional semiconductor memory device may include a first chip C1 and a second chip C2. The second chip C2 may be vertically stacked on the first chip C1. The first chip C1 may include a first peripheral circuit region PR1, a second peripheral circuit region PR2, a third peripheral circuit region PR3, and a fourth peripheral circuit region PR4. The first peripheral circuit regions PR1 may be separated from each other in a second direction Y. The second peripheral circuit regions PR2 may be disposed between the first peripheral circuit regions PR1. The third peripheral circuit regions PR3 may be separated from each other in a first direction X intersecting the second direction Y, and the second peripheral circuit regions PR2 may be disposed between the third peripheral circuit regions PR3. Each fourth peripheral circuit region PR4 may be disposed between a subgroup of an adjacent first peripheral circuit region PR1 and two adjacent third peripheral circuit regions PR3. For example, when viewed in a plan view, the fourth peripheral circuit regions PR4 may be disposed near the corners of the second peripheral circuit regions PR2. Unless otherwise explicitly stated, the term "subgroup" should be understood to have at least one of a plurality of "..."

[0032] The second chip C2 may include a first region R1, a second region R2, a third region R3, and a fourth region R4. The first peripheral circuit region PR1 of the first chip C1 may be vertically stacked with the first region R1 of the second chip C2; the second peripheral circuit region PR2 of the first chip C1 may be vertically stacked with the second region R2 of the second chip C2; the third peripheral circuit region PR3 of the first chip C1 may be vertically stacked with the third region R3 of the second chip C2; and the fourth peripheral circuit region PR4 of the first chip C1 may be vertically stacked with the fourth region R4 of the second chip C2.

[0033] The cell array can be disposed on the first region R1, the second region R2, and the third region R3 of the second chip C2. The second chip C2 may include a stack ST, which contains gate electrodes GE1, GE2, and GE3 (e.g., see...). Figure 4 The second chip C2 consists of a vertical channel portion (VC), cell contact plugs (CCP), and a bit line (BL). The cell contact plugs (CCP), electrically connected to the gate electrodes GE1, GE2, and GE3, can be located on the first region R1 of the second chip C2. The end of the bit line (BL) can be located on the third region R3 of the second chip C2. The vertical channel portion (VC) can be located on the second region R2 of the second chip C2. The cell array may not be located on the fourth region R4 of the second chip C2.

[0034] Reference Figure 3 and Figure 4Active devices, such as a first transistor TR1, can be disposed on the first peripheral circuit region PR1 and the third peripheral circuit region PR3 of the first chip C1. The first transistor TR1 can be a transistor used to operate the cell array. The first transistor TR1 may not be disposed on the fourth peripheral circuit region PR4 and / or the second peripheral circuit region PR2 of the first chip C1. The second transistor TR2 can be disposed on the second peripheral circuit region PR2 of the first chip C1. The second transistor TR2 can be a transistor used to operate a passive device. The third transistor TR3 can be disposed on the fourth peripheral circuit region PR4 of the first chip C1. The third transistor TR3 can be a transistor used to operate a passive device. A "passive device" can be a component whose current cannot be controlled by another electrical signal. Exemplary passive devices may include resistors, capacitors, inductors, and transformers. Further aspects of the exemplary "passive devices" will be described in more detail below.

[0035] In addition to the first transistor TR1, the second transistor TR2, and the third transistor TR3, the first chip C1 may also include a first substrate 100, a first contact plug 40, a second contact plug 42 and a third contact plug 44, a first via 50, a second via 52 and a third via 54, a first pad (or "soldering pad") 60, a second pad 62 and a third pad 64, and a first contact line 90, a second contact line 92 and a third contact line 94.

[0036] The first substrate 100 may include a first peripheral circuit region PR1, a second peripheral circuit region PR2, a third peripheral circuit region PR3, and a fourth peripheral circuit region PR4. The first substrate 100 may be a silicon wafer, a silicon-germanium wafer, a germanium wafer, or a single-crystal silicon wafer, and a single-crystal epitaxial layer grown therefrom. A first transistor TR1 may be disposed on the first peripheral circuit region PR1 of the first substrate 100. Each first transistor TR1 may include a first peripheral gate electrode 10, a first gate insulating layer 12, and a first source / drain region 14. The first peripheral gate electrode 10 may be disposed on the first peripheral circuit region PR1 of the first substrate 100. The first gate insulating layer 12 may be disposed between the first peripheral gate electrode 10 and the first substrate 100. The first source / drain region 14 may be disposed in the portion of the first substrate 100 located on both sides of the first peripheral gate electrode 10.

[0037] The second transistor TR2 can be disposed on the second peripheral circuit region PR2 of the first substrate 100. Each second transistor TR2 may include a second peripheral gate electrode 20, a second gate insulating layer 22, and a second source / drain region 24. The second peripheral gate electrode 20 can be disposed on the second peripheral circuit region PR2 of the first substrate 100. The second gate insulating layer 22 can be disposed between the second peripheral gate electrode 20 and the first substrate 100. The second source / drain region 24 can be disposed in the portion of the first substrate 100 located on both sides of the second peripheral gate electrode 20.

[0038] The third transistor TR3 can be disposed on the fourth peripheral circuit region PR4 of the first substrate 100. Each third transistor TR3 may include a third peripheral gate electrode 30, a third gate insulating layer 32, and a third source / drain region 34. The third peripheral gate electrode 30 can be disposed on the fourth peripheral circuit region PR4 of the first substrate 100. The third gate insulating layer 32 can be disposed between the third peripheral gate electrode 30 and the first substrate 100. The third source / drain region 34 can be disposed in the portion of the first substrate 100 located on both sides of the third peripheral gate electrode 30.

[0039] The first peripheral gate electrode 10, the second peripheral gate electrode 20, and the third peripheral gate electrode 30 may be formed of or comprise at least one metallic material (e.g., tungsten and aluminum). The first gate insulating layer 12, the second gate insulating layer 22, and the third gate insulating layer 32 may comprise, for example, a thermal oxide layer or a high-k dielectric layer. In an embodiment, the first source / drain region 14, the second source / drain region 24, and the third source / drain region 34 may have a conductivity type different from that of the first substrate 100.

[0040] A first interlayer insulating layer (ILD1) may be disposed on the first substrate 100. The ILD1 may cover the first transistor TR1, the second transistor TR2, and the third transistor TR3. The ILD1 may include, for example, a silicon oxide layer. A first contact plug 40 may be disposed on the first peripheral circuit region PR1 of the first substrate 100. The first contact plug 40 may be configured to penetrate the ILD1 and be electrically connected to the first source / drain region 14. A second contact plug 42 may be disposed on the second peripheral circuit region PR2 of the first substrate 100. Each second contact plug 42 may be configured to penetrate the ILD1 and be electrically connected to one of the second source / drain region 24 and the second peripheral gate electrode 20. A third contact plug 44 may be disposed on the fourth peripheral circuit region PR4 of the first substrate 100. Each third contact plug 44 may be configured to penetrate the ILD1 and be electrically connected to one of the third source / drain region 34 and the third peripheral gate electrode 30. Each of the first contact plug 40, the second contact plug 42, and the third contact plug 44 may be formed of or comprise at least one metallic material (e.g., copper, tungsten, and aluminum) or a metal nitride (titanium nitride, tungsten nitride, and aluminum nitride).

[0041] The second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 may be sequentially stacked on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 may be formed of or include at least one insulating material (e.g., silicon oxide).

[0042] A first via 50 may be disposed on the first contact plug 40. The first via 50 may be configured to penetrate the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3. The first via 50 may be formed of or comprise at least one metallic material (e.g., tungsten and copper). A first pad 60 may be disposed between the first vias 50, which are adjacent to each other in a direction orthogonal to the top surface of the first substrate 100 (e.g., the third direction Z). The first pad 60 may electrically connect the first vias 50 that are adjacent to each other in the third direction Z. A lowermost subgroup of the first pad 60 may be disposed between the first contact plug 40 and the lowermost subgroup of the first vias 50. The lowermost subgroup of the first pad 60 may connect the first contact plug 40 to the lowermost subgroup of the first vias 50. The first pad 60 may be formed of or comprise at least one metallic material (e.g., tungsten and copper).

[0043] A second via 52 may be disposed on the second contact plug 42. The second via 52 may be configured to penetrate the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3. The second via 52 may be formed of or comprise at least one metallic material (e.g., tungsten and copper). A second pad 62 may be disposed between the second vias 52, the second vias 52 being adjacent to each other in a direction orthogonal to the top surface of the first substrate 100 (e.g., a third direction Z). The second pad 62 can electrically connect the second vias 52 adjacent to each other in the third direction Z. A lowermost subgroup of the second pad 62 may be disposed between the second contact plug 42 and the lowermost subgroup of the second vias 52. The lowermost subgroup of the second pad 62 can connect the second contact plug 42 to the lowermost subgroup of the second vias 52. The second pad 62 may be formed of or comprise at least one metallic material (e.g., tungsten and copper).

[0044] A third via 54 may be disposed on the third contact plug 44. The third via 54 may be configured to penetrate the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3. The third via 54 may be formed of or comprise at least one metallic material (e.g., tungsten and copper). Third pads 64 may be disposed between the third vias 54, which are adjacent to each other in a direction orthogonal to the top surface of the first substrate 100 (e.g., third direction Z). The third pads 64 can electrically connect the third vias 54 that are adjacent to each other in the third direction Z. The lowermost subgroup of the third pads 64 may be disposed between the third contact plug 44 and the lowermost subgroup of the third vias 54. The lowermost subgroup of the third pads 64 can connect the third contact plug 44 to the lowermost subgroup of the third vias 54. The third pads 64 may be formed of or comprise at least one metallic material (e.g., tungsten and copper).

[0045] A fourth interlayer insulating layer (ILD4) may be disposed on the third interlayer insulating layer (ILD3). The fourth interlayer insulating layer (ILD4) may cover the top surface of the third interlayer insulating layer (ILD3) and the top surface of the uppermost subgroup of the first via 50, the second via 52, and the third via 54. The fourth interlayer insulating layer (ILD4) may be formed of or include at least one insulating material (e.g., silicon oxide).

[0046] The first contact line 90 may be disposed on the first contact plug 40. The first contact line 90 may be disposed in the fourth interlayer insulating layer ILD4 and may be disposed on the uppermost subgroup of the first via 50, and may contact the first via 50. It will be understood that when an element is referred to as "in contact with" another element, the element may directly contact said other element, or there may be an intermediate element. Conversely, when an element is referred to as "in direct contact with" another element, there is no intermediate element. The first contact line 90 may be electrically connected to the first contact plug 40 through the first via 50 and the first pad 60. The first contact line 90 may be electrically connected to the first transistor TR1 through the first contact plug 40. The first contact line 90 may be formed of and / or comprise at least one metallic material (e.g., tungsten and copper).

[0047] The second contact line 92 can be disposed on the second contact plug 42. The second contact line 92 can be disposed in the fourth interlayer insulating layer ILD4 and on the uppermost subgroup of the second via 52, and can contact the second via 52. The second contact line 92 can be electrically connected to the second contact plug 42 through the second via 52 and the second pad 62. The second contact line 92 can be electrically connected to the second transistor TR2 through the second contact plug 42. The second contact line 92 can be electrically disconnected from the second chip C2. For example, the second contact line 92 can be electrically disconnected from the second substrate 200 of the second chip C2. The second contact line 92 can be formed of or comprise at least one metallic material (e.g., tungsten and copper).

[0048] In this embodiment, the second contact line 92 can be configured as a passive device. (Refer to...) Figures 6A to 6C The passive component can correspond to, for example, resistor 2, capacitor 4, or inductor 6. When the second contact line 92 is resistor 2 or inductor 6, the second contact line 92 can be configured as follows: Figure 6A and Figure 6CThe single object shown is a single line, for example, having a shape such as a zigzag or spiral, for which multiple line segments are arranged sequentially with spaces between them in a cross-sectional view. Although not shown in the figures, when the second contact line 92 is part of the capacitor 4, multiple second contact lines 92 (e.g., two continuously formed conductors) can be configured as line segments horizontally separated from each other in a cross-sectional view. Two horizontally adjacent segments of the second contact lines 92 can constitute electrodes of the capacitor 4, and a fourth interlayer insulating layer (ILD4) located between the segments of the second contact lines 92 can constitute the dielectric layer of the capacitor 4. Each electrode of the capacitor 4 can have a shape resembling the teeth of a fork, or can have a shape including a trunk with branches extending from it. Each electrode can be a single object, which can be a continuously formed conductor, for example, having a shape for which multiple line segments are arranged sequentially with spaces between them in a cross-sectional view. When the second contact line 92 constitutes an electrode of the capacitor 4, the uppermost horizontally adjacent subgroups in the second via 52 located below the second contact line 92 can also constitute electrodes of the capacitor 4. Furthermore, the third interlayer insulating layer ILD3 located between the uppermost horizontally adjacent subgroups in the second via 52 can constitute the dielectric layer of the capacitor 4.

[0049] The third contact line 94 can be disposed on the third contact plug 44. The third contact line 94 can be disposed in the fourth interlayer insulating layer ILD4 and can be disposed on the uppermost subgroup of the third via 54, and can contact the third via 54. The third contact line 94 can be electrically connected to the third contact plug 44 through the third via 54 and the third pad 64. The third contact line 94 can be electrically connected to the third transistor TR3 through the third contact plug 44. The third contact line 94 can be electrically disconnected from the second chip C2. For example, the third contact line 94 can be electrically disconnected from the second substrate 200 of the second chip C2. The third contact line 94 can have a surface coplanar with the surface of the first contact line 90 and the surface of the second contact line 92. The third contact line 94 can be formed of or comprise at least one metallic material (e.g., tungsten and copper).

[0050] In this embodiment, the third contact line 94 can be configured as a passive device. (Refer to...) Figures 6A to 6C Passive components can correspond to, for example, resistor 2, capacitor 4, or inductor 6. In the case where the third contact line 94 is part of capacitor 4, the third contact line 94 can be as follows: Figure 6BThe third contact lines 94 are horizontally separated from each other. Horizontally adjacent third contact lines 94 can form electrodes of capacitor 4, and the fourth interlayer insulating layer (ILD4) located between the third contact lines 94 can form the dielectric layer of capacitor 4. When the third contact lines 94 form electrodes of capacitor 4, the uppermost horizontally adjacent subgroups in the third via 54 located below the third contact lines 94 can also form electrodes of capacitor 4. Additionally, the third interlayer insulating layer (ILD3) located between the uppermost horizontally adjacent subgroups in the third via 54 can form the dielectric layer of capacitor 4. Although not shown in the figures, if the third contact line 94 is a resistor 2 or an inductor 6, the third contact line 94 can be a single object.

[0051] The second chip C2 disposed on the first chip C1 may include a second substrate 200, a stack body ST, a vertical channel portion VC, a charge storage structure CSS, a cell contact plug CCP, and a bit line BL.

[0052] The second substrate 200 may be disposed on the fourth interlayer insulating layer ILD4. It will be understood that when an element is referred to as being "on" another element, the element may be directly on said other element, or an intermediate element may be present. The second substrate 200 may include a first region R1, a second region R2, a third region R3, and a fourth region R4. The second region R2 of the second substrate 200 may be a cell array region. The first region R1 of the second substrate 200 may be a contact region on which cell contact plugs CCPs are disposed. The third region R3 of the second substrate 200 may be a contact region on which the ends of bit lines BLs are disposed. The fourth region R4 of the second substrate 200 may be an external region on which the stack ST is exposed. The second substrate 200 may be, for example, a silicon wafer, a silicon-germanium wafer, a germanium wafer, or a single-crystal silicon wafer and a single-crystal epitaxial layer grown therefrom.

[0053] The stacked bodies ST can be disposed between the first region R1 of the second substrate 200 and the fourth interlayer insulating layer ILD4, and between the second region R2 of the second substrate 200 and the fourth interlayer insulating layer ILD4. The stacked bodies ST can be spaced apart from each other in the first direction X and can extend in the second direction Y. Each stacked body ST may include a buffer insulating layer 201, gate electrodes GE1, GE2 and GE3, and an insulating pattern 210.

[0054] In the following description, for ease of description, the features of the first chip C1 and the second chip C2 in the third direction Z will be described in reverse (i.e., inverted) manner. Gate electrodes GE1, GE2, and GE3 may be stacked on the first region R1 and the second region R2 of the second substrate 200. Gate electrodes GE1, GE2, and GE3 may include a ground-select gate electrode GE1, a string-select gate electrode GE3, and a unit gate electrode GE2 located between the ground-select gate electrode GE1 and the string-select gate electrode GE3. The lengths of gate electrodes GE1, GE2, and GE3 in the second direction Y may decrease as the distance from the second substrate 200 increases. For example, among gate electrodes GE1, GE2, and GE3, the ground-select gate electrode GE1 may be the longest in the second direction Y, and the string-select gate electrode GE3 may be the shortest in the second direction Y. Gate electrodes GE1, GE2, and GE3 may have ends on the first region R1 of the second substrate 200. Gate electrodes GE1, GE2, and GE3 may be formed of or comprise at least one metallic material (e.g., tungsten) or a metal nitride (e.g., tungsten nitride, titanium nitride, and tantalum nitride). A buffer insulating layer 201 may be disposed between the second substrate 200 and the ground-selective gate electrode GE1. The buffer insulating layer 201 may include, for example, a thermal oxide layer.

[0055] Insulating patterns 210 may be disposed between adjacent gate electrodes GE1, GE2, and GE3 in the third direction Z. The uppermost insulating pattern 210 may be disposed on the string select gate electrode GE3. The length of the insulating pattern 210 in the second direction Y may decrease as the distance from the second substrate 200 increases. For example, the length of each insulating pattern 210 in the second direction Y may be substantially equal to the length of the gate electrode adjacent to the second substrate 200 between adjacent gate electrodes GE1, GE2, and GE3 in the third direction Z. The length of the uppermost insulating pattern 210 in the second direction Y may be substantially equal to the length of the string select gate electrode GE3 in the second direction Y. The insulating pattern 210 may be formed of, for example, silicon oxide or may include, for example, silicon oxide.

[0056] A vertical channel portion VC can be disposed on a second region R2 of the second substrate 200. The vertical channel portion VC can be disposed within a stack ST. For example, the vertical channel portion VC can be configured to penetrate the cell gate electrode GE2, the string select gate electrode GE3, and the insulating pattern 210 except for the insulating pattern 210 closest to and farthest from the second substrate 200. The width of the vertical channel portion VC can increase with increasing distance from the second substrate 200. The vertical channel portion VC can be arranged in a zigzag shape formed in the second direction Y. The sidewalls of the vertical channel portion VC can be flat. Each vertical channel portion VC can include a first portion P1 penetrating the cell gate electrode GE2 and a second portion P2 penetrating the string select gate electrode GE3. In some embodiments, the first portion P1 constitutes a relatively larger portion of the vertical channel portion VC compared to the second portion P2. Additionally, the first portion P1 can be disposed above the second portion P2. The sidewalls of the first portion P1 and the second portion P2 can be inclined but aligned with each other. For example, the first sidewall of the first portion P1 and the second sidewall of the second portion P2 may each be tilted by the same amount or angle and thus aligned. Each vertical channel portion VC may comprise a single layer or multiple layers. The vertical channel portion VC may be formed of or comprise at least one of, for example, monocrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0057] The semiconductor pillar SP can be disposed between the vertical channel portion VC and the second substrate 200. The semiconductor pillar SP can be disposed on the top surface of the second substrate 200 and can penetrate to select the gate electrode GE1. The semiconductor pillar SP and the vertical channel portion VC can be in contact with each other. The semiconductor pillar SP can be formed of a doped semiconductor material or an intrinsic semiconductor material whose conductivity type is the same as that of the second substrate 200, or include a doped semiconductor material or an intrinsic semiconductor material whose conductivity type is the same as that of the second substrate 200.

[0058] The charge storage structure CSS can be disposed between the vertical channel portion VC and the unit gate electrode GE2, and between the vertical channel portion VC and the series selection gate electrode GE3. The charge storage structure CSS can extend along the outer wall of the vertical channel portion VC and can extend in the third direction Z. For example, the charge storage structure CSS can have a shape surrounding the outer wall of the vertical channel portion VC. The charge storage structure CSS can include at least one of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer, and can have a single-layer or multi-layer structure.

[0059] like Figure 5As shown, each charge storage structure CSS may include a tunnel insulating layer TL, a barrier insulating layer BLL, and a charge storage layer CTL. The tunnel insulating layer TL may be configured to be adjacent to each vertical channel portion VC and may surround the outer wall of the vertical channel portion VC. The barrier insulating layer BLL may be configured to be adjacent to the cell gate electrode GE2 and the string selection gate electrode GE3. The charge storage layer CTL may be disposed between the tunnel insulating layer TL and the barrier insulating layer BLL. The tunnel insulating layer TL may be formed of, for example, silicon oxide and at least one of a high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)) or may include, for example, silicon oxide and at least one of a high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The barrier insulating layer (BLL) can be formed of, for example, silicon oxide and at least one of a high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)), or include, for example, silicon oxide and at least one of a high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The charge storage layer (CTL) can be formed of, for example, silicon nitride or include, for example, silicon nitride.

[0060] An interstitial filling layer 230 may be disposed within the internal space of the vertical channel portion VC. The interstitial filling layer 230 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, or may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. A channel pad CP may be disposed on a portion of the top surface of the vertical channel portion VC and a portion of the side surface of the charge storage structure CSS. The channel pad CP may be formed of, or include, at least one of a conductive material and a semiconductor material doped to have a conductivity type different from that of the vertical channel portion VC. A gate insulating pattern 240 may be disposed between each semiconductor pillar SP and the ground select gate electrode GE1. The gate insulating pattern 240 may have side surfaces that are convexly curved in opposite directions. The gate insulating pattern 240 may include, for example, a thermal oxide layer.

[0061] A horizontal insulating layer PL may be disposed between the charge storage structure CSS and the unit gate electrode GE2, and between the charge storage structure CSS and the series selection gate electrode GE3. The horizontal insulating layer PL may extend to cover the top and bottom surfaces of the unit gate electrode GE2 and the top and bottom surfaces of the series selection gate electrode GE3. The horizontal insulating layer PL may be formed of or include at least one of a high-k dielectric material (e.g., alumina (Al2O3) and hafnium oxide (HfO2)).

[0062] A common-source region CSR can be disposed within the second substrate 200 between stack bodies ST. The common-source region CSR can have a different conductivity type than that of the second substrate 200. The common-source region CSR can extend into a fourth region R4 of the second substrate 200. The stack bodies ST can be configured to expose the common-source region CSR.

[0063] An interlayer insulating pattern (IDP) can be disposed on the first region R1 and the fourth region R4 of the second substrate 200. The IDP can cover the stepped structure STS of the stack ST, which is disposed on the top surface of the first region R1 and the fourth region R4 of the second substrate 200. The IDP can be formed of, for example, silicon oxide or include, for example, silicon oxide. A fifth interlayer insulating layer (ILD5) can be disposed on the stack ST and the IDP. The ILD5 can be formed of, for example, silicon oxide or include, for example, silicon oxide.

[0064] Cell contact plugs (CCPs) may be disposed on a first region R1 of the second substrate 200. Cell contact plugs (CCPs) may be disposed on the ends of gate electrodes GE1, GE2, and GE3, each of the ends of gate electrodes GE1, GE2, and GE3 extending into the first region R1 of the second substrate 200. Cell contact plugs (CCPs) may be configured to penetrate the fifth interlayer insulating layer (ILD5) and the interlayer insulating pattern (IDP), and may contact the ends of gate electrodes GE1, GE2, and GE3. Cell contact plugs (CCPs) may be electrically connected to gate electrodes GE1, GE2, and GE3. Cell contact plugs (CCPs) may be formed of at least one metallic material (e.g., tungsten, copper, and aluminum) or a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, and aluminum nitride), or may include at least one metallic material (e.g., tungsten, copper, and aluminum) or a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, and aluminum nitride).

[0065] The bit line contact plug BCP can be disposed on the second region R2 of the second substrate 200. The bit line contact plug BCP can be configured to penetrate the fifth interlayer insulation layer ILD5 and can be disposed on the channel pad CP. The bit line contact plug BCP can be electrically connected to the vertical channel portion VC. The bit line contact plug BCP can be formed of at least one metallic material (e.g., tungsten, copper, and aluminum) or a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, and aluminum nitride), or include at least one metallic material (e.g., tungsten, copper, and aluminum) or a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, and aluminum nitride).

[0066] A sixth interlayer insulating layer (ILD6) may be disposed on the fifth interlayer insulating layer (ILD5). The sixth interlayer insulating layer (ILD6) may be formed of, for example, silicon oxide or include, for example, silicon oxide. A fourth via 241 may be disposed on the cell contact plug (CCP). The fourth via 241 may be configured to penetrate the sixth interlayer insulating layer (ILD6) and contact the cell contact plug (CCP). A fifth via 242 may be disposed on the bit line contact plug (BCP). The fifth via 242 may be configured to penetrate the sixth interlayer insulating layer (ILD6) and contact the bit line contact plug (BCP). The fourth via 241 and the fifth via 242 may be formed of or include at least one metallic material (e.g., tungsten, copper, and aluminum).

[0067] A fourth pad 244 may be disposed on the sixth interlayer insulating layer ILD6. The fourth pad 244 may contact the surface of the fourth via 241. A bit line BL may be disposed on the sixth interlayer insulating layer ILD6. The bit line BL may contact the surface of the fifth via 242. The bit line BL may be electrically connected to the vertical channel portion VC. The bit line BL may extend in a first direction X and may be spaced apart from each other in a second direction Y intersecting the first direction X. The fourth pad 244 and the bit line BL may be formed of or comprise at least one metallic material (e.g., tungsten, copper, and aluminum). A seventh interlayer insulating layer ILD7 may be disposed on the sixth interlayer insulating layer ILD6. The seventh interlayer insulating layer ILD7 may cover the fourth pad 244 and the bit line BL. The seventh interlayer insulating layer ILD7 may comprise a silicon oxide layer. A sixth via 248 may be disposed in the seventh interlayer insulating layer ILD7. The sixth via 248 may contact the fourth pad 244. The sixth via 248 may be formed of or include at least one metallic material (e.g., tungsten, copper and aluminum).

[0068] An eighth interlayer insulating layer (ILD8) may be disposed on the seventh interlayer insulating layer (ILD7). The eighth interlayer insulating layer (ILD8) may cover the surface of the sixth via 248. The eighth interlayer insulating layer (ILD8) may include, for example, a silicon oxide layer. A fourth contact line 250 may be disposed in the eighth interlayer insulating layer (ILD8). The fourth contact line 250 may contact and be electrically connected to the sixth via 248. The fourth contact line 250 may be configured to correspond to and contact the first contact line 90. For example, the first contact line 90 and the fourth contact line 250 may be used as bonding pads to connect the first chip C1 and the second chip C2 to each other.

[0069] In this embodiment, gate electrodes GE1, GE2, and GE3 can be electrically connected to a first transistor TR1. The first transistor TR1 can apply voltage to the gate electrodes GE1, GE2, and GE3. The first transistor TR1 can be electrically connected to a second chip C2, while the second transistor TR2 and the third transistor TR3 can be electrically disconnected from the second chip C2.

[0070] According to an embodiment of the inventive concept, passive devices can be disposed on the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4 of the first chip C1. In the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4 of the first chip C1, no bonding pads are provided to electrically connect the transistors of the first chip C1 to the cell array of the second chip C2. For example, no bonding pads are present in the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4, and the passive device is disposed in at least one of the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4. Therefore, since the passive device is disposed in a region that has not been used previously, it is possible to improve the operating characteristics of the three-dimensional semiconductor memory device and to reduce the chip size.

[0071] Figure 7 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0072] Reference Figure 7 The second chip C2 may include a fifth contact line 252 and a sixth contact line 253. The fifth contact line 252 may be disposed in the eighth interlayer insulating layer (ILD8), may contact the third contact line 94, and may be electrically connected to the third transistor TR3. The surface of the fifth contact line 252 may be coplanar with the surface of the fourth contact line 250, and the surface of the fourth contact line 250 may be in direct contact with the first contact line 90. The fifth contact line 252 may be electrically disconnected from the second substrate 200 and / or the common-source region (CSR). For example, the fifth contact line 252 may be electrically disconnected from other conductive elements of the second chip C2.

[0073] The sixth contact line 253 can be disposed in the eighth interlayer insulating layer (ILD8), can contact the second contact line 92, and can be electrically connected to the second transistor TR2. The surface of the sixth contact line 253 can be coplanar with the surface of the fourth contact line 250, and the surface of the fourth contact line 250 is in direct contact with the first contact line 90. The sixth contact line 253 can be electrically disconnected from the second substrate 200 and / or the common source region CSR. For example, the sixth contact line 253 can be electrically disconnected from other conductive elements of the second chip C2.

[0074] According to embodiments of the inventive concept, by providing a fifth contact line 252 on a third contact line 94 constituting a passive device, or by providing a sixth contact line 253 on a second contact line 92 constituting a passive device, the vertical thickness (i.e., the thickness in the third direction Z) of the passive device can be increased. Therefore, by adjusting the resistance and capacitance of the passive device, the electrical characteristics of the three-dimensional semiconductor memory device can be improved.

[0075] Figure 8 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0076] Reference Figure 8 The semiconductor pillar SP and gate insulating pattern 240 can be omitted from the second chip C2. In this case, the vertical channel portion VC and the charge storage structure CSS can be in direct contact with the second substrate 200.

[0077] Figure 9 It is along Figure 3 The line I-I' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0078] Reference Figure 9 Each stack ST may include a lower stack LST and an upper stack UST. The lower stack LST may be disposed on the second substrate 200, and the upper stack UST may be disposed on the lower stack LST. The upper stack UST may be disposed between the lower stack LST and the fifth interlayer insulating layer ILD5.

[0079] The lower stack (LST) may include a buffer insulating layer 201, a ground select gate electrode GE1, a unit gate electrode GE2, and an insulating pattern 210. The ground select gate electrode GE1 may be disposed on the buffer insulating layer 201, and the unit gate electrodes GE2 may be sequentially formed on the ground select gate electrode GE1. The insulating pattern 210 may be disposed between the ground select gate electrode GE1 and the unit gate electrodes GE2 adjacent to the second substrate 200, may be disposed between adjacent unit gate electrodes GE2, and may be disposed on the other unit gate electrode GE2 farthest from the second substrate 200.

[0080] The upper stack UST can be disposed on the lower stack LST. The upper stack UST may include a unit gate electrode GE2, a series select gate electrode GE3, and an insulating pattern 210. The unit gate electrodes GE2 of the upper stack UST can be sequentially formed on the lower stack LST, and the series select gate electrode GE3 can be disposed on the unit gate electrodes GE2 away from the lower stack LST. The insulating pattern 210 of the upper stack UST can be disposed between the unit gate electrodes GE2 and on the series select gate electrode GE3.

[0081] A vertical channel portion VC can be configured to penetrate both the lower stack LST and the upper stack UST. Each vertical channel portion VC may include a first portion P1 penetrating the lower stack LST and a second portion P2 penetrating the upper stack UST. The sidewall of the first portion P1 of the vertical channel portion VC may not be aligned with the sidewall of the second portion P2 of the vertical channel portion VC. For example, the first sidewall of the first portion P1 of the vertical channel portion VC may not be aligned with the second sidewall of the second portion P2 of the vertical channel portion VC, or it may be offset relative to the second sidewall of the second portion P2 of the vertical channel portion VC. Additionally, in a side view, the lowermost portion of the second portion P2 may have the maximum width in the horizontal direction, and the uppermost portion of the second portion P2 may have the minimum width in the horizontal direction. Furthermore, in a side view, the lowermost portion of the first portion P1 may have the maximum width in the horizontal direction, and the uppermost portion of the first portion P1 may have the minimum width in the horizontal direction. Moreover, in the region of the vertical channel portion VC corresponding to the transition region between the first portion P1 and the second portion P2, the sidewall of the first portion P1 may extend outward beyond the edge of the sidewall of the second portion P2.

[0082] Figure 10 This is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 11 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0083] Reference Figure 10 and Figure 11The second chip C2 may include a common-source contact plug CSCP, a seventh via 260, a fifth pad 262, an eighth via 264, and a fifth contact line 266. The common-source contact plug CSCP may be disposed on a fourth region R4 of the second substrate 200. The common-source contact plug CSCP may be disposed on a fourth region R4 of the second substrate 200 to penetrate the interlayer insulation pattern IDP and the fifth interlayer insulation layer ILD5, and may be electrically connected to the common-source region CSR. The common-source contact plug CSCP may be formed of or include at least one metallic material (e.g., tungsten, copper, and aluminum) or a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, and aluminum nitride).

[0084] A seventh via 260 may be disposed on the common-source contact plug CSCP. The seventh via 260 may be configured to penetrate the sixth interlayer insulating layer ILD6 and contact the common-source contact plug CSCP. A fifth pad 262 may be disposed on the seventh via 260. The fifth pad 262 may be disposed in the seventh interlayer insulating layer ILD7 and may contact the seventh via 260. An eighth via 264 may be disposed on the fifth pad 262. The eighth via 264 may be disposed in the seventh interlayer insulating layer ILD7 and may contact the fifth pad 262. The seventh via 260, the fifth pad 262, and the eighth via 264 may be formed of or comprise at least one metallic material (e.g., tungsten, copper, and aluminum).

[0085] The fifth contact line 266 may be disposed on the eighth via 264. The fifth contact line 266 may be disposed in the eighth interlayer insulating layer (ILD8) and may contact the eighth via 264. When viewed in a plan view, the fifth contact line 266 may be misaligned with the third contact line 94 (e.g., misaligned or offset). For example, the fifth contact line 266 may not contact the third contact line 94. The fifth contact line 266 and the third contact line 94 may be electrically disconnected from each other. For example, the fifth contact line 266 may be electrically disconnected from the third transistor TR3. For example, the third contact line 94 may be electrically disconnected from the common-source region (CSR).

[0086] In some embodiments, the fifth contact line 266 may be connected to a driving device that applies voltage to the common-source region CSR. Exemplary driving devices may include circuitry or another electronic component for controlling different circuits or electronic components. In some embodiments, the fifth contact line 266, together with the third contact line 94, may constitute a passive device. In this case, the fifth contact line 266 may constitute the first electrode of a metal-insulator-metal (MIM) capacitor, the third contact line 94 may constitute the second electrode of the MIM capacitor, and the fourth interlayer insulating layer ILD4 and the eighth interlayer insulating layer ILD8 may serve as the dielectric layers of the MIM capacitor. The fifth contact line 266 and the third contact line 94 may be applied with different voltages. In some embodiments, the fifth contact line 266 may constitute a passive device without being combined with the third contact line 94. In this case, the fifth contact line 266 may constitute a capacitor, inductor, or resistor.

[0087] Figure 12 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0088] Reference Figure 12 The second chip C2 may include a seventh contact line 270 and an eighth contact line 272. The seventh contact line 270 may be disposed in the eighth interlayer insulating layer ILD8 and may be aligned with the third contact line 94 in the third direction Z. The seventh contact line 270 may contact and be electrically connected to the third contact line 94. The seventh contact line 270 may be horizontally displaced from the fifth contact line 266. The seventh contact line 270 may be electrically connected to the third transistor TR3. The seventh contact line 270, together with the third contact line 94, may constitute a passive device.

[0089] The eighth contact line 272 can be disposed in the eighth interlayer insulating layer ILD8 and can be aligned with the second contact line 92 in the third direction Z. The eighth contact line 272 can contact the second contact line 92 and can be electrically connected to the second contact line 92. The eighth contact line 272 can be electrically connected to the second transistor TR2. The eighth contact line 272 and the second contact line 92 together can constitute a passive device.

[0090] Figure 13 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0091] Reference Figure 13The second chip C2 may include a ninth via 274 and a tenth via 276. The ninth via 274 may be disposed in the seventh interlayer insulating layer (ILD7). The ninth via 274 may be aligned with the seventh contact line 270 in the third direction Z. The ninth via 274 may contact and be electrically connected to the seventh contact line 270. The ninth via 274 may be horizontally displaced from the eighth via 264. In other words, the ninth via 274 may be electrically disconnected from the eighth via 264 and the common-source contact plug CSCP. The ninth via 274 may be electrically connected to the third transistor TR3. The ninth via 274, together with the seventh contact line 270 and the third contact line 94, can constitute a passive device.

[0092] The tenth via 276 can be disposed in the seventh interlayer insulating layer (ILD7). The tenth via 276 can be disposed in the seventh interlayer insulating layer (ILD7) to contact and be electrically connected to the eighth contact line 272. The tenth via 276 can be electrically disconnected from the second chip C2. The tenth via 276 can be electrically connected to the second transistor TR2. The tenth via 276, together with the eighth contact line 272 and the second contact line 92, can constitute a passive device.

[0093] Figure 14 It is along Figure 10 The section cut by line II-II' shows a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0094] Reference Figure 14The stack ST may include a first source pattern CSP1 and a second source pattern CSP2. The first source pattern CSP1 may be disposed between the second substrate 200 and the insulating pattern 210 closest to the second substrate 200, and the second source pattern CSP2 may be disposed between the first source pattern CSP1 and the insulating pattern 210 closest to the second substrate 200. A vertical channel portion VC may be configured to penetrate the stack ST and be partially inserted into the second substrate 200. The first source pattern CSP1 may extend at least partially (e.g., protrude) into the region between a portion of the sidewall of the vertical channel portion VC and a portion of the sidewall of the second source pattern CSP2, and into the region between a portion of the sidewall of the vertical channel portion VC and a portion of the sidewall of the second substrate 200. For example, the first source pattern CSP1 may protrude at least partially into the lower region of the second substrate 200 and the upper region of the second source pattern CSP2 in regions adjacent to (adjacent to) the upper portions of the respective vertical channel portions VC. A common-source region (CSR) can be disposed in the first region R1, the second region R2, and the fourth region R4 of the second substrate 200. The common-source region (CSR) can be electrically connected to the first source pattern (CSP1). The first source pattern (CSP1) and the second source pattern (CSP2) can be formed of or include at least one conductive material containing n-type impurities (e.g., phosphorus (P) or arsenic (As)). For example, the first source pattern (CSP1) and the second source pattern (CSP2) can be n-type polysilicon patterns.

[0095] According to embodiments of the inventive concept, a first chip having transistors and a second chip having a cell array can be vertically stacked. Passive devices can be disposed on a second peripheral circuit region PR2 and a fourth peripheral circuit region PR4 of the first chip. In the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4 of the first chip, no bonding pads are provided to electrically connect the transistors of the first chip to the cell array of the second chip. For example, no bonding pads are present in the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4, and passive devices are disposed in at least one of the second peripheral circuit region PR2 and the fourth peripheral circuit region PR4. For example, a first passive device can be disposed in the second peripheral circuit region PR2, and different second passive devices can be disposed in the fourth peripheral circuit region PR4. Therefore, since the passive devices are disposed in areas that have not been used previously, the operating characteristics of the three-dimensional semiconductor memory device can be improved, and the chip size can be reduced.

[0096] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising a first chip and a second chip stacked on the first chip, in, The first chip includes: The first substrate includes a first peripheral circuit region and a second peripheral circuit region; The first contact plug is located on the first peripheral circuit area of ​​the first substrate; The second contact plug is located on the second peripheral circuit region of the first substrate; and The first passive device is located on and electrically connected to the second contact plug. The second chip includes: A second substrate is disposed on the first chip. The second substrate includes a cell array region and a contact region, wherein the cell array region and the contact region are vertically stacked with the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. A gate electrode is stacked on the cell array region and contact region of the second substrate and disposed between the second substrate of the first chip and the second chip; and The cell contact plug is disposed on the contact area of ​​the second substrate and on the end of the gate electrode, and is connected to the first contact plug. The first passive device is vertically located between the gate electrode and the second contact plug, and includes a first contact line.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The first chip also includes a second contact line located on the first contact plug. The second chip also includes a third contact line located on the unit contact plug, and The second contact wire contacts the third contact wire.

3. The three-dimensional semiconductor memory device according to claim 1, wherein, The first passive device includes multiple first contact lines. The plurality of first contact lines are disposed on the second contact plug and are horizontally separated from each other. The multiple first contact lines constitute the electrodes of the capacitor.

4. The three-dimensional semiconductor memory device according to claim 1, wherein, The first passive device physically contacts the second chip and is electrically connected to the first chip, and The first passive device is electrically disconnected from the second chip at the point where it contacts the second chip.

5. The three-dimensional semiconductor memory device according to claim 1, wherein, The second chip also includes: A second contact line is disposed on the first passive device and contacts the first surface of the first passive device; and The third contact line is located on the unit contact plug. The third contact line electrically connects the first chip and the second chip to each other, and The second contact wire is electrically connected to the first chip and electrically disconnected from the second chip.

6. The three-dimensional semiconductor memory device according to claim 1, wherein, The first chip also includes transistors located on a second peripheral circuit region of the first substrate. The transistor includes a peripheral gate electrode and source / drain regions, the source / drain regions being disposed in portions of a first substrate located on either side of the peripheral gate electrode, and... The second contact plug is electrically connected to at least one of the source / drain region and the peripheral gate electrode.

7. The three-dimensional semiconductor memory device according to claim 1, wherein, The first substrate also includes a third peripheral circuit region. The second substrate also includes an outer region that is vertically stacked with the third peripheral circuit region and exposed by a gate electrode. The first chip also includes: The transistor is located on the third peripheral circuit region of the first substrate; The third contact plug connects to the transistor; and The second passive device is disposed on and electrically connected to the third contact plug, wherein... The second passive device includes a second contact wire.

8. The three-dimensional semiconductor memory device according to claim 7, wherein, The surface of the second passive device is coplanar with the surface of the first passive device.

9. The three-dimensional semiconductor memory device according to claim 1, wherein, The first substrate also includes a third peripheral circuit region. The second substrate further includes: an outer region, vertically stacked with the third peripheral circuit region and exposed by a gate electrode; and a common-source region, disposed in the outer region of the second substrate. The first chip includes: The transistor is located on the third peripheral circuit region of the first substrate; The third contact plug connects to the transistor; and The second contact wire is disposed on and connected to the third contact plug. The second chip includes: A common-source contact is located on the outer region of the second substrate; and The third contact line is disposed on and connected to the common source contact element, and When viewed in a plan view, the third contact line is not aligned with the second contact line.

10. The three-dimensional semiconductor memory device according to claim 9, wherein, The second and third contact lines, which are adjacent to each other, constitute the electrodes of the capacitor.

11. The three-dimensional semiconductor memory device according to claim 9, wherein, The second contact wire constitutes a passive device, and The third contact line is connected to a driver device configured to apply voltage to the common source region.

12. The three-dimensional semiconductor memory device according to claim 1, wherein, The gate electrode includes a first gate electrode and a second gate electrode located on the first gate electrode. The second chip also includes a vertical channel portion disposed on the cell array region of the second substrate to penetrate the first gate electrode and the second gate electrode. The vertical channel portion includes: a first portion penetrating a first gate electrode; and a second portion disposed on the first portion to penetrate a second gate electrode, and The sidewalls of the first part are aligned with the sidewalls of the second part.

13. The three-dimensional semiconductor memory device according to claim 1, wherein, The gate electrode includes a first gate electrode and a second gate electrode located on the first gate electrode. The three-dimensional semiconductor memory device further includes a vertical channel portion disposed on the cell array region of the second substrate to penetrate the gate electrode. The vertical channel portion includes: a first portion penetrating a first gate electrode; and a second portion disposed on the first portion to penetrate a second gate electrode, and The first part and the second part are not aligned.

14. The three-dimensional semiconductor memory device according to claim 1, wherein, The gate electrode includes the uppermost gate electrode adjacent to the second substrate. The second chip also includes: The first source pattern is located between the second substrate and the topmost gate electrode; The second source pattern is located between the first source pattern and the topmost gate electrode; and The vertical channel portion is disposed on the cell array region of the second substrate to penetrate the gate electrode and the first and second source patterns, and is disposed in a portion of the second substrate. The first source pattern contacts the sidewall of the vertical channel portion and extends into the region between a portion of the sidewall of the vertical channel portion and a portion of the sidewall of the second source pattern, and into the region between a portion of the sidewall of the vertical channel portion and a portion of the sidewall of the second substrate.

15. The three-dimensional semiconductor memory device according to claim 1, wherein, From a top-down view, the contact area of ​​the second chip corresponds to the bonding area, where the first chip is electrically connected and physically connected to the second chip. In the top-down view, the cell array region of the second chip corresponds to the non-bonded region, where the first chip is not electrically connected to the second chip.

16. The three-dimensional semiconductor memory device according to claim 2, wherein, In the cross-sectional view, the upper surface of the first passive device is at the same height as the surface of the second contact line of the first chip, and the second contact line is electrically connected and physically connected to the conductive portion of the second chip.

17. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: The first substrate includes a first peripheral circuit region and a second peripheral circuit region; The first transistor is located on the first peripheral circuit region of the first substrate; The first contact plug is connected to the first transistor; The first contact line is located on the first contact plug; The second transistor is located on the second peripheral circuit region of the first substrate; The second contact plug is connected to the second transistor; The second substrate is disposed on the first contact line. The second substrate includes a first region and a second region that are vertically stacked with the first peripheral circuit region and the second peripheral circuit region, respectively. A gate electrode is stacked on a second region of a second substrate and located between the second substrate and the second contact plug; as well as A cell contact plug is disposed on a second region of the second substrate and on the end of the gate electrode, and is connected to the second contact plug. The first contact line is electrically disconnected from the second substrate and is included in a first passive device located vertically between the gate electrode and the first contact plug.

18. The three-dimensional semiconductor memory device of claim 17, further comprising: The second contact line is located on the second contact plug; The third contact line is located between the unit contact plug and the second contact line; as well as The fourth contact line is located above the first contact line but does not contact the first contact line. The second contact wire contacts the third contact wire.

19. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: The first substrate includes a first peripheral circuit region and a second peripheral circuit region; The first transistor is located on the first peripheral circuit region of the first substrate; An interlayer insulating layer covers the first transistor on the first substrate; The first contact plug is configured to penetrate the interlayer insulation layer and connect to the first transistor; The first contact line is located on the first contact plug; The second substrate is disposed on the interlayer insulating layer. The second substrate includes a first region and a second region that are vertically stacked with the first peripheral circuit region and the second peripheral circuit region, respectively. A gate electrode is disposed between the second substrate and the interlayer insulating layer and stacked on a second region of the second substrate; as well as The vertical channel section penetrates the gate electrode. Wherein, adjacent first contact lines in the first contact line constitute the electrodes of a capacitor located vertically between the gate electrode and the first contact plug.

20. The three-dimensional semiconductor memory device according to claim 19, wherein, The first substrate also includes a third peripheral circuit region. The second substrate also includes a third region that is vertically superimposed on the third peripheral circuit region of the first substrate. The gate electrode extends into the third region. The three-dimensional semiconductor memory device further includes: The second transistor is located on the third peripheral circuit region of the first substrate; The second contact plug is configured to penetrate the interlayer insulation layer and connect to the second transistor; A cell contact plug is disposed on the third region of the second substrate and on the end of the gate electrode, and is connected to the second contact plug; The second contact line is located on the second contact plug; and The third contact line is located between the unit contact plug and the second contact line, and The second contact wire contacts the third contact wire.

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