A high-voltage high-electron-mobility transistor

Abstract

The present application relates to a semiconductor power device, and more specifically, to a high-voltage high-electron-mobility transistor. The high-voltage high-electron-mobility transistor comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; the channel layer is located between the barrier layer and the substrate, and the channel layer comprises a P-type III-V semiconductor layer, wherein the projections of the nucleation layer and the drain electrode on the substrate overlap at least partially, the drain electrode is in electrical contact with the two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V semiconductor layer, and the gate electrode is located on the barrier layer.

Description

Technical Field

[0001] The present application relates to a semiconductor power device, and in particular to a high-voltage and high-electron-mobility transistor. Background Art

[0002] Group III-V compound semiconductors include at least one Group III element and at least one Group V element, including but not limited to gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), etc. Group III nitride semiconductors include nitrogen and at least one Group III element, including but not limited to GaN, AlGaN, InN, AlN, InGaN, InAlGaN, etc.

[0003] High electron mobility transistors (HEMTs) utilize III-V heterojunction structures, such as III-nitride heterojunctions, to generate two-dimensional electron gas (2DEG) at the heterojunction interface formed by III-nitride materials, which allows high current density to pass through with relatively low resistance loss, and gradually achieves a voltage resistance of 600V or even 1200V. Conventional III-nitride high electron mobility transistors are usually depletion-type devices. Due to the advantages of high breakdown voltage, high current density, and low on-resistance, III-nitride high electron mobility transistors need to avoid the high electron mobility transistor from being turned off without gate voltage control to protect the circuit and load. Therefore, it is desirable to provide a III-nitride high electron mobility transistor that is normally off, or an enhancement mode transistor.

[0004] Thus, there is a need to overcome the shortcomings and deficiencies in the prior art and manufacture high voltage high electron mobility transistors and enhanced III-V group high electron mobility transistors.

[0005] In the relevant patent application, we have proposed to realize normally-off devices and or higher voltage resistance through structures such as P-type buried layers, and have also described the relevant device structures in detail. However, in the specific implementation process, during the selective epitaxy, the nucleation area is located at the source. This is mainly because the high electron mobility transistor is a symmetrical structure for the source, with gate electrodes and drain electrodes on both sides from the source. At the same time, the distance from the source electrode to the gate electrode is usually much smaller than the distance from the gate electrode to the drain electrode, and the lateral epitaxy from the source to the gate is much shorter than the distance from the drain to the gate, which is conducive to the fabrication accuracy of complex structures at the source and gate through epitaxy. At the same time, the voltage in the source area is very low, and the crystal quality in the nucleation area is relatively poor, so when the source is located in a low-quality area, the impact is minimal due to the low voltage.

[0006] In comparison, if the nucleus is formed from the gate or other regions and then epitaxially grown, the structures on both sides of the epitaxial growth are basically symmetrical, which is not conducive to forming many asymmetric structures. And if the epitaxial growth starts from the gate electrode region, the distance between the gate source and the gate drain is quite different, which is not conducive to making good use of the chip area.

[0007] However, it is also possible to nucleate from the area corresponding to the projection of the drain region on the substrate and then grow laterally. This is also conducive to forming some special structures in the drain region to improve certain performance. At the same time, before forming the complex structure at the source and the gate, the crystal quality of the epitaxial layer can be optimized. In this way, the complex structure at the source and the gate can also obtain better crystal quality and good electrical properties. Regardless of whether the nucleation is from the source or the drain region, the required stacked layout structure can be formed from source to gate to drain or from drain to gate to source in sequence. Summary of the invention

[0008] The basic principle of the present application is to introduce a P-type III-V semiconductor layer and use doping modulation technology to adjust the electric field distribution of a high electron mobility transistor device and improve its voltage resistance and realize an enhanced device.

[0009] The basic structure of the high electron mobility transistor provided by the present application is to selectively epitaxially grow the III-V semiconductor layer from the corresponding area of ​​the drain electrode, form semiconductor layer areas with different doping concentrations through modulation doping technology, and finally form a high electron mobility transistor structure. The high electric field in the local channel layer is reduced, the electric field distribution is improved, and the device performance and reliability are improved.

[0010] The high-voltage high-electron-mobility transistor provided in the present application comprises a device structure including a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; the channel layer is located between the barrier layer and the substrate, and the channel layer includes a P-type III-V semiconductor layer, and the P-type III-V semiconductor layer is at least partially located between the drain electrode and the gate electrode, which is insufficient to significantly deplete the two-dimensional electron gas in the channel except the gate electrode stack, wherein the nucleation layer corresponds to the drain electrode region, the drain electrode is electrically in contact with the channel layer above the nucleation layer, and the source electrode is electrically in contact with the P-type III-V semiconductor layer.

[0011] On the other hand, the device electrode structure can be configured as follows: the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas, the gate electrode is located above the barrier layer, and the independent body electrode is in electrical contact with the P-type III-V semiconductor layer near the source electrode.

[0012] On the other hand, a low-doped or unintentionally doped Group III-V semiconductor layer may be inserted between the barrier layer and the P-type Group III-V semiconductor layer.

[0013] On the other hand, a SiNx passivation layer can be in-situ grown on the barrier layer.

[0014] On the other hand, a gate dielectric layer may be formed on the barrier layer.

[0015] On the other hand, an insulating layer is provided on the substrate, and after an opening is formed in the insulating layer through masking, etching and other processes, a nucleation layer is formed at the opening, and then an epitaxial layer structure including a P-type III-V semiconductor layer is grown by lateral epitaxy; or a nucleation layer is grown on the substrate, and an insulating layer is formed on the nucleation layer, and an opening is formed in the insulating layer through masking, etching and other processes to expose the nucleation layer, and then an epitaxial layer structure including a P-type III-V semiconductor layer is grown by lateral epitaxy.

[0016] On the other hand, an epitaxial layer structure is grown on the substrate in a lateral epitaxial manner, with the drain electrode region as the center and expanding outward to form a symmetrical high electron mobility transistor structure with the drain electrode region as the center.

[0017] On the other hand, when the epitaxial layer structure is grown by lateral epitaxy on the substrate, a lightly doped III-V semiconductor layer first doping region, a strongly P-type III-V semiconductor layer first doping region, and a P-type III-V semiconductor layer first doping region are first epitaxially formed on the nucleation layer, and part of the III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the lightly doped III-V semiconductor layer first doping region, the strongly P-type III-V semiconductor layer first doping region, and the modulated P-type III-V semiconductor layer of the P-type III-V semiconductor layer first doping region; a drain electrode is formed above the lightly doped III-V semiconductor layer first doping region, a gate stack structure is correspondingly formed above the strongly P-type III-V semiconductor layer first doping region, and a source electrode is formed above the P-type III-V semiconductor layer first doping region.

[0018] On the other hand, when the epitaxial layer structure is grown on the substrate by lateral epitaxy, a lightly doped group III-V semiconductor layer first doping region is first formed on the nucleation layer by epitaxy, and then a P-type group III-V semiconductor layer first doping region and a P-type group III-V semiconductor layer second doping region are formed by epitaxy, and a portion of the group III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the lightly doped group III-V semiconductor layer first doping region, the P-type group III-V semiconductor layer first doping region, and the P-type group III-V semiconductor layer second doping region. -V group semiconductor layer; a drain electrode is formed above the first doped region of the lightly doped III-V group semiconductor layer, and a gate stack structure is formed in the portion of the second doped region of the P-type III-V group semiconductor layer close to the first doped region of the P-type III-V group semiconductor layer, that is, the first doped region of the P-type III-V group semiconductor layer is located between the drain electrode and the gate electrode, the doping concentration of the first doped region of the P-type III-V group semiconductor layer is adjustable, which can improve the electric field distribution near the drain side below the gate electrode, and a source electrode and / or a body electrode are formed above the second doped region of the P-type III-V group semiconductor layer.

[0019] On the other hand, when the epitaxial layer structure is grown by lateral epitaxy on the substrate, a lightly doped first doped region of the group III-V semiconductor layer is first epitaxially formed on the nucleation layer, and then a first doped region of the group III-V semiconductor layer, a first doped region of the group III-V semiconductor layer with a strong P-type, and a second doped region of the group III-V semiconductor layer are epitaxially formed. A portion of the group III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the first doped region of the lightly doped group III-V semiconductor layer, the first doped region of the group III-V semiconductor layer, the first doped region of the group III-V semiconductor layer with a strong P-type, and the second doped region of the group III-V semiconductor layer. a modulated P-type III-V semiconductor layer in the second doping region of the layer; a drain electrode is formed above the first doping region of the lightly doped III-V semiconductor layer, and a gate stack structure is correspondingly formed above the first doping region of the strongly P-type III-V semiconductor layer, the first doping region of the P-type III-V semiconductor layer is located between the first doping region of the lightly doped III-V semiconductor layer and the first doping region of the strongly P-type III-V semiconductor layer, the doping concentration of the first doping region of the P-type III-V semiconductor layer is adjustable, which can improve the electric field distribution below the gate electrode near the drain side, and a source electrode and / or a body electrode is formed above the second doping region of the P-type III-V semiconductor layer.

[0020] On the other hand, a low-doped or unintentionally doped Group III-V semiconductor layer may be inserted above the modulated P-type Group III-V semiconductor layer.

[0021] On the other hand, the barrier layer above the P-type III-V semiconductor layer may further cover the passivation layer.

[0022] On the other hand, the first doped region of the lightly doped Group III-V semiconductor layer is lightly doped or undoped.

[0023] The P-type III-V semiconductor layer of the present application is grown laterally epitaxially starting from the area corresponding to the drain electrode. The P-type doping concentration can adjust the proportion of the doped carrier gas atmosphere during the growth process as needed. By adjusting the electric field distribution through P-type doping, high-quality P-type doping and its spatial regulation of the two-dimensional electron gas 2DEG at the AlGaN / GaN heterojunction interface can be obtained; and by modulating the doping concentration of the semiconductor layer under the drain electrode, the gate electrode, and the source electrode, and using the source electrode or the body electrode to control the modulation of the potential of the P-type III-V semiconductor layer, the voltage resistance of the high electron mobility transistor can be improved, and functions such as normally-off operation can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the implementation methods of the present application, the drawings required for use in the implementation methods of the present application will be briefly introduced below. It should be understood that the following drawings only show certain implementation methods of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A basic structure of a high withstand voltage high electron mobility transistor provided in an embodiment of the present application;

[0026] Figure 2-Figure 4 An example diagram of a high electron mobility transistor formation process provided in an embodiment of the present application;

[0027] Figure 5 Another example diagram of a high electron mobility transistor formation process provided in an embodiment of the present application;

[0028] Figure 6-Figure 13 Several other complex high electron mobility transistors and formation process diagrams provided for the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0030] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. "Up and down" etc. indicate a relative position relationship and do not mean that the two are directly adjacent.

[0031] The basic concept of the high-voltage high electron mobility transistor of the present invention is to start lateral epitaxial growth from the area corresponding to the drain. Since selective epitaxy can achieve higher crystal quality, this has certain advantages over the existing planar growth.

[0032] On the basis of the above basic structure, by lateral epitaxial doping and modulating the doping concentration, the following structures and their combinations can be formed: a strong P-type region is formed at the gate electrode stack and the two-dimensional electron gas there is depleted, realizing the normally-off enhancement type of the device; in addition to forming a strong P-type region at the gate electrode stack, a P-type layer is also formed near the source electrode, which will not significantly deplete the two-dimensional electron gas between the source and gate electrodes, but can connect the strong P-type region at the gate electrode stack and connect to the electrode. The electrode can be a source electrode or an independent body electrode. A P-type region is formed between the gate electrode and the drain electrode, which will not significantly deplete the two-dimensional electron gas but can improve the electric field distribution and reduce the maximum electric field strength.

[0033] In the high electron mobility transistor of the present application, the doping concentration of the strongly doped transistor is usually 5E18 / cm 3 Above, the doping concentration of light doping is generally 5E18 / cm 3 Below. In a high electron mobility transistor, strong doping or light doping is relative, and is related to the concentration of the two-dimensional electron gas at the interface of the channel layer / barrier layer. Generally, the higher the concentration of the intrinsic (referring to the situation when there is no doping) two-dimensional electron gas at the interface of the channel layer / barrier layer, the higher the doping concentration corresponding to the strong doping, and the light doping can also have a relatively higher doping concentration. Conversely, the lower the concentration of the intrinsic two-dimensional electron gas, the lower the doping concentration corresponding to the strong doping, and the light doping also has a relatively lower doping concentration.

[0034] Please see Figure 1 , Figure 1A basic structure of a high withstand voltage high electron mobility transistor provided in an embodiment of the present application. The basic structure comprises an insulating layer 102 and a nucleation layer 103 on a substrate 101, a channel layer 104 on the insulating layer 102 and the nucleation layer 103, the channel layer 104 may be a P-type semiconductor layer, more specifically a P-type III-V semiconductor layer, a barrier layer 105 on the P-type III-V semiconductor layer, a two-dimensional electron gas 2DEG is formed at the interface of the heterojunction of the channel layer 104 and the barrier layer 105, a source electrode 107 and a drain electrode 106 are connected to the two-dimensional electron gas and form an ohmic contact, and a gate electrode 108 is located on the barrier layer 105; wherein the projections of the nucleation layer 103 and the drain electrode 106 on the substrate 101 overlap at least partially, forming a high electron mobility transistor structure with the drain electrode extending outward. The doping concentration of the P-type III-V semiconductor layer is low, and the P-type III-V semiconductor layer will not seriously deplete the two-dimensional electron gas at the interface between the barrier layer and the P-type III-V semiconductor layer, and a high concentration of two-dimensional electron gas still exists at the heterojunction interface. The III-V semiconductor layer is generally a nitride semiconductor layer, and the P-type III-V semiconductor layer is at least partially located below the two-dimensional electron gas region between the gate electrode and the drain electrode and the gate electrode and the source electrode. Except for the gate electrode stacking region, the P-type III-V semiconductor layer depletes the channel 2DEG concentration less than 80% of the channel 2DEG concentration when the P-type III-V semiconductor layer is not present, that is, at least 20% of the two-dimensional electron gas is retained. The P-type III-V semiconductor layer located in the area between the gate and drain electrodes will also be partially depleted under the action of the electric field, exposing the background negative charge. These negative charges can effectively offset the influence of positive charges in the channel and the positive charges in the drain, adjust the distribution of the electric field, reduce the intensity of the local electric field peak, and improve the voltage resistance of the device.

[0035] Figure 1 The high withstand voltage high electron mobility transistor provided in the embodiment can be Figure 2-4 The steps shown in the above are as follows. Figure 2 As shown, an insulating layer 202 is formed on a substrate 201, an opening region is formed on the insulating layer through masking, etching and other processes, a nucleation layer 203 is epitaxially grown in the opening region of the insulating layer, and then a P-type III-V semiconductor layer is grown by lateral epitaxy; or Figure 3 As shown in the figure, a nucleation layer 302 is epitaxially grown on a substrate 301, and then an insulating layer 303 is formed. An opening area 304 is formed on the insulating layer through masking, etching and other processes to expose the nucleation layer 302, and then a P-type III-V semiconductor layer is epitaxially grown on the nucleation layer in the opening area of ​​the insulating layer by lateral epitaxy.

[0036] Under certain substrates (such as Al2O3 substrates) and process conditions, the nucleation layer can selectively grow on the exposed substrate, but not on the insulating layer. However, when using a silicon substrate, AlN is usually required as the nucleation layer, but the growth selectivity of AlN as the nucleation layer is poor. At this time, the AlN on the insulating layer can be etched / removed after the nucleation layer is grown, but under certain growth conditions, the deposition of AlN on the insulating layer is very small, and the nucleation growth matrix of the subsequent nitride epitaxial layer cannot be formed on the insulating layer. In addition to the growth in the nucleation area, there is no obvious subsequent growth of the P-type III-V semiconductor layer in other areas, so the step of removing the AlN on the insulating layer can be omitted and the subsequent growth can be carried out directly.

[0037] Since the AlN on the insulating layer is polycrystalline or amorphous, under appropriate process conditions, it can only nucleate and grow on the single crystal AlN in the opening area, but not on the polycrystalline AlN on the insulating layer. At this time, the polycrystalline AlN layer plays an insulating role to a large extent.

[0038] like Figure 4 As shown, an insulating layer 402 is formed on a substrate 401, an opening area is formed on the insulating layer through masking, etching and other processes, a nucleation layer 403 is epitaxially grown in the opening area of ​​the insulating layer, a buffer layer 404 is first formed, and then a high-crystalline quality P-type III-V semiconductor layer 405 is formed as a channel layer.

[0039] like Figure 5 As shown, an insulating layer 502 is formed on a substrate 501, and an opening region is formed on the insulating layer through masking, etching and other processes. A nucleation layer 503 is epitaxially grown in the opening region of the insulating layer, and a P-type III-V semiconductor layer 504 is grown on the nucleation layer by lateral epitaxy, and then a barrier layer 505 is formed, and then a SiNx passivation layer (not shown) is in-situ deposited in the same deposition equipment to obtain a barrier layer / SiNx layer with a low interface defect state density. After the in-situ SiNx layer is subjected to a mask etching process, only the SiNx layer below the gate electrode 508 is retained and used as a gate dielectric layer 509, as shown in FIG. Figure 5 As shown, the channel layer, the barrier layer, and the in-situ SiNx layer are sequentially grown in the same growth device to improve the device utilization rate and the growth quality. The drain electrode 506 and the source electrode 507 are formed in the barrier layer. The drain electrode 506 and the source electrode 507 are in ohmic contact with the two-dimensional electron gas. Finally, the following can be formed: Figure 5 The high electron mobility transistor structure shown.

[0040] Figure 1 and Figure 5The high electron mobility transistor structure shown in the latter embodiment of the present application is a basic device structure of a P-type III-V semiconductor layer formed by lateral epitaxial modulation of the doping concentration in the region corresponding to the drain electrode. It may also include a low-doped or non-doped III-V semiconductor layer such as a P-GaN layer inserted between the P-type III-V semiconductor layer and the barrier layer, a cap layer, and a field plate, a back barrier layer, an additional electrode for controlling the channel electric field, etc.; a gate dielectric layer and / or a p-GaN layer may exist under the gate electrode. The above-mentioned structures or other structures disclosed in the prior art are not excluded from the embodiments of the present invention application.

[0041] like Figure 6-9 As shown, an insulating layer 602-902 is formed on a substrate 601-901, an opening area is formed on the insulating layer through masking, etching and other processes, a nucleation layer 603-903 is epitaxially grown in the opening area of ​​the insulating layer, and a P-type III-V semiconductor layer 604-904 is grown on the nucleation layer by lateral epitaxy.

[0042] like Figure 7 As shown, when a P-type III-V semiconductor layer is grown laterally epitaxially, a doping modulation technique is used to first form a lightly doped III-V semiconductor layer first doping region (704-1) on the nucleation layer by lateral epitaxy; then a P-type layer-1 (704-2) is formed, and the P-type layer-1 (704-2) is a strong P-type III-V semiconductor layer, which is conducive to depleting the two-dimensional electron gas in the corresponding channel layer to realize a normally-off device; then a second doping region (704-3) of the III-V semiconductor layer is grown laterally epitaxially; and then a part of the III-V semiconductor layer in the height direction is removed by a flattening or etching process to expose the lightly doped III-V semiconductor layer first doping region (704-1) , a strong P-type III-V semiconductor layer (704-2), and a modulated P-type III-V semiconductor layer of the second doped region (704-3) of the III-V semiconductor layer; then forming a stacked structure of a channel layer 705, a barrier layer 706, and an in-situ SiNx layer 707; forming a source electrode 709, a drain electrode 708, and a gate electrode 710, wherein the gate electrode 710 corresponds to the strong P-type III-V semiconductor layer region, the source electrode 709 is substantially located above the second doped region (704-3) of the III-V semiconductor layer and is in ohmic contact with the two-dimensional electron gas, and the drain electrode is above the first doped region (704-1) of the lightly doped III-V semiconductor layer and is in ohmic contact with the two-dimensional electron gas, and finally forming Figure 7 The high withstand voltage normally-off high electron mobility transistor structure shown.

[0043] The strong P-type III-V semiconductor layer disposed under the gate electrode can deplete more than 95% of the two-dimensional electron gas under the gate electrode stack at zero gate voltage, or make the two-dimensional electron gas concentration under the gate electrode stack less than 5E11 / cm at zero gate voltage.2 .

[0044] In addition, in order to strengthen the control of the source electrode on the second doped region of the III-V semiconductor layer, and then control the potential of the strong P-type III-V semiconductor layer through this layer, so as to obtain a stable threshold voltage of the high electron mobility transistor. Figure 8 As shown, when the second doping region (804-3) of the III-V semiconductor layer is laterally epitaxially grown, P-type doping growth is performed to form a P-type III-V semiconductor layer, and finally a modulated P-type III-V semiconductor layer 804 structure layer of a lightly doped III-V semiconductor layer first doping region (804-1), a strong P-type III-V semiconductor layer (804-2), and a P-type III-V semiconductor layer (804-3) is formed, and the drain electrode 808 is in ohmic contact with the two-dimensional electron gas above the lightly doped III-V semiconductor layer first doping region (804-1); Masking, etching and other processes expose the P-type III-V semiconductor layer (804-3) and the barrier layer 806 in a step-type manner, and then deposit to form a source electrode 809, so that a part of the source electrode 809 is in contact with the two-dimensional electron gas, and a part of the source electrode 809 is in direct contact with the P-type III-V semiconductor layer 804-3 through the channel layer 805. Through the good electrical contact between the source electrode and the P-type III-V semiconductor layer, the potential of the strong P-type III-V semiconductor layer 804-2 can be better controlled to obtain a stable threshold voltage of the high electron mobility transistor. Optionally, the portion of the source electrode 809 in contact with the P-type III-V semiconductor layer 804-3 and the portion of the source electrode 809 in contact with the two-dimensional electron gas are physically connected (i.e., they together constitute the source electrode); or the source electrode 809 is in contact with the two-dimensional electron gas, and the metal material in contact with the P-type III-V semiconductor layer 804-3 is electrically connected to the source electrode 809, so as to facilitate integrated control of the source electrode potential.

[0045] A gate dielectric layer 807 may also be provided. The gate dielectric layer may be in-situ SiNx or other dielectric materials such as SiO 2 , high-k, etc. The gate dielectric layer is provided below the gate electrode 810 to completely cover the barrier layer 806 .

[0046] and Figure 8 The embodiment shown differs in that Fig. 9In the illustrated embodiment, the electrode in contact with the P-type III-V semiconductor layer 904-3 is an independent body electrode 911 that is not connected to the source electrode 909. The body electrode is electrically connected to the P-type III-V semiconductor layer 904-3 through the passivation layer, the barrier layer, and the channel layer. The source electrode 909 is located above the channel layer, which is beneficial to independent control of the source electrode potential and the operating potential of the P-type III-V semiconductor layer 904-3. In particular, when the source potential is fixed at the 0 potential point, the potential of the body electrode can be independently controlled according to the operating voltage or stable operating voltage required to turn off the channel, which is beneficial to stable and efficient operation of the enhancement type device.

[0047] For example Fig.10 As shown, an insulating layer 1002 is formed on a substrate 1001, an opening region is formed on the insulating layer through masking, etching and other processes, a nucleation layer 1003 is epitaxially grown in the opening region of the insulating layer, and a P-type III-V semiconductor layer 1004 is grown on the nucleation layer by lateral epitaxy. When the P-type III-V semiconductor layer is grown by lateral epitaxy, a doping modulation technology is used to first form a lightly doped III-V semiconductor layer first doping region (1004-1) on the nucleation layer by lateral epitaxy; and then form a P-type III-V semiconductor layer first doping region (1004-2). The epitaxial growth time of the P-type III-V semiconductor layer first doping region (1004-2) is shorter than that of the nucleation layer. Figure 6 The epitaxial growth time of the first doped region (604-2) of the P-type III-V semiconductor layer is short. Fig.10 The first doped region of the P-type III-V semiconductor layer formed as shown is relatively narrow; the second doped region (1004-3) of the P-type III-V semiconductor layer is then epitaxially grown laterally; then, a portion of the region in the height direction of the III-V semiconductor layer is removed by a planarization or etching process to expose the modulated P-type III-V semiconductor layer of the first doped region (1004-1) of the lightly doped III-V semiconductor layer, the first doped region (1004-2) of the P-type III-V semiconductor layer, and the second doped region (1004-3) of the P-type III-V semiconductor layer; and then Fig.11 As shown, a stacked structure of a channel layer 1105, a barrier layer 1106, and an in-situ SiNx layer 1107 is formed; a source electrode 1109, a drain electrode 1108, and a gate electrode 1110 are formed, wherein the gate electrode 1110 deviates from the first doped region (1104-2) of the P-type III-V semiconductor layer in the lateral direction, the drain electrode 1108 is substantially located on the channel layer 1105 above the first doped region (1104-1) of the lightly doped III-V semiconductor layer, and the source electrode 1109 is in contact with the first doped region of the lightly doped III-V semiconductor layer (with the gate electrode 1110). Figure 8 The embodiment shown in the figure adopts the same method to form the source electrode), and finally forms Fig.11 The high voltage high electron mobility transistor structure shown.

[0048] Fig.11 In the high-voltage high electron mobility transistor shown, the drain electrode corresponds to the nucleation region, and the first doped region of the P-type III-V semiconductor layer is located between the gate electrode and the drain electrode, which can improve the high electric field distribution near the area near the drain electrode side under the gate electrode and avoid the local electric field strength being too large to cause device failure. The channel layer, the in-situ SiN passivation layer, and the gate insulation layer are all optional and not necessary.

[0049] like Fig.12 As shown, the electrode in contact with the second doped region of the P-type III-V semiconductor layer is an independent body electrode, which is conducive to independent control of the source potential and the operating potential of the P-type III-V semiconductor layer. In particular, when the source potential is fixed at the 0 potential point, it can be independently controlled according to the operating voltage required to turn off the channel or the stable operating voltage.

[0050] and Fig.11 The embodiment shown differs in that Fig.12 In the illustrated embodiment, the electrode in contact with the P-type III-V semiconductor layer 1204-3 is an independent body electrode 1211 that is not connected to the source electrode 1209. The body electrode is electrically connected to the P-type III-V semiconductor layer 1204-3 through the passivation layer, the barrier layer, and the channel layer. The source electrode 1209 is located above the channel layer, which is beneficial to independent control of the source electrode potential and the operating potential of the P-type III-V semiconductor layer 1204-3. In particular, when the source potential is fixed at the 0 potential point, the potential of the body electrode can be independently controlled according to the operating voltage required to turn off the channel or the stable operating voltage, which is beneficial to the stable and efficient operation of the enhanced high electron mobility transistor.

[0051] While reducing the leakage electric field strength under the gate electrode and enhancing the voltage resistance of the high electron mobility transistor, Figure 11-12 The high-voltage high-electron-mobility transistor shown in the figure can be made by doping modulation technology with Figure 7-Figure 9 The enhanced high electron mobility transistor structure shown in FIG. Fig.13 The enhanced high electron mobility transistor with higher withstand voltage is shown in FIG. Fig.13The high electron mobility transistor shown in the figure has an insulating layer 1302 formed on a substrate 1301, an opening region is formed on the insulating layer through masking, etching and other processes, a nucleation layer 1303 is epitaxially grown in the opening region of the insulating layer, and a P-type III-V semiconductor layer 1304 is grown on the nucleation layer by lateral epitaxy. When the P-type III-V semiconductor layer is grown by lateral epitaxy, a doping modulation technique is used. During the lateral epitaxial growth process, lightly doped III A first doped region (1304-1) of a group-V semiconductor layer, a first doped region (1304-2) of a p-type group-III-V semiconductor layer, a strong p-type group-III-V semiconductor layer (1304-3), and a second doped region (1304-4) of a p-type group-III-V semiconductor layer, wherein the strong p-type group-III-V semiconductor layer (1304-3) is located at the gate electrode stack, and a normally-off device is obtained by depleting part or all of the two-dimensional electron gas at the gate electrode stack.

[0052] The P-type III-V semiconductor layer (1304-4) and the barrier layer 1306 are exposed in a step-type manner through masking, etching and other processes, and then a source electrode 1309 is deposited to form a source electrode 1309, so that a portion of the source electrode 1309 is in contact with the two-dimensional electron gas, and a portion of the source electrode 1309 is in direct contact with the P-type III-V semiconductor layer 804-3 through the channel layer 1305, and a good electrical contact is formed with the second doped region (1304-4) of the P-type III-V semiconductor layer through the source electrode 1309, and the potential of the strong P-type III-V semiconductor layer (1304-3) is controlled through the second doped region (1304-4) of the P-type III-V semiconductor layer to obtain a stable threshold voltage. The first doped region (1304-2) of the P-type III-V semiconductor layer is located between the gate electrode 1310 and the drain electrode 1308, which can improve the high electric field distribution near the area below the gate electrode near the drain electrode side, and avoid the local electric field strength being too large to cause device failure. The channel layer, the in-situ SiN passivation layer, and the gate insulation layer are all optional and not necessary.

[0053] In addition, Fig.13 In another embodiment of the embodiment shown in the figure, the electrode in contact with the second doped region of the P-type III-V semiconductor layer is an independent body electrode (the source electrode, the body electrode is connected to the growth connection method and the Fig.12 The connection mode is the same as shown), so as to facilitate independent control of the source potential and the operating potential of the second doped region of the P-type III-V semiconductor layer, which is conducive to the stable and efficient operation of the enhancement mode device under high voltage conditions.

[0054] The above is only an implementation method of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A high-voltage high-electron-mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; wherein the projections of the nucleation layer and the drain electrode on the substrate overlap at least partially, a channel layer comprising a P-type III-V semiconductor layer is located between the barrier layer and the substrate, and is insufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode and the drain electrode are both electrically in contact with the two-dimensional electron gas, the gate electrode is located on the barrier layer, and an independent body electrode is electrically in contact with the P-type III-V semiconductor layer near the source electrode.

2. The high electron mobility transistor according to claim 1, characterized in that: There is also a low-doped or unintentionally doped III-V semiconductor layer between the barrier layer and the P-type III-V semiconductor layer.

3. The high electron mobility transistor according to claim 1, characterized in that: A SiNx passivation layer is formed by in-situ growth on the barrier layer, and a gate dielectric layer is disposed under the gate electrode.

4. The high electron mobility transistor according to claim 1, characterized in that: The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, the first doping area of ​​the lightly doped III-V semiconductor layer, the first doping area of ​​the strongly P-type III-V semiconductor layer, and the first doping area of ​​the P-type III-V semiconductor layer are sequentially arranged outward. A drain electrode is formed above the first doping area of ​​the lightly doped III-V semiconductor layer, a gate stack structure is correspondingly formed above the first doping area of ​​the strongly P-type III-V semiconductor layer, and a source electrode is formed above the first doping area of ​​the P-type III-V semiconductor layer.

5. The high electron mobility transistor according to claim 4, characterized in that: A first doped region of a strong P-type III-V semiconductor layer under the gate electrode can deplete more than 95% of the two-dimensional electron gas under the gate electrode stack at zero gate voltage, or make the two-dimensional electron gas concentration under the gate electrode stack less than 5E11 / cm at zero gate voltage 2 .

6. The high electron mobility transistor according to claim 4, characterized in that: The doping concentration of the first doping region of the lightly doped III-V semiconductor layer is less than 5E17 / cm 3 .

7. The high electron mobility transistor according to claim 1, characterized in that: The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, a first doping area of ​​a lightly doped III-V semiconductor layer, a first doping area of ​​a P-type III-V semiconductor layer, and a second doping area of ​​a P-type III-V semiconductor layer are sequentially arranged outward, a drain electrode is formed above the first doping area of ​​the lightly doped III-V semiconductor layer, and a gate stack structure is formed in a portion of the second doping area of ​​the P-type III-V semiconductor layer close to the first doping area of ​​the P-type III-V semiconductor layer, that is, the first doping area of ​​the P-type III-V semiconductor layer is located between the drain electrode and the gate electrode, the doping concentration of the first doping area of ​​the P-type III-V semiconductor layer is adjustable, and the electric field distribution near the drain side below the gate electrode can be improved, and a source electrode is formed above the second doping area of ​​the P-type III-V semiconductor layer.

8. The high electron mobility transistor according to claim 1, characterized in that: The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, a lightly doped III-V semiconductor layer first doping area, a P-type III-V semiconductor layer first doping area, a strongly P-type III-V semiconductor layer first doping area, and a P-type III-V semiconductor layer second doping area are sequentially arranged outward; a drain electrode is arranged above the lightly doped III-V semiconductor layer first doping area, and a gate stack structure is correspondingly formed above the strongly P-type III-V semiconductor layer first doping area. The first doping area of ​​the P-type III-V semiconductor layer is located between the first doping area of ​​the lightly doped III-V semiconductor layer and the first doping area of ​​the strongly P-type III-V semiconductor layer. The doping concentration of the first doping area of ​​the P-type III-V semiconductor layer is adjustable, which can improve the electric field distribution below the gate electrode and close to the drain side. A source electrode is formed above the second doping area of ​​the P-type III-V semiconductor layer.

9. A high-voltage high-electron-mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; the channel layer comprising a P-type III-V semiconductor layer is located between the barrier layer and the substrate, wherein the projections of the nucleation layer and the drain electrode on the substrate at least partially overlap, the drain electrode is in electrical contact with the two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V semiconductor layer, and the gate electrode is located on the barrier layer; The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, the first doping area of ​​the lightly doped III-V semiconductor layer, the first doping area of ​​the strongly P-type III-V semiconductor layer, and the first doping area of ​​the P-type III-V semiconductor layer are sequentially arranged outward. A drain electrode is formed above the first doping area of ​​the lightly doped III-V semiconductor layer, a gate stack structure is correspondingly formed above the first doping area of ​​the strongly P-type III-V semiconductor layer, and a source electrode is formed above the first doping area of ​​the P-type III-V semiconductor layer.

10. According to the high-voltage high electron mobility transistor according to claim 9, the first doped region of the strong P-type III-V semiconductor layer under the gate electrode can deplete more than 95% of the two-dimensional electron gas under the gate electrode stack at 0 gate voltage, or make the concentration of the two-dimensional electron gas under the gate electrode stack less than 5E11 / cm2 at 0 gate voltage.

11. The high electron mobility transistor according to claim 9, characterized in that: The doping concentration of the first doping region of the lightly doped III-V group semiconductor layer is less than 5E17 / cm3.

12. A high-voltage high-electron-mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; the channel layer comprising a P-type III-V semiconductor layer is located between the barrier layer and the substrate, wherein the projections of the nucleation layer and the drain electrode on the substrate at least partially overlap, the drain electrode is in electrical contact with the two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V semiconductor layer, and the gate electrode is located on the barrier layer; The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, a first doping area of ​​a lightly doped III-V semiconductor layer, a first doping area of ​​a P-type III-V semiconductor layer, and a second doping area of ​​a P-type III-V semiconductor layer are sequentially arranged outward, a drain electrode is formed above the first doping area of ​​the lightly doped III-V semiconductor layer, and a gate stack structure is formed in a portion of the second doping area of ​​the P-type III-V semiconductor layer close to the first doping area of ​​the P-type III-V semiconductor layer, that is, the first doping area of ​​the P-type III-V semiconductor layer is located between the drain electrode and the gate electrode, the doping concentration of the first doping area of ​​the P-type III-V semiconductor layer is adjustable, and the electric field distribution near the drain side below the gate electrode can be improved, and a source electrode is formed above the second doping area of ​​the P-type III-V semiconductor layer.

13. A high withstand voltage high electron mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; the channel layer comprising a P-type III-V semiconductor layer is located between the barrier layer and the substrate, wherein the projections of the nucleation layer and the drain electrode on the substrate at least partially overlap, the drain electrode is in electrical contact with the two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V semiconductor layer, and the gate electrode is located on the barrier layer; The P-type III-V semiconductor layer includes modulation areas with different doping concentrations. With the nucleation layer area as the center, a lightly doped III-V semiconductor layer first doping area, a P-type III-V semiconductor layer first doping area, a strongly P-type III-V semiconductor layer first doping area, and a P-type III-V semiconductor layer second doping area are sequentially arranged outward; a drain electrode is arranged above the lightly doped III-V semiconductor layer first doping area, and a gate stack structure is correspondingly formed above the strongly P-type III-V semiconductor layer first doping area. The first doping area of ​​the P-type III-V semiconductor layer is located between the first doping area of ​​the lightly doped III-V semiconductor layer and the first doping area of ​​the strongly P-type III-V semiconductor layer. The doping concentration of the first doping area of ​​the P-type III-V semiconductor layer is adjustable, which can improve the electric field distribution below the gate electrode and close to the drain side. A source electrode is formed above the second doping area of ​​the P-type III-V semiconductor layer.

14. The high withstand voltage high electron mobility transistor according to claim 1, claim 9, claim 12 or claim 13, characterized in that: When the source electrode is in electrical contact with the P-type III-V semiconductor layer, a portion of the source electrode is in contact with the two-dimensional electron gas and a portion of the source electrode is in direct contact with the P-type III-V semiconductor layer through the channel layer.

15. The high withstand voltage high electron mobility transistor according to claim 1, claim 9, claim 12 or claim 13, characterized in that: When the source electrode is in electrical contact with the two-dimensional electron gas, the metal material in contact with the P-type III-V semiconductor layer is electrically connected to the source electrode, which facilitates integrated control of the source electrode potential.

16. A method for preparing a high withstand voltage high electron mobility transistor as claimed in claim 1, claim 9, claim 12 or claim 13, characterized in that: A P-type III-V semiconductor layer is grown on the nucleation layer by lateral epitaxy. During the lateral epitaxial growth, a modulation-doped P-type III-V semiconductor layer is formed according to different doping concentrations in different regions. A precursor mixed atmosphere containing hydrogen and / or chlorine is used during the lateral epitaxial growth of the P-type III-V semiconductor layer.

17. The method according to claim 16, characterized in that The method for forming a nucleation layer opening on a substrate is to grow a nucleation layer on the substrate, form an insulating layer on the nucleation layer, and form an opening in the insulating layer to expose the nucleation layer through masking, etching and other processes; then grow an epitaxial layer structure including a P-type III-V semiconductor layer through lateral epitaxy.

18. The method according to claim 16, characterized in that An epitaxial layer is grown from a nucleation layer at an opening on the substrate in a lateral epitaxial manner, and is expanded outward with the projection area of ​​the drain electrode on the substrate as the center, thereby forming a symmetrical high electron mobility transistor structure with the drain electrode area as the center.

19. The method according to claim 16, characterized in that When the epitaxial layer structure is grown by lateral epitaxy on the substrate, a lightly doped III-V semiconductor layer first doping region, a strongly P-type III-V semiconductor layer first doping region, and a P-type III-V semiconductor layer first doping region are first epitaxially formed on the nucleation layer, and a portion of the III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the lightly doped III-V semiconductor layer first doping region, the strongly P-type III-V semiconductor layer first doping region, and the modulated P-type III-V semiconductor layer of the P-type III-V semiconductor layer first doping region; a drain electrode is formed above the lightly doped III-V semiconductor layer first doping region, a gate stack structure is correspondingly formed above the strongly P-type III-V semiconductor layer first doping region, and a source electrode is formed above the P-type III-V semiconductor layer first doping region.

20. The method according to claim 16, characterized in that When the epitaxial layer structure is grown by lateral epitaxy on the substrate, a lightly doped group III-V semiconductor layer first doping region is first formed by epitaxy on the nucleation layer, and then a P-type group III-V semiconductor layer first doping region and a P-type group III-V semiconductor layer second doping region are formed by epitaxy. A portion of the group III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the lightly doped group III-V semiconductor layer first doping region, the P-type group III-V semiconductor layer first doping region, and the P-type group III-V semiconductor layer second doping region. -V group semiconductor layer; a drain electrode is formed above the first doping region of the lightly doped III-V group semiconductor layer, and a gate stack structure is formed in the portion of the second doping region of the P-type III-V group semiconductor layer close to the first doping region of the P-type III-V group semiconductor layer, that is, the first doping region of the P-type III-V group semiconductor layer is located between the drain electrode and the gate electrode, the doping concentration of the first doping region of the P-type III-V group semiconductor layer is adjustable, which can improve the electric field distribution near the drain side below the gate electrode, and a source electrode is formed above the second doping region of the P-type III-V group semiconductor layer.

21. The method according to claim 16, characterized in that When the epitaxial layer structure is grown by lateral epitaxy on the substrate, a lightly doped group III-V semiconductor layer first doping region is first formed by epitaxy on the nucleation layer, and then a P-type group III-V semiconductor layer first doping region, a strongly P-type group III-V semiconductor layer first doping region, and a P-type group III-V semiconductor layer second doping region are formed by epitaxy. A portion of the group III-V semiconductor layer in the height direction is removed by a planarization or etching process to expose the lightly doped group III-V semiconductor layer first doping region, the P-type group III-V semiconductor layer first doping region, the strongly P-type group III-V semiconductor layer first doping region, and the P-type group III-V semiconductor layer second doping region. A modulated P-type III-V semiconductor layer in the second doping region of the body layer; a drain electrode is formed above the first doping region of the lightly doped III-V semiconductor layer, and a gate stack structure is correspondingly formed above the first doping region of the strongly P-type III-V semiconductor layer, the first doping region of the P-type III-V semiconductor layer is located between the first doping region of the lightly doped III-V semiconductor layer and the first doping region of the strongly P-type III-V semiconductor layer, the doping concentration of the first doping region of the P-type III-V semiconductor layer is adjustable, which can improve the electric field distribution below the gate electrode near the drain side, and a source electrode is formed above the second doping region of the P-type III-V semiconductor layer.

22. The method according to any one of claims 19 to 21, characterized in that A precursor mixed atmosphere containing hydrogen and / or chlorine is used when the structure containing a P-type III-V semiconductor layer is grown epitaxially laterally.

Images