Semiconductor element and method for manufacturing the same

Abstract

The present invention discloses a semiconductor element and a method for manufacturing the same, wherein the method for manufacturing the semiconductor element is to first provide a substrate including a magnetic tunneling junction (MTJ) region and a logic region, then form an MTJ on the MTJ region, form an upper electrode on the MTJ, form an intermetallic dielectric layer to surround the MTJ, remove the intermetallic dielectric layer directly above the upper electrode to form a groove, form a first hard mask on the intermetallic dielectric layer and fill the groove, remove the first hard mask and the intermetallic dielectric layer in the logic region to form a contact hole, and then form a metal layer in the groove and the contact hole to form a connection structure above the upper electrode and form a metal inner connection in the logic region.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. Background Art

[0002] It is known that the magnetoresistance (MR) effect is the effect that the resistance of a material changes with the change of an external magnetic field. The definition of its physical quantity is the resistance difference in the presence and absence of a magnetic field divided by the original resistance, which is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully used in hard disk production and has important commercial application value. In addition, by utilizing the characteristics of giant magnetoresistance materials having different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be made. Its advantage is that the stored data can continue to be retained when no power is supplied.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensors. For example, the electronic compass components of the global positioning system (GPS) in mobile phones are used to provide users with information such as their moving position. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: more chip area, more expensive manufacturing process, more power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and further improvement is necessary. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device. First, a substrate is provided including a magnetic tunneling junction (MTJ) region and a logic region, then an MTJ is formed on the MTJ region, a top electrode is formed on the MTJ, an intermetallic dielectric layer is formed to surround the MTJ, the intermetallic dielectric layer directly above the top electrode is removed to form a groove, a first hard mask is formed on the intermetallic dielectric layer and filled into the groove, the first hard mask and the intermetallic dielectric layer of the logic region are removed to form a contact hole, and then a metal layer is formed in the groove and the contact hole to form a connection structure above the top electrode and a metal interconnection in the logic region.

[0005] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an MTJ arranged on the MTJ region, an upper electrode arranged on the MTJ, a connection structure arranged on the upper electrode and a first metal interconnect arranged in the logic region, wherein the first metal interconnect further includes a contact hole conductor arranged on the substrate and a trench conductor, and the lower surface of the trench conductor is lower than the lower surface of the connection structure.

[0006] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an MTJ disposed on the MTJ region, an upper electrode disposed on the MTJ and a connection structure disposed on the upper electrode, wherein the connection structure includes a hard mask disposed on the upper electrode, a barrier layer disposed on the hard mask and a metal layer disposed on the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 9 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0008] Fig.10 FIG. 4 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0009] Main component symbols

[0010] 12 substrate 14 MTJ region

[0011] 16 Logic area 18 Interlayer dielectric layer

[0012] 20 Metal interconnect structure 22 Metal interconnect structure

[0013] 24 Intermetallic dielectric layer 26 Metal interconnect

[0014] 28 stop layer 30 intermetallic dielectric layer

[0015] 32 Metal interconnect 34 Barrier layer

[0016] 36 Metal layer 38 MTJ stacking structure

[0017] 40 Covering layer 42 Covering layer

[0018] 44 first electrode layer 46 fixed layer

[0019] 48 barrier layer 50 free layer

[0020] 52 second electrode layer 54 patterned mask

[0021] 56 Organic dielectric layer 58 Silicon-containing hard mask and anti-reflective layer

[0022] 60 Patterned photoresist 62 MTJ

[0023] 64 first inclined side wall 66 second inclined side wall

[0024] 68 Covering layer 72 MTJ

[0025] 76 lower electrode 78 upper electrode

[0026] 80 Intermetallic dielectric layer 82 Hard mask

[0027] 84 Organic dielectric layer 86 Silicon-containing hard mask and anti-reflective layer

[0028] 88 photoresist layer 90 groove

[0029] 92 Hard mask 94 Contact hole

[0030] 96 Barrier layer 98 Metal layer

[0031] 100 Connection structure 102 Metal interconnect

[0032] 104 stop layer 106 intermetallic dielectric layer

[0033] 108 barrier layer 110 metal layer

[0034] 112 Metal interconnects 114 Metal interconnects

[0035] 116 stop layer 118 contact hole conductor

[0036] 120 Groove Conductor DETAILED DESCRIPTION

[0037] Please refer to Figures 1 to 9 , Figures 1 to 9 A schematic diagram of a method for manufacturing a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figures 1 to 9 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and a magnetic tunneling junction (MTJ) region 14 and a logic region 16 are preferably defined on the substrate 12.

[0038] The substrate 12 may include active (active) components such as metal-oxide semiconductor (MOS) transistors, passive (passive) components, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar (such as fin-structured transistors) MOS transistor components, wherein the MOS transistor may include a gate structure (such as a metal gate) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor components. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 18 may have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistor. Since the related manufacturing processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they are not further described here.

[0039] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 of the MTJ area 14 and the logic area 16 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 20 includes an intermetallic dielectric layer 24 and a metal interconnect 26 embedded in the intermetallic dielectric layer 24, and the metal interconnect structure 22 includes a stop layer 28, an intermetallic dielectric layer 30 and a plurality of metal interconnects 32 embedded in the stop layer 28 and the intermetallic dielectric layer 30.

[0040] In the present embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably comprises a trench conductor, and the metal interconnect 32 in the metal interconnect structure 22 disposed in the MTJ region 14 comprises a via conductor. In addition, each metal interconnect 26, 32 in each metal interconnect structure 20, 22 may be embedded in the intermetallic dielectric layer 24, 30 and / or the stop layer 28 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 26, 32 may further comprise a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since the single damascene or dual damascene manufacturing process is well known in the art, it will not be described in detail here. In addition, in this embodiment, the metal layer 36 preferably includes copper, the intermetallic dielectric layers 24 and 30 preferably include silicon oxide, and the stop layer 28 includes nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0041] Then, an MTJ stack structure 38 is formed on the metal interconnect structure 22, a cap layer 40 is formed on the MTJ stack structure 38, and another cap layer 42 is formed on the cap layer 40. In the present embodiment, the MTJ stack structure 38 may be formed by first sequentially forming a first electrode layer 44, a fixed layer 46, a barrier layer 48, a free layer 50, and a second electrode layer 52. In the present embodiment, the first electrode layer 44 and the second electrode layer 52 preferably include conductive materials, such as but not limited to tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or titanium nitride (TiN). The fixed layer 46 may be composed of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layer. The barrier layer 48 may be formed of an insulating material including an oxide, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited thereto. The free layer 50 may be formed of a ferromagnetic material, such as iron, cobalt, nickel or their alloys such as cobalt-iron-boron (CoFeB), but is not limited thereto. The magnetization direction of the free layer 50 will be "freely" changed by an external magnetic field. In addition, the cap layer 40 and the cap layer 42 preferably include different materials. For example, the cap layer 40 of the present embodiment preferably includes silicon nitride and the cap layer 42 preferably includes silicon oxide, but is not limited thereto.

[0042] Then, a patterned mask 54 is formed on the capping layer 42. In the present embodiment, the patterned mask 54 may include an organic dielectric layer (ODL) 56, a silicon-containing hard mask bottom anti-reflective coating (SHB) layer 58, and a patterned photoresist 60.

[0043] like Figure 2As shown, one or more etching processes are then performed using the patterned mask 54 as a mask to remove a portion of the capping layers 40, 42, a portion of the MTJ stacking structure 38, and a portion of the intermetallic dielectric layer 30 to form MTJs 62, 72 in the MTJ region 14, wherein the first electrode layer 44 preferably becomes the lower electrode 76 of the MTJ 62, 72 at this stage, and the second electrode layer 52 preferably becomes the upper electrode 78 of the MTJ 62, 72, and the capping layers 40, 42 can be removed together during the etching process. It is worth noting that in this embodiment, a reactive ion etching process (RIE) can be performed using the patterned mask 54 to remove a portion of the capping layers 40, 42 and a portion of the MTJ stacking structure 38, and then the patterned mask 54 is removed, and then the patterned capping layer 42 is used as a mask to perform an ion beam etching process (IBE) to remove a portion of the MTJ stacking structure 38 and a portion of the intermetallic dielectric layer 30 to form MTJs 62, 72. Due to the characteristics of the ion beam etching process, the upper surface of the remaining IMD layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32 and the upper surface of the IMD layer 30 is preferably in an arc or curved shape.

[0044] It should also be noted that when the present embodiment utilizes the ion beam etching process to remove a portion of the intermetal dielectric layer 30 , it is preferred to also remove a portion of the metal interconnect 32 , so that the metal interconnect 32 forms a first inclined sidewall 64 and a second inclined sidewall 66 near the junction of the MTJ 62 , 72 .

[0045] Then as Figure 3 As shown, a cap layer 68 and an intermetallic dielectric layer 80 are first formed on the MTJ 62 and 72 and cover the surface of the intermetallic dielectric layer 30, and then a planarization process is performed, such as using a chemical mechanical polishing (CMP) process to remove part of the intermetallic dielectric layer 80, so that the remaining intermetallic dielectric layer 80 is still slightly higher than the surface of the cap layer 68 directly above the upper electrode 78. In this embodiment, the cap layer 68 preferably includes silicon nitride, but other dielectric materials can be selected according to the requirements of the manufacturing process, such as silicon oxide, silicon oxynitride or silicon nitride carbide. The intermetallic dielectric layer 80 preferably includes an ultra-low dielectric constant dielectric layer, which can include a porous dielectric material such as but not limited to silicon oxycarbide (SiOC).

[0046] Then Figure 4As shown, a hard mask 82 and a mask layer are sequentially formed on the surface of the intermetallic dielectric layer 80. In the present embodiment, the hard mask 82 preferably comprises silicon oxynitride (SiON) and the mask layer may comprise an organic dielectric layer (ODL) 84, a silicon-containing hard mask bottom anti-reflective coating (SHB) layer 86 and a photoresist layer 88.

[0047] like Figure 5 As shown, a photolithography and etching process is performed, for example, the photoresist layer 88 may be patterned first, and then a single or multiple etching process may be used to sequentially remove a portion of the SHB layer 86, a portion of the ODL 84, a portion of the hard mask 82, a portion of the intermetallic dielectric layer 80, and a portion of the cap layer 68 to form a groove 90 to expose the surface of the upper electrode 78. Thereafter, the photoresist layer 88, the SHB layer 86, and the ODL 84 are removed to expose the surface of the hard mask 82.

[0048] Then as Figure 6 As shown, another hard mask 92 is first formed on the surface of the hard mask 82 and fills the groove 90 but does not fill the groove 90. In this embodiment, the hard mask 82 and the hard mask 92 preferably include different materials, wherein the hard mask 92 preferably includes metal nitride or more specifically titanium nitride. Then, a pattern transfer process is performed, for example, a pattern mask (not shown) can be used as a mask to remove part of the hard mask 92, part of the hard mask 82, part of the inter-metal dielectric layer 80, part of the cap layer 68, part of the inter-metal dielectric layer 30 and part of the stop layer 28 of the logic region 16 to form a contact hole 94 and expose the metal interconnect 26.

[0049] Afterwards Figure 7 As shown, a barrier layer 96 and a metal layer 98 are sequentially formed in the groove 90 of the MTJ region 14 and in the contact hole 94 of the logic region 16 to fill the groove 90 and the contact hole 94 at the same time, wherein the barrier layer 96 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the metal layer 98 may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, CoWP) or a combination thereof and other low resistance materials.

[0050] like Figure 8As shown, a planarization process is then performed, such as using CMP to remove part of the metal layer 98, part of the barrier layer 96, part of the hard mask 92 and part of the hard mask 82 to form a connection structure 100 above each upper electrode 78 and simultaneously form a metal interconnect 102 or a contact plug in the logic area 16.

[0051] Then Fig. 9 As shown, a stop layer 104 and another intermetallic dielectric layer 106 are sequentially formed on the MTJ 62 and 72 and cover the surface of the intermetallic dielectric layer 80, and then one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 106 and part of the stop layer 104 in the MTJ region 14 and the logic region 16 to form contact holes (not shown). Then, a barrier layer 108 and a metal layer 110 are sequentially formed in each contact hole to fill the contact hole, wherein the barrier layer 108 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the metal layer 110 may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) or a combination thereof. Low resistance materials. Then, a planarization process is performed, such as using CMP to remove part of the metal layer 110 and part of the barrier layer 108 to form metal interconnects 112 and 114 in the MTJ region 14 and the logic region 16 to connect the underlying connection structure 100 and the metal interconnect 102, respectively, wherein the metal interconnect 112 in the MTJ region 14 is preferably directly in contact with the underlying connection structure 100, and the metal interconnect 114 in the logic region 16 is in contact with the underlying metal interconnect 102. Finally, another stop layer 116 is formed on the intermetallic dielectric layer 106 and covers the metal interconnects 112 and 114. At this point, the fabrication of the semiconductor device of one embodiment of the present invention is completed.

[0052] Please refer to Fig. 9 , Fig. 9 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. Fig. 9 As shown, the semiconductor element mainly includes a metal interconnect 32 arranged in the MTJ area 14, an intermetallic dielectric layer 30 surrounding the metal interconnect 32, MTJs 62 and 72 arranged on the metal interconnect 32, an upper electrode 78 arranged on the MTJs 62 and 72, a cover layer 68 arranged on the side walls of the MTJs 62 and 72 and the upper electrode 78, a connection structure 100 arranged on the upper electrode 78, a metal interconnect 102 arranged in the logic area 16, and an intermetallic dielectric layer 80 surrounding the cover layer 68 and the metal interconnect 102.

[0053] In the present embodiment, the connection structure 100 preferably includes a hard mask 92 disposed on the upper electrode 78, a barrier layer 96 disposed on the hard mask 92, and a metal layer 98 disposed on the barrier layer 96, wherein the width of the upper electrode 78 is preferably smaller than the width of the connection structure 100, the bottom of the connection structure 100 is preferably directly in contact with the upper electrode 78, the cap layer 68, and the intermetallic dielectric layer 80, and the hard mask 92 and the upper electrode 78 may include the same or different materials. In detail, the hard mask 92 and the upper electrode 78 preferably include metal nitrides such as but not limited to titanium nitride, the barrier layer 96 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the metal layer 98 may include low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) or a combination thereof.

[0054] Compared to the connection structure 100 of the MTJ region 14 including a three-layer structure, the metal interconnect 102 of the logic region 16 only includes a barrier layer 96 and a metal layer 98. Since the connection structure 100 and the metal interconnect 102 are preferably prepared in the same step, the barrier layer 96 and the metal layer 98 of the metal interconnect 102 in the logic region 16 respectively include the same materials as the barrier layer 96 and the metal layer 98 in the connection structure 100. In addition, the metal interconnect 102 further includes a contact hole conductor 118 and a trench conductor 120, wherein the lower surface of the trench conductor 120 is preferably lower than the lower surface of the connection structure 100, and the bottom of the metal interconnect 32 of the MTJ region 14 is preferably flush with the bottom of the contact hole conductor 118.

[0055] Please continue to refer to Fig.10 , Fig.10 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. Fig.10 As shown, the semiconductor element mainly includes a metal interconnect 32 arranged in the MTJ area 14, an intermetallic dielectric layer 30 surrounding the metal interconnect 32, MTJs 62 and 72 arranged on the metal interconnect 32, an upper electrode 78 arranged on the MTJs 62 and 72, a cover layer 68 arranged on the side walls of the MTJs 62 and 72 and the upper electrode 78, a connection structure 100 arranged on the upper electrode 78, a metal interconnect 102 arranged in the logic area 16, and an intermetallic dielectric layer 80 surrounding the cover layer 68 and the metal interconnect 102.

[0056] Compared to the connection structure 100 in the aforementioned embodiment including a hard mask 92, a barrier layer 96 and a metal layer 98, the connection structure 100 in the present embodiment includes only two materials, namely a barrier layer 96 and a metal layer 98, but does not include any hard mask disposed between the barrier layer 96 and the upper electrode 78, wherein the width of the upper electrode 78 is preferably smaller than the width of the connection structure 100, the bottom of the connection structure 100 is preferably in direct contact with the upper electrode 78 and the cover layer 68 but may optionally contact or not contact the intermetallic dielectric layer 80, the lower surface of the trench conductor 120 of the metal interconnect 102 in the logic region 16 is preferably lower than the lower surface of the connection structure 100, and the bottom of the metal interconnect 32 in the MTJ region 14 is preferably flush with the bottom of the contact hole conductor 118. As in the previous embodiments, the barrier layer 96 may include a low resistance material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the metal layer 98 may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) or a combination thereof.

[0057] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a magnetic tunneling junction (MTJ) region and a logic region; Forming a first intermetallic dielectric layer on the substrate in the magnetic tunneling junction region and the logic region, wherein the first intermetallic dielectric layer is provided with a metal interconnection; Forming a magnetic tunnel junction on the metal interconnect of the first intermetallic dielectric layer in the magnetic tunnel junction region, wherein the metal interconnect forms a first curved sidewall and a second curved sidewall near the junction of the magnetic tunnel junction, and the first curved sidewall and the second curved sidewall directly connect the junction of the metal interconnect and the magnetic tunnel junction; forming a top electrode on the magnetic tunnel junction; Forming a capping layer on the magnetic tunneling junction region and the first intermetallic dielectric layer of the logic region and covering the magnetic tunneling junction; forming a second intermetallic dielectric layer on the cap layer and surrounding the magnetic tunnel junction; Removing the second intermetallic dielectric layer and the cover layer directly above the upper electrode to form a groove; forming a first hard mask on the second intermetal dielectric layer and filling the groove; Removing the first hard mask, the second intermetallic dielectric layer, the capping layer, and the first intermetallic dielectric layer of the logic region to form a contact hole; A metal layer is formed in the groove and the contact hole to form a connection structure above the upper electrode and another metal inner connection in the logic area, wherein the height of the connection structure is lower than the height of the upper electrode and the cover layer contacts the bottom surface of the connection structure.

2. The method according to claim 1, further comprising: forming a second hard mask on the second intermetal dielectric layer; removing the second hard mask and the second intermetal dielectric layer to form the groove; forming the first hard mask on the second hard mask; as well as The first hard mask, the second hard mask and the first intermetallic dielectric layer of the logic region are removed to form the contact hole. 3 . The method of claim 2 , wherein the first hard mask and the second hard mask comprise different materials. The method of claim 2 , wherein the second hard mask comprises silicon oxynitride. 5 . The method of claim 2 , further comprising planarizing the metal layer, the first hard mask, and the second hard mask of the magnetic tunneling junction region and the logic region to form the connection structure and the other metal interconnect. The method of claim 1 , wherein the first hard mask comprises metal nitride. The method according to claim 1 , wherein the width of the upper electrode is smaller than the width of the connection structure.

8. A semiconductor element, characterized in that: Include: A substrate including a magnetic tunneling junction (MTJ) region and a logic region; A first intermetallic dielectric layer is disposed on the substrate in the magnetic tunneling junction region and the logic region; A magnetic tunnel junction is disposed on the first intermetallic dielectric layer in the magnetic tunnel junction region; An upper electrode is disposed on the magnetic tunnel junction; A cover layer is disposed on the magnetic tunnel junction region and the first intermetallic dielectric layer of the logic region and covers the magnetic tunnel junction; A connecting structure is disposed on the upper electrode, wherein the height of the connecting structure is lower than the height of the upper electrode and the covering layer contacts the surface of the bottom of the connecting structure; A first metal interconnect is disposed in the logic region, wherein the first metal interconnect comprises: A contact hole conductor is disposed on the substrate; and A trench conductor, wherein a lower surface of the trench conductor is lower than a lower surface of the connection structure; and A second metal interconnect is disposed in the first intermetallic dielectric layer, wherein the magnetic tunnel junction is disposed on the second metal interconnect. The second metal interconnect forms a first arcuate side wall and a second arcuate side wall near the junction of the magnetic tunnel junction. The first arcuate side wall and the second arcuate side wall directly connect the junction of the metal interconnect and the magnetic tunnel junction. 9 . The semiconductor device as claimed in claim 8 , wherein a bottom of the second metal interconnect is flush with a bottom of the contact hole conductor. 10 . The semiconductor device as claimed in claim 8 , wherein an upper surface of the trench conductor is flush with an upper surface of the connecting structure. 11 . The semiconductor device as claimed in claim 8 , wherein the connection structure and the first metal interconnection comprise the same material. 12 . The semiconductor device as claimed in claim 8 , wherein a width of the upper electrode is smaller than a width of the connecting structure.

13. A semiconductor element, characterized in that: Include: A substrate including a magnetic tunneling junction (MTJ) region and a logic region; A first intermetallic dielectric layer is disposed on the substrate in the magnetic tunneling junction region and the logic region; A magnetic tunnel junction is disposed on the first intermetallic dielectric layer in the magnetic tunnel junction region; An upper electrode is disposed on the magnetic tunnel junction; A cover layer is disposed on the magnetic tunnel junction region and the first intermetallic dielectric layer of the logic region and covers the magnetic tunnel junction; A connection structure is disposed on the upper electrode, wherein the height of the connection structure is lower than the height of the upper electrode, the cover layer contacts the bottom surface of the connection structure, and the connection structure comprises: A hard mask is disposed on the upper electrode; a barrier layer disposed on the hard mask; as well as a metal layer disposed on the barrier layer; and A second metal interconnect is disposed in the first intermetallic dielectric layer, wherein the magnetic tunnel junction is disposed on the second metal interconnect. The second metal interconnect forms a first arcuate side wall and a second arcuate side wall near the junction of the magnetic tunnel junction. The first arcuate side wall and the second arcuate side wall directly connect the junction of the metal interconnect and the magnetic tunnel junction.

14. The semiconductor device according to claim 13, further comprising: A first metal interconnect is disposed in the logic region, wherein the first metal interconnect comprises: A contact hole conductor is disposed on the substrate; and A trench conductor, wherein a lower surface of the trench conductor is lower than a lower surface of the connection structure. 15 . The semiconductor device as claimed in claim 14 , wherein an upper surface of the trench conductor is flush with an upper surface of the connecting structure. 16 . The semiconductor device as claimed in claim 14 , wherein a bottom of the second metal interconnect is flush with a bottom of the contact hole conductor. 17 . The semiconductor device as claimed in claim 13 , wherein a width of the upper electrode is smaller than a width of the connecting structure.

18. The semiconductor device as claimed in claim 13, wherein the hard mask and the top electrode comprise the same material.

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