Semiconductor device

Abstract

Provided is a semiconductor device (600) capable of inhibiting breakdown at a peripheral terminal region, including an active region (150) for passing a main current; a gate ring region (160) surrounding the periphery of the active region; a source ring region (170) surrounding the periphery of the gate ring region; and a terminal region (168) surrounding the periphery of the source ring region. The active region includes a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer (6) of a second conductivity type; a first semiconductor region (7) of the first conductivity type; a gate insulating film (9); a first gate electrode (10a); an interlayer insulating film (11); a first electrode (12a); a first plating film (14a); and a second electrode (13). The source ring region includes a semiconductor substrate; a first semiconductor layer; a second semiconductor layer; a second electrode (12b) disposed on the surface of the second semiconductor layer; and a second plating film (14b) disposed on the second electrode.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] In the past, silicon (Si) was used as the constituent material for power semiconductor devices that control high voltage and high current. Power semiconductor devices include various types such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are used according to their applications.

[0003] For example, compared to MOSFETs, bipolar transistors (BPTs) and IGBTs have higher current densities and can handle larger currents, but they cannot switch at high speeds. Specifically, the use of BPTs is limited to switching frequencies in the range of a few kHz, and the use of IGBTs is limited to switching frequencies in the range of tens of kHz. On the other hand, although power MOSFETs have lower current densities and are more difficult to scale up compared to BPTs and IGBTs, they can perform high-speed switching operations up to several MHz.

[0004] However, the market demand for power semiconductor devices that combine high current and high speed is strong, and all efforts are being devoted to improving IGBTs and power MOSFETs. Currently, development has reached almost the limits of materials. From the perspective of power semiconductor devices, semiconductor materials to replace silicon have been studied. As a semiconductor material that can be used to manufacture next-generation power semiconductor devices with low on-state voltage, high speed characteristics, and excellent high-temperature characteristics, silicon carbide (SiC) has attracted much attention.

[0005] Silicon carbide (SiC) is a chemically very stable semiconductor material with a wide bandgap of up to 3 eV, allowing it to function extremely stably as a semiconductor even at high temperatures. Furthermore, because SiC's maximum electric field strength is more than an order of magnitude greater than that of silicon, it is highly anticipated as a semiconductor material capable of significantly reducing on-state resistance. These advantages of SiC are also applicable to other wide-bandgap semiconductors with even wider bandgaps than silicon, such as gallium nitride (GaN). Therefore, by using wide-bandgap semiconductors, high voltage withstand capability can be achieved in semiconductor devices.

[0006] The structure of existing silicon carbide semiconductor devices is explained using a vertical MOSFET as an example. Figure 22 This is a top view showing the structure of an existing silicon carbide semiconductor device. For example... Figure 22As shown, the semiconductor chip (vertical MOSFET) 1600 has an edge termination region 1168 surrounding the active region 1150 and maintaining voltage resistance on its outer periphery. Within the active region 1150, there are gate electrode pads 1100 electrically connected to the gate electrode and source electrode pads 1104 electrically connected to the source electrode. Furthermore, between the active region 1150 and the edge termination region 1168, a gate ring region 1160 is provided, and wiring for connecting the gate electrode to the gate electrode pads 1100 is formed in the gate ring region 1160.

[0007] To further improve the reliability of silicon carbide semiconductor devices, a semiconductor device is proposed in which high-functionality regions 1400, such as a current sensing unit, a temperature sensing unit (not shown), and an overvoltage protection unit (not shown), are disposed on the same semiconductor substrate as the semiconductor chip 1600. In the case of the high-functionality structure, to stably form the high-functionality regions 1400, a region containing only the high-functionality regions 1400 is provided in the active region 1150, separated from the unit cell of the main semiconductor element and adjacent to the edge termination region 1168. The active region 1150 is the region where the main current flows when the main semiconductor element is turned on. The edge termination region 1168 is a region used to mitigate the electric field on the front side of the semiconductor substrate and maintain withstand voltage. Withstand voltage refers to the limit voltage that will not cause malfunction or damage to the component.

[0008] The current sensing section includes an active region 1230 with the same structure as the active region 1150 and a current sensing pad 1202 for current detection. The temperature sensing section has the function of detecting the temperature of the semiconductor chip using the temperature characteristics of a diode.

[0009] Figure 23 This represents the structure of existing silicon carbide semiconductor devices. Figure 22 AA section diagram. Figure 23 This is a cross-sectional view showing the structure of an existing trench-type silicon carbide semiconductor device. In the trench-type MOSFET 1600, at n... + An n-type silicon carbide epitaxial layer 1002 is deposited on the front side of a silicon carbide substrate 1001. In the active region 1150, the n-type silicon carbide epitaxial layer 1002 is connected to the n... + An n-type high-concentration region 1005 is provided on the surface opposite to the silicon carbide substrate 1001. Furthermore, a second p-type high-concentration region 1005 is selectively provided in the n-type high-concentration region 1005 such that it covers the entire bottom surface of the trench 1016. + Type base region 1004. In the n-type high concentration region 1005, with n... + The surface layer on the opposite side of the silicon carbide substrate 1001 is selectively provided with a first p + Base region 1003.

[0010] In addition, a p-type substrate 1006 and an n-type substrate 1006 are further provided in the active region 1150 of the existing trench MOSFET 1600. + Source region 1007, p ++ Type contact area 1008, gate insulating film 1009, gate electrode 1010, interlayer insulating film 1011, source electrode 1012, back electrode 1013, trench 1016, source electrode pad (not shown) and drain electrode pad (not shown).

[0011] Source electrode 1012 is in n + Source region 1007, p ++ A multilayer film consisting of a NiSi electrode 1015, a first TiN film 1020, a first Ti film 1021, a second TiN film 1022, a second Ti film 1033, and an Al alloy film 1029 is sequentially stacked on the contact area 1008. Additionally, a coating 1014, solder 1024, external electrode leads 1026, a first protective film 1023, and a second protective film 1025 are disposed on the upper part of the source electrode 1012.

[0012] Additionally, a first p is provided in the gate ring region 1160 of the existing trench MOSFET 1600. + Type 1003 base layer, type p base layer 1006, p ++ Type contact area 1008. In p ++ The contact area 1008 is provided with an insulating film 1530, a gate electrode 1010, an interlayer insulating film 1011, a gate wiring electrode 1017 and a first protective film 1023.

[0013] Additionally, in the edge termination region 1168 of the existing trench MOSFET 1600, the p-type substrate 1006 and p-type MOSFET are removed from the entire region. ++ The contact area 1008 is formed on the front side, and a step (concave towards the drain side) is formed so that the edge terminal area 1168 is lower than the active area 1150, and the n-type silicon carbide epitaxial layer 1002 is exposed at the bottom of the step.

[0014] Additionally, in the edge terminal area 1168, multiple p-type grounding configurations are provided. + The JTE structure is formed by two JTE regions (the first JTE region 1163 and the second JTE region 1165). Additionally, an n-type region acting as a channel cutoff region is provided on the outer side of the JTE structure (on the chip end side). + Type semiconductor region 1167.

[0015] The first JTE region 1163 and the second JTE region 1165 are selectively disposed on the exposed portion of the n-type silicon carbide epitaxial layer 1002 at the bottom surface of the step. When a high voltage is applied, the lateral high voltage in the region other than the active region 1150 is ensured by the pn junction between the first JTE region 1163, the second JTE region 1165 and the n-type silicon carbide epitaxial layer 1002.

[0016] Additionally, the following semiconductor device is known, wherein the semiconductor device comprises: n - The semiconductor device has a type epitaxial layer having a cell portion and an outer peripheral portion disposed around the cell portion; and a surface insulating film disposed across the cell portion and the outer peripheral portion, and being formed in the cell portion thinner than in the outer peripheral portion, and the semiconductor device is able to improve the flatness of the surface metal layer without sacrificing existing breakdown voltage characteristics (see, for example, Patent Document 1 below).

[0017] In addition, the following semiconductor device is known: at the boundary between the high-function region and the edge terminal region, an extraction electrode is provided on the front side of the semiconductor substrate, which has the function of extracting hole current flowing from the edge terminal region to the high-function region when the main semiconductor element is turned off, and can suppress damage at the edge terminal region (for example, see Patent Document 2 below).

[0018] Existing technical documents

[0019] Patent documents

[0020] Patent Document 1: Japanese Patent Application Publication No. 2014-175314

[0021] Patent Document 2: International Publication No. 2019 / 069580 Summary of the Invention

[0022] Technical issues

[0023] In the aforementioned existing semiconductor devices (refer to...) Figure 23 In this design, because a wide-bandgap semiconductor is used as the semiconductor material, the width of the edge termination region 1168 can be reduced by 1 / 5 to 1 / 2 times compared to the case where silicon is used as the semiconductor material. Furthermore, the thickness of the edge termination region 1168 can be reduced by more than 1 / 2 times. Therefore, by reducing the width and thickness of the edge termination region 1168, a low on-state resistance (RonA) of the MOSFET can be achieved.

[0024] However, by reducing the width and thickness of the edge termination region 1168, the capacitance (pn junction capacitance) of the depletion layer extending from the pn junction of the p-type substrate 1006 and the n-type silicon carbide epitaxial layer 1002 towards the chip end in a direction parallel to the front side of the semiconductor substrate (lateral) is reduced when the MOSFET is turned off. Therefore, during MOSFET switching (especially when the MOSFET is turned off), if the drain-source voltage changes within a small time frame due to noise such as surges (hereinafter referred to as dv / dt surge), the displacement current flowing through the pn junction capacitance increases significantly. Specifically, the displacement current flowing during the charging and discharging of the pn junction capacitance becomes a multiple of the current value when silicon is used as the semiconductor material, i.e., this multiple is equal to the value of the reduced volume of the edge termination region 1168.

[0025] When the MOSFET is turned off, the displacement current caused by holes (hereinafter referred to as hole current) flows from the edge termination region 1168 to the active region 1150, and from the p-terminal region 1150... ++ The contact region 1008 is directed to the source electrode 1012. The gate ring region 1160, due to the lack of an n-type contact area... + Source region 1007, etc., therefore p ++ The area of ​​the contact region 1008 is larger than that of the other parts of the active region 1150. ++ The contact area 1008 is large. Therefore, in particular, the hole current is concentrated in the gate ring region 1160, but in the gate ring region 1160, due to the connection between the gate electrode 1010 and the p-type contact area... ++ An insulating film 1530 is disposed between the contact areas 1008, so hole current is not drawn out. Therefore, since the hole current is concentrated at the end of the MOSFET in the active region 1150, it is possible for the device to be damaged at the end of the active region 1150.

[0026] In order to eliminate the problems of the prior art, the present invention aims to provide a semiconductor device capable of suppressing damage at the edge terminal region.

[0027] Technical solution

[0028] To solve the above-mentioned problems and achieve the objective of the present invention, the semiconductor device of the present invention has the following features. The semiconductor device includes: an active region for which a main current flows; a gate ring region surrounding the active region; a ring region surrounding the gate ring region; and a termination region surrounding the ring region. The active region includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type disposed on the front side of the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second semiconductor layer of a second conductivity type disposed on the surface of the first semiconductor layer opposite to the semiconductor substrate side; a first semiconductor region of the first conductivity type selectively disposed on the surface layer of the second semiconductor layer opposite to the semiconductor substrate side; a gate insulating film in contact with the second semiconductor layer; and a first gate electrode disposed on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer. The gate ring region comprises: an interlayer insulating film disposed on the first gate electrode; a first electrode disposed on the surface of the second semiconductor layer and the first semiconductor region; a first coating selectively disposed on the first first electrode; and a second electrode disposed on the back side of the semiconductor substrate. The gate ring region comprises: the semiconductor substrate; the first semiconductor layer; the second semiconductor layer; a first insulating film in contact with the second semiconductor layer; a second gate electrode disposed on the surface of the first insulating film opposite to the surface in contact with the second semiconductor layer; and a gate wiring electrode disposed on the second gate electrode. The ring region comprises: the semiconductor substrate; the first semiconductor layer; the second semiconductor layer; a second first electrode disposed on the surface of the second semiconductor layer; and a second coating disposed on the second first electrode.

[0029] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the active region further has a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, and the first gate electrode is disposed inside the trench through the gate insulating film.

[0030] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the gate ring region has an isolation region in which the gate wiring electrode is not disposed, and in the isolation region, a first short-circuit electrode is disposed to electrically connect the first first electrode and the second first electrode.

[0031] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the second gate electrode is not provided in the above-described isolation region.

[0032] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, a second insulating film is partially provided on the gate wiring electrode, and a first short-circuit electrode is provided on the second insulating film to electrically connect the first first electrode and the second first electrode.

[0033] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, a first solder is provided on the first coating, a first electrode pin is provided on the first solder, a second solder is provided on the second coating, a second electrode pin is provided on the second solder, and the semiconductor device is provided with a short-circuit electrode that electrically connects the first electrode pin and the second electrode pin.

[0034] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the area of ​​the portion of the second first electrode in contact with the surface of the second semiconductor layer is more than twice the area of ​​the portion of the first first electrode in contact with the surface of the second semiconductor layer and the first semiconductor region.

[0035] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the active region is rectangular in shape, and at the corner of the ring region surrounding the active region and the gate ring region, the width of the second first electrode is wider than the width of the straight portion of the second first electrode.

[0036] According to the invention described above, a source ring region is provided between the gate ring region and the edge termination region in a manner that surrounds the gate ring region. A second source electrode is provided in the source ring region, which has the function of diverting the hole current flowing from the edge termination region to the active region through the p-type substrate when the main semiconductor device is turned off. Therefore, the source ring region can mitigate the concentration of current at the end of the active region. In addition, by providing a coating on the second source electrode in the source ring region, the resistance of the second source electrode can be reduced, and the damage resistance of the second source electrode can be improved.

[0037] Invention Effects

[0038] The semiconductor device according to the present invention has the effect of suppressing damage at the edge terminal region. Attached Figure Description

[0039] Figure 1 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0040] Figure 2 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 AA section diagram.

[0041] Figure 3This is one of the cross-sectional views showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0042] Figure 4 This is a cross-sectional view (part two) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0043] Figure 5 This is a cross-sectional view (part 3) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0044] Figure 6 This is a cross-sectional view (fourth in a series) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0045] Figure 7 This is a cross-sectional view (part 5) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0046] Figure 8 This is a cross-sectional view (part six) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0047] Figure 9 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 2.

[0048] Figure 10 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 9 AA section diagram.

[0049] Figure 11 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 3.

[0050] Figure 12 This represents the structure of the silicon carbide semiconductor device in Embodiment 3. Figure 11 AA section diagram.

[0051] Figure 13 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 4.

[0052] Figure 14 This represents the structure of the silicon carbide semiconductor device in Embodiment 4. Figure 13 AA section diagram.

[0053] Figure 15 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 5.

[0054] Figure 16 This is another cross-sectional view showing the structure of the silicon carbide semiconductor device in Embodiment 5.

[0055] Figure 17 This is another top view showing the structure of the silicon carbide semiconductor device of Embodiment 5.

[0056] Figure 18 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6.

[0057] Figure 19 This is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6.

[0058] Figure 20 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 7.

[0059] Figure 21 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 8.

[0060] Figure 22 It is a top view showing the structure of an existing silicon carbide semiconductor device.

[0061] Figure 23 This represents the structure of existing silicon carbide semiconductor devices. Figure 22 AA section diagram.

[0062] Symbol Explanation

[0063] 1. 1001: n + Silicon carbide substrate

[0064] 2. 1002: n-type silicon carbide epitaxial layer

[0065] 2a: First n-type silicon carbide epitaxial layer

[0066] 2b: Second n-type silicon carbide epitaxial layer

[0067] 3. 1003: First p + Base region

[0068] 3a: Lower part, first p + Base region

[0069] 3b: First p of the upper part + Base region

[0070] 4. 1004: Second p + Base region

[0071] 5. 1005: High concentration area of ​​n-type

[0072] 5a: Lower n-type high concentration zone

[0073] 5b: Upper n-type high concentration zone

[0074] 6. 1006: P-type base layer

[0075] 7. 1007: n + Source area

[0076] 8, 1008: p ++ Type contact area

[0077] 9, 1009: Gate insulating film

[0078] 10, 1010: Gate electrode

[0079] 10a: First gate electrode

[0080] 10b: Second gate electrode

[0081] 11, 1011: Interlayer insulating film

[0082] 12, 1012: Source electrode

[0083] 12a: First source electrode

[0084] 12b: Second source electrode

[0085] 13, 1013: Back electrode

[0086] 14, 1014: Coating

[0087] 14a: First coating

[0088] 14b: Second coating

[0089] 15, 1015: NiSi electrode

[0090] 16, 1016: Trench

[0091] 16a: First trench

[0092] 16b: Second trench

[0093] 17, 1017: Gate wiring electrodes

[0094] 20, 1020: The first TiN film

[0095] 21, 1021: First Ti film

[0096] 22, 1022: Second TiN film

[0097] 23, 1023: First protective film

[0098] 24, 1024: Solder

[0099] 24a: First solder

[0100] 24b: Second solder

[0101] 25, 1025: Second protective film

[0102] 25a: First secondary protective film

[0103] 25b: Second protective film

[0104] 26, 1026: External electrode pins

[0105] 26a: First external electrode pin

[0106] 26b: Second external electrode pin

[0107] 29, 1029: Al alloy film

[0108] 30:p + Type area

[0109] 31:n + Type area

[0110] 32: Lifespan Control Zone

[0111] 33, 1033: Second Ti film

[0112] 34: p-type region

[0113] 100, 1100: Gate electrode pads

[0114] 104, 1104: Source electrode pads

[0115] 150, 1150: Active area

[0116] 150a: Effective area

[0117] 160, 1160: Gate ring region

[0118] 163, 1163: First JTE Zone

[0119] 165, 1165: Second JTE Zone

[0120] 167, 1167: n + Type cutoff region

[0121] 168, 1168: Edge terminal area

[0122] 170: Source Ring Region

[0123] 202, 1202: Electrode pads of the current sensing section

[0124] 230, 1230: Active regions of the current sensing section

[0125] 400, 1400: High-functionality areas

[0126] 500: Short-circuit electrode

[0127] 530, 1530: Insulating film

[0128] 532: Second insulating film

[0129] 540: Metal rod (short-circuit electrode)

[0130] 550: Partition Area

[0131] 600, 1600: Semiconductor chips Detailed Implementation

[0132] Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked on n and p respectively indicate that the impurity concentration is higher and lower than that of unmarked layers and regions. When the markings of n and p containing + and - are the same, it indicates similar concentrations, not necessarily the same concentration. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used for the same configurations, and repeated descriptions are omitted. Additionally, in this specification, in the representation of Miller indices, "-" is a symbol placed on the index following it, and a negative index is indicated by marking "-" before the index.

[0133] (Implementation Method 1)

[0134] The semiconductor device of Embodiment 1 is constructed using a semiconductor with a wider bandgap than silicon (Si) (denoted as a wide bandgap semiconductor). Taking, for example, silicon carbide (SiC) as the wide bandgap semiconductor, the structure of the semiconductor device of Embodiment 1 will be described. Figure 1 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 The diagram shows the layout of the electrode pads and regions of each component disposed on the semiconductor substrate (semiconductor chip).

[0135] Figure 1 The silicon carbide semiconductor device of Embodiment 1 shown has a main semiconductor element and high-functionality units such as a current sensing unit, a temperature sensing unit (not shown), an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown) on the same semiconductor substrate made of silicon carbide. These high-functionality units serve as circuitry for protecting and controlling the main semiconductor element. The main semiconductor element is a trench-type MOSFET 600 in the on-state, which carries drift current along the longitudinal direction (depth direction z of the semiconductor substrate). It is composed of multiple unit cells (functional units: not shown) arranged adjacent to each other and performs main operation.

[0136] The main semiconductor element is disposed in the effective region 150a of the active region 150 (the region that functions as the MOS gate). The effective region 150a of the active region 150 is the region where the main current flows when the main semiconductor element is turned on, and it is surrounded by the gate ring region 160. In the effective region 150a of the active region 150, the source electrode 12 of the main semiconductor element is disposed on the front side of the semiconductor substrate. The source electrode 12 (first source electrode 12a) covers, for example, the entire surface of the effective region 150a of the active region 150. In addition, a source electrode pad 104 having a planar shape, for example, rectangular, is disposed on the front side of the source electrode 12.

[0137] The edge termination region 168 is the area between the active region 150 and the side of the chip (semiconductor substrate), and is used to mitigate the electric field on the front side of the semiconductor substrate to maintain withstand voltage. The edge termination region 168 is provided with withstand voltage structures such as a guard ring, a p-type region constituting a junction termination extension (JTE) structure (described later), a field plate, and a surface electric field reduction structure (not shown). Withstand voltage refers to the limit of voltage that will not cause malfunction or damage to the component.

[0138] Additionally, a high-function region 400 is disposed adjacent to the gate ring region 160 in the active region 150. The high-function region 400 has a planar shape, for example, generally rectangular. High-function components such as a current sensing unit, a temperature sensing unit (not shown), an overvoltage protection unit (not shown), and an operational circuit unit (not shown) are disposed in the high-function region 400. Figure 1 The diagram only shows the current sensing unit as a high-function unit, but other high-function units besides the current sensing unit can also be configured in the high-function area 400.

[0139] The current sensing unit has the function of detecting overcurrent (OC) flowing in the main semiconductor element. The current sensing unit is disposed below the electrode pad 202 of the current sensing unit (in the depth direction z of the semiconductor substrate), and has several vertical MOSFETs with the same configuration as the main semiconductor element in the active region 230 of the current sensing unit.

[0140] Furthermore, in the high-function area 400, on the front side of the semiconductor substrate, the gate electrode pad 100 of the main semiconductor element and the electrode pad 202 of the current sensing unit are disposed along the boundary between the active area 150 and the edge termination area 168 in a manner that they are in contact with each other and are separated from the source electrode 12 (first source electrode 12a) and the edge termination area 168. These electrode pads have, for example, a generally rectangular planar shape.

[0141] The gate electrode pad 100 is provided by a gate channel (gate wiring electrode, see reference) disposed in the gate ring region 160. Figure 2 ) and the gate electrodes of all unit cells of the main semiconductor element (refer to Figure 2 Electrical connection. The gate ring region 160 is disposed between the active region 150 and the edge termination region (termination region) 168 in a manner that surrounds the active region 150.

[0142] Additionally, a source ring region (ring region) 170 is disposed between the gate ring region 160 and the edge termination region 168, surrounding the gate ring region 160. The source ring region 170, as described later, is provided with a second source electrode 12b and is fixed to the potential (source potential) of the first source electrode 12a in the active region 150 via the p-type substrate 6, described later. The source ring region 170 has the function of diverting the hole current flowing from the edge termination region 168 to the active region 150 via the p-type substrate 6 when the main semiconductor element is turned off. Since the source ring region 170 surrounds the gate ring region 160, the influence on the active region 150 can be eliminated by diverting the hole current flowing from the edge termination region 168 via the p-type substrate 6.

[0143] Next, an example of the cross-sectional structure of the above-mentioned active region 150, gate ring region 160, edge termination region 168 and source ring region 170 will be described. Figure 2 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 A cross-sectional view of the main semiconductor element. Only the two adjacent unit cells of the main semiconductor element are shown; other unit cells of the main semiconductor element adjacent to the central part of the chip (semiconductor substrate) of that unit cell are omitted.

[0144] The main semiconductor element is a trench MOSFET 600 with a trench gate structure on the front side (the side of the p-type substrate 6) of the semiconductor substrate. The silicon carbide semiconductor substrate is formed by bonding an n-type substrate made of silicon carbide. + The n-type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 and the p-type substrate (second semiconductor layer of the second conductivity type) 6 are epitaxially grown sequentially on the n-type silicon carbide substrate (semiconductor substrate of the first conductivity type). This allows for the epitaxial growth of the n-type high-concentration region 5 on the n-type silicon carbide epitaxial layer 2.

[0145] A MOS gate is disposed in the active region 150. The MOS gate is composed of a p-type substrate 6 and an n-type substrate 7. + Source region (first semiconductor region of the first conductivity type) 7, p ++ It consists of a contact area 8, a trench 16, a gate insulating film 9, and a first gate electrode 10a.

[0146] Specifically, the trench 16 extends from the front side of the semiconductor substrate through the p-type base layer 6 along the depth direction z to reach the n-type high-concentration region 5 (which is the n-type silicon carbide epitaxial layer 2, hereinafter referred to as (2) if the n-type high-concentration region 5 is not provided). The depth direction z is from the front side of the semiconductor substrate toward the back side. The trench 16 is configured, for example, in a stripe shape.

[0147] Viewed from the front side of the semiconductor substrate, the trenches 16 can be configured in a matrix, for example. Inside the trenches 16, a gate insulating film 9 is disposed along the inner wall of the trenches 16, and a first gate electrode 10a is disposed on the gate insulating film 9 in such a way that it is embedded inside the trenches 16. The first gate electrode 10a in one trench 16 and the mesa region (the region between adjacent trenches 16) sandwiching the first gate electrode 10a constitute a unit cell of the main semiconductor element.

[0148] On the surface layer of the n-type silicon carbide epitaxial layer 2 on the source side (first source electrode 12a side), an n-type region (hereinafter referred to as the n-type high-concentration region) 5 may be provided in such a way that it contacts the p-type substrate 6. The surface layer on the source side of the n-type silicon carbide epitaxial layer 2 refers to the layer inside the n-type silicon carbide epitaxial layer 2 that is closest to the source side and exposed on the surface of the n-type silicon carbide epitaxial layer 2, and so on for the following "surface layer". The n-type high-concentration region 5 is a so-called current spreading layer (CSL) that reduces the diffusion resistance of charge carriers. This n-type high-concentration region 5 is uniformly provided, for example, in a direction parallel to the front side of the substrate (the front side of the semiconductor substrate) in a way that covers the inner wall of the trench 16.

[0149] The n-type high-concentration region 5 extends from its interface with the p-type substrate 6 to a deeper position on the drain side (back electrode 13 side) compared to the bottom surface of the trench 16. Within the n-type high-concentration region 5, first p-type electrodes can be selectively disposed. + Type base region 3, second p + Type base region 4. First p + Type base region 3 with the second p + The base area 4 and the trench 16 are separated and located between adjacent trenches 16 (platform area), and are in contact with the p-type base layer 6. The second p... + The base region 4 covers at least the bottom surface of the trench 16 and the bottom corner. The bottom corner of the trench 16 refers to the boundary between the bottom surface of the trench 16 and the sidewall.

[0150] First p + Type base region 3, second p + The pn junction of the base region 4 and the n-type high-concentration region 5 (2) is formed at a position deeper than the bottom surface of the trench 16 towards the drain side. Alternatively, the n-type high-concentration region 5 can be omitted, and the first pn junction can be formed inside the n-type silicon carbide epitaxial layer 2.+ Type base region 3, second p + Type base region 4. As long as the first p + Type base region 3, second p + The pn junction of the base region 4 and the n-type high-concentration region 5(2) can be located deeper on the drain side than the bottom surface of the trench 16, then the first p + Type base region 3, second p + The depth of the drain-side end of base region 4 can be varied according to design conditions. This is achieved through the first p... + Type base region 3, second p + The base region 4 is able to prevent a high electric field from being applied to the gate insulating film 9 along the bottom surface of the trench 16.

[0151] n is selectively arranged inside the p-type base layer 6. + Type source region 7. Can be used with n + The contact method of the source area 7 is selectively set with p ++ Type 8 contact area. + The source region 7 is in contact with the gate insulating film 9 on the sidewall of the trench 16, and is opposite to the first gate electrode 10a across the gate insulating film 9 on the sidewall of the trench 16.

[0152] An interlayer insulating film 11 is disposed on the entire front side of the semiconductor substrate such that it covers the first gate electrode 10a and the second gate electrode 10b of the gate ring region 160 (described later). All the first gate electrodes 10a are connected to the gate electrode pad 100 (see reference 100) by the second gate electrode 10b of the gate ring region 160 and the gate wiring electrode 17. Figure 1 Electrical connection. A contact hole is provided in the interlayer insulating film 11, which penetrates the interlayer insulating film 11 along the depth direction z and reaches the front side of the substrate.

[0153] The first source electrode (first first electrode) 12a is in contact with the semiconductor substrate (n) within the contact hole. + The source region 7) is an ohmic contact and is electrically insulated from the first gate electrode 10a through the interlayer insulating film 11. The first source electrode 12a is in the n + A multilayer film consisting of a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29 is sequentially stacked on the source region 7. A p-type multilayer film is provided. ++ In the case of contact region 8, the first source electrode 12a and p ++ Type 8 contact area with 8 ohms.

[0154] On the first source electrode 12a, one end of a first external electrode pin (first electrode pin) 26a is bonded via a first plating film (first plating film) 14a and a first solder (first solder) 24a. The first plating film 14a corresponds to the source electrode pad 104. The other end of the first external electrode pin 26a is bonded to a metal rod (not shown) arranged facing the front of the semiconductor substrate. Additionally, the other end of the first external electrode pin 26a is exposed on the outside of a housing (not shown) on which the semiconductor chip is mounted, and is electrically connected to an external device (not shown). The surface of the first source electrode 12a, excluding the first plating film 14a, is covered by a first protective film 23. Specifically, the first protective film 23 is provided to cover the first source electrode 12a, and the first plating film 14a is provided at the opening of the first protective film 23. The first external electrode pin 26a is bonded to the surface of the first plating film 14a via the first solder 24a. To limit the area of ​​the first solder 24a, a first second protective film 25a may be provided on the surface of the first plating film 14a. The first protective film 23 and the second protective film 25 are, for example, polyimide films.

[0155] In n + A back electrode (second electrode) 13, which serves as a drain electrode, is provided on the back side of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the back electrode 13.

[0156] Additionally, in the gate ring region 160, in the p of the silicon carbide semiconductor substrate ++ A second gate electrode 10b is disposed on the contact area 8, separated by an insulating film (first insulating film) 530. The second gate electrode 10b is connected to the p-type contact area 8 through the insulating film 530. ++ The contact area 8 is insulated. The second gate electrode 10b is covered by an interlayer insulating film 11. A contact hole is formed in the interlayer insulating film 11, penetrating the interlayer insulating film 11 along the depth direction z and reaching the second gate electrode 10b. A gate wiring electrode 17 is embedded in the contact hole. The gate wiring electrode 17 electrically connects the first gate electrode 10a of the active region 150 to the gate electrode pad 100. In addition, a first protective film 23 is provided on the interlayer insulating film 11 and the gate wiring electrode 17.

[0157] In edge terminal region 168, p is removed from the entire region. ++ The system includes a p-type contact region 8 and a p-type base layer 6, and forms a step (recessed towards the drain side) on the front side of the silicon carbide semiconductor substrate, which lowers the edge termination region 168 compared to the active region 150, exposing the n-type silicon carbide epitaxial layer 2 at the bottom of the step. Furthermore, in the edge termination region 168, multiple p-type contact regions are provided. +A JTE structure is formed by two adjacent JTE regions (the first JTE region 163 and the second JTE region 165). Additionally, an n-type region acting as a channel cutoff region is provided on the outer side of the JTE structure (on the chip end side). + Type cutoff region 167.

[0158] The first JTE region 163 and the second JTE region 165 are selectively disposed on the exposed portion of the n-type silicon carbide epitaxial layer 2 at the bottom surface of the step. When a high voltage is applied, the high lateral withstand voltage of the region other than the active region 150 is ensured by the pn junction between the first JTE region 163, the second JTE region 165 and the n-type silicon carbide epitaxial layer 2.

[0159] Additionally, in the source ring region 170, in the p of the silicon carbide semiconductor substrate ++ Type contact area 8 (p not set) ++ In the case of contact area 8, a p-type base layer 6 is provided on (6) and an interlayer insulating film 11 is provided thereon. In the interlayer insulating film 11, a part is formed that penetrates the interlayer insulating film 11 along the depth direction z and reaches p. ++ The contact hole of the contact area 8(6). A second source electrode 12b is embedded in the contact hole. Therefore, the second source electrode (second first electrode) 12b is disposed on p in the same manner as the first source electrode 12a. ++ On the p-type contact region 8(6). The second source electrode 12b, like the first source electrode 12a, is a multilayer film consisting of a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29. Inside the silicon carbide semiconductor substrate, due to the p-type region (p...) located at the lower part of the active region 150... ++ The p-type contact region 8(6) and the p-type region located at the lower part of the source ring region 170 are connected, so the second source electrode 12b has the same potential as the first source electrode 12a.

[0160] A coating (second coating) 14 is formed on the surface of the second source electrode 12b, and the portion other than the second coating 14b is covered by a first protective film 23. Specifically, the first protective film 23 is formed to cover the second source electrode 12b, and the second coating 14b is formed at the opening of the first protective film 23. The second coating 14b and a portion of the first protective film 23 can be covered by a second second protective film 25b. The second coating 14b can be formed on the entire surface of the second source electrode 12b, or selectively, for example, only on the second source electrode 12b at the corner of the source ring region 170.

[0161] As described above, the source ring region 170 has the function of diverting the hole current flowing from the edge termination region 168 to the active region 150 through the p-type substrate 6 when the main semiconductor device is turned off. Therefore, the source ring region 170 can mitigate the concentration of current at the end of the active region 150. In addition, by providing the second coating 14b on the second source electrode 12b, the resistance of the second source electrode 12b can be reduced, and the damage resistance of the second source electrode 12b can be improved. Furthermore, by bulging the source ring region 170 outward at the corners of the active region 150 and the edge termination region 168, the width of the source ring region 170 can be wider than the width of the straight portion, and the width of the corners of the second source electrode 12b can be wider than the width of the straight portion (see reference). Figure 1 Region S). Figure 1 In this case, only one corner can be expanded, but all four corners can also be expanded, or only two corners can be expanded. This further facilitates the extraction of hole current and further mitigates the current concentration in the active region 150. Additionally, the second source electrode 12b and the silicon carbide semiconductor substrate (p... ++ Type contact area 8, without setting p ++ When the contact area 8 is a p-type substrate 6, the contact area is preferably greater than that of the first source electrode 12a and the silicon carbide semiconductor substrate (p). ++ Type contact area 8, without setting p ++ When the contact area is 8, it is more than twice the size of the contact area of ​​the p-type base layer 6.

[0162] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1)

[0163] Next, the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 will be described. Figures 3-8 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0164] First, prepare n-type silicon carbide. + Type 1 silicon carbide substrate. Then, on the n... + On the first main surface of the silicon carbide substrate 1, an n-type impurity, such as nitrogen atoms (N), is doped, and a first n-type silicon carbide epitaxial layer 2a formed of silicon carbide is epitaxially grown to a thickness of, for example, about 30 μm. The state up to this point is shown in... Figure 3 .

[0165] Next, on the surface of the first n-type silicon carbide epitaxial layer 2a, an ion implantation mask with predetermined openings is formed using photolithography, for example, by using an oxide film. Then, p-type impurities such as aluminum are implanted into the openings of the oxide film to form a lower first p-type epitaxial layer with a depth of approximately 0.5 μm. + Type base region 3a and second p + Type base region 4.

[0166] Additionally, make the adjacent lower first p + Type base region 3a and second p + The distance between the four base regions is approximately 1.5 μm. The lower first p... + Type base region 3a and second p + The impurity concentration in base region 4 is set to, for example, 5 × 10⁻⁶. 18 / cm 3 about.

[0167] Next, a portion of the ion implantation mask can be removed, and ion implantation of n-type impurities such as nitrogen can be performed at the opening to form a lower n-type high-concentration region 5a with a depth of approximately 0.5 μm, for example, on a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high-concentration region 5a is set to, for example, 1 × 10⁻⁶. 17 / cm 3 Left and right. The current state up to this point is shown. Figure 4 .

[0168] Next, on the surface of the first n-type silicon carbide epitaxial layer 2a, a second n-type silicon carbide epitaxial layer 2b, doped with n-type impurities such as nitrogen, is formed to a thickness of approximately 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is set to 3 × 10⁻⁶. 15 / cm 3 Left and right. Then, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b are merged into an n-type silicon carbide epitaxial layer 2.

[0169] Next, on the surface of the second n-type silicon carbide epitaxial layer 2b, an ion implantation mask with predetermined openings is formed using photolithography, for example, by using an oxide film. Then, p-type impurities such as aluminum are implanted into the openings of the oxide film to connect with the lower first p-type epitaxial layer. + The upper first p-type region with a depth of approximately 0.5 μm is formed by overlapping the 3a base regions. + Base region 3b. Lower first p + Type base region 3a and upper first p + The base region 3b forms a continuous region, becoming the first p. + Type base region 3. The upper first p + The impurity concentration in base region 3b is set to, for example, 5 × 10⁻⁶. 18 / cm 3 about.

[0170] Next, a portion of the ion implantation mask can be removed, and ion implantation of n-type impurities such as nitrogen can be performed at the opening to form an upper n-type high-concentration region 5b with a depth of approximately 0.5 μm, on a portion of the surface region of the second n-type silicon carbide epitaxial layer 2b. The impurity concentration of the upper n-type high-concentration region 5b is set to, for example, 1 × 10⁻⁶.17 / cm 3 Left and right. The upper n-type high-concentration region 5b and the lower n-type high-concentration region 5a are formed in at least partial contact, forming an n-type high-concentration region 5. There are cases where the n-type high-concentration region 5 is formed on the entire surface of the substrate and cases where it is not formed on the entire surface of the substrate. The state up to this point is shown. Figure 5 .

[0171] Next, a p-type substrate 6 with a thickness of approximately 1.1 μm is formed on the surface of the n-type silicon carbide epitaxial layer 2 through epitaxial growth. The impurity concentration of the p-type substrate 6 is set to 4 × 10⁻⁶. 17 / cm 3 Approximately. After forming the p-type substrate 6 through epitaxial growth, ion implantation of p-type impurities such as aluminum can be further performed on the p-type substrate 6.

[0172] Next, an ion implantation mask with predetermined openings is formed on the surface of the p-type substrate 6 using photolithography, for example, by using an oxide film. Nitrogen (N), phosphorus (P), and other n-type impurities are implanted into these openings, forming n-type impurities on a portion of the surface of the p-type substrate 6. + Type source region 7. Next, the region used to form n can be removed. + An ion implantation mask for the source region 7 is formed using the same method, and an ion implantation mask with a predetermined opening is formed. Ions of p-type impurities such as phosphorus are implanted onto a portion of the surface of the p-type substrate 6 to form a p-type base layer. ++ Type contact area 8. p ++ The impurity concentration in contact zone 8 is set higher than that in p-type substrate 6. The state up to this point is shown in... Figure 6 .

[0173] Next, heat treatment (annealing) was carried out in an inert gas atmosphere at around 1700℃ to implement the first p + Type base region 3, second p + Type base region 4, n + Type source region 7 and p ++ Activation treatment of contact region 8. It should be noted that, as described above, each ion implantation region can be activated by a single heat treatment, or it can be activated by heat treatment during each ion implantation.

[0174] Next, on the surface of the p-type substrate 6, a trench forming mask with predetermined openings is formed by photolithography, for example using an oxide film. Then, a trench 16 is formed by dry etching, penetrating the p-type substrate 6 and reaching the n-type high-concentration region 5(2). The bottom of the trench 16 can reach the second p-type layer formed in the n-type high-concentration region 5(2). + Base region 4. Next, remove the mask used for trench formation. The state up to this point is shown in... Figure 7.

[0175] Next, along n + A gate insulating film 9 is formed on the surface of the source region 7 and the bottom and sidewalls of the trench 16. This gate insulating film 9 can be formed by thermal oxidation at a temperature of approximately 1000°C in an oxygen atmosphere. Alternatively, the gate insulating film 9 can also be formed by deposition using chemical reactions such as high-temperature oxidation (HTO).

[0176] Next, a polysilicon layer doped with, for example, phosphorus atoms is formed on the gate insulating film 9. This polysilicon layer can be formed by embedding it within the trench 16. The polysilicon layer is patterned by photolithography and remains inside the trench 16, thereby forming the first gate electrode 10a.

[0177] Next, a phosphor glass film with a thickness of approximately 1 μm is formed, covering the gate insulating film 9 and the first gate electrode 10a, to form an interlayer insulating film 11. Then, a barrier metal composed of titanium (Ti), titanium nitride (TiN), or a stack of titanium and titanium nitride can be formed covering the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned using photolithography to form a barrier metal that allows n to pass through. + Type source region 7 and p ++ The contact holes in contact area 8 are exposed. Subsequently, heat treatment (reflow) is performed to planarize the interlayer insulating film 11. The state up to this point is shown in... Figure 8 Furthermore, after forming contact holes in the interlayer insulating film 11, a barrier metal composed of titanium (Ti), titanium nitride (TiN), or a stack of titanium and titanium nitride can be formed. At this time, n is also provided in the barrier metal. + Type source region 7 and p ++ Type 8 contact area exposed contact hole.

[0178] Next, a conductive film to be used as the NiSi electrode 15 is formed in the contact holes and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. Additionally, in n + A nickel (Ni) film is also formed on the second main surface of the silicon carbide substrate 1. Subsequently, a heat treatment is performed, for example, at a temperature of approximately 970°C, to silicide and physicochemically form the nickel film inside the contact hole, thus creating a NiSi electrode 15. Simultaneously, the nickel film formed on the second main surface becomes a NiSi electrode 15. + A back electrode 13 with ohmic bonding is formed on a silicon carbide substrate 1. Thereafter, unreacted nickel film is selectively removed, for example, leaving only the NiSi electrode 15 inside the contact hole. A first gate electrode 10a and the NiSi electrode 15 are also formed in the source ring region 170 in the same way.

[0179] Next, for example, by sputtering, a first TiN film 20, a first Ti film 21, a second TiN film 22, and a second Ti film 33 are sequentially stacked to cover the NiSi electrode 15 and the interlayer insulating film 11 on the front side of the silicon carbide semiconductor substrate, thereby forming an Al alloy film 29 with a thickness of, for example, about 5 μm. The Al alloy film 29 can also be an Al film. The Al alloy film 29 can be, for example, an Al-Si film or an Al-Si-Cu film. This conductive film is patterned by photolithography and remains in the active region 150 of the entire device, thereby forming the first source electrode 12a. Similarly, the first TiN film 20, the first Ti film 21, the second TiN film 22, and the second Ti film 33 are sequentially stacked in the source ring region 170 to form the Al alloy film 29, thereby forming the second source electrode 12b.

[0180] Next, after forming a polyimide film on the Al alloy film 29, the polyimide film is selectively removed by photolithography and etching to form a first protective film 23, and an opening is formed in the first protective film 23. Next, a first coating 14a is formed on the Al alloy film 29 exposed at the opening of the first protective film 23. Similarly, a second coating 14b and the first protective film 23 are formed in the source ring region 170.

[0181] Next, a first second protective film 25a is formed to cover the boundary between the first coating 14a and the first protective film 23. The first second protective film 25a is, for example, a polyimide film. Subsequently, a first external electrode pin 26a is formed on the first coating 14a, with the first solder 24a in between.

[0182] As described above, complete Figure 1 The semiconductor device shown.

[0183] As described above, in the silicon carbide semiconductor device according to Embodiment 1, a source ring region is provided between the gate ring region and the edge termination region in a manner that surrounds the gate ring region. A second source electrode is provided in the source ring region, which has the function of drawing out the hole current flowing from the edge termination region to the active region through the p-type substrate when the main semiconductor element is turned off. Therefore, the source ring region can mitigate the concentration of current at the end of the active region. Furthermore, even if avalanche carriers increase rapidly due to cosmic rays, they can be absorbed by the source ring, thus preventing avalanche carriers from affecting the active region and improving damage resistance. In addition, by providing a coating on the second source electrode in the source ring region, the resistance of the second source electrode can be reduced, improving the damage resistance of the second source electrode.

[0184] (Implementation Method 2)

[0185] Next, the structure of the silicon carbide semiconductor device of Embodiment 2 will be described. Figure 9This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The silicon carbide semiconductor device of Embodiment 2 differs from that of Embodiment 1 in that it is provided with a short-circuit electrode 500 that connects the first source electrode 12a of the active region 150 to the second source electrode 12b of the source ring region 170.

[0186] Specifically, an isolation region 550 is provided in the gate ring region 160, and a short-circuit electrode 500 is provided in the isolation region 550 instead of the second gate electrode 10b and the gate wiring electrode 17. Figure 10 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 9 AA section diagram. Figure 10 It is the cross-section of the portion where the short-circuit electrode 500 is located. For example... Figure 10 As shown, in the gate ring region 160, in the p of the silicon carbide semiconductor substrate ++ An insulating film 530 and an interlayer insulating film 11 are provided on the contact area 8, and a short-circuit electrode 500 is provided on the interlayer insulating film 11. By connecting the first source electrode 12a and the second source electrode 12b using the short-circuit electrode 500, the hole current drawn from the source ring region 170 can flow from the second source electrode 12b to the first source electrode 12a, which can further mitigate the concentration of current at the end of the active region 150.

[0187] At least one short-circuit electrode 500 is required in the semiconductor chip 600. However, to reduce the resistance between the first source electrode 12a and the second source electrode 12b, a short-circuit electrode 500 is preferred. Figure 9 Thus, one or more short-circuit electrodes 500 are provided on each side. Furthermore, in the portion where the isolation region 550 is provided, the path from the second gate electrode 10b to the gate electrode pad 100 becomes longer, and the resistance increases. Therefore, in the portion where the isolation region 550 is provided, it is preferable not to form a MOS structure, for example, not to provide n... + Source region 7. Here, since the second gate electrode 10b and gate wiring electrode 17 are not formed in the isolation region 550, the second gate electrode 10b is not ring-shaped. Therefore, in the case of providing multiple isolation regions 550, in order to apply the full voltage to the second gate electrode 10b, it is preferable to stagger the positions of the two opposing sides of the isolation regions 550 in the stripe direction of the trench 16.

[0188] As described above, according to Embodiment 2, by providing a short-circuit electrode connecting the first source electrode and the second source electrode, the hole current drawn from the source ring region can flow to the first source electrode, further mitigating the concentration of current at the end of the active region. Thus, the same effect as Embodiment 1 can be achieved.

[0189] (Implementation Method 3)

[0190] Next, the structure of the silicon carbide semiconductor device of Embodiment 3 will be described. Figure 11 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The silicon carbide semiconductor device of Embodiment 3 differs from that of Embodiment 2 in that it does not have an isolation region 550, but instead has a short-circuit electrode 500 that connects the first source electrode 12a of the active region 150 to the second source electrode 12b of the source ring region 170.

[0191] Figure 12 This represents the structure of the silicon carbide semiconductor device in Embodiment 3. Figure 11 AA section diagram. (See diagram below.) Figure 12 As shown, a second insulating film (second insulating film) 532 is provided in the gate ring region 160 at the location where the short-circuit electrode 500 is provided, so as to cover the gate wiring electrode 17, and the short-circuit electrode 500 is provided on the second insulating film 532. The short-circuit electrode 500 is insulated from the second gate electrode 10b by the second insulating film 532.

[0192] Alternatively, the gate wiring electrode 17 can be omitted at the location where the short-circuit electrode 500 is provided in the gate ring region 160, or the short-circuit electrode 500 can be provided on the interlayer insulating film 11 covering the second gate electrode 10b.

[0193] In Embodiment 2 described above, since the gate wiring electrode 17 is isolated by the short-circuit electrode 500, the path to the gate electrode pad 100 sometimes becomes longer near the second gate electrode 10b where the isolation point is located. On the other hand, in Embodiment 3, since at least the second gate electrode 10b is not isolated, the path to the gate electrode pad 100 does not become longer.

[0194] As described above, according to Embodiment 3, by providing a short-circuit electrode connecting the first source electrode and the second source electrode without at least disconnecting the second gate electrode, it is possible to prevent the path between the second gate electrode and the gate electrode pad from becoming longer. Furthermore, the same effects as in Embodiments 1 and 2 can be obtained.

[0195] (Implementation Method 4)

[0196] Next, the structure of the silicon carbide semiconductor device of Embodiment 4 will be described. Figure 13 This is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 4. The silicon carbide semiconductor device of Embodiment 4 differs from that of Embodiment 2 in that a short-circuit electrode 500 is provided on the first external electrode pin 26a and the second external electrode pin 26b to connect the first source electrode 12a of the active region 150 and the second source electrode 12b of the source ring region 170.

[0197] Figure 14 This represents the structure of the silicon carbide semiconductor device in Embodiment 4. Figure 13 AA section diagram. (See diagram below.) Figure 14 As shown, in the source ring region 170, a second external electrode pin (second electrode pin) 26b is bonded to the coating (second coating) 14 via a second solder (second solder) 24b. The second solder 24b can be surrounded by a second second protective film 25b. The other end of the second external electrode pin 26b is connected to a metal rod 540 via the second solder 24b, the metal rod 540 being arranged to face the front of the silicon carbide semiconductor substrate. This metal rod 540 serves as a short-circuit electrode 500. In Embodiment 4, since the gate wiring electrode 17 is not blocked, similar to Embodiment 3, the path to the gate electrode pad 100 remains unchanged. Figure 13 In the process, metal rods 540 that serve as short-circuit electrodes 500 are provided at three locations, but metal rods 540 may also be provided at only one location.

[0198] As described above, according to Embodiment 4, by providing short-circuit electrodes connecting the first source electrode and the second source electrode on the first external electrode pin and the second external electrode pin, it is possible to prevent the path between the second gate electrode and the gate electrode pad from becoming longer. Furthermore, the same effects as in Embodiments 1 and 2 can be obtained.

[0199] (Implementation Method 5)

[0200] Next, the structure of the silicon carbide semiconductor device of Embodiment 5 will be described. Figure 15 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 5. The top view is the same as that of Embodiment 1, so it is omitted. The silicon carbide semiconductor device of Embodiment 5 differs from the silicon carbide semiconductor devices of Embodiments 1 to 4 in that, in the n-type silicon carbide epitaxial layer 2 of the source ring region 170, a first p is formed deeper at a position opposite to the second source electrode 12b along the depth direction. + Type base region 3. This deeper formed portion is called p. + Type region (second semiconductor region of the second conductivity type) 30.

[0201] like Figure 15 As shown, p is preferred. + In the source ring region 170, the n-type silicon carbide epitaxial layer 2 is formed into a ring shape, and its width is wider than that of the second source electrode 12b. Preferably, p... + The width of the type region 30 is at least wider than the width of the contact hole opened in the interlayer insulating film 11. + Type 30 is because it is the first p + The base region 3 is formed in a deeper part, so its impurity concentration is similar to that of the first p-type region.+ The impurity concentration in base region 3 is the same. Additionally, p is preferred. + The depth of region 30 does not reach n + Type 1 silicon carbide substrate.

[0202] By setting p + In region 30, the hole current flowing from edge terminal region 168 to active region 150 during turn-off flows to the p-type region, which has a lower resistance than the n-type silicon carbide epitaxial layer 2. + The type region 30 can further facilitate the extraction of hole current to the second source electrode 12b, further mitigating the concentration of current in the active region 150.

[0203] Figure 16 This is another cross-sectional view showing the structure of the silicon carbide semiconductor device in Embodiment 5. (As shown...) Figure 16 As shown, n can be set. + The type region (second semiconductor region of the first conductivity type) 31 replaces p. + Type 30. In order to match p + Similarly, region 30 makes it easier for hole current to flow to n + Type 31 circulation, n + The impurity concentration in region 31 is higher than that in the n-type silicon carbide epitaxial layer 2. Additionally, n + The depth and width of region 31 can be related to p + Type region 30 is the same. Additionally, if n + If the impurity concentration in region 31 is higher than that in the n-type silicon carbide epitaxial layer 2, then the hole current will flow through the n-type region 31. + In the upper part of region 31, hole current can easily flow to the second source electrode 12b, so n + The impurity concentration of the n-type silicon carbide epitaxial layer 2 is set to be higher than that of the n-type silicon carbide epitaxial layer 2.

[0204] Figure 17 This is another top view showing the structure of the silicon carbide semiconductor device according to Embodiment 5. In this example, with Figure 15 The similarity is that p + The mold area 30, the second source electrode 12b, and the second coating 14b are quadrilaterals when viewed from above, but the difference lies in the intentional inclusion of corner portions on their sides. Specifically, in Figure 17 In the middle, make p + The molding area 30, the second source electrode 12b, and the second coating 14b are made into an uneven shape. Thus, by making p... + The type region 30, the second source electrode 12b, and the second coating 14b form a closed loop with corners, thereby p + The radial width of region 30 increases, and the electric field concentrates at p. +The corner of the type region 30 thus easily allows for the extraction of hole current. Furthermore, even if the second source electrode 12b and the second coating 14b become... Figure 15 The same straight line shape, only making p + The same effect is achieved when the shaped area 30 becomes uneven. It should be noted that p + Type 30 can be any closed-loop shape that includes the corners of the straight-line portion of the edge, and can be of various shapes. For example, it can be not only concave-convex, but also serrated. Additionally, p can be... + Type 30 changed to n + Type 31.

[0205] Furthermore, in the silicon carbide semiconductor device of Embodiment 5, the first source electrode 12a and the second source electrode 12b of Embodiment 1 are shown not being electrically connected by the short-circuit electrode 500, but the short-circuit electrode 500 can also be provided as in Embodiment 2. In this case, the top view and... Figure 9 Same as in Embodiment 3. Alternatively, the short-circuit electrode 500 can be provided without the partition region 550, as in Embodiment 3. In this case, the top view is the same as... Figure 11 Same as in Embodiment 4. Alternatively, a metal rod 540 (short-circuit electrode) can be provided on the first external electrode pin 26a and the second external electrode pin 26b. In this case, the top view is the same as... Figure 13 same.

[0206] As described above, according to Embodiment 5, the first p is formed at a relatively deep position opposite to the second source electrode along the depth direction. + Type base region, set p + Type region. Or, in relation to p + n is set at the same position in the type area + Type region. Hole current flows to p + Type area or n + The improved flow in the active region allows for easier extraction of hole current to the second source electrode, further mitigating current concentration at the active region end. This achieves the same effect as in Embodiment 1. Furthermore, by providing the same short-circuit electrode as in Embodiments 2-4, the same effect as in Embodiments 2-4 can be obtained.

[0207] (Implementation Method 6)

[0208] Next, the structure of the silicon carbide semiconductor device of Embodiment 6 will be described. Figure 18This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6. The top view is the same as that of Embodiment 1, so it is omitted. The silicon carbide semiconductor device of Embodiment 6 differs from that of Embodiment 5 in that the second source electrode 12b of the source ring region 170 is disposed in the trench 16. Hereinafter, the trench 16 of the active region 150 will be referred to as the first trench (first trench) 16a, and the trench 16 of the source ring region 170 will be referred to as the second trench (second trench) 16b.

[0209] like Figure 18 As shown, the second trench 16b penetrates the interlayer insulating film 11 and p. ++ Type 8 contact area, type 6 base layer and reaching the first p + Type base region 3. A second source electrode 12b is embedded in the second trench 16b. The second source electrode 12b is similar to that in Embodiment 1, and is a multilayer film formed by stacking a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29. A portion of the second source electrode 12b protrudes from the upper part of the second trench 16b toward the side of the second protective film 25b.

[0210] A second coating 14b is formed on the surface of the second source electrode 12b. The portion of the surface of the second source electrode 12b other than the second coating 14b is covered by a first protective film 23. Specifically, the first protective film 23 is formed to cover the second source electrode 12b, and the second coating 14b is formed at the opening of the first protective film 23. The second coating 14b can be surrounded by a second second protective film 25b. The second coating 14b can be formed on the entire surface of the second source electrode 12b, or selectively, for example, only on the second source electrode 12b at the corner of the source ring region 170. Furthermore, the width of the second source electrode 12b in Embodiment 6 can be the same as the width of the second source electrode 12b in Embodiments 1 to 5.

[0211] Additionally, p can be set at the bottom of the second trench 16b. + Type 30. p + Type 30 and the second p + The base region 4 similarly protects the second trench 16b, and is consistent with p in embodiment 5. + Similarly, the p-type region 30 can easily draw hole current to the second source electrode 12b. Thus, by placing the second source electrode 12b within the second trench 16b, the interaction between the second source electrode 12b and the p-type region (p...) can be increased. ++ Type contact area 8, first p + The contact area of ​​the base region 3 and the p-type base layer 6 is increased to reduce the contact resistance.

[0212] Figure 19This is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6. (As shown) Figure 19 As shown, n can be set. + The method of replacing p in type 31 + Type 30. In order to match p + Similarly, region 30 makes it easier for hole current to flow to n + Type 31 circulation, for example, n + The impurity concentration in region 31 is higher than that in the n-type silicon carbide epitaxial layer 2. Additionally, n + The depth and width of region 31 can be related to p + Type 30 is the same.

[0213] Furthermore, in the silicon carbide semiconductor device of Embodiment 6, the first source electrode 12a and the second source electrode 12b of Embodiment 1 are shown not being electrically connected by the short-circuit electrode 500, but the short-circuit electrode 500 can also be provided as in Embodiment 2. In this case, the top view and... Figure 9 Same as in Embodiment 3. Alternatively, the short-circuit electrode 500 can be provided without the partition region 550, as in Embodiment 3. In this case, the top view is the same as... Figure 11 Same as in Embodiment 4. Alternatively, a metal rod 540 (short-circuit electrode) can be provided on the first external electrode pin 26a and the second external electrode pin 26b. In this case, the top view is the same as... Figure 13 same.

[0214] As described above, according to Embodiment 6, by providing a second source electrode within the second trench, the contact area between the second source electrode and the p-type region can be increased, thereby reducing the contact resistance. Furthermore, a p-type region is provided at the bottom of the second trench. + Type area or n + Type region. Hole current flows to p + Type area or n + The flow in the active region allows for easier extraction of hole current from the second source electrode, further mitigating the concentration of current at the active region end. Therefore, the same effect as in Embodiment 1 can be achieved. Furthermore, by providing the same short-circuit electrode as in Embodiments 2-4, the same effect as in Embodiments 2-4 can be obtained.

[0215] (Implementation Method 7)

[0216] Next, the structure of the silicon carbide semiconductor device of Embodiment 7 will be described. Figure 20 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 7. The top view is the same as that of Embodiment 1, so it is omitted. The silicon carbide semiconductor device of Embodiment 7 differs from the silicon carbide semiconductor devices of Embodiments 1 to 4 in that the n-type silicon carbide epitaxial layer 2 in the source ring region 170 and the first p+ At the interface of the base region 3, a lifetime control region 32 is provided at a position opposite to the second source electrode 12b along the depth direction.

[0217] like Figure 20 As shown, the lifetime control region 32 is disposed between the n-type silicon carbide epitaxial layer 2 and the first p-type silicon carbide epitaxial layer 170 in the source ring region 170. + At the interface of the base region 3. In other words, the surface of the second source electrode 12b side of the lifetime control region 32 is disposed at the first p + Within the base region 3, the surface of the drain electrode 13 side of the lifetime control region 32 is disposed within the n-type silicon carbide epitaxial layer 2. The surface of the drain electrode 13 side of the lifetime control region 32 can reach n + Silicon carbide substrate 1. Preferably, the width of the lifetime control region 32 is wider than the width of the second source electrode 12b. Preferably, the width of the lifetime control region 32 is at least wider than the width of the contact hole formed in the interlayer insulating film 11.

[0218] Lifetime control region 32 is, for example, irradiated by an electron beam, protons (H) + Elements such as helium (He) and platinum (Pt) can cause damage to the crystal structure. By setting a lifetime control region 32, the lifetime of carriers in the source ring region 170 can be shortened, the hole current flowing from the edge terminal region 168 to the active region 150 can be reduced, and the concentration of current in the active region 150 can be further mitigated. Alternatively, a lifetime control region 32 and p can be set. + Alternatively, the lifespan control area 32 and n can be set in the two-way configuration of the type area 30. + Type 31, these two methods.

[0219] Furthermore, in the silicon carbide semiconductor device of Embodiment 7, the first source electrode 12a and the second source electrode 12b of Embodiment 1 are shown not being electrically connected by the short-circuit electrode 500, but the short-circuit electrode 500 can also be provided as in Embodiment 2. In this case, the top view and... Figure 9 Same as in Embodiment 3. Alternatively, the short-circuit electrode 500 can be provided without the partition region 550, as in Embodiment 3. In this case, the top view is the same as... Figure 11 Same as in Embodiment 4. Alternatively, a metal rod 540 (short-circuit electrode) can be provided on the first external electrode pin 26a and the second external electrode pin 26b. In this case, the top view is the same as... Figure 13 same.

[0220] As described above, according to Embodiment 7, a lifetime control region is provided at a position opposite the second source electrode along the depth direction. The lifetime control region shortens the carrier lifetime in the source ring region, reduces the hole current flowing from the edge terminal region to the active region, and further mitigates the concentration of current at the end of the active region. Therefore, the same effect as Embodiment 1 can be obtained. Furthermore, by providing the same short-circuit electrode as Embodiments 2-4, the same effect as Embodiments 2-4 can be obtained.

[0221] (Implementation Method 8)

[0222] Next, the structure of the silicon carbide semiconductor device of Embodiment 8 will be described. Figure 21 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 8. The top view is the same as that of Embodiment 1, so it is omitted. The difference between the silicon carbide semiconductor device of Embodiment 8 and the silicon carbide semiconductor device of Embodiment 7 is that the second source electrode 12b of the source ring region 170 is disposed in the second trench 16b.

[0223] like Figure 21 As shown, the second trench 16b penetrates the interlayer insulating film 11 and p. ++ Type 8 contact area and type 6 base layer and reach the first p + Type base region 3. A second source electrode 12b is embedded in the second trench 16b. The second source electrode 12b is similar to that in Embodiment 1, and is a multilayer film formed by stacking a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29. A portion of the second source electrode 12b protrudes from the upper part of the second trench 16b toward the side of the second protective film 25b.

[0224] A second coating 14b is formed on the surface of the second source electrode 12b. The portion of the surface of the second source electrode 12b other than the second coating 14b is covered by a first protective film 23. Specifically, the first protective film 23 is formed to cover the second source electrode 12b, and the second coating 14b is formed at the opening of the first protective film 23. The second coating 14b can be surrounded by a second second protective film 25b. The second coating 14b can be formed on the entire surface of the second source electrode 12b, or selectively, for example, only on the second source electrode 12b at the corner of the source ring region 170. Furthermore, the width of the second source electrode 12b in Embodiment 8 can be the same as the width of the second source electrode 12b in Embodiments 1 to 4.

[0225] like Figure 21 As shown, the lifetime control region 32 is disposed between the n-type silicon carbide epitaxial layer 2 and the first p-type silicon carbide epitaxial layer 170 in the source ring region 170. +At the interface of the base region 3. In other words, the surface of the second source electrode 12b side of the lifetime control region 32 is disposed at the first p + Within the base region 3, the surface of the drain electrode 13 side of the lifetime control region 32 is disposed within the n-type silicon carbide epitaxial layer 2. The surface of the drain electrode 13 side of the lifetime control region 32 can reach n + Silicon carbide substrate 1. Preferably, the width of the lifetime control region 32 is wider than the width of the second trench 16b.

[0226] Lifetime control region 32 is, for example, irradiated by an electron beam, protons (H) + Helium (He), platinum (Pt), etc., have damaged regions in the crystal structure. By setting the lifetime control region 32, the lifetime of carriers in the source ring region 170 can be shortened, the hole current flowing from the edge terminal region 168 to the active region 150 can be reduced, and the concentration of current in the active region 150 can be further mitigated.

[0227] Furthermore, in the silicon carbide semiconductor device of Embodiment 8, the first source electrode 12a and the second source electrode 12b of Embodiment 1 are shown not being electrically connected by the short-circuit electrode 500, but the short-circuit electrode 500 can also be provided as in Embodiment 2. In this case, the top view and... Figure 9 Same as in Embodiment 3. Alternatively, the short-circuit electrode 500 can be provided without the partition region 550, as in Embodiment 3. In this case, the top view is the same as... Figure 11 Same as in Embodiment 4. Alternatively, a metal rod 540 (short-circuit electrode) can be provided on the first external electrode pin 26a and the second external electrode pin 26b. In this case, the top view is the same as... Figure 13 same.

[0228] As described above, according to Embodiment 8, by providing a second source electrode within the second trench, the contact area between the second source electrode and the p-type region can be increased, thereby reducing the contact resistance. Furthermore, a lifetime control region is provided at the bottom of the second trench. This lifetime control region shortens the carrier lifetime in the source ring region, reduces the hole current flowing from the edge terminal region to the active region, and further mitigates the concentration of current at the end of the active region. Thus, the same effects as in Embodiment 1 can be achieved. Additionally, by providing the same short-circuit electrode as in Embodiments 2-4, the same effects as in Embodiments 2-4 can be achieved.

[0229] As described above, various modifications can be made to the present invention without departing from its spirit. In each of the above embodiments, for example, the dimensions of each part, impurity concentration, etc., are set according to the required specifications. Furthermore, while the above embodiments use silicon carbide as a wide-bandgap semiconductor as an example, it can also be applied to wide-bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Additionally, in each embodiment, the first conductivity type is set to n-type and the second conductivity type to p-type; however, in the present invention, setting the first conductivity type to p-type and the second conductivity type to n-type is also valid.

[0230] Industrial applicability

[0231] As described above, the semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machinery, ignition systems for automobiles, etc.

Claims

1. A semiconductor device, characterized in that, have: The active region is where the main current flows; A gate ring region that surrounds the active region; The source ring region, which surrounds the gate ring region; and The terminal region surrounds the source ring region. The active region has: First conductivity type semiconductor substrate; A first semiconductor layer of a first conductivity type is disposed on the front side of the semiconductor substrate, and the impurity concentration is lower than that of the semiconductor substrate. A second semiconductor layer of a second conductivity type is disposed on the surface of the first semiconductor layer opposite to the semiconductor substrate side; A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate side; A gate insulating film that is in contact with the second semiconductor layer; The first gate electrode is disposed on the surface of the gate insulating film opposite to the surface that contacts the second semiconductor layer; An interlayer insulating film is disposed on the first gate electrode; The first electrode, which is disposed on the surface of the second semiconductor layer and the first semiconductor region in such a way as to cover the interlayer insulating film, is a multilayer film formed by sequentially stacking a NiSi electrode, a first TiN film, a first Ti film, a second TiN film, a second Ti film and an Al alloy film; A first coating is selectively applied to the first electrode; as well as The second electrode is disposed on the back side of the semiconductor substrate. The gate ring region has: The semiconductor substrate; The first semiconductor layer; The second semiconductor layer; A first insulating film is in contact with the second semiconductor layer; The second gate electrode is disposed on the surface of the first insulating film opposite to the surface that contacts the second semiconductor layer; as well as A gate wiring electrode is disposed on the second gate electrode. The source ring region has: The semiconductor substrate; The first semiconductor layer; The second semiconductor layer; The second first electrode is disposed on the surface of the second semiconductor layer; as well as The second coating is disposed on the second first electrode. A second insulating film is partially disposed on the gate wiring electrode. A first short-circuit electrode is provided on the second insulating film to electrically connect the first electrode and the second electrode.

2. The semiconductor device according to claim 1, characterized in that, The active region also has a trench that penetrates the first semiconductor region and the second semiconductor layer, and reaches the first semiconductor layer. The first gate electrode is disposed inside the trench, separated by the gate insulating film.

3. A semiconductor device, characterized in that, have: The active region is where the main current flows; A gate ring region that surrounds the active region; The source ring region, which surrounds the gate ring region; and The terminal region surrounds the source ring region. The active region has: First conductivity type semiconductor substrate; A first semiconductor layer of a first conductivity type is disposed on the front side of the semiconductor substrate, and the impurity concentration is lower than that of the semiconductor substrate. A second semiconductor layer of a second conductivity type is disposed on the surface of the first semiconductor layer opposite to the semiconductor substrate side; A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate side; A gate insulating film that is in contact with the second semiconductor layer; The first gate electrode is disposed on the surface of the gate insulating film opposite to the surface that contacts the second semiconductor layer; An interlayer insulating film is disposed on the first gate electrode; The first electrode, which is disposed on the surface of the second semiconductor layer and the first semiconductor region in such a way as to cover the interlayer insulating film, is a multilayer film formed by sequentially stacking a NiSi electrode, a first TiN film, a first Ti film, a second TiN film, a second Ti film and an Al alloy film; A first coating is selectively applied to the first electrode; as well as The second electrode is disposed on the back side of the semiconductor substrate. The gate ring region has: The semiconductor substrate; The first semiconductor layer; The second semiconductor layer; A first insulating film is in contact with the second semiconductor layer; The second gate electrode is disposed on the surface of the first insulating film opposite to the surface that contacts the second semiconductor layer; as well as A gate wiring electrode is disposed on the second gate electrode. The source ring region has: The semiconductor substrate; The first semiconductor layer; The second semiconductor layer; The second first electrode is disposed on the surface of the second semiconductor layer; as well as The second coating is disposed on the second first electrode. A first solder is disposed on the first coating. A first electrode pin is provided on the first solder. A second solder is disposed on the second coating. A second electrode pin is provided on the second solder. The semiconductor device is provided with a second short-circuit electrode that electrically connects the first electrode pin to the second electrode pin.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The area of ​​the portion where the second first electrode contacts the surface of the second semiconductor layer is more than twice the area of ​​the portion where the first first electrode contacts the surface of the second semiconductor layer and the first semiconductor region.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The active region is rectangular in shape. At the corner of the source ring region surrounding the active region and the gate ring region, the width of the second first electrode is wider than the width of the straight portion of the second first electrode.

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