A dynamically reconfigurable intelligent microsystem based on system-level package

Abstract

The present invention discloses a dynamically reconfigurable intelligent microsystem based on system-level packaging, comprising: a processor unit, a programmable unit, a first memory and a second memory; wherein the processor unit comprises a low-speed communication interface, a high-speed communication interface, a DDR interface, a ROM interface, an SRAM interface, a general IO module and an IO space; the programmable unit comprises a configuration interface, a programmable logic resource, a high-speed transceiver interface, a programmable IO interface and an optional configuration interface. The present invention meets the urgent needs of aerospace equipment for miniaturization, low power consumption and intelligence of electronic systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of dynamically reconfigurable intelligent microsystem hardware platform based on system-level packaging, and in particular relates to a dynamically reconfigurable intelligent microsystem based on system-level packaging. Background Art

[0002] With the development of aerospace equipment systems, the functional complexity of aerospace electronic systems has gradually increased, and the space inside aerospace equipment is limited, which makes it increasingly difficult to control circuit size. Traditional electronic systems can no longer meet the development needs of future aerospace equipment. Integration is a key technology to cope with miniaturization, lightweight, high reliability and high functional density. However, current semiconductor process technology has reached its physical limit, and the microelectronics industry has entered the post-Moore era. In addition, when aerospace electronic systems are working, they cannot physically contact these devices, but the problems they may encounter are uncertain, which requires them to be reconstructed to meet the specific requirements of new problems. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a dynamically reconfigurable intelligent microsystem based on system-level packaging, to establish a heterogeneous reconfigurable intelligent microsystem of processors, programmable units and memory units based on the ideas of function integration, system integration and hardware integration; to integrate the processor unit, programmable unit and memory unit into one through the system packaging process; to introduce a wealth of peripheral interfaces, configuration interfaces, debugging interfaces, expansion interfaces and high-speed communication interfaces, to realize the functions of hardware reconstruction, system control, intelligent computing and high-speed communication of the electronic system, and to meet the urgent needs of aerospace equipment for miniaturization, low power consumption and intelligence of electronic systems.

[0004] The object of the present invention is achieved through the following technical solutions: a dynamically reconfigurable intelligent microsystem based on system-level packaging, comprising: a processor unit, a programmable unit, a first memory and a second memory; wherein the processor unit comprises a low-speed communication interface, a high-speed communication interface, a DDR interface, a ROM interface, an SRAM interface, a general IO module and an IO space; the programmable unit comprises a configuration interface, a programmable logic resource, a high-speed transceiver interface, a programmable IO interface and an optional configuration interface; wherein the low-speed communication interface and the high-speed communication interface of the processor unit communicate with external modules respectively; the processor unit stores signal streams through the DDR interface and the ROM interface to achieve the expansion of data and program storage capacity; the ROM interface of the processor unit is interconnected with the first memory to achieve data interaction; the SRAM interface of the processor unit is interconnected with the second memory to achieve data interaction; the general IO module of the processor unit is connected to the configuration interface of the programmable unit, and the processor unit completes the configuration of the programmable unit through the configuration signal flow; the IO space of the processor unit is connected to the programmable logic resource to interact with the data signal flow; the high-speed transceiver interface of the programmable unit performs high-speed data communication with the outside world.

[0005] The above-mentioned dynamically reconfigurable intelligent microsystem based on system-level packaging also includes: a special-shaped multi-layer substrate and a packaging body; wherein the programmable unit is arranged on the top layer of the special-shaped multi-layer substrate by a flip-chip welding process, and the programmable unit is electrically connected to the special-shaped multi-layer substrate; the processor unit is arranged in the bottom cavity of the special-shaped multi-layer substrate, and the processor unit is electrically connected to the special-shaped multi-layer substrate through a wire bonding process; the first memory and the second memory are both arranged in the bottom cavity of the special-shaped multi-layer substrate, and the first memory and the second memory are electrically connected to the special-shaped multi-layer substrate through a gold wire bonding process; wherein the first memory and the second memory are stacked and arranged; the packaging body packages the processor unit, the programmable unit, the memory unit and the special-shaped multi-layer substrate together.

[0006] The above-mentioned dynamically reconfigurable intelligent microsystem based on system-level packaging also includes: a heat sink and a heat sink; wherein the heat sink is attached to the top layer of the package body to dissipate heat for the programmable unit; and the heat sink is attached to the bottom layer of the package body.

[0007] In the above-mentioned dynamically reconfigurable intelligent microsystem based on system-level packaging, the processor unit includes a processor circuit, a first pull-up resistor R1, a second pull-up resistor R2, a third pull-up resistor R3, a first pull-down resistor R4 and a second pull-down resistor R5; wherein, the positive end of the first pull-up resistor R1 is connected to a power supply, and the negative end of the first pull-up resistor R1 is connected to the TMS port of the processor circuit; the positive end of the second pull-up resistor R2 is connected to the power supply, and the negative end of the second pull-up resistor R2 is connected to the TDI port of the processor circuit; the positive end of the third pull-up resistor R3 is connected to the power supply, and the negative end of the third pull-up resistor R3 is connected to the resetn port of the processor circuit; the positive end of the first pull-down resistor R4 is connected to the TRST port of the processor circuit, and the negative end of the first pull-down resistor R4 is grounded; the positive end of the second pull-down resistor R5 is connected to the TCK port of the processor circuit, and the negative end of the second pull-down resistor R5 is grounded.

[0008] In the above-mentioned dynamically reconfigurable intelligent microsystem based on system-level packaging, the programmable unit includes a field programmable gate array circuit, a fourth pull-up resistor R6, a fifth pull-up resistor R7, a sixth pull-up resistor R8, a seventh pull-up resistor R9 and a third pull-down resistor R10; wherein, the positive end of the fourth pull-up resistor R6 is connected to the power supply, and the negative end of the fourth pull-up resistor R6 is connected to the HSWAPEN_0 port of the field programmable gate array circuit; the positive end of the fifth pull-up resistor R7 is connected to the power supply, and the negative end of the fifth pull-up resistor R7 is connected to the PROGRAM_B port of the field programmable gate array circuit; the positive end of the sixth pull-up resistor R8 is connected to the power supply, and the negative end of the sixth pull-up resistor R8 is connected to the M1 port of the field programmable gate array circuit; the positive end of the seventh pull-up resistor R9 is connected to the power supply, and the negative end of the seventh pull-up resistor R9 is connected to the M2 port of the field programmable gate array circuit; the positive end of the third pull-down resistor R10 is connected to the M0 port of the field programmable gate array circuit, and the negative end of the third pull-down resistor R10 is grounded.

[0009] Compared with the prior art, the present invention has the following beneficial effects:

[0010] (1) The dynamically reconfigurable microsystem designed by the present invention uses system-level packaging technology to reduce the original single-board level or small stand-alone system-level integrated electronic system to the size of a traditional chip, greatly improving the computing weight ratio and computing volume ratio of the electronic system.

[0011] (2) The dynamically reconfigurable microsystem designed by the present invention adopts a heterogeneous multi-layer substrate structure, which realizes the three-dimensional integration of the microsystem, greatly reduces the signal length and the area of ​​the package, and greatly improves the system integration.

[0012] (3) The dynamically reconfigurable microsystem designed by the present invention includes high-performance processing units and rich logic units, which can realize on-orbit reconstruction functions and have the capabilities of high-speed image information processing, adaptive situational awareness, dynamic control, and large-scale data throughput communication.

[0013] (4) The dynamically reconfigurable microsystem designed by the present invention connects a large number of key signals on the substrate and reduces the number of signal leads, which greatly reduces the difficulty of hardware design for users. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0015] Figure 1 is a structural block diagram of a dynamically reconfigurable intelligent microsystem based on system-level packaging provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a physical packaging structure provided by an embodiment of the present invention;

[0017] Figure 3 is a circuit diagram of a processor unit provided by an embodiment of the present invention;

[0018] Figure 4 It is a circuit diagram of a programmable unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] Figure 1 is a structural block diagram of a dynamically reconfigurable intelligent microsystem based on system-level packaging provided by an embodiment of the present invention. Figure 1 As shown, the dynamically reconfigurable intelligent microsystem based on system-level packaging includes: a processor unit, a programmable unit, a first memory and a second memory; wherein the processor unit includes a low-speed communication interface, a high-speed communication interface, a DDR interface, a ROM interface, an SRAM interface, a general IO module and an IO space; the programmable unit includes a configuration interface, a programmable logic resource, a high-speed transceiver interface, a programmable IO interface and an optional configuration interface.

[0021] The processor unit communicates with other modules bidirectionally through the low-speed communication interface and the high-speed communication interface; the expansion of data and program storage capacity is achieved through the storage signal flow through the DDR interface and the ROM interface; the ROM interface is also interconnected with the memory 1 inside the intelligent microsystem to achieve data interaction; the SRAM interface is interconnected with the memory 2 inside the intelligent microsystem to achieve data interaction; the general IO module is connected to the configuration interface of the programmable unit, and the processor unit configures the programmable unit through the configuration signal flow; the IO space is connected to some programmable logic resources to interact with the data signal flow; in addition, the processor unit and the programmable unit are also interconnected through the SPI interface to achieve the processor's control of the programmable unit. The programmable unit leads to a high-speed transceiver interface for high-speed data communication with the outside world; leads to a programmable IO interface to achieve the expansion of the intelligent microsystem function; leads to an optional configuration interface to provide developers with a variety of configuration methods for the programmable unit.

[0022] The dynamically reconfigurable intelligent microsystem based on system-level packaging is composed of a heterogeneous core architecture consisting of a processor unit, a programmable unit and a memory unit. The high-performance processor unit is responsible for completing task allocation, system control, fault handling and communication functions; the programmable unit is responsible for completing high-performance computing and large-capacity data processing functions. The memory is responsible for completing data and program storage functions. The processing unit and the programmable unit are interconnected with other interfaces through the configuration interface to realize reconfigurable configuration, data interaction and low-speed communication functions; the processing unit and the programmable unit are interconnected with the memory through the bus to realize data storage and program configuration functions.

[0023] Figure 2 Schematic diagram of the physical packaging structure provided by the embodiment of the present invention. Figure 2 As shown, the dynamically reconfigurable intelligent microsystem based on system-level packaging also includes: a special-shaped multi-layer substrate, a packaging body, a heat sink and a heat sink.

[0024] The programmable unit is arranged on the top layer of the heterogeneous multi-layer substrate by a flip-chip process, and the programmable unit is electrically connected to the heterogeneous multi-layer substrate; the processor unit is arranged in the bottom cavity of the heterogeneous multi-layer substrate, and the processor unit is electrically connected to the heterogeneous multi-layer substrate by a wire bonding process; the first memory and the second memory are both arranged in the bottom cavity of the heterogeneous multi-layer substrate, and the first memory and the second memory are electrically connected to the heterogeneous multi-layer substrate by a gold wire bonding process; wherein the first memory and the second memory are stacked and arranged; the package encapsulates the processor unit, the programmable unit, the memory unit and the heterogeneous multi-layer substrate together.

[0025] A heat sink is attached to the top layer of the package body to dissipate heat for the programmable unit; a heat sink is attached to the bottom layer of the package body to dissipate heat for each unit in the lower cavity of the special-shaped multi-layer substrate.

[0026] like Figure 3 As shown, the processor unit includes a processor circuit, a first pull-up resistor R1, a second pull-up resistor R2, a third pull-up resistor R3, a first pull-down resistor R4 and a second pull-down resistor R5; wherein,

[0027] The positive end of the first pull-up resistor R1 is connected to the power supply, and the negative end of the first pull-up resistor R1 is connected to the TMS port of the processor circuit; the positive end of the second pull-up resistor R2 is connected to the power supply, and the negative end of the second pull-up resistor R2 is connected to the TDI port of the processor circuit; the positive end of the third pull-up resistor R3 is connected to the power supply, and the negative end of the third pull-up resistor R3 is connected to the resetn port of the processor circuit; the positive end of the first pull-down resistor R4 is connected to the TRST port of the processor circuit, and the negative end of the first pull-down resistor R4 is grounded; the positive end of the second pull-down resistor R5 is connected to the TCK port of the processor circuit, and the negative end of the second pull-down resistor R5 is grounded.

[0028] like Figure 4 As shown, the programmable unit includes a field programmable gate array circuit, a fourth pull-up resistor R6, a fifth pull-up resistor R7, a sixth pull-up resistor R8, a seventh pull-up resistor R9 and a third pull-down resistor R10; wherein,

[0029] The positive end of the fourth pull-up resistor R6 is connected to the power supply, and the negative end of the fourth pull-up resistor R6 is connected to the HSWAPEN_0 port of the field programmable gate array circuit; the positive end of the fifth pull-up resistor R7 is connected to the power supply, and the negative end of the fifth pull-up resistor R7 is connected to the PROGRAM_B port of the field programmable gate array circuit; the positive end of the sixth pull-up resistor R8 is connected to the power supply, and the negative end of the sixth pull-up resistor R8 is connected to the M1 port of the field programmable gate array circuit; the positive end of the seventh pull-up resistor R9 is connected to the power supply, and the negative end of the seventh pull-up resistor R9 is connected to the M2 port of the field programmable gate array circuit; the positive end of the third pull-down resistor R10 is connected to the M0 port of the field programmable gate array circuit, and the negative end of the third pull-down resistor R10 is grounded.

[0030] The processor unit uses a SPARC V8 architecture high-performance processor with a maximum operating frequency of 300MHz; the programmable unit uses a 9.5 million gate FPGA with a maximum operating frequency of 500MHz; the memory unit consists of a 16Mb asynchronous SRAM, a 256MbNor type FLASH and a 16GB Nand type FLASH, and both the 16Mb asynchronous SRAM and the 256MbNor type FLASH support the EDAC function.

[0031] The processor and FPGA are connected through the SelectMap interface and the low-speed communication interface; the 16Mb asynchronous SRAM and 256Mb Nor-type FLASH are connected to the processor through the data bus / address bus / control line; the 16GB Nand-type FLASH is connected to the FPGA through the data bus / address bus / control line. The processor configures the FPGA through the SelectMap interface to achieve dynamic reconfiguration of the microsystem.

[0032] The processor, SRAM, Nor-type FLASH and Nand-type FLASH are all electrically connected to the substrate using wire bonding technology, and the FPGA is electrically connected to the substrate using flip-chip bonding technology. The microsystem is packaged with composite materials. Finally, the top of the plastic package is thinned and a heat sink is attached. The appearance structure is as follows: Figure 2 shown.

[0033] The dynamically reconfigurable microsystem designed by the present invention adopts system-level packaging technology, which reduces the original single-board level or small stand-alone system-level integrated electronic system to the size of a traditional chip, greatly improving the computing weight ratio and computing volume ratio of the electronic system; the dynamically reconfigurable microsystem designed by the present invention adopts a special-shaped multi-layer substrate structure, realizes the three-dimensional integration of the microsystem, greatly reduces the signal length and the area of ​​the package, and greatly improves the system integration; the dynamically reconfigurable microsystem designed by the present invention includes a high-performance processing unit and a rich logic unit, can realize the on-orbit reconstruction function, and has the capabilities of high-speed image information processing, adaptive situational awareness, dynamic control, large data throughput communication, etc.; the dynamically reconfigurable microsystem designed by the present invention connects a large number of key signals on the substrate, and streamlines the number of signal lead-outs, which greatly reduces the user's hardware design difficulty.

[0034] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A dynamically reconfigurable intelligent microsystem based on system-level packaging, characterized in that include: A processor unit, a programmable unit, a first memory and a second memory; wherein, The processor unit includes a low-speed communication interface, a high-speed communication interface, a DDR interface, a ROM interface, an SRAM interface, a general IO module and an IO space; The programmable unit includes a configuration interface, a programmable logic resource, a high-speed transceiver interface, a programmable IO interface and an optional configuration interface; wherein, The low-speed communication interface and the high-speed communication interface of the processor unit communicate with the external module respectively; The processor unit stores signal streams through the DDR interface and the ROM interface to achieve expansion of data and program storage capacity; The ROM interface of the processor unit is interconnected with the first memory to realize data interaction; The SRAM interface of the processor unit is interconnected with the second memory to realize data interaction; The general IO module of the processor unit is connected to the configuration interface of the programmable unit, and the processor unit configures the programmable unit through the configuration signal flow; The IO space of the processor unit is connected to the programmable logic resources to interact with the data signal flow; The high-speed transceiver interface of the programmable unit communicates high-speed data with the outside world; It also includes: a special-shaped multi-layer substrate and a package; wherein, The programmable unit is arranged on the top layer of the special-shaped multi-layer substrate by using a flip-chip bonding process, and the programmable unit is electrically connected to the special-shaped multi-layer substrate; The processor unit is disposed in a bottom cavity of the special-shaped multi-layer substrate, and the processor unit is electrically connected to the special-shaped multi-layer substrate through a wire bonding process; The first memory and the second memory are both disposed in a bottom cavity of the special-shaped multi-layer substrate, and the first memory and the second memory are both electrically connected to the special-shaped multi-layer substrate through a gold wire bonding process; wherein the first memory and the second memory are stacked; The packaging body packages the processor unit, the programmable unit, the memory unit and the special-shaped multi-layer substrate together; Also includes: a heat sink and a heat sink; wherein, A heat sink is pasted on the top layer of the package body to dissipate heat for the programmable unit; and a heat sink is pasted on the bottom layer of the package body.

2. The dynamically reconfigurable intelligent microsystem based on system-level packaging according to claim 1, characterized in that: The processor unit includes a processor circuit, a first pull-up resistor R1, a second pull-up resistor R2, a third pull-up resistor R3, a first pull-down resistor R4 and a second pull-down resistor R5; wherein, The positive end of the first pull-up resistor R1 is connected to the power supply, and the negative end of the first pull-up resistor R1 is connected to the TMS port of the processor circuit; the positive end of the second pull-up resistor R2 is connected to the power supply, and the negative end of the second pull-up resistor R2 is connected to the TDI port of the processor circuit; the positive end of the third pull-up resistor R3 is connected to the power supply, and the negative end of the third pull-up resistor R3 is connected to the resetn port of the processor circuit; the positive end of the first pull-down resistor R4 is connected to the TRST port of the processor circuit, and the negative end of the first pull-down resistor R4 is grounded; the positive end of the second pull-down resistor R5 is connected to the TCK port of the processor circuit, and the negative end of the second pull-down resistor R5 is grounded.

3. The dynamically reconfigurable intelligent microsystem based on system-level packaging according to claim 1, characterized in that: The programmable unit includes a field programmable gate array circuit, a fourth pull-up resistor R6, a fifth pull-up resistor R7, a sixth pull-up resistor R8, a seventh pull-up resistor R9 and a third pull-down resistor R10; wherein, The positive end of the fourth pull-up resistor R6 is connected to the power supply, and the negative end of the fourth pull-up resistor R6 is connected to the HSWAPEN_0 port of the field programmable gate array circuit; the positive end of the fifth pull-up resistor R7 is connected to the power supply, and the negative end of the fifth pull-up resistor R7 is connected to the PROGRAM_B port of the field programmable gate array circuit; the positive end of the sixth pull-up resistor R8 is connected to the power supply, and the negative end of the sixth pull-up resistor R8 is connected to the M1 port of the field programmable gate array circuit; the positive end of the seventh pull-up resistor R9 is connected to the power supply, and the negative end of the seventh pull-up resistor R9 is connected to the M2 port of the field programmable gate array circuit; the positive end of the third pull-down resistor R10 is connected to the M0 port of the field programmable gate array circuit, and the negative end of the third pull-down resistor R10 is grounded.

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