Package and method of forming the same

Abstract

An embodiment of the present application provides a method of forming a package, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in the plurality of dielectric layers; forming stacked vias in the plurality of dielectric layers, wherein the stacked vias form a continuous electrical connection through the plurality of dielectric layers; forming a dielectric layer over the stacked vias and the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer; and bonding a device die to the dielectric layer and a first portion of the plurality of bonding pads by hybrid bonding. An embodiment of the present application also provides another method of forming a package and a package.

Description

[0001] This application is a divisional application of the patent application entitled “Package and method for forming the same” filed on December 6, 2017 and with patent application number 201711279542.7. Technical Field

[0002] Embodiments of the present application relate to the field of semiconductors, and more particularly, to packages and methods of forming the same. Background Art

[0003] Integrated circuit packages are becoming increasingly complex, with more device dies packaged in the same package to achieve more functionality. For example, a package may include multiple device dies, such as a processor and a memory cube bonded to the same interposer. An interposer may be formed based on a semiconductor substrate, wherein through silicon vias are formed in the semiconductor substrate to interconnect components formed on opposite sides of the interposer. A molding compound encapsulates the device dies therein. The package including the interposer and the device dies are further bonded to a package substrate. In addition, surface mount devices may also be bonded to the substrate. A heat sink may be attached to the top surface of the device die to dissipate heat generated in the device die. The heat sink may have a skirt fixed to the package substrate. Summary of the invention

[0004] According to an embodiment of the present application, a method for forming a package is provided, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in the plurality of dielectric layers; forming stacked vias in the plurality of dielectric layers, wherein the stacked vias form a continuous electrical connection extending through the plurality of dielectric layers; forming a dielectric layer above the stacked vias and the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer; and bonding a first device die to the dielectric layer and a first portion of the plurality of bonding pads by hybrid bonding.

[0005] According to an embodiment of the present application, a method for forming a package is provided, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in each of the plurality of dielectric layers; forming passive devices in the plurality of dielectric layers; forming a first dielectric through-hole and a second dielectric through-hole penetrating the plurality of dielectric layers; forming a dielectric layer above the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer and electrically coupled to the first dielectric through-hole, the second dielectric through-hole, and the plurality of redistribution lines; and bonding a first device die and a second device die to the dielectric layer and the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically interconnected by the plurality of redistribution lines, and the first device die and the second device die are respectively connected to the first dielectric through-hole and the second dielectric through-hole.

[0006] According to an embodiment of the present application, a package is provided, comprising: a plurality of dielectric layers; a plurality of redistribution lines in each of the plurality of dielectric layers; dielectric through-holes extending through the plurality of dielectric layers, wherein the dielectric through-holes have substantially straight edges extending through the plurality of dielectric layers; stacked through-holes in the plurality of dielectric layers, wherein the stacked through-holes are electrically connected to each other to form a continuous electrical connection extending through the plurality of dielectric layers; a plurality of bonding pads above the dielectric through-holes and the plurality of redistribution lines and connected to the dielectric through-holes and the plurality of redistribution lines; a first dielectric layer, wherein the plurality of bonding pads are located in the first dielectric layer; and a first device die bonded to the first dielectric layer and a first portion of the plurality of bonding pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 27A A cross-sectional view illustrating an intermediate stage in the formation of a silicon-free substrate (Si-free) package in accordance with some embodiments.

[0009] Fig.27B , Fig.27C , Fig.27D ,and Fig.27E A cross-sectional view of a Si-free package is shown in accordance with some embodiments.

[0010] Figure 28 to Figure 32 A cross-sectional view illustrating an intermediate stage in the formation of a Si-free package in accordance with some embodiments.

[0011] Figure 33 to Figure 35 A cross-sectional view illustrating an intermediate stage in the formation of a Si-free package in accordance with some embodiments.

[0012] Fig.36 and Fig.37 A cross-sectional view of a package embedding a Si-free package is shown in accordance with some embodiments.

[0013] Fig.38 Some top views of self-aligned metal pads used in Si-free packages are shown in accordance with some embodiments.

[0014] Fig.39 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative position terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] According to various exemplary embodiments, a package formed based on a silicon-free substrate (Si-free) interposer and a method for forming the same are provided. According to some embodiments, intermediate stages of forming a package are shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements.

[0018] Figures 1 to 27A A cross-sectional view illustrating an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. Figures 1 to 27A The steps shown in Fig.39 The process flow 300 shown in FIG.

[0019] Figure 1A carrier 20 and a release layer 22 formed on the carrier 20 are shown. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, or the like. The carrier 20 may have a circular top view shape and may have the size of a commonly used silicon wafer. For example, the carrier 20 may have a diameter of 8 inches, a diameter of 12 inches, or the like. The release layer 22 may be formed of a light-to-heat conversion (LTHC) material, which may be removed from the upper structure to be formed in a subsequent step together with the carrier 20. According to some embodiments of the present disclosure, the release layer 22 is formed of an epoxy-based thermal release material. The release layer 22 may be coated onto the carrier 20. The top surface of the release layer 22 is flat and has a high degree of coplanarity. According to an optional embodiment, instead of using the carrier 20 and the release layer 22, a silicon wafer marked as 23 is used. A dielectric layer 24 is formed on the release layer 22. According to some embodiments of the present disclosure, the dielectric layer 24 is formed of a non-polymer (inorganic material) that may be silicon oxide, silicon nitride, silicon oxynitride, or the like. When a silicon wafer is used, layer 24 may be formed directly on silicon wafer 23 .

[0020] Redistribution lines (RDL) 26 are formed on dielectric layer 24. The formation of RDL 26 may include forming a seed layer (not shown) over dielectric layer 24, forming a patterned mask (not shown) such as a photoresist over the seed layer, and then performing metal electroplating on the exposed seed layer. The patterned mask and the portion of the seed layer covered by the patterned mask are then removed, leaving a portion such as Figure 1 According to some embodiments of the present disclosure, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). The electroplating may be performed using, for example, chemical plating.

[0021] Further references Figure 1 , a dielectric layer 28 is formed on the RDL 26. The bottom surface of the dielectric layer 28 contacts the top surface of the RDL 26 and the dielectric layer 24. According to some embodiments of the present disclosure, the dielectric layer 28 is formed of a non-polymer (inorganic material) that may be silicon oxide, silicon nitride, etc. According to some embodiments of the present invention, the dielectric layer 28 is formed of a polymer that may be polyimide, polybenzoxazole (PBO), etc. Then, the dielectric layer 28 is patterned to form an opening 30 therein. Therefore, some portions of the RDL 26 are exposed through the opening 30 in the dielectric layer 28.

[0022] Next, refer to Figure 2, RDL 32 is formed to connect to RDL 26. RDL 32 includes metal traces (metal lines) above dielectric layer 28. RDL 32 also includes vias extending into openings in dielectric layer 28. RDL 32 is also formed in an electroplating process, wherein each of RDL 32 includes a seed layer (not shown) and an electroplated metal material above the seed layer. The seed layer and the electroplated material may be formed of the same material or different materials. RDL 32 may include a metal or a metal alloy, including aluminum, copper, tungsten, or alloys thereof. The steps for forming dielectric layer 28 and dielectric layer 34 and RDL 32 and RDL 36 are represented as follows. Fig.39 Step 302 in process flow 300 is shown.

[0023] refer to Figure 3 , a dielectric layer 34 is formed over the RDL 32 and the dielectric layer 28. The dielectric layer 34 may be formed of an inorganic material, and the inorganic material may be selected from silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and the like.

[0024] Figure 3 Also shown is the formation of RDL 36 electrically connected to RDL 32. The formation of RDL 36 may employ methods and materials similar to those used to form RDL 32. It is understood that although two dielectric layers 28 and 34 and respective RDL 32 and RDL 36 formed therein are discussed in the illustrative exemplary embodiment, fewer or more dielectric layers may be employed depending on the wiring requirements and the requirements of using a polymer for buffering stress. For example, there may be a single dielectric layer or three, four, or more dielectric layers.

[0025] Figure 4 The formation of passivation layer 38 and passivation layer 42 and RDL 40 and RDL 44 are shown. The corresponding steps are shown as Fig.39 . According to some embodiments of the present disclosure, the passivation layer 38 and the passivation layer 42 are formed of an inorganic material such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, undoped silicate glass (USG), or a multilayer thereof. Each of the passivation layer 38 and the passivation layer 42 may be a single layer or a composite layer and may be formed of a non-porous material. According to some embodiments of the present disclosure, one or both of the passivation layer 38 and the passivation layer 42 is a composite layer including a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) above the silicon oxide layer. The passivation layer 38 and the passivation layer 42 have the function of blocking moisture and harmful chemicals from entering the conductive features such as fine-pitch RDL in the package, as will be discussed in subsequent paragraphs.

[0026] RDL 40 and RDL 44 may be formed of aluminum, copper, aluminum-copper, nickel, or alloys thereof. According to some embodiments of the present disclosure, some portions of RDL 44 are formed as metal pads large enough to attach subsequently formed through dielectric vias (TDVs), such as Fig.11 Therefore, according to some embodiments, these metal pads are referred to as metal pads 44 or aluminum pads 44. In addition, the number of passivation layers can be any integer such as one, two (as shown), three or more.

[0027] Figure 5 The formation of one or more dielectric layers is shown. For example, as shown, a dielectric layer 46 can be formed to embed the top RDL 44 therein. A dielectric layer 48 is formed over the dielectric layer 46, and the dielectric layer 48 can be used as an etch stop layer. According to some embodiments of the present disclosure, the dielectric layer 46 and the dielectric layer 48 can also be replaced with a single dielectric layer. Available materials for the dielectric layer 46 and the dielectric layer 48 include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc.

[0028] Figure 6 , Figure 7 ,and Figure 8 The formation of dielectric layers and fine pitch RDL according to some embodiments of the present disclosure is shown. The corresponding steps are shown as Fig.39 306 in the process flow 300 shown in FIG. The formation method may adopt a method for forming an interconnect structure of a device die based on a silicon substrate. For example, the formation method of the interconnect structure may include a single damascene and / or a dual damascene process. Therefore, the resulting RDL may also be optionally referred to as a metal line and a via, and the corresponding dielectric layer may be optionally referred to as an intermetallic dielectric (IMD) layer.

[0029] refer to Figure 6 , forming a through hole 55, a dielectric layer 50A and a dielectric layer 54A, and an etch stop layer 52A. The dielectric layer 50A and the dielectric layer 54A may be formed of silicon oxide, silicon oxynitride, silicon nitride, etc., or a low-k dielectric material having a k value lower than about 3.0. The low-k dielectric material may include Black Diamond (a registered trademark of Applied Materials, Inc.), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The etch stop layer 52A is formed of a material having a higher etch selectivity relative to the dielectric layer 50A and the dielectric layer 54A, and may be formed of silicon carbide, silicon carbonitride, etc. According to an optional embodiment, the etch stop layer 52A is not formed.

[0030] A micro-pitch RDL 56A is formed in the dielectric layer 52A and the dielectric layer 54A for wiring. Although in some exemplary embodiments, the via 55 and the micro-pitch RDL 56A are shown as having a single damascene structure, the via 55 and the micro-pitch RDL 56A combination may have a dual damascene structure. It is understood that the single micro-pitch RDL 56A shown represents a plurality of micro-pitch RDLs. Since the micro-pitch RDL is formed using a damascene process according to some embodiments of the present disclosure, it can be formed very thinly with a pitch of less than, for example, 0.8 μm (from the top of the structure). In addition, since the dielectric layer 34, the dielectric layer 38, the dielectric layer 42, the dielectric layer 46, and the dielectric layer 48 can all be formed of inorganic materials, the pitch and width of the micro-pitch RDL can be smaller. If the dielectric layer 28 is also formed of an inorganic material, the pitch and width of the micro-pitch RDL can be further reduced, so that there is no polymer layer under the dual damascene structure. This significantly improves the density and wiring capability of the micro-pitch RDL. According to some embodiments of the present disclosure in which via 55 and fine pitch RDL 56A are formed using a dual damascene process, the formation process includes etching dielectric layer 48 and dielectric layer 50A to form a via opening and etching dielectric layer 50A and dielectric layer 52A to form a trench, filling the via opening and the trench with a conductive material, and performing planarization such as chemical mechanical polishing (CMP) or mechanical grinding to remove portions of the conductive material above the dielectric layer.

[0031] According to some embodiments of the present disclosure, the conductive material used to form the through hole 55 and the micro-pitch RDL 56A is a homogeneous material. According to other embodiments of the present disclosure, the conductive material is a composite material including a barrier layer formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and a copper-containing material (which may be copper or a copper alloy) above the barrier layer.

[0032] Figure 7 The formation of dielectric layers 50B and 54B and etch stop layer 52B is shown. The materials of dielectric layers 50B and 54B can be selected from the same candidate materials used to form dielectric layers 50A and 54A, and the material of etch stop layer 52B can be selected from the same candidate materials used to form etch stop layer 52A.

[0033] A fine pitch RDL 56B is also formed in dielectric layer 50B, dielectric layer 52B, and dielectric layer 54B. Fine pitch RDL 56B includes metal lines formed in dielectric layer 54B and dielectric layer 52B and vias in dielectric layer 50B. The formation may include a dual damascene process, which includes forming trenches in dielectric layer 54B and dielectric layer 52B and forming via openings in dielectric layer 50B, filling with conductive materials, and then performing planarization such as mechanical grinding or chemical mechanical polishing (CMP). Similarly, fine pitch RDL 56B may be formed of a homogeneous material, or may be formed of a composite material including a barrier layer and a copper-containing material over the barrier layer.

[0034] Figure 8 The formation of dielectric layer 50C and dielectric layer 54C, etch stop layer 52C, and micro-pitch RDL 56C is shown. The formation method and material may be similar to the corresponding layer below, and therefore are not repeated here. In addition, according to some embodiments of the present disclosure, etch stop layer 52A, etch stop layer 52B, and etch stop layer 52C may be omitted, and a time mode may be used to perform the corresponding etching for forming the groove to control the depth of the groove. It is understood that more dielectric layers and micro-pitch RDL layers may be formed. In addition, even if some or all of etch stop layer 52A, etch stop layer 52B, and etch stop layer 52C may be skipped, since the dielectric layer in which the micro-pitch RDL is present is formed in different processes, a distinguishable interface between dielectric layers for forming micro-pitch RDL 56A, micro-pitch RDL 56B, and micro-pitch RDL 56C may be provided, regardless of whether the dielectric layers are formed of the same dielectric material or different dielectric materials. In the following paragraphs, for ease of identification, dielectric layer 50A, dielectric layer 52A, dielectric layer 54A, dielectric layer 50B, dielectric layer 52B, dielectric layer 54B, dielectric layer 50C, dielectric layer 52C, and dielectric layer 54C are collectively and individually referred to as dielectric layer 58. Fine pitch RDL 56A, fine pitch RDL 56B, and fine pitch RDL 56C are also collectively and individually referred to as fine pitch RDL 56.

[0035] According to some embodiments of the present disclosure, passive device 61 is formed while forming fine pitch RDL 56. Therefore, passive device 61 is embedded in dielectric layer 58. Passive device 61 may be a capacitor, an inductor, a radio frequency (RF) transmission line, a transformer, or a combination of these devices. Passive device 61 is electrically coupled to a subsequently bonded device die.

[0036] In addition, while forming the fine pitch RDL 56, stacked vias 67 are also formed, each stacked via 67 including a plurality of dual damascene structures (and may or may not include a single damascene structure) stacked to form a connection structure that penetrates the dielectric layer 58. The combined stacked vias 67 have the same Fig.10 The through dielectric via (TDV) 62 shown has a similar function. Forming stacked vias is advantageous because they are formed using a dual damascene process and can have widths as small as metal lines in a dual damascene structure.

[0037] Stacked vias 67 can also be used for routing. For example, portion 56D in RDL 56 is schematically shown to show that for routing purposes, metal lines can be formed simultaneously as stacked vias 67. Thus, stacked vias 67 can be laterally electrically connected to other electrical components. Routing metal lines can be formed in any metal layer of the micro-pitch RDL 56.

[0038] refer to Fig. 9 , dielectric layer 48 and dielectric layer 58 are etched to form through dielectric via (TDV) opening 60. The corresponding steps are shown as Fig.39 3. The process flow 300 shown in FIG. 308 is shown in FIG. 309. The metal pad 44 is exposed to the TDV opening 60. The top view shape of the via opening 60 may be rectangular, circular, hexagonal, etc.

[0039] Next, the TDV opening 60 is filled with a conductive material to form a TDV 62, and the resulting structure is as shown. Fig.10 The corresponding steps are shown as Fig.39 310 in the process flow 300 shown in FIG. According to some embodiments of the present disclosure, the TDV 62 is formed of a uniform conductive material, which may be a metal or a metal alloy, including copper, aluminum, tungsten, etc. According to an optional embodiment of the present disclosure, the TDV 62 has a composite structure including a conductive barrier layer formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and a metal-containing material above the barrier layer. According to some embodiments of the present disclosure, a dielectric isolation layer is formed to surround each TDV 62. According to an optional embodiment, a dielectric isolation layer is not formed surrounding the TDV 62, and the TDV 62 is in physical contact with the dielectric layer 58. The formation of the TDV 62 also includes depositing a conductive material into the TDV opening 60 ( Fig. 9 ), and planarization is performed to remove excess portions of the deposited material above the dielectric layer 58. Since it is difficult to form a deep opening 60 ( Fig. 9), TDV 62 may have a greater width than stacked via 67. TDV 62 has a lower resistance. Therefore, due to the small number of TDVs 62, TDV 62 can be used to conduct power, and the area occupied by TDV 62 is not significant. Combining stacked via 67 and TDV 62 can increase the number of signal connectors (using stacked via 67) while still being able to use wide TDV 62 to serve low-loss power transmission. According to some embodiments, TDV 62 is not formed.

[0040] Fig.11 The formation of the bonding pad 66 and the dielectric layer 64 is shown, and the bonding pad 66 is located in the dielectric layer 64. The corresponding steps are shown as Fig.39 3. Step 312 in process flow 300 shown in FIG. Bond pad 66 may be formed of a metal that is susceptible to forming a hybrid bond. According to some embodiments of the present disclosure, bond pad 66 is formed of copper or a copper alloy. For example, dielectric layer 64 may be formed of silicon oxide. The top surfaces of bond pad 66 and dielectric layer 64 are coplanar. For example, planarization may be achieved by a planarization step such as a CMP or mechanical grinding step.

[0041] According to some embodiments of the present disclosure, bonding pads 66 and dielectric layer 64 are not formed. Therefore, device die 68A and device die 68B are directly bonded to top RDL 56 (at Figure 8 56C) and possible dielectric layer 54C ( Figure 8 ).

[0042] Throughout the specification, the components above layer 22 (or silicon wafer 23) are collectively referred to as interposer 100. Unlike conventional interposers formed based on a silicon substrate, interposer 100 is formed based on dielectric layer 58. There is no silicon substrate in interposer 100, and therefore interposer 100 is referred to as a silicon-free substrate interposer or a Si-free interposer. Stacked vias 67 and TDVs 62 are formed in dielectric layer 58 to replace conventional through-silicon vias. Since the silicon substrate is semiconductive, it may have an adverse effect on the performance of the circuits and connections formed therein and thereon. For example, signal degradation may be caused by the silicon substrate, and since TDVs 62 and stacked vias 67 are formed in the dielectric layer, such degradation can be avoided in the embodiments of the present disclosure.

[0043] Next, if Fig.12 As shown, the first layer device die 68A and the first layer device die 68B are bonded to the interposer 100. The corresponding steps are shown as Fig.39. According to some embodiments of the present disclosure, device die 68A and device die 68B include a logic die that may be a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input-output (IO) die, a baseband (BB) die, or an application processor (AP) die. Device die 68A and device die 68B may also include a memory die. Device die 68A and device die 68B include a semiconductor substrate 70A and a semiconductor substrate 70B, respectively, which may be a silicon substrate. Through silicon vias (TSVs) 71A and through silicon vias (TSVs) 71B (sometimes referred to as semiconductor through vias or through vias) are formed to penetrate semiconductor substrate 70A and semiconductor substrate 70B, respectively, and are used to connect devices and metal lines formed on the front side (bottom side shown) of semiconductor substrate 70A and semiconductor substrate 70B to the back side. Additionally, device die 68A and device die 68B include interconnect structures 72A and 72B, respectively, for connecting to active and passive devices in device die 68A and device die 68B. Interconnect structures 72A and 72B include metal lines and vias (not shown).

[0044] Device die 68A includes bonding pad 74A and dielectric layer 76A at the illustrated bottom surface of device die 68A. The illustrated bottom surface of bonding pad 74A is coplanar with the illustrated bottom surface of dielectric layer 76A. Device die 68B includes bonding pad 74B and dielectric layer 76B at the illustrated bottom surface. The illustrated bottom surface of bonding pad 74B is coplanar with the illustrated bottom surface of dielectric layer 76B.

[0045] The bonding may be achieved by hybrid bonding. For example, bonding pad 74A and bonding pad 74B are bonded to bonding pad 66 by metal-to-metal direct bonding. According to some embodiments of the present disclosure, the metal-to-metal direct bonding is copper-to-copper direct bonding. In addition, dielectric layer 76A and dielectric layer 76B are bonded to dielectric layer 64, for example, by generated Si-O-Si bonds. Hybrid bonding may include pre-bonding and annealing so that the metal in bonding pad 74A (and 74B) interdiffuses the metal in the corresponding underlying bonding pad 66.

[0046] The micro-pitch RDL 56 electrically interconnects the bonding pad 74A and the bonding pad 74B, and is used for signal communication between the device die 68A and the device die 68B. The micro-pitch RDL 56 has a smaller pitch and a smaller width. Therefore, the density of the micro-pitch RDL 56 is higher, and therefore sufficient communication channels for direct communication between the device die 68A and the device die 68B can be formed. On the other hand, the TDV 62 and the stacked via 67 provide a direct connection from the device die 68A and the device die 68B to the component to be bonded to the interposer 100 (which may be a package substrate, a printed circuit board (PCB), etc.). In addition, the bonding between the bonding pad 74A / 74B and the bonding pad 66 is through the bonding pad, rather than through a solder joint that is usually much larger than the bonding pad. Accordingly, the lateral size of the key is smaller, and more keys can be implemented to provide sufficient communication channels.

[0047] Further references Fig.12 , back grinding is performed to thin device die 68A and device die 68B to a thickness of, for example, between about 15 μm and about 30 μm. The corresponding steps are shown as Fig.39 316 in process flow 300 shown in FIG. By thinning, the aspect ratio of gap 78 between adjacent device die 68A and device die 68B is reduced to perform gap filling. Otherwise, gap filling is difficult due to the high aspect ratio of opening 78. After back grinding, TSV 71A and TSV 71B can be exposed. Optionally, TSV 71A and TSV 71B are not exposed at this time. Instead, they can be Fig.17 TSV 71A and TSV 71B are exposed in the step shown.

[0048] Next, the gap 78 is filled with a gap filling material 80, such as Fig.13 The corresponding steps are shown as Fig.39 Step 318 in the process flow 300 shown in . According to some embodiments of the present disclosure, the gap filling material 80 includes an oxide such as silicon oxide, which can be formed using tetraethyl orthosilicate (TEOS). The formation method may include chemical vapor deposition (CVD), high density plasma chemical vapor deposition (HDPCVD), etc. According to an optional embodiment, the gap filling material 80 is formed of a polymer such as PBO, polyimide, etc. Then, a planarization step is performed to remove excess portions of the gap filling material 80, thereby exposing the substrate 70A and substrate 70B of the device die 68A and the device die 68B. The resulting structure is as shown in FIG. Fig.14 shown.

[0049] Fig.15The formation of TDV 162 is shown by etching through gap fill material 80 in an anisotropic etch step to form via openings and filling each opening with a conductive material. The corresponding steps are shown as Fig.39 3. Step 320 in process flow 300 shown in FIG. Some of bonding pads 66 are exposed to the through-hole opening, wherein the etching can be performed using bonding pads 66 as an etch stop layer. TDV 162 can have a structure similar to that of TDV 62 and can include a barrier layer and a metal material over the barrier layer. The material of TDV 162 can also be selected from similar candidate materials used to form TDV 62.

[0050] refer to Fig.16 , substrate 70A and substrate 70B are recessed to form groove 73, and the top ends of TSV 71A and TSV 71B protrude slightly above the top surfaces of substrate 70A and substrate 70B, respectively. The corresponding steps are shown as Fig.39 The process flow 300 shown in step 322 is then shown. Then, the recess 73 is filled with a dielectric material such as silicon oxide to form dielectric layers 75A and 75B, and the resulting structure is Fig.17 The corresponding steps are shown as Fig.39 The formation process includes a deposition process to deposit a blanket dielectric layer, and a planarization process to remove portions of the blanket dielectric layer above the tops of the TSVs 71A and 71B.

[0051] Next, if Fig.18 As shown, the second layer device die 168A and the second layer device die 168B are bonded to the device die 68A and the device die 68B. The corresponding steps are shown as Fig.39. According to some embodiments of the present disclosure, device die 168A and device die 168B include logic die, memory die, or a combination thereof. Device die 168A and device die 168B include semiconductor substrate 170A and semiconductor substrate 170B, respectively, and semiconductor substrate 170A and semiconductor substrate 170B may be semiconductor substrates such as silicon substrates. If there is a third layer of device die bonded above device die 168A and device die 168B, TSVs (not shown) may be formed in semiconductor substrate 170A and semiconductor substrate 170B. Optionally, TSVs are not formed in semiconductor substrate 170A and semiconductor substrate 170B. In addition, device die 168A and device die 168B include interconnect structures 172A and interconnect structures 172B, respectively, for connecting to active devices and passive devices in device die 168A and device die 168B. Interconnect structures 172A and 172B include metal lines and vias (not shown).

[0052] Device die 168A includes bonding pads 174A and dielectric layer 176A at the bottom surface of device die 168A as shown. The bottom surface of bonding pads 174A is shown to be coplanar with the bottom surface of dielectric layer 176A as shown. Device die 168B includes bonding pads 174B and dielectric layer 176B at the bottom surface as shown. The bottom surface of bonding pads 174B is shown to be coplanar with the bottom surface of dielectric layer 176B as shown.

[0053] The bonding can be achieved by hybrid bonding. For example, the bonding pad 174A and the bonding pad 174B are directly bonded to the TSV 71A and the TSV 71B by direct metal-to-metal bonding. According to some embodiments of the present disclosure, the direct metal-to-metal bonding is a direct copper-to-copper bonding. In addition, the dielectric layer 176A and the dielectric layer 176B are bonded to the dielectric layer 75A and the dielectric layer 75B, for example, by the generated Si-O-Si bond. Depending on the material of the gap filling material 80, the dielectric layer 176A and the dielectric layer 176B can be bonded to the gap filling material 80, or can be in contact with the gap filling material 80 but not bonded to (no bond is formed) the gap filling material 80.

[0054] Next, device die 168A and device die 168B may be thinned, similar to the thinning of device die 68A and device die 68B. Fig.19 As shown, the gap between adjacent device dies 168A and 168B is filled with gap fill material 180. The corresponding steps are shown as Fig.39328 in the process flow 300 shown in FIG. According to some embodiments of the present disclosure, gap fill material 180 is formed using a method selected from the same candidate methods used to form gap fill material 80. Gap fill material 180 may include an oxide such as silicon oxide, silicon nitride, PBO, polyimide, etc. Then, a planarization step is performed to remove excess portions of gap fill material 180, thereby exposing substrates 170A and 170B of device die 168A and device die 168B.

[0055] Then, dielectric layer 182 is deposited as a blanket layer, for example, using CVD, PECVD, ALD, etc. The resulting structure is also Fig.19 The corresponding steps are shown as Fig.39 Step 330 of the process flow 300 is shown in FIG. According to some embodiments of the present disclosure, the dielectric layer 182 is formed of an oxide such as silicon oxide, silicon oxynitride, or the like.

[0056] Next, refer to Fig. 20 , trench 184 is formed by etching dielectric layer 182 and substrates 170A and 170B so that trench 184 extends into dielectric layer 182 and substrates 170A and 170B. The depth D1 of the portion of trench 184 inside substrates 170A and 170B may be greater than about 1 μm and may be between about 2 μm and about 5 μm, depending on the thickness T1 of substrates 170A and 170B. For example, depth D1 may be between about 20% and about 60% of thickness T1. It should be understood that the values ​​listed throughout the specification are examples and may be changed to different values.

[0057] The grooves 184 may be distributed in various patterns. For example, the grooves 184 may be formed as discrete openings, which may be distributed in an array pattern, a honeycomb pattern, or other repeating patterns. The top view shape of the grooves 184 may be rectangular, circular, hexagonal, etc. According to an optional embodiment, when the grooves 184 are Fig. 20 When viewed in a top view of the structure shown in , the grooves 184 can be parallel grooves with a length direction in a single direction. The grooves 84 can also be interconnected to form a grid. The grid may include a first plurality of grooves that are parallel to each other and evenly or unevenly spaced, and a second plurality of grooves that are parallel to each other and evenly or unevenly spaced. The first plurality of grooves and the second plurality of grooves intersect each other to form a grid, and the first plurality of grooves and the second plurality of grooves may or may not be perpendicular to each other in the top view.

[0058] Then, if Fig.21 As shown, the trench 184 is filled to form a bonding pad 187. The corresponding steps are shown as Fig.39332 in the process flow 300 shown in FIG. It should be understood that although component 187 is referred to as a bonding pad, component 187 may be a discrete pad, an interconnecting metal line, or a metal grid. According to some embodiments of the present disclosure, bonding pad 187 is formed of copper or other metal suitable for hybrid bonding (due to the relative ease of diffusion). After filling, planarization is performed to flatten the top surface of bonding pad 187 through the top surface of dielectric layer 182. Planarization may include CMP or mechanical grinding.

[0059] Next, if Fig. 22 As shown, blank die 88 is bonded to device die 168A and device die 168B. The corresponding steps are shown as Fig.39 . The blank die 88 includes a bulk substrate 194, which can be a silicon substrate or a metal substrate. When formed of metal, the substrate 194 can be formed of copper, aluminum, stainless steel, etc. When the substrate 194 is formed of silicon, no active devices and passive devices are formed in the blank die 88. The blank die 88 includes two functions. First, since the device die 68A, device die 68B, device die 168A, and device die 168B have been thinned to allow better gap filling, the blank die 88 provides mechanical support for the underlying structure. In addition, silicon or metal (of the substrate 194) has a high thermal conductivity, and therefore the blank die 88 can act as a heat sink. Since Fig. 22 The formation of the structures in is at the wafer level, so multiple blank dies identical to the illustrated blank die 88 are also bonded to corresponding underlying device dies identical to device die 168A and device die 168B.

[0060] A dielectric layer 190 is formed at the surface of the substrate 194. For example, the dielectric layer 190 may be formed of silicon oxide or silicon oxynitride. In addition, a bonding pad 192 is formed in the dielectric layer 190, and the bottom surface of the bonding pad 192 is shown to be coplanar with the bottom surface of the dielectric layer 190. The pattern and lateral dimensions of the bonding pad 192 may be the same or similar to the dimensions of the corresponding bonding pad 187, so that the bonding pad 192 and the bonding pad 187 may be bonded to each other in a one-to-one correspondence.

[0061] The bonding of the blank die 88 to the device die 168A and the device die 168B can be achieved by hybrid bonding. For example, the dielectric layer 182 and the dielectric layer 190 are bonded to each other and Si-O-Si bonds can be formed. The bonding pad 192 is bonded to the corresponding bonding pad 187 by metal-to-metal direct bonding.

[0062] Advantageously, by contacting (and even being inserted into) substrate 170A and substrate 170B, bonding pad 187 provides a good heat dissipation path so that heat generated in device die 68A, device die 68B, device die 168A, and device die 168B can be easily diffused into bulk substrate 194, and thus bulk substrate 194 is used as a heat sink.

[0063] refer to Fig.23 , photoresist 183 is applied and patterned. Then, dielectric layer 182 and gap fill material 180 are etched using patterned photoresist 183 as an etch mask to expose portions of interposer 100. The corresponding steps are shown as Fig.39 3. Step 334 of process flow 300 shown in FIG. According to some embodiments of the present disclosure, some device dies, such as device die 68B, are exposed. Some of TSVs 71B and TDVs 162 may also be exposed.

[0064] Fig.24 The bonding of the die stack 212 to the first layer structure is shown. The corresponding steps are shown as Fig.39 . The die stack 212 may be bonded to the TDV 162, the device die (such as die 68B), or both the TDV 162 and the device die. The die stack 212 may be a memory stack including a plurality of stacked dies 214, wherein TSVs (not shown) may be formed in the die 214 to perform interconnection. The die stack 212 may also be a high bandwidth memory (HBM) cube. According to some embodiments of the present disclosure, the die stack 212 is bonded to the underlying structure by hybrid bonding, wherein the electrical connectors 216 (bonding pads in some embodiments) in the die stack 212 are bonded to the TDV 162 and the TSV 71B by direct metal-to-metal bonding, and the dielectric layer 218 of the die stack 212 is bonded to the gap fill material 80 (e.g., oxide) and the dielectric layer 75B by oxide-to-oxide bonding (or fusion bonding). According to an alternative embodiment, the electrical connector 216 is a solder region and the bond is a solder bond. According to another alternative embodiment, the electrical connector 216 is a microbump that protrudes beyond the surface dielectric layer 218 of the die stack 212. The microbump 216 can be bonded to the TDV 162 and the TSV 71B by direct metal-to-metal bonding or solder bonding, and no oxide-to-oxide bonding occurs between the die stack 212 and the gap fill material 80 and the dielectric layer 75B.

[0065] Next, the gap filling material 220 ( Fig.25) is filled into the gap between the blank die 88 and the die stack 212. The gap filling material 220 may be formed of an oxide such as silicon oxide or a polymer such as PBO or polyimide. According to some embodiments in which a carrier 20 (rather than a silicon wafer 23) is used, the structure formed on the carrier 20 is debonded from the carrier 20, for example, by projecting light such as UV light or laser on the release layer 22 to decompose the release layer 22. The resulting structure is as shown in FIG. Fig.26 As shown. The carrier 20 and the release layer 22 are formed from a composite wafer 102 ( Fig.26 ) above the structure is removed. The corresponding steps are shown as Fig.39 Step 338 of the process flow 300 shown in FIG. 1 is a process flow in which a silicon wafer 23 (rather than a carrier wafer 20) is used. Fig.24 ) of the present disclosure, the silicon wafer 23 may be removed by mechanical grinding, CMP, or dry etching. If necessary, before the carrier 20 (or silicon wafer 23) is removed, a carrier exchange may be performed to attach another carrier 222 over the structure shown, and the new carrier 222 is used to provide mechanical support during the formation of electrical connections in subsequent steps.

[0066] Fig.26 Also shown is the formation of electrical connectors 110 that may penetrate dielectric layer 24 and connect to RDL 26. According to some embodiments, a polymer layer (not shown) is formed on dielectric layer 24, and electrical connectors 110 may also extend into the polymer layer. Electrical connectors 110 may be metal bumps, solder bumps, metal pillars, bonding wires, or other suitable connectors. A die sawing step is performed on composite wafer 102 to separate composite wafer 102 into a plurality of packages 104. The corresponding steps are shown as Fig.39 2. The packages 104 are identical to one another, and each of the packages 104 may include a device die and two layers of die stack 212. Fig.27A The resulting package 104 is shown in FIG.

[0067] Fig.27B , Fig.27C , Fig.27D ,and Fig.27E as well as Figure 28 to Figure 35 The cross-sectional views of packages and intermediate stages in the formation of packages according to some embodiments of the present disclosure are shown. Unless otherwise specified, the materials and formation methods of the components in these embodiments are substantially the same as similar components. Figures 1 to 27A In the embodiments shown in FIG. 1 , similar components are denoted by the same reference numerals. Figures 1 to 27A The discussion of the illustrated embodiments can be found in Fig.27B ,, Fig.27C , Fig.27D ,and Fig.27E as well as Figure 28 to Figure 35 Details of the formation process and materials of the components shown in .

[0068] Fig.27B 1 shows a package formed according to some embodiments of the present disclosure. Fig.27A In the embodiment shown, except that the bonding pads 187 and the bonding pads 192 and the dielectric layer 190 (such as Fig.27A A bulk substrate 194, which may be a blank silicon die, is bonded to the dielectric layer 182 by a fusion bonding.

[0069] According to an optional embodiment of the present disclosure, the bulk substrate 194 is a blank metal substrate. Fig.27B Layer 182 in may be formed of a thermal interface material (TIM), which is an adhesive having a high thermal conductivity, for example, above about 1 W / k*m or above about 5 W / k*m.

[0070] Fig.27C A package 104 is shown formed according to some embodiments of the present disclosure. These embodiments are similar to Fig.27A , except that device dies having different thicknesses may be placed at the same level. For example, device die 68B is thicker than device die 68A. Therefore, device die 68B includes a portion that extends to the same level as device die 68A and device die 168A. It will be appreciated that although blank substrate 194 is shown as being bonded to device die 168A and device die 68B by fusion bonding or by oxide / TIM 182, Fig.27A The same bonding structure including bonding pad 187 and bonding pad 192 shown in FIG. 2 may be used. In accordance with some embodiments, die stack 212 has a portion flush with a portion of blank die 88 .

[0071] Fig.27D FIG. 1 shows a package 104 formed according to some embodiments of the present disclosure. Fig.27C The embodiment shown in FIG. 8 is similar to that shown in FIG. 8 , except that a blank die 88 (eg, Fig.27C Instead of being placed over the gap fill material 80 , the die stack 212 extends into the gap fill material 80 .

[0072] Fig.27E A package 104 is shown formed according to some embodiments of the present disclosure. These embodiments are similar to Fig.27A, except that the die stack 212 does not extend into the encapsulation material 180, but is located above the encapsulation material 180. A through-via 262 is formed in the encapsulation material 180 to electrically couple to the underlying through-via 162 and the stacking via 67.

[0073] Figure 28 to Figure 32 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. The corresponding package includes a single layer of device dies. The initial steps are similar to Figures 1 to 17 The resulting structure is also Fig.17 Next, refer to Fig.28 , dielectric layer 182 and bonding pad 187 may or may not be formed, and bonding pad 187 is shown with a dotted line.

[0074] Next, if Fig.29 As shown, a blank die 88 is bonded by hybrid bonding, fusion bonding, or adhesive bonding through a TIM. Fig.30 The bonding of the die stack 212 is shown. Fig.31 In the process, the blank die 88 and the die stack 212 are encapsulated in the gap fill material 220. Planarization may be performed to expose the blank die 88. In a subsequent step, the interposer 100 and the structure above are debonded from the carrier 20. Fig.32 The formation of electrical connectors 110 is shown. Then, die sawing is performed to form the packages 104.

[0075] Figure 33 to Figure 35 A cross-sectional view illustrating an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. Fig.33 The corresponding packaging and formation process of the structure shown in Figure 28 to Figure 32 , except that TDV 162 and their connecting conductive features including stacked via 67, TDV 62, and some of RDL 32, RDL 36, and RDL 44 are not formed. The bonding of die stack 212 to the underlying structure (e.g., gap filler material 80) is by fusion bonding. Therefore, the bonding pads 216 of the stacked die 212 are in contact with the gap filler material 80 or a dielectric layer formed thereon.

[0076] Fig.33 Some metal pads 44B are included that are connected to RDL 44A. Metal pads 44B and RDL 44A are part of RDL 44. Metal pads 44B may form a hollow ring. Fig.38 Some exemplary metal pads 44B and connecting RDLs 44A are shown. The metal pads 44B are formed as rings, wherein the openings 45 within the rings are filled with dielectric layers 46 ( Fig.33). It will be appreciated that although metal pad 44B is shown as part of RDL 44, similar metal pads may be formed in any layer in interposer 100. Thus, metal pad 44B is electrically connected to other conductive features in interposer 100.

[0077] Next, refer to Fig.34 , deep TDV 162 is formed from the bottom surface of interposer 100. The formation process includes etching the dielectric layer to form an opening, and then filling the opening with a conductive material. The formation process and materials are similar to the formation of TDV 62. In the formation of the opening, metal pad 44B is used as an etch stop layer so that the upper portion of the opening is defined by the size and shape of opening 45 ( Fig.38 ). The opening is further stopped by metal pad 216 in die stack 212. Thus, the formation of TDV 162 is self-aligned by metal pad 44B. Metal pad 44B and RDL 44A in combination electrically connect device die 68A and device die 68B to die stack 212 through TDV 162. Electrical connector 110 is then formed, and package 104 is obtained after die sawing, as shown in FIG. Fig.35 shown.

[0078] Fig.36 The embedded package 104 (reference Fig.27A , Fig.27B , Fig.27C , Fig.27D , Fig.27E , Fig.32 ,and Fig.35 ) package 112. The package includes a memory cube 114, which includes a plurality of stacked memory dies (not shown separately). The package 104 and the memory cube 114 are encapsulated in an encapsulation material 118, which may be a molding compound. A dielectric layer and RDL (collectively referred to as 116) are located below and connected to the package 104 and the memory cube 114. According to some embodiments of the present disclosure, Figures 1 to 11 Similar to that shown in , the dielectric layer and RDL 116 are formed using similar materials and have similar structures.

[0079] Fig.37 A package-on-package (PoP) structure is shown having an integrated fan-out (InFO) package 138 bonded to a top package 140. The InFO package 138 also includes a package 104 embedded therein. The package 104 and the through vias 134 are encapsulated in an encapsulation material 130, which may be a molding compound. The package 104 is bonded to a dielectric layer and RDL, which are collectively referred to as 146. Figures 1 to 11 Similar to that shown in , the dielectric layer and RDL 146 may also be formed using similar materials and have similar structures.

[0080] Embodiments of the present disclosure have some advantageous features. By forming a micro-pitch RDL in an interposer using a process typically used on a silicon wafer, such as a damascene process, the micro-pitch RDL can be formed thin enough to provide the ability for two or more device dies to communicate all through the micro-pitch RDL. Stacked vias are formed to replace some TDVs, thereby reducing chip area occupancy. Self-aligned TDVs are formed to connect to the die stack, wherein the metal pads used to align the TDVs are also used to connect the self-aligned TDVs to other components and device dies in the package. In addition, passive devices can also be formed when forming the micro-pitch RDL.

[0081] According to some embodiments, a method includes forming a plurality of dielectric layers; forming a plurality of redistribution lines in the plurality of dielectric layers; forming stacked vias in the plurality of dielectric layers simultaneously while forming the plurality of redistribution lines, wherein the stacked vias form a continuous electrical connection through the plurality of dielectric layers; forming a dielectric layer over the stacked vias and the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer; and bonding a first device die to a first portion of the dielectric layer and the plurality of bonding pads by hybrid bonding. In one embodiment, the method includes bonding a second device die to a second portion of the dielectric layer and the plurality of bonding pads by hybrid bonding, wherein the plurality of redistribution lines connect the first device die to the second device die. In one embodiment, forming the plurality of redistribution lines includes a damascene process. In one embodiment, the method includes etching the plurality of dielectric layers to form openings; and filling the openings to form dielectric through holes that penetrate the plurality of dielectric layers. In one embodiment, the method includes bonding an additional device die to a first device die, wherein the additional device die is bonded directly to a through silicon via in the first device die; forming an oxide layer over a semiconductor substrate of the additional device die and in contact with the semiconductor substrate of the additional device die; forming a bonding pad extending into the oxide layer; and bonding a blank die to the oxide layer and the bonding pad by hybrid bonding. In one embodiment, a plurality of dielectric layers are formed over a glass carrier; and the method also includes debonding the glass carrier; and after debonding the glass carrier, forming a self-aligned dielectric through hole to penetrate the plurality of dielectric layers, wherein the self-aligned dielectric through hole stops on a bonding pad of the die stack. In one embodiment, a plurality of dielectric layers are formed over a silicon wafer, and the method also includes grinding, polishing, or etching the silicon wafer from the plurality of dielectric layers.

[0082] According to some embodiments, a method includes forming a plurality of dielectric layers; forming a plurality of redistribution lines in each of the plurality of dielectric layers; forming passive devices in the plurality of dielectric layers; forming a first dielectric through hole and a second dielectric through hole through the plurality of dielectric layers; forming a dielectric layer over the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer and the plurality of bonding pads are electrically coupled to the first dielectric through hole, the second dielectric through hole, and the plurality of redistribution lines; and bonding a first device die and a second device die to the dielectric layer and the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically interconnected by the plurality of redistribution lines, and the first device die and the second device die are connected to the first dielectric through hole and the second dielectric through hole, respectively. In one embodiment, the plurality of redistribution lines are formed using a damascene process. In one embodiment, the method includes filling a gap filling material on opposite sides of the first device die and the second device die; forming a third dielectric through hole through the gap filling material; and bonding the die stack to the third dielectric through hole. In one embodiment, a plurality of dielectric layers are formed over a silicon wafer, and the method further comprises removing the silicon wafer from the plurality of dielectric layers. In one embodiment, forming a first dielectric through-hole and a second dielectric through-hole comprises etching a plurality of dielectric layers to form a first opening and a second opening; and filling the first opening and the second opening with a conductive material. In one embodiment, the method comprises: forming stacked vias in a plurality of dielectric layers simultaneously while forming a plurality of redistribution lines, wherein the stacked vias form a continuous electrical connection through the plurality of dielectric layers. In one embodiment, the method comprises bonding a third device die on top of the first device die; forming a dielectric layer over the third device die; and bonding a blank die to the dielectric layer.

[0083] According to some embodiments, a package includes a plurality of dielectric layers; a plurality of redistribution lines in each of the plurality of dielectric layers; dielectric through-holes extending through the plurality of dielectric layers, wherein the dielectric through-holes have substantially straight edges extending through the plurality of dielectric layers; stacked through-holes in the plurality of dielectric layers, wherein the stacked through-holes are electrically connected to each other to form a continuous electrical connection extending through the plurality of dielectric layers; a plurality of bonding pads above and connected to the dielectric through-holes and the plurality of redistribution lines; a first dielectric layer in which the plurality of bonding pads are located; and a first device die bonded to the first dielectric layer and a first portion of the plurality of bonding pads by hybrid bonding. In one embodiment, the package also includes a second device die bonded to the first dielectric layer and a second portion of the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically coupled to each other by the plurality of redistribution lines. In one embodiment, the package further includes a second device die over and bonded to the first device die; a bonding pad contacting the semiconductor substrate of the second device die, wherein at least a portion of the bonding pad is over the semiconductor substrate of the second device die; a second dielectric layer, wherein the bonding pad has at least a portion in the second dielectric layer; and a bulk substrate over and bonded to the second dielectric layer and the bonding pad. In one embodiment, the bulk substrate is formed of silicon, and no active devices and passive devices are formed on the bulk substrate. In one embodiment, the bonding pad further extends into the semiconductor substrate of the second device die. In one embodiment, the bonding pad forms a grid.

[0084] According to some embodiments, a method includes forming a plurality of dielectric layers over a silicon wafer; forming a plurality of redistribution lines in the plurality of dielectric layers; while forming the plurality of redistribution lines, simultaneously forming stacked vias in the plurality of dielectric layers, wherein the stacked vias form a continuous electrical connection through the plurality of dielectric layers; forming a dielectric layer over the stacked vias and the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer; bonding a first device die to the dielectric layer and a first portion of the plurality of bonding pads by hybrid bonding; removing the silicon wafer from the plurality of dielectric layers; and forming an electrical connection electrically coupled to the plurality of redistribution lines. In one embodiment, removing the silicon wafer includes mechanical grinding on the silicon wafer. In one embodiment, removing the silicon wafer includes performing chemical mechanical polishing on the silicon wafer. In one embodiment, removing the silicon wafer includes performing dry etching on the silicon wafer. In one embodiment, the method includes forming passive devices in the plurality of dielectric layers. In one embodiment, the method includes encapsulating the first device die in a gap fill material; and after removing the silicon wafer, forming a dielectric through hole through the plurality of dielectric layers and the gap fill material.

[0085] According to some embodiments, a package includes a plurality of dielectric layers; stacked vias extending through the plurality of dielectric layers, wherein the stacked vias have a dual damascene structure and the stacked vias are interconnected to form a continuous electrical connection structure; a device die above the plurality of dielectric layers, wherein the device die is bonded to an underlying structure by hybrid bonding and the device die is electrically coupled to the stacked vias; and a die stack above the device die and bonded to the device die. In one embodiment, the die stack is bonded to the device die by hybrid bonding.

[0086] According to some embodiments, a package includes multiple dielectric layers; passive devices in the multiple dielectric layers; dielectric through-vias that penetrate the multiple dielectric layers; a first device die above and electrically coupled to the dielectric through-vias, wherein the first device die includes a semiconductor substrate; a dielectric layer above the first device die; a bonding pad in the dielectric layer, wherein the bonding pad penetrates the dielectric layer and further extends into the semiconductor substrate of the first device die; and a die stack above and bonded to the first device die. In one embodiment, a package also includes a second device die located between the first device die and the dielectric through-vias.

[0087] According to an embodiment of the present application, a method for forming a package is provided, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in the plurality of dielectric layers; forming stacked vias in the plurality of dielectric layers, wherein the stacked vias form a continuous electrical connection extending through the plurality of dielectric layers; forming a dielectric layer above the stacked vias and the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer; and bonding a first device die to the dielectric layer and a first portion of the plurality of bonding pads by hybrid bonding.

[0088] According to an embodiment of the present application, further comprising bonding a second device die to the dielectric layer and the second portion of the plurality of bonding pads by hybrid bonding, wherein the plurality of redistribution lines connect the first device die to the second device die.

[0089] According to an embodiment of the present application, forming a plurality of redistribution lines includes a damascene process.

[0090] According to an embodiment of the present application, the method further includes: etching a plurality of dielectric layers to form openings; and filling the openings to form dielectric through holes penetrating the plurality of dielectric layers.

[0091] According to an embodiment of the present application, it also includes: bonding an additional device die to the first device die, wherein the additional device die is directly bonded to a through silicon via in the first device die; forming an oxide layer above the semiconductor substrate of the additional device die and the oxide layer is in contact with the semiconductor substrate of the additional device die; forming a bonding pad extending into the oxide layer; and bonding a blank die to the oxide layer and the bonding pad by hybrid bonding.

[0092] According to an embodiment of the present application, multiple dielectric layers are formed above a glass carrier; and the method also includes: debonding the glass carrier; and after the glass carrier is debonded, forming self-aligned dielectric through holes to penetrate the multiple dielectric layers, wherein the self-aligned dielectric through holes stop on the bonding pads of the tube core stack.

[0093] According to an embodiment of the present application, a plurality of dielectric layers are formed over the silicon wafer, and the method further includes grinding, polishing, or etching the silicon wafer from the plurality of dielectric layers.

[0094] According to an embodiment of the present application, a method for forming a package is provided, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in each of the plurality of dielectric layers; forming passive devices in the plurality of dielectric layers; forming a first dielectric through-hole and a second dielectric through-hole penetrating the plurality of dielectric layers; forming a dielectric layer above the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer and electrically coupled to the first dielectric through-hole, the second dielectric through-hole, and the plurality of redistribution lines; and bonding a first device die and a second device die to the dielectric layer and the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically interconnected by the plurality of redistribution lines, and the first device die and the second device die are respectively connected to the first dielectric through-hole and the second dielectric through-hole.

[0095] According to an embodiment of the present application, a plurality of redistribution lines are formed using a damascene process.

[0096] According to an embodiment of the present application, the method further includes: filling a gap filling material on opposite sides of the first device die and the second device die; forming a third dielectric through-hole penetrating the gap filling material; and bonding the die stack to the third dielectric through-hole.

[0097] According to an embodiment of the present application, a plurality of dielectric layers are formed over the silicon wafer, and the method further includes removing the silicon wafer from the plurality of dielectric layers.

[0098] According to an embodiment of the present application, forming a first dielectric through-hole and a second dielectric through-hole includes: etching a plurality of dielectric layers to form a first opening and a second opening; and filling the first opening and the second opening with a conductive material.

[0099] According to an embodiment of the present application, the method further includes: when forming a plurality of redistribution lines, simultaneously forming stacked vias in a plurality of dielectric layers, wherein the stacked vias form a continuous electrical connection that penetrates the plurality of dielectric layers.

[0100] According to an embodiment of the present application, the method further includes: bonding a third device die on top of the first device die; forming a dielectric layer over the third device die; and bonding a blank die to the dielectric layer.

[0101] According to an embodiment of the present application, a package is provided, comprising: a plurality of dielectric layers; a plurality of redistribution lines in each of the plurality of dielectric layers; dielectric through-holes extending through the plurality of dielectric layers, wherein the dielectric through-holes have substantially straight edges extending through the plurality of dielectric layers; stacked through-holes in the plurality of dielectric layers, wherein the stacked through-holes are electrically connected to each other to form a continuous electrical connection extending through the plurality of dielectric layers; a plurality of bonding pads above the dielectric through-holes and the plurality of redistribution lines and connected to the dielectric through-holes and the plurality of redistribution lines; a first dielectric layer, wherein the plurality of bonding pads are located in the first dielectric layer; and a first device die bonded to the first dielectric layer and a first portion of the plurality of bonding pads.

[0102] According to an embodiment of the present application, further included is a second device die bonded to the first dielectric layer and the second portion of the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically coupled to each other by the plurality of redistribution lines.

[0103] According to an embodiment of the present application, it also includes: a second device die above the first device die and bonded to the first device die; a bonding pad contacting the semiconductor substrate of the second device die, wherein at least a portion of the bonding pad is above the semiconductor substrate of the second device die; a second dielectric layer, the bonding pad having at least a portion in the second dielectric layer; and a block substrate above the second dielectric layer and the bonding pad and bonded to the second dielectric layer and the bonding pad.

[0104] According to an embodiment of the present application, the bulk substrate is formed of silicon, and no active devices and no passive devices are formed on the bulk substrate.

[0105] According to an embodiment of the present application, the bonding pad further extends into the semiconductor substrate of the second device die.

[0106] According to an embodiment of the present application, the bonding pads form a grid.

[0107] The features of several embodiments are discussed above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A package comprising: multiple dielectric layers; a plurality of redistribution lines in each of the plurality of dielectric layers; a dielectric through hole extending through the plurality of dielectric layers, wherein the dielectric through hole has a straight edge extending through the plurality of dielectric layers; stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection through the plurality of dielectric layers; a plurality of bonding pads over and connected to the dielectric through vias and the plurality of redistribution lines; a first dielectric layer, the plurality of bonding pads being located in the first dielectric layer; and A first device die is bonded to the first dielectric layer and a first portion of the plurality of bond pads, the first portion of the plurality of bond pads including a first bond pad that physically contacts a top surface of the stacked via and a bottom surface of additional bond pads of the first device die.

2. The package of claim 1 , further comprising a second device die bonded to the first dielectric layer and a second portion of the plurality of bond pads by hybrid bonding, wherein: The first device die and the second device die are electrically coupled to each other through the plurality of redistribution lines.

3. The package according to claim 1, further comprising: a second layer device die over and bonded to the first device die; a bonding pad contacting a semiconductor substrate of the second layer device die, wherein at least a portion of the bonding pad is above the semiconductor substrate of the second layer device die; a second dielectric layer, the bonding pad having at least a portion therein; and A bulk substrate is over and bonded to the second dielectric layer and the bond pad.

4. The package according to claim 3, wherein: The bulk substrate is formed of silicon, and no active devices and no passive devices are formed on the bulk substrate.

5. The package according to claim 3, wherein: The bonding pad further extends into the semiconductor substrate of the second tier device die.

6. The package according to claim 3, wherein: The bonding pads form a grid.

7. An integrated circuit package, the package comprising: multiple dielectric layers; Passive devices in said dielectric layers; A dielectric through hole extending through the plurality of dielectric layers; stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection through the plurality of dielectric layers; a first bonding pad over the stacked via and in physical contact with a top via of the stacked via; a second bonding pad over and in contact with the dielectric through-hole; A device die is over and bonded to the first and second bond pads, the first bond pad physically contacting a bottom surface of an additional bond pad of the device die.

8. The package according to claim 7, wherein: The device die includes a semiconductor substrate, and the package further includes a third bonding pad extending to an intermediate level of the semiconductor substrate, and wherein the intermediate level is between a top surface and a bottom surface of the semiconductor substrate.

9. The package according to claim 8, wherein: The bottom surface of the third bonding pad contacts a surface of the semiconductor substrate to form an interface.

10. The package according to claim 8, further comprising: The encapsulant encapsulating the device die in the encapsulant; and A dielectric layer is above and contacts a top surface of the semiconductor substrate and a top surface of the encapsulant, wherein the third bonding pad further extends into the dielectric layer. 11 . The package of claim 8 , further comprising a bulk substrate bonded to the third bond pad.

12. The package according to claim 11, wherein: The bulk substrate further comprises: an additional dielectric layer on a bottom surface of the semiconductor substrate; and A bulk substrate additional bonding pad is provided in the additional dielectric layer, wherein the bulk substrate additional bonding pad is physically bonded to the third bonding pad.

13. The package of claim 8, further comprising a first dielectric layer over and contacting the plurality of dielectric layers, wherein: The first bonding pad and the second bonding pad are located in the first dielectric layer, The device die is bonded to a structure below through a bonding structure, and the bonding structure includes: Dielectric-to-dielectric bonding, the surface dielectric layer of the device die is bonded to the first dielectric layer via Si-O-Si bonds; A copper-to-copper bond, the copper of the first bond pad being bonded and physically connected to the copper of the additional bond pad in the device die.

14. A method of forming a package, comprising: forming a plurality of dielectric layers; forming a plurality of redistribution lines in each of the plurality of dielectric layers; forming passive devices in the plurality of dielectric layers; forming stacked vias, first dielectric through vias, and second dielectric through vias that are electrically connected to each other and penetrate the plurality of dielectric layers; forming a dielectric layer over the plurality of dielectric layers; forming a plurality of bonding pads in the dielectric layer and electrically coupled to the first through dielectric via, the second through dielectric via, and the plurality of redistribution lines; as well as bonding a first device die and a second device die to the dielectric layer and the plurality of bonding pads by hybrid bonding, wherein the first device die and the second device die are electrically interconnected by the plurality of redistribution lines, and the first device die and the second device die are connected to the first dielectric through-via and the second dielectric through-via, respectively, and the plurality of bonding pads include a first bonding pad that physically contacts a top surface of the stacked through-via and a bottom surface of an additional bonding pad of the first device die; filling a gap-fill material on opposite sides of the first device die and the second device die; forming a third dielectric through hole penetrating the gap-filling material; and A die stack is bonded to the third through dielectric via.

15. The method according to claim 14, wherein: The plurality of redistribution lines are formed using a damascene process.

16. The method according to claim 14, wherein: The plurality of dielectric layers are formed over a silicon wafer, and the method further includes removing the silicon wafer from the plurality of dielectric layers.

17. The method according to claim 14, wherein: Forming the first dielectric through hole and the second dielectric through hole includes: etching the plurality of dielectric layers to form a first opening and a second opening; and The first opening and the second opening are filled with a conductive material.

18. The method according to claim 14, further comprising: The stacked vias are simultaneously formed in the plurality of dielectric layers while forming the plurality of redistribution lines, wherein the stacked vias form a continuous electrical connection.

19. The method according to claim 14, further comprising: bonding a third device die on top of the first device die; forming a dielectric layer over the third device die; as well as A blank die is bonded to the dielectric layer.

20. The method of claim 14, further comprising: The stacked vias are simultaneously formed in the multiple dielectric layers while the multiple redistribution lines are formed in the multiple dielectric layers, wherein the stacked vias combine to form a conductive path that penetrates the multiple dielectric layers, and wherein the third dielectric through-hole is electrically connected to one of the stacked vias.

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