Adjustable Duty Cycle Circuit

Abstract

The present invention discloses an adjustable duty cycle circuit, which includes: a frequency discriminator module, which is used to output a trigger signal based on the frequency of an input signal and a reset signal; a delay module, which has a long delay path and a short delay path, and is used to respond to the trigger signal, select the long delay path or the short delay path, delay the input signal, and output an initial clock signal; a clock generation module, which is used to perform signal pulse width processing on the initial clock signal based on a duty cycle control signal, and output a target clock signal with a preset duty cycle. By applying the technical solution provided by the present invention, the duty cycle of the clock signal can be controlled more accurately, and the speed and accuracy of data transmission can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to an adjustable duty cycle circuit. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] Electronic devices need to adjust the duty cycle of signals through adjustable duty cycle circuits. Taking NAND Flash memory devices as an example, in applications of this type, the ONFI protocol is used as the standard. The ONFI protocol stipulates that the frequency range for duty cycle calibration when the signal is working is getting wider and wider, and the requirements for the signal duty cycle are becoming more and more stringent. Summary of the invention

[0004] In view of this, the present invention provides an adjustable duty cycle circuit, which can more accurately control the duty cycle of a clock signal and improve the speed and accuracy of data transmission.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] An adjustable duty cycle circuit, the adjustable duty cycle circuit comprising:

[0007] A frequency discriminator module, the frequency discriminator module is used to output a trigger signal based on the frequency of the input signal and a reset signal;

[0008] A delay module, the delay module having a long delay path and a short delay path, for responding to the trigger signal, selecting the long delay path or the short delay path, delaying the input signal, and outputting an initial clock signal;

[0009] A clock generation module is used to perform signal pulse width processing on the initial clock signal based on a duty cycle control signal, and output a target clock signal with a preset duty cycle.

[0010] Preferably, in the above-mentioned adjustable duty cycle circuit, the delay module includes: X first delay units and one first dummy delay unit, X is a positive integer greater than 1; the X first delay units are sequentially the first delay unit of the first stage to the first delay unit of the Xth stage;

[0011] The input signal is input into the input terminal of the first delay unit of the first stage;

[0012] The output end of the first delay unit of the i-1th stage is connected to the input end of the first delay unit of the ith stage, where i is a positive integer greater than 1 and not greater than X;

[0013] The output ends of the first delay unit of the 1st stage to the first delay unit of the Xth stage are respectively connected to the clock generation module;

[0014] The input end of the first dummy delay unit is connected to the output end of the X-th stage first delay unit, and the output end of the first dummy delay unit is floating.

[0015] Preferably, in the above-mentioned adjustable duty cycle circuit, the first delay unit includes:

[0016] A first multiplexer having two input terminals, a trigger terminal and an output terminal; the trigger terminal is used to receive the trigger signal;

[0017] The input end of the first delay unit is connected to one input end of the first multiplexer through a plurality of first buffers connected in series, and the input end of the first delay unit is directly connected to another input end of the first multiplexer; the output end of the first multiplexer is the output end of the first delay unit.

[0018] Preferably, in the above-mentioned adjustable duty cycle circuit, the circuit structure of the first delay unit and the first dummy delay unit are the same.

[0019] Preferably, in the above-mentioned adjustable duty cycle circuit, X is an odd number, and each of the first delay units correspondingly outputs one of the initial clock signals;

[0020] The clock generation module comprises:

[0021] an adjustment selection unit, configured to perform signal pulse width processing on the X initial clock signals based on the first control code to the third control code, and output a first clock signal and a second clock signal;

[0022] A second multiplexer having two input terminals, a trigger terminal and an output terminal; the two input terminals of the second multiplexer are respectively input with the first clock signal and the second clock signal; the second multiplexer is used for selecting to output the first clock signal or the second clock signal through its output terminal based on a fourth control code connected to its trigger terminal;

[0023] A matched delay line, the matched delay line being used to output a falling edge of an edge combiner based on an initial clock signal output by the first delay unit of the xth stage; x=(X+1) / 2;

[0024] a first inverter, the first inverter being used to output a rising edge of the edge combiner based on an output signal of the second multiplexer;

[0025] Wherein, the edge combiner outputs the target clock signal based on the output signal of the matching delay line and the first inverter; and the duty cycle control signal includes the first control code to the fourth control code.

[0026] Preferably, in the above-mentioned adjustable duty cycle circuit, the adjustment selection unit includes:

[0027] two third inverters, namely a first-stage third inverter for outputting the first clock signal and a second-stage third inverter for outputting the second clock signal;

[0028] X second inverters, the X second inverters are sequentially the first-stage second inverter to the X-stage second inverter; the input end of the p-th-stage second inverter is connected to the output end of the p-th-stage first delay unit, and p is a positive integer not greater than X;

[0029] X switch elements, the X switch elements are sequentially from the 1st-stage switch element to the Xth-stage switch element; the input end of the pth-stage switch element is connected to the output end of the pth-stage second inverter; the output ends of the 1st-stage switch element to the x-1th-stage switch element are all connected to the input end of the 1st-stage third inverter; the output ends of the xth-stage switch element to the Xth-stage switch element are all connected to the 2nd-stage third inverter.

[0030] Preferably, in the above-mentioned adjustable duty cycle circuit, the adjustment selection unit further comprises: X-1 fourth inverters;

[0031] The input ends of the 1st to x-1th second inverters and the input ends of the x+1th to xth second inverters are respectively connected to an input end of the fourth inverter, and the output ends of the fourth inverters are both floating.

[0032] Preferably, in the above-mentioned adjustable duty cycle circuit, the edge combiner comprises:

[0033] An RS flip-flop having two input terminals and one output terminal, wherein the output terminal is used to output the target clock signal;

[0034] two short pulse generators;

[0035] An input end of the short pulse generator is connected to the output end of the matching delay line, and an output end of the short pulse generator is connected to an input end of the RS trigger;

[0036] Another input terminal of the short pulse generator is connected to the output terminal of the first inverter, and an output terminal thereof is connected to another input terminal of the RS trigger.

[0037] Preferably, in the above-mentioned adjustable duty cycle circuit, the short pulse generator comprises: a PMOS, a first NMOS, a second NMOS and a fifth inverter;

[0038] The source of the PMOS is connected to a power source, the gate of the PMOS is connected to the gate of the first NMOS, and the drain of the PMOS is connected to the drain of the first NMOS;

[0039] The input end of the fifth inverter is connected to the drain of the PMOS, and the output end thereof is connected to the output end of the short pulse generator;

[0040] A plurality of sixth inverters are connected in series between the input end of the short pulse generator and the gate of the first NMOS; the input end of the short pulse generator is directly connected to the gate of the second NMOS;

[0041] The source of the second NMOS is grounded, and the drain of the second NMOS is connected to the source of the first NMOS.

[0042] Preferably, in the above-mentioned adjustable duty cycle circuit, the frequency discriminator module includes:

[0043] A half frequency divider, used for dividing the input signal into two frequencies to form a first signal and a second signal;

[0044] A second buffer, used for buffering the second signal;

[0045] a delay trigger submodule, configured to output a plurality of third signals based on the reset signal, the first signal and the buffered second signal;

[0046] The output submodule is used to perform logic processing on the third signal and output the trigger signal.

[0047] Preferably, in the above-mentioned adjustable duty cycle circuit, the delay trigger submodule outputs Y third signals, and the Y third signals are sequentially the first-level third signal to the Y-th-level third signal, and Y is a positive integer greater than 1; the delay trigger submodule includes:

[0048] Y second delay units, the Y second delay units are sequentially a 1st-stage second delay unit to a Yth-stage second delay unit, an input end of the 1st-stage second delay unit is connected to the first signal, an output end of the jth-stage second delay unit is connected to an input end of the j+1th-stage second delay unit, and j is a positive integer less than Y;

[0049] Y first AND gates, each of which has three input terminals; the Y first AND gates are sequentially the first AND gate of the 1st stage to the first AND gate of the Yth stage; one input terminal of the first AND gate of the 1st stage is connected to a power supply, and the other two input terminals are respectively connected to the output terminal of the second buffer and the output terminal of the second delay unit of the 1st stage; among the first AND gates of the jth stage to the first AND gates of the Yth stage, one input terminal of the first AND gate of the j+1th stage is connected to the output terminal of the first AND gate of the jth stage, and the other two input terminals of the first AND gate of the j+1th stage are respectively connected to the output terminal of the second buffer and the output terminal of the second delay unit of the j+1th stage;

[0050] Y D flip-flops, which are the 1st-level D flip-flop to the Yth-level D flip-flop in sequence; the input terminal D of the jth-level D flip-flop is connected to the power supply, its in-phase output terminal Q outputs the jth-level third signal, its clock input terminal is connected to the output terminal of the jth-level first AND gate, and its reset terminal is connected to the reset signal.

[0051] Preferably, in the above-mentioned adjustable duty cycle circuit, the delay trigger submodule outputs Y third signals, and the Y third signals are sequentially the first-level third signal to the Y-th-level third signal, and Y is a positive integer greater than 1;

[0052] The output submodule comprises:

[0053] Y-1 seventh inverters, the Y-1 seventh inverters are sequentially a 1st-stage seventh inverter to a Y-1th-stage seventh inverter;

[0054] Y-1 second AND gates, each of which has a first input terminal and a second input terminal; the Y-1 second AND gates are sequentially the first-stage second AND gate to the Y-1-stage second AND gate;

[0055] An OR gate, the OR gate being used to output the trigger signal based on the output signals of the Y-1 second AND gates;

[0056] Among them, the j-th level third signal is directly connected to the first input terminal of the j-th level second AND gate; the j+1-th level third signal is inverted by the j-th level seventh inverter and then connected to the j-th level second AND gate.

[0057] From the above description, it can be seen that in the adjustable duty cycle circuit provided by the technical solution of the present invention, the frequency of the input signal is automatically determined by the frequency discriminator module, and a trigger signal is output based on the frequency of the input signal and the reset signal. The delay module automatically selects a suitable long delay path or short delay path based on the trigger signal, delays the input signal, and outputs an initial clock signal. After determining the delay path, the clock generation module performs signal pulse width processing on the initial clock signal based on the duty cycle control signal, and finally outputs a target clock signal with a preset duty cycle, thereby being able to more accurately control the duty cycle of the clock signal and improve the speed and accuracy of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0059] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0060] Figure 1 It is a schematic diagram of a fully digital adjustable duty cycle circuit structure;

[0061] Figure 2 It is another schematic diagram of the structure of a fully digital adjustable duty cycle circuit;

[0062] Figure 3 A schematic diagram of an adjustable duty cycle circuit structure provided by an embodiment of the present invention;

[0063] Figure 4 A schematic diagram of the circuit structure of a delay module provided by an embodiment of the present invention;

[0064] Figure 5 A schematic diagram of the circuit structure of a first delay unit provided in an embodiment of the present invention;

[0065] Figure 6 A schematic diagram of the circuit structure of a clock generation module provided in an embodiment of the present invention;

[0066] Figure 7A schematic diagram of the circuit structure of an adjustment selection unit provided in an embodiment of the present invention;

[0067] Figure 8 A schematic diagram of the circuit structure of an edge combiner provided in an embodiment of the present invention;

[0068] Fig. 9 A waveform diagram showing the working principle of the edge combiner provided by an embodiment of the present invention;

[0069] Fig.10 A schematic diagram of the circuit structure of a short pulse generator provided in an embodiment of the present invention;

[0070] Fig.11 A schematic diagram of the circuit structure of a frequency discriminator module provided in an embodiment of the present invention;

[0071] Fig.12 A waveform diagram of the working principle of an adjustable duty cycle circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0073] The interface timing of the communication between NAND Flash memory represented by SSD (solid state drive) and the host meets the timing requirements of the international ONFI (Open NAND Flash Interface) standard. The latest ONFI standard is ONFI 4.2, which needs to support high-speed interfaces such as NV-DDR, NV-DDR2 and NV-DDR3, thus placing more stringent requirements on the speed and timing of data transmission.

[0074] The ONFI 4.2 protocol stipulates that for NV-DDR2 and NV-DDR3 high-speed interfaces, when the clock frequency is 533MHz (1.875ns), 600MHz (1.667ns), 667MHz (1.5ns), 733MHz (1.364ns) and 800MHz (1.25ns), DCC (Duty Cycle Correction) Training can be added when there is a deviation in the transmitted data, that is, the duty cycle of the clock signal can be calibrated to ensure correct timing.

[0075] In order to increase the data transmission speed, high-speed interfaces such as NV-DDR use double-edge sampling to sample data. To ensure correct data transmission, the duty cycle of the clock signal when sampling is required to be accurate to 50%. Due to the influence of PVT (Process, Voltage, Temperature), NMOS and PMOS intrinsic mismatch, etc., the edge of the clock signal sent from the control end will be offset, and the deterioration is more serious at high frequencies. In this way, the duty cycle of the clock signal during sampling seriously deviates from 50%, resulting in data transmission errors.

[0076] In the future, as new ONFI protocols are continuously introduced, data transmission speed will become faster and faster, and the application frequency of DCC Training (duty cycle correction) will also develop towards high frequency. Therefore, using DCC training can offset the offset of the clock signal during transmission due to PVT and other factors, so that the clock signal has a 50% duty cycle during sampling to ensure correct data transmission.

[0077] refer to Figure 1 , Figure 1 The present invention is a schematic diagram of a fully digital adjustable duty cycle circuit structure, which is composed of a duty cycle detector 11 (Duty cycle Detector, referred to as DCD), a digitally controlled delay line 12 (Digitally controlled delay line, referred to as DCDL) and an edge combiner 13 (Edge Combiner, referred to as EC). The duty cycle detector 11 structure can output a digital code representing its duty cycle by detecting the input clock signal Clk, and the digitally controlled delay line 12 structure adjusts the delay time according to the input digital code.

[0078] like Figure 1 As shown, the duty cycle detector 11 first detects the input clock signal Clk and outputs a digital code representing its duty cycle information. Then, this digital code and the externally input duty cycle setting code Dcsc (Duty cycle setting code) are calculated through the operation unit 14 to obtain the desired duty cycle control code to control the numerically controlled delay line 12 to produce different delays. Finally, the edge combiner 13 combines two clock signals with different delays and outputs a clock signal Clk_out with a desired duty cycle.

[0079] refer to Figure 2 , Figure 2 This is another fully digital adjustable duty cycle circuit structure diagram, based on Figure 1 As shown, Figure 2In the illustrated embodiment, the matching delay line 121 is a matching delay line used to match the intrinsic delay of the digital control delay line 12, the counter 141 is a counter for calculating the control code of the digital control delay line 12 according to the detected duty cycle digital code and the externally input duty cycle setting code, and the driving module CD is used to provide a drive for the clock output. The digital control delay line 12 includes a plurality of delay units connected in series. Figure 2 The delay unit is not shown.

[0080] like Figure 2 As shown, when the reset signal Reset changes and the circuit starts working, the duty cycle detector 11 first detects the clock duty cycle digital code according to the input clock signal Clk, and then the counter 141 obtains the control code of the digitally controlled delay line 12 by addition counting or subtraction counting according to the relationship between the detected duty cycle digital code and the externally input duty cycle setting code Dcsc; the digitally controlled delay line 12 adjusts the delay time of the matching delay line 121 according to the size of the control code; the edge combiner 13 combines the clock signals with different edges output by the matching delay line 121 and the digitally controlled delay line 12 to generate a clock signal Clk_out with a desired duty cycle, and then drives the output through the driver module CD.

[0081] Figure 1 and Figure 2 In the manner shown, the operating frequency range and the delay chain length of the duty cycle detector 11 are mutually constrained. The total length of the delay chain of the duty cycle detector 11 should be determined by the delay time of a single delay unit and the minimum operating frequency of the clock. However, if the chain length is reasonably extended, errors will occur in the duty cycle detector 11 at high frequencies.

[0082] The delay chain in the digital control delay line 12 has different adjustment steps for the duty cycle under different operating frequency conditions, such as Figure 2 In the numerically controlled delay line 12, the delay unit of the delay chain has a fixed delay. If the delay size is set according to the low-frequency adjustment step, the adjustment step will be too large for the high frequency. If it is set according to the high-frequency adjustment step, more delay units and control codes are required within the same adjustment range at low frequencies.

[0083] Therefore, a wide operating frequency range cannot be met. Taking ONFI4.2 as an example, the frequency range of the duty cycle circuit is required to be from 533MHz to 800MHz. If the delay chain is set according to the 1.875ns clock cycle under 533MHz conditions, then the delay chain adjustment step size is too long under 800MHz conditions. In addition, the future ONFI protocol will require a faster operating speed of up to 1.5GHz. If the delay chain is set according to the 666ps clock cycle under 1.5GHz conditions, then under 533MHz conditions, a very long delay chain and complex control circuit are required.

[0084] Therefore, in order to solve the above problem, the present invention provides an adjustable duty cycle circuit, the adjustable duty cycle circuit comprising:

[0085] A frequency discriminator module, the frequency discriminator module is used to output a trigger signal based on the frequency of the input signal and a reset signal;

[0086] A delay module, the delay module having a long delay path and a short delay path, for responding to the trigger signal, selecting the long delay path or the short delay path, delaying the input signal, and outputting an initial clock signal;

[0087] A clock generation module is used to perform signal pulse width processing on the initial clock signal based on a duty cycle control signal, and output a target clock signal with a preset duty cycle.

[0088] From the above description, it can be seen that in the adjustable duty cycle circuit provided by the technical solution of the present invention, the frequency of the input signal is automatically determined by the frequency discriminator module, and a trigger signal is output based on the frequency of the input signal and the reset signal. The delay module automatically selects a suitable long delay path or short delay path based on the trigger signal, delays the input signal, and outputs an initial clock signal. After determining the delay path, the clock generation module performs signal pulse width processing on the initial clock signal based on the duty cycle control signal, and finally outputs a target clock signal with a preset duty cycle, thereby being able to more accurately control the duty cycle of the clock signal and improve the speed and accuracy of data transmission.

[0089] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0090] refer to Figure 3 , Figure 3 A schematic diagram of an adjustable duty cycle circuit structure provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the adjustable duty cycle circuit includes:

[0091] A frequency discriminator module 31, the frequency discriminator module 31 is used to output a trigger signal FS based on the frequency of the input signal Clk_in and the reset signal R;

[0092] A delay module 32, wherein the delay module 32 has a long delay path and a short delay path, and is used to respond to the trigger signal FS, select the long delay path or the short delay path, delay the input signal Clk_in, and output an initial clock signal CK[0:N];

[0093] The clock generating module 33 is used to perform signal pulse width processing on the initial clock signal CK[0:N] based on a duty cycle control signal Dccc (dutycycle control code), and output a target clock signal Clk_out with a preset duty cycle.

[0094] In the embodiment of the present invention, the frequency detector module 32 automatically determines the frequency of the input signal Clk_in. When the input signal Clk_in is low frequency, the trigger signal FS output is 0, and the long delay chain is selected. When the input signal Clk_in is high frequency, the trigger signal FS output is 1, and the short delay chain is selected. After determining the delay path, the clock generation module 33 performs signal pulse width processing on the initial clock signal CK[0:N] based on the duty cycle control signal DCCC, and finally outputs the target clock signal Clk_out with a preset duty cycle.

[0095] It should be noted that the delay module 32 is not limited to controlling the two extension paths of long and short. The frequency discriminator module 31 can realize the judgment of more frequency bands of the clock signal according to design requirements; at the same time, the delay path can also be divided into more paths based on different delay units; according to the output result of the frequency discriminator module 31, different delay paths are selected to achieve clock duty cycle adjustment with a wider frequency range and higher frequency resolution.

[0096] refer to Figure 4 , Figure 4 A circuit structure diagram of a delay module provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the delay module includes: X first delay units 41 (Delay unit) and a first dummy delay unit 42 (dummy), X is a positive integer greater than 1; the X first delay units 41 are sequentially the first delay unit of the first stage to the first delay unit of the Xth stage;

[0097] The input signal Clk_in is input to the input terminal of the first delay unit 41 of the first stage;

[0098] The output end of the first delay unit of the i-1th stage is connected to the input end of the first delay unit of the ith stage, where i is a positive integer greater than 1 and not greater than X;

[0099] The output ends of the first delay unit of the 1st stage to the first delay unit of the Xth stage are respectively connected to the clock generating module 33;

[0100] The input end of the first dummy delay unit 42 is connected to the output end of the X-th stage first delay unit 41 , and the output end of the first dummy delay unit 42 is floating.

[0101] In the embodiment of the present invention, X is an odd number, the xth stage outputs CK_0, x=(X+1) / 2; the 1st to x-1th stages output CK_m[x-1] to CK_m[1] in sequence, and the x+1th to xth stages output CK_a[1] to CK_a[x-1] in sequence. For example, if X=15, the 8th stage outputs CK_0, the 1st to 7th stages output CK_m[7] to CK_m[1] in sequence, and the 9th to 15th stages output CK_a[1] to CK_a[7] in sequence.

[0102] refer to Figure 5 , Figure 5 A schematic diagram of the circuit structure of a first delay unit provided in an embodiment of the present invention is shown in FIG. Figure 5 As shown, the first delay unit 41 includes:

[0103] The first multiplexer 412 has two input terminals, a trigger terminal and an output terminal; the trigger terminal is used to receive the trigger signal FS;

[0104] The input end of the first delay unit 41 is connected to one input end of the first multiplexer 412 through a plurality of first buffers 411 connected in series, and the input end of the first delay unit 41 is directly connected to another input end of the first multiplexer 412; the output end of the first multiplexer 412 is the output end of the first delay unit 41.

[0105] The circuit structure of the first delay unit 41 is the same as that of the first dummy delay unit 42 .

[0106] In an embodiment of the present invention, the trigger signal FS includes a first trigger signal 0 and a second trigger signal 1; when the trigger signal FS is the first trigger signal 0, the first multiplexer 412 is controlled to output the input signal A of the first input end; when the trigger signal FS is the second trigger signal 1, the first multiplexer 412 is controlled to output the input signal B of the second input end.

[0107] It should be noted that when all the first delay units 41 input the first trigger signal 0 at the same time, the long delay path is selected, and when all the first delay units 41 input the second trigger signal 1 at the same time, the short delay path is selected.

[0108] In the embodiment of the present invention, X is an odd number, and each of the first delay units 41 outputs a corresponding initial clock signal CK[0:N], including CK_m[x-1] to CK_m[1], CK_0, and CK_a[1] to CK_a[x-1].

[0109] refer to Figure 6 , Figure 6The circuit structure diagram of a clock generation module provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the clock generation module 33 includes:

[0110] The adjustment selection unit 331 (Adjustable Select) is used to perform signal pulse width processing on the X initial clock signals CK[0:N] based on the first control code A[1] to the third control code A[3], and output the first clock signal CK_A and the second clock signal CK_M; specifically, the clock generation module 33 processes the initial clock signals CK[0:N], and the adjustment selection unit 331 selects a suitable signal from the initial clock signals CK[0:N] as the first clock signal CK_A and the second clock signal CK_M;

[0111] A second multiplexer 332 has two input terminals, a trigger terminal and an output terminal; the two input terminals of the second multiplexer 332 are respectively input with the first clock signal CK_A and the second clock signal CK_M; the second multiplexer 332 is used for selecting to output the first clock signal CK_A or the second clock signal CK_M through its output terminal based on the fourth control code A[4] connected to its trigger terminal;

[0112] A matching delay line 333 (Matching Delay), the matching delay line 333 is used to output the falling edge (Fall_edge) of the edge combiner 335 based on the initial clock signal CK[0:N] (ie, CK_0) output by the first delay unit 41 of the xth stage; x=(X+1) / 2;

[0113] a first inverter 334, wherein the first inverter 334 is used to output a rising edge (Rise_edge) of the edge combiner 335 based on an output signal of the second multiplexer 332;

[0114] The edge combiner 335 outputs the target clock signal Clk_out based on the output signals of the matching delay line 333 and the first inverter 334; the duty cycle control signal dccc (duty cycle control code) includes a first control code A[1] to a fourth control code A[4].

[0115] In the embodiment of the present invention, the clock generation module 33 processes the clock signals with the same phase interval output by the delay module 32, and the clock signal CK_0 at the middle phase is input to the falling edge (Fall_edge) of the edge combiner 335 to generate the falling edge of Clk_out. In the adjustment selection unit 331, taking the four-bit control codes A[4], A[3], A[2] and A[1] as an example, the clock signal C of the n delay units away from the clock signal CK_0 is selected by the control codes A[1], A[2] and A[3]. K_m[n] and CK_a[n] are output as CK_M and CK_A respectively. If the fourth control code A[4] is 1, the rising edge (Rise_edge) of CK_M input to the edge combiner 335 is selected, indicating a reduction in the duty cycle. If the fourth control code A[4] is 0, CK_A is selected, indicating an increase in the duty cycle. The edge combiner 335 combines the rising edge Fall_edge and the rising edge Rise_edge of the input signals to output a target clock signal Clk_out with a desired duty cycle.

[0116] It should be noted that the number of control code bits is not limited to four bits and can be changed according to design requirements. If the number of control code bits increases, the number of delay units in the delay module will increase, and vice versa.

[0117] refer to Figure 7 , Figure 7 A schematic diagram of the circuit structure of the adjustment selection unit provided in an embodiment of the present invention is shown in FIG. Figure 7 As shown, the adjustment selection unit 331 includes:

[0118] Two third inverters 51, which are respectively a first-stage third inverter for outputting the first clock signal CK_A and a second-stage third inverter for outputting the second clock signal CK_M;

[0119] X second inverters 52, the X second inverters 52 are sequentially the 1st-stage second inverter to the Xth-stage second inverter; the input end of the pth-stage second inverter is connected to the output end of the pth-stage first delay unit 41, where p is a positive integer not greater than X;

[0120] X switch elements 53, the X switch elements 53 are sequentially from the 1st switch element to the Xth switch element; the input end of the pth switch element is connected to the output end of the pth second inverter 52; the output ends of the 1st switch element 53 to the x-1th switch element 53 are all connected to the input end of the 1st third inverter 51; the output ends of the xth switch element 53 to the Xth switch element 53 are all connected to the 2nd third inverter 52. Wherein, the switch element 53 includes a transmission gate.

[0121] Furthermore, the adjustment selection unit 331 further includes: X-1 fourth inverters 54;

[0122] The input ends of the 1st-stage second inverter 52 to the x-1th-stage second inverter and the input ends of the x+1th-stage second inverter to the xth-stage second inverter are respectively connected to an input end of the fourth inverter 54, and the output ends of the fourth inverter 54 are both floating.

[0123] In the embodiment of the present invention, the control signals of the switch elements 53 are generated by the same decoder. If X=15, 15 switch elements are required. The 8th-level switch element corresponds to a separate control signal Y[0], the 7th-level and 9th-level switches correspond to the control signal Y[1], the 6th-level and 10th-level switch elements correspond to the control signal Y[2]… The 1st-level and 15th-level switch elements correspond to the control signal Y[7]. In this case, the decoder is a three-input 8-output decoder, which can output switch control signals Y[0]-Y[7] based on the input first control code A[1] to the third control code A[3].

[0124] In the embodiment of the present invention, the adjustment selection unit 331 selects corresponding CK_M and CK_A to output according to different control codes.

[0125] The intermediate phase clock signal CK_0 output by the delay module 32 is connected to the matching delay line 333 . To ensure that the delay differences between the clocks output by the delay module 32 are close, the other outputs of the delay module 32 are all added with inverters as the first pseudo delay unit 42 .

[0126] The adjustment selection unit 331 uses a transmission gate composed of complementary NMOS and PMOS transistors, such as the above-mentioned switch element 53. When the selection signal Y changes, the parasitic capacitance of the switch element 53 in the adjustment selection unit 331 changes. In order to avoid the influence of the change of parasitic capacitance on the delay difference of the output clock of the delay module 32, an inverter is added between the switch element 53 in the adjustment selection unit 331 and the output of the delay module 32 to play a buffering and isolating role.

[0127] Assume that input A[2:0] = 011, after passing through the 3_8 decoder, the decoder output Y <3> is 1, and the rest are 0, so CK_M selects to output CK_m[3] which is three delay units to the left of the middle phase CK_0, and CK_A selects to output CK_a[3] which is three delay units to the right of the middle phase CK_0.

[0128] refer to Figure 8 and Fig. 9 , Figure 8 A schematic diagram of the circuit structure of an edge combiner provided in an embodiment of the present invention, Fig. 9This is a waveform diagram of the working principle of the edge combiner provided in an embodiment of the present invention.

[0129] like Figure 8 As shown, the edge combiner 335 includes:

[0130] The RS flip-flop 61 has two input terminals and one output terminal, and the output terminal is used to output the target clock signal Clk_out;

[0131] Two short pulse generators 62;

[0132] An input end of the short pulse generator 62 is connected to the output end of the matching delay line 333, and an output end thereof is connected to an input end R of the RS trigger 61;

[0133] Another input terminal of the short pulse generator 62 is connected to the output terminal of the first inverter 334 , and an output terminal thereof is connected to another input terminal S of the RS trigger 61 .

[0134] In the embodiment of the present invention, the short pulse generator 62 (SPG) generates a short pulse signal that coincides with the rising edge of the input signal but has a narrower pulse width. The short pulse signal input to the input terminal R of the RS trigger 61 triggers the falling edge (Fall_edge) of the target clock signal Clk_out, and the short pulse signal input to the input terminal S triggers the rising edge (Rise_edge) of the target clock signal Clk_out.

[0135] Fig. 9 The working principle waveform diagram shows the working process of the edge combiner 335 outputting the target clock signal Clk_out. The signals input to Fall_edge and Rise_edge generate short pulse signals after passing through the short pulse generator 62 (SPG). According to the truth table of the RS trigger 61, when S=1 and R=0, the output is high. When S and R are both 0, the output remains unchanged. When S=0 and R=1, the output is low. In this way, the target clock signal Clk_out with an adjustable duty cycle can be obtained by changing the position of the rising edge of the input terminal R and the input terminal S signal.

[0136] refer to Fig.10 , Fig.10 A schematic diagram of the circuit structure of a short pulse generator provided in an embodiment of the present invention.

[0137] like Fig.10As shown, the short pulse generator 62 includes: PMOS621, a first NMOS622, a second NMOS623 and a fifth inverter 624; the source of the PMOS621 is connected to the power supply, the gate thereof is connected to the gate of the first NMOS622, and the drain thereof is connected to the drain of the first NMOS622; the input end of the fifth inverter 624 is connected to the drains of the PMOS621 and the first NMOS622, and the output end thereof is connected to the output end of the short pulse generator 62; a plurality of sixth inverters 625 are connected in series between the input end of the short pulse generator 62 and the gate of the first NMOS622; the input end of the short pulse generator 62 is directly connected to the gate of the second NMOS623; the source of the second NMOS623 is grounded, and the drain thereof is connected to the source of the first NMOS622.

[0138] refer to Fig.11 , Fig.11 A schematic diagram of the circuit structure of a frequency discriminator module provided in an embodiment of the present invention is shown in FIG. Fig.11 As shown, the frequency discriminator module 31 includes:

[0139] A half frequency divider 311, used for dividing the input signal Clk_in by two to form a first signal and a second signal;

[0140] A second buffer 312, used for buffering the second signal;

[0141] A delay trigger submodule 313, configured to output a plurality of third signals based on the reset signal R, the first signal and the buffered second signal;

[0142] The output submodule 314 is used to perform logic processing on the third signal and output the trigger signal FS.

[0143] The delayed trigger submodule 313 outputs Y third signals, which are the 1st-level third signal to the Yth-level third signal, such as Y=5, corresponding to five third signals N1-N5, and Y is a positive integer greater than 1.

[0144] like Fig.11 As shown, the delay trigger submodule 313 includes:

[0145] There are Y second delay units 71, which are the 1st-level second delay unit to the Yth-level second delay unit in sequence, the input end of the 1st-level second delay unit is connected to the first signal, the output end of the jth-level second delay unit is connected to the input end of the j+1th-level second delay unit, and j is a positive integer less than Y; wherein, the delay time of the 1st-level second delay unit is delay1, and the delay time of the 2nd to Yth-level second delay units is delay2, and delay1 and delay2 are different.

[0146] Y first AND gates 72, each of which has three input terminals; the Y first AND gates 72 are sequentially the first AND gate of the 1st stage to the first AND gate of the Yth stage; one input terminal of the first AND gate of the 1st stage is connected to the power supply, and the other two input terminals are respectively connected to the output terminal of the second buffer 312 and the output terminal of the second delay unit of the 1st stage; among the first AND gates of the jth stage to the first AND gates of the Yth stage, one input terminal of the first AND gate of the j+1th stage is connected to the output terminal of the first AND gate of the jth stage, and the other two input terminals of the first AND gate of the j+1th stage are respectively connected to the output terminal of the second buffer 312 and the output terminal of the second delay unit of the j+1th stage;

[0147] Y D flip-flops 73, which are the 1st-level D flip-flops to the Yth-level D flip-flops in sequence; the input terminal D of the jth-level D flip-flop is connected to the power supply, its in-phase output terminal Q outputs the jth-level third signal, its clock input terminal Clk is connected to the output terminal of the jth-level first AND gate 72, and its reset terminal Reset is connected to the reset signal R.

[0148] The delay trigger submodule 313 outputs Y third signals, and the Y third signals are sequentially the first-level third signal to the Y-th-level third signal, and Y is a positive integer greater than 1;

[0149] like Fig.11 As shown, the output submodule 314 includes:

[0150] Y-1 seventh inverters 74, wherein the Y-1 seventh inverters 74 are sequentially the 1st-stage seventh inverter to the Y-1th-stage seventh inverter;

[0151] Y-1 second AND gates 75, each of which has a first input terminal and a second input terminal; the Y-1 second AND gates 75 are sequentially a first-stage second AND gate to a Y-1-stage second AND gate;

[0152] An OR gate 76, the OR gate 76 is used to output the trigger signal FS based on the output signals of the Y-1 second AND gates 75;

[0153] Among them, the j-th level third signal is directly connected to the first input terminal of the j-th level second AND gate; the j+1-th level third signal is inverted by the j-th level seventh inverter and then connected to the j-th level second AND gate.

[0154] In the embodiment of the present invention, the input signal Clk_in is first passed through the half frequency divider 311 to determine a 50% duty cycle to avoid detection errors; if f max is the highest frequency of the system, then the delay time of the second delay unit 71 of the first stage must be less than or equal to f max cycle time, when the input frequency is lower than f max When fc is the intermediate frequency point between high frequency and low frequency, the sum of the delays of the first-stage second delay unit 71 and the four-fold second-stage second delay unit 71 is the clock period of fc. max When the frequency of the input signal Clk_in is between fc and fc, at least one of N1-N5 is 0, then the output of the trigger signal FS is 1; when the frequency of the input signal Clk_in is lower than fc, N1-N5 are all 1, then the output of FS is 0.

[0155] Assume f max is 1.5GHz, fc is 800MHz, then the delay time of the second delay unit 71 of the 1st stage is 666ps, and the delay time of the second delay unit 71 from the 2nd stage to the Yth stage is 146ps; if the clock frequency of the input signal Clk_in is 1GHz, because 1ns=666ps+2x146ps+42ps, N1, N2 and N3 are all 1, N4 and N5 are 0, and the trigger signal FS output is 1, then the short delay path is selected.

[0156] refer to Fig.12 , Fig.12 The following is a waveform diagram showing the working principle of an adjustable duty cycle circuit provided by an embodiment of the present invention. Fig.12 As shown, the R signal changes from high to low, the circuit starts to work, and the frequency detector module detects that the frequency of the input signal Clk_in is at f maxand fc, the trigger signal FS output is 1, and the short delay path is selected; A[2:0]=101, after passing through the delay module 32, CK_A and CK_M output clock signals that are five delay units away from the middle phase CK_0, A[4]=1 means increasing the duty cycle, and selecting the CK_A signal as the rising edge (Rise_edge) output; after matching the delay line and adjusting the selection unit, CK_0 and CK_A are sent to the falling edge (Fall_edge) and rising edge (Rise_edge) ports of the edge combiner, and after the short pulse generator (SPG) generates a short pulse signal, its rising edge triggers the R and S ends of the RS trigger respectively, and finally outputs the target clock signal Clk_out with the desired duty cycle.

[0157] In the embodiment of the present invention, the duty cycle of the target clock signal Clk_out can be adjusted by changing the size of A[2:0], and the direction of the duty cycle adjustment can be achieved by changing the size of A[4].

[0158] As shown in Table 1 below, Table 1 is a performance description of the adjustable duty cycle circuit in the embodiment of the present invention under the 28nm process. Taking the use of 28nm process and 0.9V power supply voltage as an example, according to the previous analysis and the performance description of the adjustable duty cycle circuit under the 28nm process summarized in Table 1, the circuit can work normally at the 533MHz (1.875ns), 600MHz (1.667ns), 667MHz (1.5ns), 733MHz (1.364ns) and 800MHz (1.25ns) frequency points required for duty cycle adjustment specified in the ONFI4.2 protocol. Since the circuit adjusts the duty cycle in frequency bands, the circuit can also meet the requirements of the future ONFI protocol for higher operating frequencies. The circuit in Table 1 can still reach a maximum frequency of 1.5GHz under the Worst condition, which can meet the ultra-high-speed transmission requirements of 3.0G MT / s of NAND memory chips in the future.

[0159]

[0160]

[0161] Table 1

[0162] In the embodiment of the present invention, the duty cycle adjustment is realized by using an open loop method, and the calibration time required is short. The circuit in Table 1 can output the desired duty cycle clock within four clock cycles. The frequency is segmented by using a frequency discriminator module, and a suitable delay path is automatically selected, and then the clock signal with the same phase difference generated by the delay path is processed, which can meet the clock duty cycle adjustment function for a wide frequency range in ONFI4.2 and future ONFI protocols. Compared with the manual switching delay chain method, the frequency discriminator module is used to automatically select the frequency switching point that can be automatically adjusted according to the PVT condition, and a more suitable delay path under the corresponding PVT is selected, so that the output calibration error is smaller, and the calibration error of the circuit in Table 1 can be controlled within 1.5% in the entire operating frequency range. The circuit structure complexity of the present invention is low, and the resources occupied in the overall DDR interface circuit are relatively small. It can not only cover the frequency points required in the ONFI4.2 protocol, but also can be extended to a higher frequency range to meet the high-speed requirements of the next generation ONFI protocol.

[0163] From the above description, it can be seen that in the adjustable duty cycle circuit provided by the technical solution of the present invention, the frequency of the input signal is automatically determined by the frequency discriminator module, and a trigger signal is output based on the frequency of the input signal and the reset signal. The delay module automatically selects a suitable long delay path or short delay path based on the trigger signal, delays the input signal, and outputs an initial clock signal. After determining the delay path, the clock generation module performs signal pulse width processing on the initial clock signal based on the duty cycle control signal, and finally outputs a target clock signal with a preset duty cycle, thereby being able to more accurately control the duty cycle of the clock signal and improve the speed and accuracy of data transmission.

[0164] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0165] It should be noted that in the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0166] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0167] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adjustable duty cycle circuit, characterized in that: The adjustable duty cycle circuit comprises: A frequency discriminator module, the frequency discriminator module is used to output a trigger signal based on the frequency of the input signal and a reset signal; A delay module, the delay module having a long delay path and a short delay path, for responding to the trigger signal, selecting the long delay path or the short delay path, delaying the input signal, and outputting an initial clock signal; A clock generation module, the clock generation module is used to perform signal pulse width processing on the initial clock signal based on the duty cycle control signal, and output a target clock signal with a preset duty cycle; The delay module includes: X first delay units and one first pseudo delay unit, the first delay unit has the same circuit structure as the first pseudo delay unit, X is a positive integer greater than 1; the X first delay units are sequentially from the 1st-stage first delay unit to the Xth-stage first delay unit; the input end of the 1st-stage first delay unit inputs the input signal; the output end of the i-1th-stage first delay unit is connected to the input end of the i-stage first delay unit, i is a positive integer greater than 1 and not greater than X; the output ends of the 1st-stage first delay unit to the Xth-stage first delay unit are respectively connected to the clock generation module; the input end of the first pseudo delay unit is connected to the output end of the Xth-stage first delay unit, and the output end of the first pseudo delay unit is floating.

2. The adjustable duty cycle circuit according to claim 1, characterized in that: The first delay unit comprises: A first multiplexer having two input terminals, a trigger terminal and an output terminal; the trigger terminal is used to receive the trigger signal; The input end of the first delay unit is connected to one input end of the first multiplexer through a plurality of first buffers connected in series, and the input end of the first delay unit is directly connected to another input end of the first multiplexer; the output end of the first multiplexer is the output end of the first delay unit.

3. The adjustable duty cycle circuit according to claim 1, characterized in that: X is an odd number, and each of the first delay units correspondingly outputs one of the initial clock signals; The clock generation module comprises: an adjustment selection unit, configured to perform signal pulse width processing on the X initial clock signals based on the first control code to the third control code, and output a first clock signal and a second clock signal; A second multiplexer having two input terminals, a trigger terminal and an output terminal; the two input terminals of the second multiplexer are respectively input with the first clock signal and the second clock signal; the second multiplexer is used for selecting to output the first clock signal or the second clock signal through its output terminal based on a fourth control code connected to its trigger terminal; A matched delay line, the matched delay line being used to output a falling edge of an edge combiner based on an initial clock signal output by the first delay unit of the xth stage; x=(X+1) / 2; a first inverter, the first inverter being used to output a rising edge of the edge combiner based on an output signal of the second multiplexer; Wherein, the edge combiner outputs the target clock signal based on the output signal of the matching delay line and the first inverter; and the duty cycle control signal includes the first control code to the fourth control code.

4. The adjustable duty cycle circuit according to claim 3, characterized in that: The adjustment selection unit comprises: two third inverters, namely a first-stage third inverter for outputting the first clock signal and a second-stage third inverter for outputting the second clock signal; X second inverters, the X second inverters are sequentially the first-stage second inverter to the X-stage second inverter; the input end of the p-th-stage second inverter is connected to the output end of the p-th-stage first delay unit, and p is a positive integer not greater than X; X switch elements, the X switch elements are sequentially from the 1st-stage switch element to the Xth-stage switch element; the input end of the pth-stage switch element is connected to the output end of the pth-stage second inverter; the output ends of the 1st-stage switch element to the x-1th-stage switch element are all connected to the input end of the 1st-stage third inverter; the output ends of the xth-stage switch element to the Xth-stage switch element are all connected to the 2nd-stage third inverter.

5. The adjustable duty cycle circuit according to claim 4, characterized in that: The adjustment selection unit further includes: X-1 fourth inverters; The input ends of the 1st to x-1th second inverters and the input ends of the x+1th to xth second inverters are respectively connected to an input end of the fourth inverter, and the output ends of the fourth inverters are both floating.

6. The adjustable duty cycle circuit according to claim 3, characterized in that: The edge combiner comprises: An RS flip-flop having two input terminals and one output terminal, wherein the output terminal is used to output the target clock signal; two short pulse generators; An input end of the short pulse generator is connected to the output end of the matching delay line, and an output end of the short pulse generator is connected to an input end of the RS trigger; Another input terminal of the short pulse generator is connected to the output terminal of the first inverter, and an output terminal thereof is connected to another input terminal of the RS trigger.

7. The adjustable duty cycle circuit according to claim 6, characterized in that: The short pulse generator comprises: a PMOS, a first NMOS, a second NMOS and a fifth inverter; The source of the PMOS is connected to a power source, the gate of the PMOS is connected to the gate of the first NMOS, and the drain of the PMOS is connected to the drain of the first NMOS; The input end of the fifth inverter is connected to the drain of the PMOS, and the output end thereof is connected to the output end of the short pulse generator; A plurality of sixth inverters are connected in series between the input end of the short pulse generator and the gate of the first NMOS; the input end of the short pulse generator is directly connected to the gate of the second NMOS; The source of the second NMOS is grounded, and the drain of the second NMOS is connected to the source of the first NMOS.

8. The adjustable duty cycle circuit according to claim 1, characterized in that: The frequency discriminator module comprises: A half frequency divider, used for dividing the input signal into two frequencies to form a first signal and a second signal; A second buffer, used for buffering the second signal; a delay trigger submodule, configured to output a plurality of third signals based on the reset signal, the first signal and the buffered second signal; The output submodule is used to perform logic processing on the third signal and output the trigger signal.

9. The adjustable duty cycle circuit according to claim 8, characterized in that: The delay trigger submodule outputs Y third signals, and the Y third signals are sequentially the first-level third signal to the Y-th-level third signal, and Y is a positive integer greater than 1; the delay trigger submodule includes: Y second delay units, the Y second delay units are sequentially a 1st-stage second delay unit to a Yth-stage second delay unit, an input end of the 1st-stage second delay unit is connected to the first signal, an output end of the jth-stage second delay unit is connected to an input end of the j+1th-stage second delay unit, and j is a positive integer less than Y; Y first AND gates, each of which has three input terminals; the Y first AND gates are sequentially the first AND gate of the 1st stage to the first AND gate of the Yth stage; one input terminal of the first AND gate of the 1st stage is connected to a power supply, and the other two input terminals are respectively connected to the output terminal of the second buffer and the output terminal of the second delay unit of the 1st stage; among the first AND gates of the jth stage to the first AND gates of the Yth stage, one input terminal of the first AND gate of the j+1th stage is connected to the output terminal of the first AND gate of the jth stage, and the other two input terminals of the first AND gate of the j+1th stage are respectively connected to the output terminal of the second buffer and the output terminal of the second delay unit of the j+1th stage; Y D flip-flops, which are the 1st-level D flip-flop to the Yth-level D flip-flop in sequence; the input terminal D of the j-th-level D flip-flop is connected to the power supply, its in-phase output terminal Q outputs the j-th-level third signal, its clock input terminal is connected to the output terminal of the j-th-level first AND gate, and the reset terminal of the j-th-level D flip-flop is connected to the reset signal R.

10. The adjustable duty cycle circuit according to claim 8, characterized in that: The delay trigger submodule outputs Y third signals, where the Y third signals are the first-level third signal to the Y-th-level third signal in sequence, and Y is a positive integer greater than 1; The output submodule comprises: Y-1 seventh inverters, the Y-1 seventh inverters are sequentially a 1st-stage seventh inverter to a Y-1th-stage seventh inverter; Y-1 second AND gates, each of which has a first input terminal and a second input terminal; the Y-1 second AND gates are sequentially the first-stage second AND gate to the Y-1-stage second AND gate; An OR gate, the OR gate being used to output the trigger signal based on the output signals of the Y-1 second AND gates; Among them, the j-th level third signal is directly connected to the first input terminal of the j-th level second AND gate; the j+1-th level third signal is inverted by the j-th level seventh inverter and then connected to the j-th level second AND gate.

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