A GIP circuit and driving method for improving display stability

Abstract

The present invention discloses a GIP circuit and driving method for improving display stability, wherein the GIP circuit includes transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, capacitor C1, capacitor C2 and capacitor C3; the above technical solution outputs the data of the gate line G(n) through transistor T4, and uses transistor T8, transistor T9 and transistor T10 to control the potential of the Q2 node. It also prevents leakage of the Q1 node, so that the GIP output signal of the subsequent output stage of the GIP circuit of this level is normal, which solves the problem of dark lines in the display of the general GIP circuit after touch. This structure solves the problem of distortion of the output signal of the GIP circuit in different touch modes, can improve the display quality and touch quality of the display panel, enhance the look and feel of the display panel, and thus improve the competitiveness of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a GIP circuit and a driving method for improving display stability. Background Art

[0002] At present, touch technology is mainly divided into On-Cell technology and In-Cell technology. On-Cell technology refers to embedding the touch screen between the display screen and the polarizer, that is, equipping the display panel with a touch sensor; In-cell technology refers to embedding the touch panel function into the array substrate. In this way, the thickness of the In-Cell panel is reduced due to the lack of a touch screen layer.

[0003] The display panel using In-Cell technology has the advantages of lighter product, lower thickness, better light transmittance, reduced screen bonding time, and improved production efficiency. However, there are some problems when the display panel using In-Cell technology uses different touch methods.

[0004] In-Cell display panels have two modes when they are in touch display mode: Figure 1 The first mode is called Long V touch display mode. When displaying a frame, Long V touch display mode divides it into Display Time and Blanking Time (touch is inserted into Blanking Time), that is, Touch is placed after Display, and the sum of the two time periods is the time of a frame. Figure 2 The second mode can be called the Long H touch display mode. The Long H touch display mode inserts Touch into the Display in batches when displaying a frame of the picture, that is, a frame of the picture is divided into a cycle of Display (i.e. display)-Touch (i.e. touch)-Display-Touch-Display from top to bottom. When the Long H touch display mode is in progress, since the touch stage is inserted into the display stage, when the GIP design is adopted, a touch segment is inserted between the two display segments, so that the Q node of the GIP circuit of the second display segment has to maintain a high potential for a long time (about 200us). Due to the leakage problem of the transistor, the Q node of the second display stage will have a large leakage problem, so that the Q node of the first row of the GIP in the second display stage and the Q node of the GIP in the first display stage will be greatly different, which may cause the difference in the output signal of the GIP of the display panel, causing the display panel to have the problem of horizontal dark lines. Summary of the invention

[0005] Therefore, it is necessary to provide a GIP circuit and a driving method for improving display stability, so as to solve the problem that the GIP output signal is affected by the leakage of the transistor, resulting in the horizontal dark lines on the display panel.

[0006] To achieve the above object, the present embodiment provides a GIP circuit for improving display stability, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2 and a capacitor C3;

[0007] The control end of the transistor T1 and the control end of the transistor T8 are respectively connected to the gate line G(n-4), the input end of the transistor T1 and the input end of the transistor T8 are respectively connected to the turn-on voltage VGH, the output end of the transistor T1 is connected to the control end of the transistor T4, and the output end of the transistor T8 is connected to the control end of the transistor T9;

[0008] The input end of the transistor T9 is connected to the start voltage VGH, and the output end of the transistor T9 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4;

[0009] The control end of the transistor T2 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, the input end of the transistor T2 is respectively connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are respectively connected to the shutdown voltage VGL;

[0010] The second plate of capacitor C1 is connected to the clock signal CK;

[0011] The input end of the transistor T3 is connected to a line connecting the output end of the transistor T1 and the control end of the transistor T4;

[0012] The input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G(n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to the line connecting the output end of the transistor T4 and the gate line G(n);

[0013] The input end of the transistor T6 and the input end of the transistor T5 are respectively connected to the gate line G(n), the control end of the transistor T5 is connected to the clock signal CKB, and the output end of the transistor T5 is connected to the shutdown voltage VGL;

[0014] The control end of the transistor T7 is connected to the gate line G(n+4), the input end of the transistor T7 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, and the output end of the transistor T7 is connected to the shutdown voltage VGL;

[0015] The control end of the transistor T10 is connected to the clock signal CK, the input end of the transistor T10 is connected to the line connecting the output end of the transistor T8 and the control end of the transistor T9, and the output end of the transistor T10 is connected to the shutdown voltage VGL;

[0016] The first plate of the capacitor C3 is connected to the output end of the transistor T8, and the second plate of the capacitor C3 is used to connect external components.

[0017] Further, the input end of the transistor T1, the input end of the transistor T2, the input end of the transistor T3, the input end of the transistor T4, the input end of the transistor T5, the input end of the transistor T6, the input end of the transistor T7, the input end of the transistor T8, the input end of the transistor T9 and the input end of the transistor T10 are all drains.

[0018] Further, the transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 , the transistor T9 and the transistor T10 are all thin film transistors.

[0019] Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the capacitor C1 and the capacitor C2 are all arranged on the display panel.

[0020] Furthermore, the display panel is an In-Cell display panel.

[0021] This embodiment further provides a GIP circuit driving method for improving display stability, which is applied to a GIP circuit for improving display stability described in any one of the above embodiments, including the following steps in a touch control stage:

[0022] In the touch pre-charge stage, the start voltage VGH is written to a high potential, the close voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a high potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential;

[0023] In the touch control voltage stabilization stage, the start voltage VGH is written to a high potential, the shutdown voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential;

[0024] In the touch output stage, the start voltage VGH is written to a high potential, the close voltage VGL is written to a low potential, the clock signal CK is written to a high potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a high potential, and the gate line G(n+4) is written to a low potential;

[0025] In the touch pull-down stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is sequentially written to a low potential, a high potential, and a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is sequentially written to a high potential and a low potential;

[0026] In the touch pull-down maintenance stage, the turn-on voltage VGH is written to a high potential, the turn-off voltage VGL is written to a low potential, the clock signal CK is cyclically written to a high potential and a low potential in sequence, the clock signal CKB is cyclically written to a low potential and a high potential in sequence, and the gate line G(n-4), the gate line G(n) and the gate line G(n+4) are respectively written to a low potential.

[0027] Furthermore, the display phase steps are also included:

[0028] In the display pre-charge stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a high potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential;

[0029] In the display output stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a high potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a high potential, and the gate line G(n+4) is written to a low potential;

[0030] In the display pull-down stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is sequentially written to a low potential, a high potential and a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is sequentially written to a high potential and a low potential;

[0031] In the display pull-down maintenance stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a high potential and a low potential in sequence, the clock signal CKB is written to a low potential and a high potential in sequence, and the gate line G(n-4), the gate line G(n) and the gate line G(n+4) are written to a low potential respectively.

[0032] Furthermore, within a preset time, the display stage steps and the touch stage steps are cycled in sequence.

[0033] Different from the prior art, the above technical solution outputs the data of the gate line G(n) through transistor T4, and uses transistors T8, T9 and T10 to control the potential of the Q2 node. It can prevent the leakage of the Q1 node, so that the GIP output signal of the subsequent output stage of the GIP circuit of this level is normal, and solves the problem of dark lines in the display of the general GIP circuit after touch. This structure solves the problem of distortion of the output signal of the GIP circuit in different touch modes, and provides a solution for realizing a high-definition display screen, which can improve the display quality and touch quality of the display panel, enhance the look and feel of the display panel, and thus improve the competitiveness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The timing diagram of the Long V touch display mode described in the background technology;

[0035] Figure 2 The timing diagram of the Long H touch display mode described in the background technology;

[0036] Figure 3 is a schematic diagram of the structure of the GIP circuit described in this embodiment;

[0037] Figure 4 is a timing diagram of the touch control stage described in this embodiment;

[0038] Figure 5 is a timing diagram of the display phase described in this embodiment;

[0039] Figure 6 It is a schematic diagram of the structure of the GIP circuit in the touch pre-charging stage according to this embodiment;

[0040] Figure 7 It is a schematic diagram of the structure of the GIP circuit in the touch control voltage stabilization stage according to this embodiment;

[0041] Figure 8 is a schematic diagram of the structure of the GIP circuit in the touch output stage of this embodiment;

[0042] Fig. 9 It is a schematic diagram of the structure of the GIP circuit in the touch pull-down stage described in this embodiment;

[0043] Fig.10 FIG. 4 is a schematic diagram of the structure of the GIP circuit in the touch pull-down maintaining stage according to the present embodiment. DETAILED DESCRIPTION

[0044] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0045] See also Figures 3 to 10, this embodiment provides a GIP circuit for improving display stability, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2 and a capacitor C3. The control end of the transistor T1 and the control end of the transistor T8 are respectively connected to the gate line G(n-4), the input end of the transistor T1 and the input end of the transistor T8 are respectively connected to the start voltage VGH, the output end of the transistor T1 is connected to the control end of the transistor T4, and the output end of the transistor T8 is connected to the control end of the transistor T9. The input end of the transistor T9 is connected to the start voltage VGH, and the output end of the transistor T9 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4. The control end of the transistor T2 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, the input end of the transistor T2 is respectively connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are respectively connected to the shutdown voltage VGL. The second plate of the capacitor C1 is connected to the clock signal CK. The input end of the transistor T3 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4. The input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G(n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to the line connecting the output end of the transistor T4 and the gate line G(n). The input end of the transistor T6 and the input end of the transistor T5 are respectively connected to the gate line G(n), the control end of the transistor T5 is connected to the clock signal CKB, and the output end of the transistor T5 is connected to the shutdown voltage VGL. The control end of the transistor T7 is connected to the gate line G(n+4), the input end of the transistor T7 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, and the output end of the transistor T7 is connected to the shutdown voltage VGL. The control end of the transistor T10 is connected to the clock signal CK, the input end of the transistor T10 is connected to the line connecting the output end of the transistor T8 and the control end of the transistor T9, and the output end of the transistor T10 is connected to the shutdown voltage VGL. The first plate of the capacitor C3 is connected to the output end of the transistor T8, and the second plate of the capacitor C3 is used to connect external components.

[0046] The above technical solution outputs the data of the gate line G(n) through transistor T4, and uses transistors T8, T9 and T10 to control the potential of the Q2 node. It can prevent the leakage of the Q1 node, so that the GIP output signal of the subsequent output stage of the GIP circuit of this level is normal, and solves the problem of dark lines in the display of the general GIP circuit after touch. This structure solves the problem of distortion of the output signal of the GIP circuit in different touch modes, and provides a solution for realizing a high-definition display screen, which can improve the display quality and touch quality of the display panel, enhance the look and feel of the display panel, and thus improve the competitiveness of the display panel.

[0047] In this embodiment, the transistor is used as a variable current switch, which can control the output current based on the input voltage. The transistors that can be used in this application include thin film transistors (Thin Film Transistor, abbreviated as TFT), MOS tubes (i.e. metal-oxide-semiconductor field effect transistors, abbreviated as MOSFET), junction field effect tubes, etc. Preferably, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9 and the transistor T10 are all thin film transistors. Using thin film transistors as switches to drive liquid crystal pixels can achieve the characteristics of high speed, high brightness and high contrast.

[0048] In this embodiment, the input end of the transistor T1, the input end of the transistor T2, the input end of the transistor T3, the input end of the transistor T4, the input end of the transistor T5, the input end of the transistor T6, the input end of the transistor T7, the input end of the transistor T8, the input end of the transistor T9 and the input end of the transistor T10 are all drains, the output ends of the above 10 transistors are sources, and the control ends of the above 10 transistors are gates.

[0049] In this embodiment, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the capacitor C1 and the capacitor C2 are all arranged on the display panel. In a preferred embodiment, the display panel is an in-cell display panel. In-cell technology refers to embedding the touch panel function into the array substrate, so that the thickness of the In-Cell panel is reduced due to the lack of a layer of touch screen thickness. The display panel using In-Cell technology has the advantages of lighter product, lower thickness, better light transmittance, reduced screen bonding time, and improved production efficiency.

[0050] In this embodiment, the display panel may be an LCD display panel, where LCD is short for Liquid Crystal Display, which means liquid crystal display in Chinese. The advantages of LCD display panels are small size, low power consumption and high brightness. Alternatively, in some embodiments, the GIP circuit may also be arranged on an OLED display panel, where OLED is short for Organic Light-Emitting Diode, which means organic electric laser display or organic light-emitting semiconductor in Chinese. OLED display panels have the characteristics of being light and thin, high brightness, low power consumption, fast response, high clarity, good flexibility, and high luminous efficiency, and can meet consumers' new demands for display technology.

[0051] It should be noted that VG(n) represents the voltage on the gate line G(n). There are multiple such GIP circuits in the display panel, each of which is connected to a sub-pixel through the gate line G(n) to drive the sub-pixel, and each GIP circuit is connected to the driver IC through the gate line G(n+4) and the gate line G(n-4), so that the driver IC drives the sub-pixel through the GIP circuit. Multiple sub-pixels are arranged in an array on the display panel, and a GIP circuit is provided on one side of each sub-pixel.

[0052] See also Figure 3 and Figure 4 This embodiment provides a GIP circuit driving method for improving display stability, which is applied to a GIP circuit for improving display stability described in any of the above embodiments, including the touch stage steps: in the touch pre-charge stage (i.e., in the touch pre-charge stage); Figure 4 The gate line G(n-4) is written with a high potential, the gate line G(n) is written with a low potential, and the gate line G(n+4) is written with a low potential. In the touch control voltage stabilization stage (i.e., in Figure 4 The upper part is marked as a2), the opening voltage VGH is written in high potential, the closing voltage VGL is written in low potential, the clock signal CK is written in low potential, the clock signal CKB is written in low potential, the gate line G(n-4) is written in low potential, the gate line G(n) is written in low potential, and the gate line G(n+4) is written in low potential; in the touch output stage (i.e., in Figure 4 The upper part is marked as a3), the opening voltage VGH is written in high potential, the closing voltage VGL is written in low potential, the clock signal CK is written in high potential, the clock signal CKB is written in low potential, the gate line G(n-4) is written in low potential, the gate line G(n) is written in high potential, and the gate line G(n+4) is written in low potential; in the touch pull-down stage (i.e., in Figure 4The upper part is marked as a4), the opening voltage VGH is written in high potential, the closing voltage VGL is written in low potential, the clock signal CK is written in low potential, the clock signal CKB is written in low potential, high potential and low potential in sequence, the gate line G(n-4) is written in low potential, the gate line G(n) is written in low potential, the gate line G(n+4) is written in high potential and low potential in sequence; in the touch pull-down maintenance stage (i.e., in Figure 4 Marked as a5), the turn-on voltage VGH is written to a high potential, the turn-off voltage VGL is written to a low potential, the clock signal CK is written to a high potential and a low potential in sequence, the clock signal CKB is written to a low potential and a high potential in sequence, and the gate line G(n-4), the gate line G(n) and the gate line G(n+4) are written to a low potential respectively.

[0053] See also Figure 3 and Figure 5 In this embodiment, the display stage step is also included: in the display pre-charge stage (i.e. Figure 5 The gate line G(n-4) is written with a high potential, the gate line G(n) is written with a low potential, and the gate line G(n+4) is written with a low potential. In the display output stage (i.e., in the Figure 5 The gate line G(n-4) is written with a low potential, the gate line G(n) is written with a high potential, the gate line G(n+4) is written with a low potential; in the display pull-down stage (i.e., in the Figure 5 The gate line G(n-4) is written with a low potential, the gate line G(n) is written with a low potential, the gate line G(n+4) is written with a high potential and a low potential in sequence; in the display pull-down maintenance stage (i.e., in the Figure 5 The above is marked as t4), the turn-on voltage VGH is written to a high potential, the turn-off voltage VGL is written to a low potential, the clock signal CK is written to a high potential and a low potential in sequence, the clock signal CKB is written to a low potential and a high potential in sequence, and the gate lines G(n-4), G(n) and G(n+4) are written to low potentials respectively.

[0054] It should be noted that within the preset time, the display stage step and the touch stage step are cycled in sequence. The display stage step and the touch stage step are cycled in sequence. This preset time can be the time of a frame of the picture. The display panel operates according to the display stage, touch stage, display stage, touch stage... to realize the Long H touch display mode described above. Of course, this preset time can be half a frame, two frames, ten frames, etc.

[0055] See also Figure 3 , Figure 4 and Figure 6 , in the touch precharge stage of the GIP circuit (i.e. Figure 4 The gate line G(n-4) and the turn-on voltage VGH are at high potential, and the transistors T1 and T8 are turned on. VGH charges the Q1 node and the Q2 node through the transistors T1 and T8, so that the potentials at the Q1 node and the Q2 node rise to high potentials, and control the transistors T2, T4, and T9 to turn on. The clock signal CK and the turn-off voltage VGL are at low potentials, and the gate line G(n) and the P node are pulled down through the transistors T2 and T4, and the potentials of the two are maintained at low potentials. It should be noted that the touch pre-charge stage (i.e., in Figure 4 The working mode and display pre-charge phase (marked as a1) Figure 5 The operation is the same as that of the first step (marked as t1).

[0056] See also Figure 3 , Figure 4 and Figure 7 , in this touch control voltage stabilization stage of the GIP circuit (i.e. Figure 4The above is marked as a2) for explanation: the turn-on voltage VGH, the Q1 node and the Q2 node are at high potential, and the transistors T2, T4 and T9 are turned on. The gate line G(n-4), the gate line G(n+4), the clock signal CK, the clock signal CKB, the turn-off voltage VGL and the P node are at low potential, and the transistors T1, T3, T5, T6, T7, T8 and T10 are turned off. The duration of the touch voltage stabilization stage is about 200us, that is, the high potential of the Q1 node of a certain level of the GIP circuit must be maintained at a high potential within 200us. However, the transistors in the existing GIP circuit will leak, which will cause the Q1 node to leak, which will cause the gate line G(n) in the subsequent output stage to output a voltage lower than that of the previous level, which will cause the display panel to have dark line problems in some positions, resulting in poor display effect of the display panel and affecting the quality of the display panel. In the touch stage of the GIP circuit of the present application, the Q2 node is at a high potential, and the transistor T9 is turned on, so that the Q1 node is replenished to the same potential as the turn-on voltage VGH through the transistor T8, thereby preventing leakage of the Q1 node and making the GIP output signal of the subsequent output stage of the GIP circuit of this level normal, thus solving the problem of dark lines displayed in the general GIP circuit after touch.

[0057] See also Figure 3 , Figure 4 and Figure 8 , in the touch output stage of the GIP circuit (i.e. Figure 4 (marked as a3) for explanation: the clock signal CK and the Q1 node are at a high potential, and the transistors T2, T4 and T10 are turned on. The gate line G(n-4), the gate line G(n+4), the shutdown voltage VGL and the clock signal CKB point are at a low potential, and the transistors T1, T3, T5, T6, T7 and T8 are turned off. Since the transistor T10 is turned on, the potential of the Q2 node is pulled down to a low potential by the shutdown voltage VGL through the transistor T10, so that the transistor T9 is turned off. Since the transistor T2 is turned on, the P node is pulled down to a low potential by the shutdown voltage VGL through the transistor T2. Since the transistor T4 is turned on, the clock signal CK is at a high potential, and the gate line G(n) is at a high potential at this time, and the Q1 node is affected by the coupling effect of the capacitor C2 and rises to a potential of 2H, thereby improving the stability of the gate line G(n) output. It should be noted that in the touch output stage (i.e., in Figure 4 The working mode of the display output stage (marked as a3) Figure 5 The operation is the same as that of the first step (marked as t2).

[0058] See also Figure 3 , Figure 4 and Fig. 9, in this touch pull-down stage of the GIP circuit (i.e. Figure 4 The gate line G(n+4), the clock signal CKB and the turn-on voltage VGH are at high potential, and the transistors T5 and T7 are turned on. The gate line G(n-4), the clock signal CK and the turn-off voltage VGL are at low potential, and the transistors T1, T2, T3, T6, T8, T9 and T10 are turned off. Since the Q1 node was at a high potential in the early stage, the transistor T4 is turned on, and the potential of the gate line G(n) is pulled down to a low potential by the clock signal CK and the turn-off voltage VGL through the transistors T4 and T5. At the same time, the potential of the Q1 node is pulled down to a low potential by the turn-off voltage VGL through the transistor T7. Since the clock signal CK is at a low potential at this time, the P node is affected by the coupling of the capacitor C1, and the P node is still at a low potential. It should be noted that in the touch pull-down stage (i.e., in the Figure 4 The working mode of the above mark a4) and the display pull-down stage (i.e. Figure 5 The operation is the same as that of the first step (marked as t3).

[0059] See also Figure 3 , Figure 4 and Fig.10 , in this stage of the touch pull-down maintenance of the GIP circuit (i.e. Figure 4 The P node is coupled by the clock signal CK. When the P point is at a high potential, the transistors T3 and T6 are both turned on, so that the potential of the Q1 node and the potential of the gate line G(n) are pulled down to a low potential by the turn-off voltage VGL through the transistors T3 and T6, respectively. When the clock signal CK is at a high potential, the Q2 node is pulled down to a low potential. It should be noted that the touch pull-down maintenance stage (i.e., in the Figure 4 The working mode of the display pull-down maintenance phase (marked as a5) and the display pull-down maintenance phase (i.e. Figure 5 The operation is the same as that of the first step (marked as t4).

[0060] The above technical solution solves the problem of distortion of the output signal of the GIP circuit under different touch modes, and provides a solution for realizing a high-definition display screen, which can improve the display quality and touch quality of the display panel, enhance the look and feel of the display panel, and thus improve the competitiveness of the display panel.

[0061] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A GIP circuit for improving display stability, characterized in that: including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2 and a capacitor C3; The control end of the transistor T1 and the control end of the transistor T8 are respectively connected to the gate line G(n-4), the input end of the transistor T1 and the input end of the transistor T8 are respectively connected to the turn-on voltage VGH, the output end of the transistor T1 is connected to the control end of the transistor T4, and the output end of the transistor T8 is connected to the control end of the transistor T9; The input end of the transistor T9 is connected to the start voltage VGH, and the output end of the transistor T9 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4; The control end of the transistor T2 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, the input end of the transistor T2 is respectively connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are respectively connected to the shutdown voltage VGL; The second plate of capacitor C1 is connected to the clock signal CK; The input end of the transistor T3 is connected to a line connecting the output end of the transistor T1 and the control end of the transistor T4; The input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G(n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to the line connecting the output end of the transistor T4 and the gate line G(n); The input end of the transistor T6 and the input end of the transistor T5 are respectively connected to the gate line G(n), the control end of the transistor T5 is connected to the clock signal CKB, and the output end of the transistor T5 is connected to the shutdown voltage VGL; The control end of the transistor T7 is connected to the gate line G(n+4), the input end of the transistor T7 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, and the output end of the transistor T7 is connected to the shutdown voltage VGL; The control end of the transistor T10 is connected to the clock signal CK, the input end of the transistor T10 is connected to the line connecting the output end of the transistor T8 and the control end of the transistor T9, and the output end of the transistor T10 is connected to the shutdown voltage VGL; The first plate of the capacitor C3 is connected to the output end of the transistor T8, and the second plate of the capacitor C3 is used to connect external components.

2. A GIP circuit for improving display stability according to claim 1, characterized in that: The input end of the transistor T1, the input end of the transistor T2, the input end of the transistor T3, the input end of the transistor T4, the input end of the transistor T5, the input end of the transistor T6, the input end of the transistor T7, the input end of the transistor T8, the input end of the transistor T9 and the input end of the transistor T10 are all drains.

3. A GIP circuit for improving display stability according to claim 1, characterized in that: The transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 , the transistor T9 and the transistor T10 are all thin film transistors.

4. The GIP circuit for improving display stability according to claim 1, characterized in that: The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the capacitor C1 and the capacitor C2 are all arranged on the display panel.

5. A GIP circuit for improving display stability according to claim 4, characterized in that: The display panel is an In-Cell display panel.

6. A GIP circuit driving method for improving display stability, characterized in that: A GIP circuit for improving display stability as claimed in any one of claims 1 to 5, comprising the following steps in the touch control stage: In the touch pre-charge stage, the start voltage VGH is written to a high potential, the close voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a high potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential; In the touch control voltage stabilization stage, the start voltage VGH is written to a high potential, the shutdown voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential; In the touch output stage, the start voltage VGH is written to a high potential, the close voltage VGL is written to a low potential, the clock signal CK is written to a high potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a high potential, and the gate line G(n+4) is written to a low potential; In the touch pull-down stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is sequentially written to a low potential, a high potential, and a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is sequentially written to a high potential and a low potential; In the touch pull-down maintenance stage, the turn-on voltage VGH is written to a high potential, the turn-off voltage VGL is written to a low potential, the clock signal CK is cyclically written to a high potential and a low potential in sequence, the clock signal CKB is cyclically written to a low potential and a high potential in sequence, and the gate line G(n-4), the gate line G(n) and the gate line G(n+4) are respectively written to a low potential.

7. A GIP circuit driving method for improving display stability according to claim 6, characterized in that: Also includes the display phase steps: In the display pre-charge stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a high potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is written to a low potential; In the display output stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a high potential, the clock signal CKB is written to a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a high potential, and the gate line G(n+4) is written to a low potential; In the display pull-down stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is sequentially written to a low potential, a high potential and a low potential, the gate line G(n-4) is written to a low potential, the gate line G(n) is written to a low potential, and the gate line G(n+4) is sequentially written to a high potential and a low potential; In the display pull-down maintenance stage, the opening voltage VGH is written to a high potential, the closing voltage VGL is written to a low potential, the clock signal CK is written to a high potential and a low potential in sequence, the clock signal CKB is written to a low potential and a high potential in sequence, and the gate line G(n-4), the gate line G(n) and the gate line G(n+4) are written to a low potential respectively.

8. The GIP circuit driving method for improving display stability according to claim 7, characterized in that: Within a preset time, the display stage steps and the touch stage steps are cycled in sequence.

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