Wide Bandgap Semiconductor Devices

Abstract

A metal oxide semiconductor field effect transistor includes: a wide bandgap substrate, a wide bandgap drift layer on the substrate, a plurality of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is divided into a first JFET sub-region and a second JFET sub-region, such that the doping concentration in the first JFET sub-region is different from the doping concentration in the second JFET sub-region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to wide bandgap semiconductor devices having a high channel fill density with a channel maintaining a high blocking voltage and a low on-state resistance. Background Art

[0002] Wide bandgap semiconductor devices are preferred for a variety of applications due to their ability to withstand high blocking voltages, provide low on-state resistance, and operate at higher frequencies and temperatures than their narrow bandgap counterparts. Those skilled in the art will appreciate that the significant advantages provided by wide bandgap semiconductor devices in certain operating aspects are often at the expense of disadvantages in other operating aspects. One such disadvantage is that wide bandgap semiconductor devices are subject to very concentrated electric fields formed therein. These concentrated electric fields, if not properly managed, may damage the device and may further reduce the ability of the wide bandgap semiconductor device to prevent voltage from exceeding a certain level without failing. Therefore, there is a need for wide bandgap semiconductor devices in which the concentration of electric fields is reduced. Summary of the invention

[0003] In one embodiment, a metal oxide semiconductor field effect transistor (MOSFET) includes a wide bandgap substrate, a wide bandgap drift layer on the substrate, a plurality of junction implants in the wide bandgap drift layer, and a junction field effect transistor (JFET) region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, so that the doping concentration in the first JFET sub-region is different from the doping concentration in the second JFET sub-region. By separating the JFET region into a first JFET sub-region and a second JFET sub-region, a trade-off between on-resistance, blocking voltage, and peak electric field can be locally designed for these sub-regions, thereby improving the overall performance of the MOSFET device.

[0004] In one embodiment, the JFET gap in the first JFET sub-region is different from the JFET gap in the second JFET sub-region. In particular, the JFET gap in the first JFET sub-region may be smaller than the JFET gap in the second JFET sub-region. The doping concentration in the first JFET sub-region may be greater than the doping concentration in the second JFET sub-region. The doping concentration in the JFET region may vary between the first JFET sub-region and the second JFET sub-region in a linear, exponential or stepwise manner.

[0005] In one embodiment, the MOSFET device provides less than 2 mΩ-cm 2The MOSFET device can have an area-normalized on-state resistance greater than 370 mm / mm 2 MOS channel filling density.

[0006] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0008] Figure 1 A cross-sectional view of a metal oxide semiconductor field effect transistor (MOSFET) cell according to one embodiment of the present disclosure is shown.

[0009] Figure 2 A top view of a MOSFET device according to one embodiment of the present disclosure is shown.

[0010] Figure 3 A top view of a MOSFET device according to one embodiment of the present disclosure is shown.

[0011] Figure 4 A top view of a MOSFET device according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A top view of a MOSFET device according to one embodiment of the present disclosure is shown.

[0013] Figure 6 A method for manufacturing a MOSFET device according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0014] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the applications of these concepts not specifically proposed herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0015] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to divide an element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intervening element. Similarly, it should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "extending directly onto another element", there is no intervening element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intervening element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intervening element.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0018] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" indicate the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups of the above.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meaning as they do in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless clearly defined in this article.

[0020] Figure 1 A vertical metal oxide semiconductor field effect transistor (MOSFET) cell 10 is shown according to one embodiment of the present disclosure. The MOSFET cell 10 includes a semiconductor stack 12 including a substrate 14 and a drift layer 16 above the substrate 14. The drift layer 16 includes a plurality of junction implants 18, each of which includes a P-well 20 and a source well 22, such that the source well 22 is within and can be encapsulated by the P-well 20. The junction implants 18 are separated from each other by a junction field effect transistor (JFET) region 24, which is defined by the distance between each of the junction implants 18 (referred to as a JFET gap 26). A gate oxide layer 28 is on a surface of the drift layer 16 opposite the substrate 14, such that the gate oxide layer 28 extends between the source wells 22 of each of the junction implants 18. A gate contact 30 is above the gate oxide layer 28. Source contact 32 is on the surface of drift layer 16 opposite substrate 14, such that source contact 32 is over a portion of P well 20 and source well 22 in each junction implant 18. Drain contact 34 is on the surface of substrate 14 opposite drift layer 16.

[0021] like Figure 1 As shown, the substrate 14 is a heavily doped n-type layer. In various embodiments, the doping concentration of the substrate 14 can be between 1×10 18 cm -3 With 1x10 20 cm -3 Between 1x10 19 cm -3 With 1x10 20 cm -3 Between, and between 1x10 18 cm -3 With 1x10 19 cm -3 The drift layer 16 may be an n-type layer having a doping concentration less than that of the substrate 14. In some embodiments, the doping concentration of the drift layer 16 may be between 1×10 14 cm -3 and 1x10 17 cm -3 Between 1x10 15 cm -3 and 1x1017 cm -3 Between 1x10 16 cm -3 and 1x10 17 cm -3 Between 1x10 14 cm -3 and 1x10 16 cm -3 Between, and between 1x10 14 cm -3 and 1x10 15 cm -3 In addition, the doping concentration of the drift layer 16 can be graded so that the doping concentration of the drift layer 16 increases in proportion to the distance from the substrate 14. The grading can be linear, exponential, stepwise, or any other configuration. Typically, the drift layer 16 is grown on the substrate 14 via an epitaxial process. The JFET region 24 can be a highly doped N-type region with a doping concentration of 5x10 15 cm -3 and 2x10 17 cm -3 Between, 5x10 16 cm -3 and 2x10 17 cm -3 Between and 5x10 15 cm -3 and 2x10 16 cm -3 The JFET region 24 may be implanted via an ion implantation process, or may be grown via an epitaxial process (e.g., by first etching a trench in the drift layer 16). The P-well 20 of each junction implant 18 may be a P-type region with a doping concentration of 5x10 15 cm -3 and 5x10 19 cm -3 Between 5x10 16 cm -3 and 5x10 19 cm -3 Between 5x10 17 cm -3 and 5x10 19 cm -3 Between 5x10 18 cm -3 and 5x10 19 cm -3 Between 5x10 15 cm -3 and 5x10 18 cm -3Between 5x10 15 cm -3 and 5x10 17 cm -3 Between, and between 5x10 15 cm -3 and 5x10 16 cm -3 The source well 22 of each junction implant 18 may be a highly doped N-type region with a doping concentration of 5x10 18 cm -3 and 5x10 21 cm -3 Between 5x10 18 cm -3 and 5x10 20 cm -3 Between 5x10 18 cm -3 and 5x10 19 cm -3 Between 5x10 19 cm -3 and 5x10 21 cm -3 Between, and between 5x10 20 cm -3 and 5x10 21 cm -3 The P well 20 and the source well 22 of the junction implant 18 are typically implanted via an ion implantation process.

[0022] Despite Figure 1 MOSFET cell 10 is shown as an NMOS device in which substrate 14 and drift layer 16 are N-type layers, but the principles of the present disclosure are equally applicable to a PMOS device in which substrate 14 and drift layer 16 are P-type layers.

[0023] Although there are many design parameters of a MOSFET device that may affect its performance, two of them are particularly noteworthy for the disclosure discussed herein. The first noteworthy design parameter of the MOSFET cell 10 is the distance between the junction implants 18, or the JFET gap 26. Increasing the JFET gap 26 will reduce the on-resistance of the MOSFET cell 10, but will also reduce its blocking voltage. In addition, increasing the JFET gap 26 will generally increase the peak electric field at the center of the JFET region 24. Reducing the JFET gap 26 will increase the blocking voltage of the MOSFET cell 10, but will also increase its on-resistance. In addition, reducing the JFET gap 26 will generally reduce the peak electric field at the center of the JFET region 24. The second noteworthy design parameter of the MOSFET cell 10 is the doping concentration of the JFET region 24. Increasing the doping concentration of the JFET region 24 will reduce the on-resistance of the MOSFET cell 10, but will also increase the peak electric field at the center of the JFET region 24. Reducing the doping concentration of the JFET region 24 will reduce the peak electric field at the center of the JFET region 24, but will also increase the on-resistance of the MOSFET cell 10. Therefore, both the JFET gap 26 and the doping concentration of the JFET region 24 must be appropriately selected to meet the desired blocking voltage, on-resistance, and peak electric field of the MOSFET cell 10. It is worth noting that if the peak electric field at the center of the JFET region 24 becomes too high, it will crack the gate oxide and destroy the MOSFET cell 10. As described above, the concentration of the electric field is particularly problematic in wide bandgap material systems such as silicon carbide (SiC) devices, which typically have much higher electric fields than narrow bandgap counterparts. Therefore, when designing the MOSFET cell 10, the doping concentrations of the JFET gap 26 and the JFET region 24 are selected to provide the desired relationship between the on-resistance, blocking voltage, and peak electric field.

[0024] It is noteworthy that the MOSFET cell 10 is so named because it is the smallest unit of a larger MOSFET device. A MOSFET device includes hundreds or thousands of MOSFET cells repeated in various geometric configurations. Figure 1The MOSFET cell 10 shown is represented as a two-dimensional cross section. In fact, the MOSFET cell 10 extends into and out of the page as a rectangular cuboid in three dimensions. The MOSFET cell 10 can be mirrored or repeated to extend into and out of the page. In addition, the MOSFET cell 10 can be mirrored symmetrically on its left and right sides and can continue to repeat in this way to achieve the desired size. The combination of the MOSFET cells 10 arranged as described above forms a MOSFET device. The gate contact 30, the source contact 32 and the drain contact 34 of the MOSFET cell 10 are tied together so that the MOSFET cell 10 operates together as a MOSFET device.

[0025] This can be best seen by looking at the MOSFET device from the top down. Figure 2 A top view of a MOSFET device 36 is shown including a plurality of junction implants 38 therein. The gate oxide, gate contact, and source contact are not shown. Figure 2 Although junction implant 38 may include several different implants with different doping types, Figure 2 They are represented as a single shaded area in FIG. 4 to better illustrate the concepts discussed herein. The area between the junction implants 38 is the JFET region 40 of the MOSFET device 36 . Figure 1 The MOSFET cell 10 shown may represent Figure 2 A cross-sectional view of MOSFET device 36 through line AA' is shown. Figure 2 The configuration shown is often referred to as a "stripe" MOSFET design because the junction implant 38 is in the form of a stripe across the device.

[0026] As mentioned above, two notable design parameters of MOSFET device 36 are JFET gap 42 and doping concentration of JFET region 40. Figure 2 The selection of these parameters for the MOSFET device 36 described is relatively simple because the JFET gap 42 is uniform throughout the device. Although the simplicity of the MOSFET device 36 has advantages in this regard, in recent years, MOSFET devices have tended to move from strip-based designs to cell-based designs to achieve higher cell (or MOS channel) filling density, thereby improving the performance of the MOSFET device 36.

[0027] Figure 3 4 shows a top view of a MOSFET device 44 including a plurality of junction implants 46 arranged in a cell configuration. In particular, Figure 3 A MOSFET device 44 is shown having a rectangular cell configuration. The gate oxide, gate contact, and source contact are not shown. Figure 3Although junction implant 46 may include several different implants with different doping types, Figure 3 4 to better illustrate the concepts discussed herein. The region between the junction implants 46 is the JFET region 48 of the MOSFET device 44. As described above, two notable design parameters of the MOSFET device 44 are the distance between the junction implants 46, or JFET gap 50, and the doping concentration of the JFET region 48. Since the JFET gap 50 is not the same in all regions of the device, Figure 3 The cell configuration of the MOSFET device 44 shown complicates its design. In particular, a first JFET gap 50A is provided between adjacent junction implants 46 having parallel faces, while a second JFET gap 50B is provided between adjacent junction implants 46 that do not have parallel faces. This is respectively Figure 3 It is shown by lines BB' and CC'. Figure 1 The MOSFET cell 10 shown in FIG. Figure 3 4 is a cross-sectional view of a MOSFET device 44 through lines BB' and CC' shown in FIG. The only area between the MOSFET cells through these lines is the JFET gap 50, which will be much larger for the MOSFET cell formed through line CC' than for the MOSFET cell formed through line BB'.

[0028] As described above, increasing the JFET gap 50 increases the peak electric field at the center of the JFET region 48. Due to the presence of the larger second JFET gap 50B in the MOSFET device 44, the most concentrated electric field in the device is formed around the center point of the second JFET gap 50B. Conventionally, the JFET region 48 is a uniformly doped region. According to conventional design principles, the doping concentration of the JFET region 48 is adjusted to accommodate the most concentrated electric field in the MOSFET device 44, which is formed at the center point between adjacent junction implants 46 that do not have parallel faces. In particular, the doping concentration of the JFET region 48 is reduced to reduce the peak electric field in this region to an acceptable level to avoid damaging the MOSFET device 44 (e.g., by cracking its gate oxide).

[0029] It is noteworthy that the doping concentration required to reduce the peak electric field to an acceptable level in the portion of the JFET region 48 between adjacent junction implants 46 that do not have parallel faces is significantly lower than the doping concentration required to reduce the peak electric field to an acceptable level in the portion of the JFET region 48 between adjacent junction implants 46 that do have parallel faces. When the doping concentration of the JFET region 48 is uniform in the MOSFET device 44, only the region in the MOSFET device 44 where the junction implants 46 are separated by the second JFET gap 50B is optimized because the doping concentration of the JFET region 48 is selected for this portion of the device. In other words, the uniform doping concentration of the JFET region 48 results in a suboptimal compromise between on-resistance, blocking voltage, and peak electric field for those regions of the MOSFET device 44 (the regions where the junction implants 46 are separated by the first JFET gap 50A). When using a wide bandgap material system such as SiC, conventional designs in which the JFET region 48 is uniformly doped prevent the MOSFET device 44 from achieving certain combinations of on-state resistance and blocking voltage because they are not achievable when the doping concentration of the JFET region 48 is reduced to a level where device damage due to peak electric fields in the region of the MOSFET device 44 separated by the second JFET gap 50B no longer occurs.

[0030] therefore, Figure 4 FIG. 4 shows a top view of a MOSFET device 44 according to one embodiment of the present disclosure. In addition to the JFET region 48 being divided into a first JFET sub-region 48A and a second JFET sub-region 48B, Figure 4 The MOSFET device 44 shown in FIG. Figure 3 The MOSFET device in FIG. 1 is substantially similar, wherein the first JFET sub-region 48A has a first JFET gap 50A, and the second JFET sub-region 48B has a second JFET gap 50B. The first JFET sub-region 48A has a first doping concentration, and the second JFET sub-region 48B has a second doping concentration different from the first doping concentration. In one embodiment, the doping concentration of the first JFET sub-region 48A is between 1×10 16 cm -3 and 2×10 17 cm -3 The doping concentration of the second JFET sub-region 48B is between 1×1015cm -3 and 5×10 16 cm -3In various embodiments, the doping concentration in the JFET region 48 may transition abruptly between the first JFET sub-region 48A and the second JFET sub-region 48B, or may transition gradually in a linear, exponential, stepwise, or any other manner. The doping concentrations of the first JFET sub-region 48A and the second JFET sub-region 48B and the transition therebetween may be obtained using masking prior to ion implantation of the sub-regions. Masking may require several steps, which may be reduced by using grayscale or pinhole masking.

[0031] Dividing the JFET region 48 into a first JFET sub-region 48A and a second JFET sub-region 48B allows the tradeoff between on-resistance, blocking voltage, and peak electric field to be optimized locally within different portions of the MOSFET device 44. Figure 4 Only the first JFET sub-region 48A and the second JFET sub-region 48B are shown, but the JFET region 48 may be divided into any number of JFET sub-regions without departing from the principles of the present disclosure, each of which may have a different doping concentration. Designing the MOSFET device 44 as described above may allow the device to achieve performance parameters that were previously unattainable in a cell-based design using conventional design principles, particularly when the MOSFET device 44 is formed using a wide bandgap material system such as SiC. For example, in various embodiments, the MOSFET device 44 is capable of achieving less than 2.5 mΩ-cm 2 、less than 2.0mΩ-cm 2 , less than 1.8mΩ-cm 2 and less than 1.6 mΩ-cm 2 The invention relates to an area-normalized on-resistance capable of achieving blocking voltages greater than 550 V, greater than 600 V, greater than 650 V, and greater than 700 V, and capable of achieving peak MOS oxide electric fields less than 4.0 MV / cm, less than 3.8 MV / cm, less than 3.5 MV / cm, less than 3.2 MV / cm, and less than 3.0 MV / cm, with a cell (or MOS channel) packing density greater than 300 mm / mm 2 , greater than 330mm / mm 2 , greater than 370mm / mm 2 , and greater than 400mm / mm 2 .

[0032] The principles of the present disclosure are similarly applied to a MOSFET device 52, which includes a MOSFET device 52 arranged as follows. Figure 5 The multiple junction implants 54 of the hexagonal cell configuration shown can provide a higher cell (or MOS channel) filling density than the rectangular cell configuration described above. Figure 3 and Figure 4In the illustrated MOSFET device 44, the JFET region 56 of the MOSFET device 52 has a non-uniform JFET gap 58. In particular, the JFET gap 58 of the MOSFET device 52 is different in the first JFET sub-region 56A and the second JFET sub-region 56B. In particular, the JFET gap 58 in the second JFET sub-region 56B is larger than the JFET gap 58 in the first JFET sub-region 56A. Due to the larger JFET gap 58 in the second JFET sub-region 56B, the MOSFET device 52 experiences a peak electric field at approximately the center of the second JFET sub-region 56B.

[0033] As described above, conventional design principles for uniformly doping the JFET region 56 require that the doping concentration of the entire JFET region 56 be reduced to prevent the peak electric field in the second JFET sub-region 56B from damaging the MOSFET device 52. The resulting doping concentration of the JFET region 56 makes it impossible to achieve certain combinations of on-state resistance and blocking voltage, especially when the MOSFET device 52 uses a wide bandgap material system such as SiC. Therefore, the doping concentration of the first JFET sub-region 56A is greater than the doping concentration of the second JFET sub-region 56B. In one embodiment, the doping concentration of the first JFET sub-region 56A is between 1×10 16 cm -3 and 2x10 17 cm -3 and the doping concentration of the second JFET sub-region 56B is between 1×10 15 cm -3 and 5x10 16 cm -3 In various embodiments, the doping concentration of the first JFET sub-region 56A may be between 2×10 16 cm -3 and 2x10 17 cm -3 Between 3x10 16 cm -3 and 2x10 17 cm -3 Between 4x10 16 cm -3 and 2x10 17 cm -3 Between 5x10 16 cm -3 and 2x10 17 cm -3 Between 6x10 16 cm -3 and 2x10 17 cm -3 Between 7x1016 cm -3 and 2x10 17 cm -3 Between 8x10 16 cm -3 and 2x10 17 cm -3 Between 9x10 16 cm -3 and 2x10 17 cm -3 Between 1x10 17 cm -3 and 2x10 17 cm -3 Between 2x10 16 cm -3 and 1x10 17 cm -3 Between 2x10 16 cm -3 and 9x10 16 cm -3 Between 2x10 16 cm -3 and 8x10 16 cm -3 Between 2x10 16 cm -3 and 7x10 16 cm -3 Between 2x10 16 cm -3 and 6x10 16 cm -3 Between 2x10 16 cm -3 and 5x10 16 cm -3 Between 2x10 16 cm -3 and 4x10 16 cm -3 Between, and between 2x10 16 cm -3 and 3x10 16 cm -3 The doping concentration of the second JFET sub-region 56B may be between 2×10 15 cm -3 and 5x10 16 Between 3x10 15 cm -3 and 5x10 16 Between 4x10 15 cm -3 and 5x10 16Between 5x10 15 cm -3 and 5x10 16 Between 6x10 15 cm -3 and 5x10 16 Between 7x10 15 cm -3 and 5x10 16 Between 8x10 15 cm -3 and 5x10 16 Between 9x10 15 cm -3 and 5x10 16 Between 1x10 16 cm -3 and 5x10 16 Between 2x10 16 cm -3 and 5x10 16 Between 3x10 16 cm -3 and 5x10 16 Between 4x10 16 cm -3 and 5x10 16 Between 2x10 15 cm -3 and 4x10 16 Between 2x10 15 cm -3 and 3x10 16 Between 2x10 15 cm -3 and 2x10 16 Between 2x10 15 cm -3 and 1x10 16 Between 2x10 15 cm -3 and 9x10 15 Between 2x10 15 cm -3 and 8x10 15 Between 2x10 15 cm -3 and 7x10 15 Between 2x10 15 cm -3 and 6x10 15 Between 2x10 15 cm -3 and 5x10 15 Between 2x10 15 cm-3 and 4x10 15 Between 2x10 15 cm -3 and 3x10 15 The doping concentration of the JFET region 56 may change suddenly between the first JFET region 56A and the second JFET region 56B, or may change gradually in a linear, exponential, stepwise, or other manner. That is, the JFET region 56 may have a graded doping concentration (in the lateral direction, or in the lateral and vertical directions) so that the transition between the first JFET sub-region 56A and the second JFET sub-region 56B occurs in a linear, exponential, stepwise, or any other manner. The doping concentrations of the first JFET sub-region 56A and the second JFET sub-region 56B and the transition therebetween may be obtained by masking prior to ion implantation of the sub-regions. Masking may require several steps, which may be reduced by using grayscale or pinhole masking.

[0034] As described above, separating the JFET region 56 into the first JFET sub-region 56A and the second JFET sub-region 56B allows the trade-offs between on-resistance, blocking voltage, and peak electric field to be optimized locally within different portions of the MOSFET device 52. Figure 5 Only the first JFET sub-region 56A and the second JFET sub-region 56B are shown, but without departing from the present disclosure, the JFET region 56 may be divided into any number of JFET sub-regions, each of which may have a different doping concentration. Designing the MOSFET device 52 as described above may allow the device to achieve performance parameters that were previously unattainable in cell-based designs using conventional design principles, particularly when the MOSFET device 52 is formed using a wide bandgap material system such as SiC. For example, the MOSFET device 52 is capable of achieving less than 2.5 mΩ-cm 2 、less than 2.0mΩ-cm 2 , less than 1.8mΩ-cm 2 , and less than 1.6mΩ-cm 2 The invention relates to an area-normalized on-resistance capable of achieving blocking voltages greater than 550 V, greater than 600 V, greater than 650 V, and greater than 700 V, and a peak MOS oxide electric field capable of achieving less than 4.0 mV / cm, less than 3.8 MV / cm, less than 3.5 MV / cm, less than 3.2 MV / cm, and less than 3.0 MV / cm, with a cell (or MOS channel) packing density greater than 300 mm / mm 2 , greater than 330mm / mm 2 , greater than 370mm / mm 2 and greater than 400mm / mm 2 .

[0035] Although discussed above with respect to rectangular and hexagonal cell designs, the principles of the present disclosure are equally applicable to any MOSFET device in which the JFET gap is not uniform throughout the device. That is, the present disclosure can be applied to MOSFET devices having cells of any shape or size.

[0036] Figure 6 1 is a flow chart showing a method for manufacturing a MOSFET device according to an embodiment of the present disclosure. First, a semiconductor stack is provided (step 100), wherein the semiconductor stack includes at least a substrate and a drift layer on the substrate. Then, the semiconductor stack is selectively implanted to form a plurality of junction implant regions (step 102). As described above, junction implants can be provided in a cell configuration, wherein the JFET gap between the junction implants is not the same in all parts of the device. Therefore, the semiconductor stack is subsequently implanted to form at least two JFET sub-regions (step 104). As described above, the JFET sub-regions have different doping concentrations so as to optimize the regions of on-state resistance, blocking voltage, and peak electric field, respectively. Finally, an oxide layer and a metallization layer are provided (step 106) to complete the MOSFET device.

[0037] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A metal oxide semiconductor field effect transistor (MOSFET) device, comprising: Wide bandgap substrates; A wide bandgap drift layer on a substrate; a plurality of junction implants in the wide bandgap drift layer; as well as a junction field effect transistor (JFET) region between the plurality of junction implants, wherein: The JFET region is defined by a JFET gap, the JFET gap being the distance between adjacent ones of the plurality of junction implants; The JFET gap is not uniform across the MOSFET device; The JFET region is divided into a first JFET sub-region and a second JFET sub-region; the doping concentration of the first JFET sub-region is different from the doping concentration of the second JFET sub-region; and The doping concentration transitions between the first JFET sub-region and the second JFET sub-region in a lateral direction in a linear or stepwise manner.

2. The MOSFET device according to claim 1, wherein: A JFET gap within the first JFET sub-region is different from a JFET gap within the second JFET sub-region.

3. The MOSFET device according to claim 2, wherein: A JFET gap within the first JFET sub-region is smaller than a JFET gap within the second JFET sub-region.

4. The MOSFET device according to claim 3, wherein: The doping concentration in the first JFET sub-region is greater than the doping concentration in the second JFET sub-region.

5. The MOSFET device of claim 1, wherein: The substrate has a first doping type; the drift layer has a first doping type; and The plurality of junction implants each have a second doping type opposite to the first doping type.

6. The MOSFET device according to claim 1, wherein: Each of the plurality of junction implants is rectangular.

7. The MOSFET device according to claim 1, wherein: Each of the plurality of junction implants is hexagonal.

8. The MOSFET device according to claim 1, wherein: The wide bandgap substrate and the wide bandgap drift layer include silicon carbide (SiC).

9. The MOSFET device of claim 1, wherein: The MOSFET device provides less than 2mΩ-cm 2 The on-state resistance is normalized by area and is capable of blocking at least 650V.

10. The MOSFET device of claim 1, wherein: The MOS channel filling density of the MOSFET device is greater than 370 mm / mm 2 .

11. A method for manufacturing a metal oxide semiconductor field effect transistor (MOSFET) device, comprising: Providing a semiconductor stack comprising a wide bandgap substrate and a wide bandgap drift layer on the substrate; providing a plurality of junction implants in the wide bandgap drift layer; as well as providing a junction field effect transistor (JFET) region between the plurality of junction implants, wherein: The JFET region is defined by a JFET gap, the JFET gap being the distance between adjacent ones of the plurality of junction implants; The JFET gap is not uniform across the MOSFET device; The JFET region is divided into a first JFET sub-region and a second JFET sub-region; the doping concentration of the first JFET sub-region is different from the doping concentration of the second JFET sub-region; and The doping concentration transitions between the first JFET sub-region and the second JFET sub-region in a lateral direction in a linear or stepwise manner.

12. The method according to claim 11, wherein: A JFET gap within the first JFET sub-region is different from a JFET gap within the second JFET sub-region.

13. The method according to claim 12, wherein: A JFET gap within the first JFET sub-region is smaller than a JFET gap within the second JFET sub-region.

14. The method according to claim 13, wherein: The doping concentration in the first JFET sub-region is greater than the doping concentration in the second JFET sub-region.

15. The method according to claim 11, wherein: The MOSFET device provides less than 2mΩ-cm 2 The on-state resistance is normalized by area and is capable of blocking at least 650V.

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