Memory controller, memory device, and memory device operating method

Abstract

A memory controller, a storage device, and a method for operating the storage device are provided. The storage device includes: a nonvolatile memory; a volatile memory; and a memory controller configured to control the nonvolatile memory and the volatile memory. The memory controller is configured to, during operation of the storage device, in response to determining that a progressive defect has occurred in at least one of the nonvolatile memory and the volatile memory, thereby determining the at least one memory as a defective memory, perform a repair operation on the defective memory based on executing memory recovery firmware.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0116356, filed on September 20, 2019, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0017144, filed on February 12, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a memory device, and more particularly, to a memory controller capable of managing a defective memory, a memory device including the memory controller, and an operating method of the memory device. Background Art

[0003] Recently, storage devices such as solid-state drives (SSDs) have become widely used and are used to store or move large amounts of data. Due to various reasons, some memories included in the storage devices may be exposed to progressive defects, and thus, the storage devices may need to be replaced. Summary of the Invention

[0004] According to some example embodiments, a storage device may include: a nonvolatile memory; a volatile memory; and a memory controller configured to control the nonvolatile memory and the volatile memory. The memory controller may be further configured to, during operation of the storage device, in response to determining that a progressive defect has occurred in at least one of the nonvolatile memory or the volatile memory, resulting in the at least one memory being determined to be a defective memory, perform a repair operation on the defective memory based on executing memory recovery firmware.

[0005] According to some example embodiments, a method for operating a storage device, the storage device including a non-volatile memory, a volatile memory, and a memory controller, the operating method may include: detecting, by the memory controller, a progressive defect in a memory of the non-volatile memory or the volatile memory, such that the memory in which the progressive defect is detected is determined to be a defective memory; entering, by the memory controller, a memory test mode in response to detecting the progressive defect; and performing, by the memory controller, a repair operation on the defective memory based on executing memory recovery firmware in the memory test mode.

[0006] According to some example embodiments, a memory controller is configured to control a memory, and the memory controller may include: a memory interface configured to transmit and receive data to and from the memory; an error checking and correction (ECC) engine configured to correct errors in data read from the memory; and memory recovery firmware configured to: perform a repair operation on the memory in response to a determination by the memory controller that an uncorrectable error has occurred in the memory, the uncorrectable error being an error that the ECC engine is unable to correct. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram illustrating a storage system according to some example embodiments;

[0009] Figure 2 is a block diagram illustrating a memory controller according to some example embodiments;

[0010] Figure 3 is a block diagram illustrating a nonvolatile memory according to some example embodiments;

[0011] Figure 4A and Figure 4B shows volatile memory according to some example embodiments;

[0012] Figure 5 is a flowchart of a method of operating a storage device according to some example embodiments;

[0013] Figure 6 is a flowchart illustrating operations between a host and a memory controller according to some example embodiments;

[0014] Figure 7 is a flowchart illustrating operations among a memory controller, a nonvolatile memory, and a volatile memory according to some example embodiments;

[0015] Figure 8 is a flowchart illustrating operations between a memory controller and a memory according to some example embodiments;

[0016] Figure 9 illustrating an error correction code (ECC) operation according to the number of erroneous bits in data according to some example embodiments;

[0017] Figure 10 is a block diagram illustrating a storage system according to some example embodiments;

[0018] Figure 11 Shown included in Figure 10A memory cell array in a non-volatile memory;

[0019] Figure 12 is a flowchart illustrating operations between a memory controller and a nonvolatile memory according to some example embodiments;

[0020] Figure 13 is a flowchart illustrating operations between a host and a storage device according to some example embodiments;

[0021] Figure 14 is a flowchart illustrating operations between a host and a storage device according to some example embodiments; and

[0022] Figure 15 A network system according to some example embodiments is shown. DETAILED DESCRIPTION

[0023] Hereinafter, some example embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0024] It will be understood that elements and / or properties thereof, which may include devices and / or operations, may be recited herein as being "the same" or "equivalent" to other elements, and it will be further understood that elements and / or properties recited herein as being "the same" or "equivalent" to other elements may be "the same" or "equivalent" or "substantially the same" or "substantially the same" as other elements and / or properties. Elements and / or properties thereof that are "substantially the same" or "substantially the same" as other elements and / or properties will be understood to include elements and / or properties thereof that are the same or equivalent to other elements and / or properties within manufacturing tolerances and / or material tolerances. Elements and / or properties that are the same or substantially the same as other elements and / or properties may be the same or substantially the same in structure, the same or substantially the same in function, and / or the same or substantially the same in composition.

[0025] It will be understood that elements and / or properties thereof described herein as being "substantially" identical may include elements and / or properties thereof that are identical within manufacturing tolerances and / or material tolerances and / or elements and / or properties thereof that have a relative size difference of 10% or less. Furthermore, regardless of whether an element and / or property thereof is modified to be "substantially," it will be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) centered around the element and / or property thereof (e.g., structure, property of one or more elements, length, distance, parallel arrangement or perpendicular arrangement, etc.) as described.

[0026] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a tolerance of ±10% centered around the stated numerical value. When a range is specified, the range includes all values ​​therebetween in increments such as 0.1%.

[0027] It will be understood that some or all of any devices, controllers, memories, engines, interfaces, firmware, decoders, units or modules, etc. according to any example embodiments as described herein (including some or all of any elements of storage system 10, storage device 100, storage device 100', host 200, host 200', memory controller 110, memory controller 110', memory 111, ECC engine 113, non-volatile memory (NVM), volatile memory (VM), memory recovery firmware, network system 1000, or any combination thereof) may be included in one or more instances of a processing circuit system (such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof), may include one or more instances of a processing circuit system and / or may be implemented by one or more instances of a processing circuit system. In some example embodiments, one or more instances of the processing circuit system may include, but are not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), etc. In some example embodiments, any memory or memory unit, etc. as described herein may include a non-transitory computer-readable storage device (e.g., a solid-state drive (SSD)) storing a program of instructions, and one or more instances of the processing circuit system may be configured to execute the program of instructions to implement some or all of the functionality of any device, controller, memory, engine, interface, firmware, decoder, unit, module, etc. according to any example embodiment as described herein (including any method of operating any device, controller, memory, engine, interface, firmware, decoder, unit, module, etc. described herein).

[0028] Figure 1 is a block diagram illustrating a memory system 10 according to some example embodiments.

[0029] Reference Figure 1, a storage system 10 may include a storage device 100 and a host 200. The storage device 100 may include a memory controller 110 and a non-volatile memory (NVM) 120 (also interchangeably referred to herein as a non-volatile memory device). In addition, the storage device 100 may also include a volatile memory (VM) 130 (also interchangeably referred to herein as a volatile memory device). In some example embodiments, the storage system 10 may include a plurality of storage devices 100. The memory controller 110 may be configured to control the NVM 120 and the VM 130, for example, to control memory read operations and / or memory write operations of one or more of the NVM 120 and the VM 130.

[0030] It will be understood that any operations described herein as being performed by the memory device 100 may be implemented at least partially or completely by the memory controller 110. Any portion of the memory device 100 (e.g., the memory controller 110) may be configured to perform some or all of any operations of any method described with respect to any example embodiment herein, for example based on the memory controller 110 including a memory storing a program of instructions and circuitry configured to execute the program of instructions, to implement some or all of any operations of any method described with respect to any example embodiment herein.

[0031] The host 200 may communicate with the storage device 100 via various interfaces and may transmit write requests, read requests, etc. to the storage device 100. In some example embodiments, the host 200 may include a server or a personal computer (PC). In some example embodiments, the host 200 may be implemented using an application processor (AP) or a system on a chip (SoC). The memory controller 110 may control the NVM 120 so that data stored in the NVM 120 is read in response to a read request from the host 200, or data is written to the NVM 120 in response to a write request from the host 200.

[0032] The memory controller 110 may include a memory 111, and the memory 111 may be referred to as an internal memory or an operating memory, etc. For example, the memory 111 may be a static random access memory (RAM) SRAM, and hereinafter, descriptions are mainly given of some example embodiments in which the memory 111 is an SRAM. However, some example embodiments are not limited thereto, and the memory 111 may include other VMs or NVMs in addition to the SRAM.

[0033] The NVM 120 may include a memory cell array (MCA) 121 in which a plurality of memory cells are arranged. For example, the NVM 120 may include a 3D vertical NAND flash memory device. In some example embodiments, the MCA 121 may include flash memory cells, which may include, for example, NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may include resistive memory cells (such as resistive RAM (ReRAM), phase change RAM (PRAM), and magnetic RAM (MRAM)).

[0034] The VM 130 may include an MCA 131 in which a plurality of memory cells are arranged. For example, the VM 130 may include dynamic RAM (DRAM). Hereinafter, descriptions will be given mainly of some example embodiments in which the VM 130 includes DRAM. However, some example embodiments are not limited thereto, and the VM 130 may include other VMs in addition to DRAM.

[0035] In this manner, the memory device 100 may include various memories (such as NVM 120, VM 130, and memory 111), and defects may occur in memory cells included in the various memories not only during the manufacturing process but also during the product use stage. Hereinafter, defects occurring during the manufacturing process stage may be referred to as "initial defects," and defects occurring during the product use stage may be referred to as "progressive defects." For example, the threshold voltage distribution of memory cells may change due to progressive defects in NVM 120, and thus, the reliability of NVM 120 and the memory device 100 including NVM 120 may be reduced.

[0036] After the storage device 100 is shipped, progressive defects may occur in some of the various memories included in the storage device 100. According to some example embodiments, when defective memory exists in the storage device 100 (e.g., in response to, for example, the memory controller 110 determining that a progressive defect has occurred in a memory in the storage device 100, such that the memory is determined to be defective memory), the storage device 100 may, in response, perform a repair operation on the defective memory based on executing memory recovery firmware FW. In some example embodiments, the storage device 100 may receive (e.g., download) memory recovery firmware FW from the host 200, perform a repair operation on the defective memory based on executing the received memory recovery firmware FW, and reuse the defective memory on which the repair operation has been performed.

[0037] It will be understood that, as described herein, “determining that a progressive defect has occurred in a memory of a storage device such that the memory is determined to be a defective memory” may be interchangeably referred to herein as “detecting a progressive defect in a memory such that the memory is determined to be a defective memory” or “detecting a defective memory” or the like.

[0038] When a defective memory is detected (e.g., in response to the detection performed by the memory controller 110, in response to the memory controller 110 determining that a progressive defect has occurred in the memory, such that the memory is determined to be defective memory), the memory device 100 may transmit information regarding the progressive defect (e.g., associated with the progressive defect) to the host 200. For example, the information regarding the progressive defect may include information regarding the occurrence of the defective memory. Additionally, for example, the information regarding the progressive defect may include information regarding the type or attributes of the memory in which the progressive defect has occurred. Subsequently (e.g., in response to the detection of the defective memory and / or in response to transmitting the information to the host 200), the memory device 100 may enter a firmware downloadable mode or a memory test mode. The firmware downloadable mode or the memory test mode may be a mode in which the memory device 100 can be controlled using non-volatile memory (NVM) Express (NVMe), serial advanced technology attachment (SATA), serial attached SCSI (small computer system interface) (SAS), or the like using in-band commands.

[0039] For example, when the memory device 100 detects (e.g., in response to the memory controller 110 determining the occurrence of) an uncorrectable error correction code (UECC) in at least one of various memories (e.g., NVM 120, VM 130, and / or memory 111), the memory device 100 (e.g., the memory controller 110) may determine the memory in which the UECC occurred as a defective memory. In some example embodiments, the memory device 100 may transmit information about the defect to the host 200, the information including information about the attributes or type of the memory in which the UECC occurred.

[0040] In response to information about defects received from the memory device 100 (e.g., based on the host processing the information to select specific memory recovery firmware FW corresponding to one or more portions of the information), the host 200 may provide (e.g., transmit) memory recovery firmware FW to the memory device 100. In some example embodiments, the memory recovery firmware FW may be referred to as firmware for performing testing and repair of defective memory. The memory recovery firmware FW may be configured to perform in-depth attribute analysis on defective cells included in the defective memory, thereby repairing the defective cells.

[0041] In some example embodiments, the host 200 may select the memory recovery firmware FW as a specific memory recovery firmware FW selected from a plurality of different memory recovery firmware FWs based on the attributes or type of the defective memory. The attributes or type of the defective memory may be indicated by information about progressive defects and may be determined by the host 200 based on processing the information. The host 200 may provide (e.g., transmit) the selected memory recovery firmware FW to the storage device 100. However, the inventive concept is not limited thereto, and the host 200 may provide the storage device 100 with memory recovery firmware FW applicable to various memories.

[0042] As described herein, the transfer of data between two devices (e.g., the transfer of memory recovery firmware FW from the host 200 to the storage device 100) can be achieved based on the receiving device accessing and / or "pulling" (e.g., downloading) data from the sending device, based on the sending device "pushing" data to the receiving device, or any combination thereof.

[0043] The storage device 100 (e.g., the memory controller 110) may store the memory recovery firmware FW received (e.g., downloaded) from the host 200. In some example embodiments, the storage device 100 may store the memory recovery firmware FW in the memory 111. For example, the memory recovery firmware FW stored in the memory 111 may include a plurality of different memory recovery firmwares, including volatile memory (e.g., DRAM) recovery firmware (e.g., a first memory recovery firmware configured to execute a first repair program on a volatile memory) and / or non-volatile memory recovery firmware (e.g., a second memory recovery firmware configured to execute a second repair program on a non-volatile memory). However, the inventive concept is not limited thereto, and the memory recovery firmware FW stored in the memory 111 may include memory recovery firmware applicable to various memories (e.g., a first memory recovery firmware configured to execute a repair program on one or both of a volatile memory and a non-volatile memory).

[0044] In some example embodiments, the storage device 100 may store the memory recovery firmware FW in the VM 130. For example, the memory recovery firmware FW stored in the VM 130 may include SRAM recovery firmware (e.g., memory recovery firmware configured to perform a repair procedure on the SRAM) and / or NVM recovery firmware. However, the inventive concept is not limited thereto, and the memory recovery firmware FW stored in the VM 130 may include memory recovery firmware applicable to various memories.

[0045] In some example embodiments, the memory recovery firmware FW stored in the memory 111 may be the same as the memory recovery firmware FW stored in the VM 130. For example, the memory recovery firmware FW may be downloaded to the memory 111 and then may be migrated (e.g., transferred) from the memory 111 to the VM 130.

[0046] The storage device 100 (e.g., the memory controller 110) can perform a test on a defective memory by executing stored memory recovery firmware FW. The storage device 100 (e.g., the memory controller 110) can identify defective cells in the defective memory, analyze the defective properties of the defective cells, and perform a repair operation on the defective cells by executing the memory recovery firmware FW. As part of performing the repair operation, the storage device 100 (e.g., the memory controller 110) can regenerate the defective memory by replacing the defective cells with redundant cells. As a result, the defective memory can be reused based on the execution of the repair operation. Therefore, because the storage device 100 does not need to be replaced, costs can be reduced.

[0047] Therefore, it will be understood that in some example embodiments, the memory controller 110 is configured to, in response to determining during operation of the memory device 100 that a progressive defect has occurred in at least one memory of the NVM 120 and the VM 130, resulting in the at least one memory being determined to be a defective memory, perform a repair operation on the defective memory based on executing the memory recovery firmware FW.

[0048] In some example embodiments, when a progressive defect occurs (e.g., in response to determining that a progressive defect has occurred), the memory controller 110 may mark a memory fail signature and reset the memory device 100. In addition, in some example embodiments, when a repair operation for a defective memory is completed (e.g., in response to completion of a repair operation performed on a defective memory), the memory controller 110 may change the memory fail signature to a memory repair signature and reset the memory device 100. Figure 13 and Figure 14 Describe the problem in more detail.

[0049] The storage system 10 may be implemented using, for example, a personal computer (PC), a data server, a network attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices may include laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital cameras, digital video cameras, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-books, and wearable devices.

[0050] In some example embodiments, the storage device 100 may include an internal memory embedded in the electronic device. For example, the storage device 100 may include an embedded universal flash memory (UFS) memory device or an embedded multimedia card (eMMC). In some example embodiments, the storage device 100 may include an external memory that can be removed from the electronic device. For example, the storage device 100 may include a universal flash memory (UFS) memory card, a compact flash memory (CF) memory card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0051] In some example embodiments, the storage device 100 or multiple storage devices may be used in a data center. For example, the storage device 100 or multiple storage devices may be included in a storage server (e.g., Figure 15 1200 or 1200n) or an application server (e.g. Figure 15 In 1100 or 1100n), the storage system 10 may include a data center.

[0052] Recently, with the development of data centers, storage services related to storage devices 100 (such as solid-state drives (SSDs)) have also expanded. Because the security of storage devices 100 is extremely important due to the nature of data centers that need to manage customers' private data, when a defect occurs in storage device 100, it may be difficult to remove storage device 100 for accurate failure analysis. In addition, as the possibility of progressive defects occurring due to the vulnerability of semiconductor microprocessors increases, storage device 100 or storage system 10 using memory (such as NVM 120, VM 130, and memory 111) may also be susceptible to progressive defects.

[0053] Furthermore, as the performance of electronic devices (such as central processing units (CPUs), memories, and storage devices) rapidly increases each year, system architectures and communication protocols may also require high-speed operations to fully utilize the performance of electronic devices. As required, the performance of electronic devices increases due to the increase in input / output (I / O) speed. However, conversely, thermal issues may occur due to the increased power consumption and may affect the reliability of storage devices (such as NVM 120, VM 130, and memory 111), thus likely accelerating the development of defects caused by fragile processes.

[0054] Figure 2 is a block diagram illustrating a memory controller 110 according to some example embodiments.

[0055] Refer to it together Figure 1 and Figure 2, the memory controller 110 may include a memory 111, a processor 112, an error checking and correction (ECC) engine 113, a host interface (IF) 114, an NVM IF 115, and a VM IF 116, which can communicate with each other via a bus 117. The processor 112 may include a CPU or a microprocessor, etc., and may control the overall operation of the memory controller 110.

[0056] Memory 111 (also referred to herein as internal memory of memory controller 110) can operate under the control of processor 112 and can be used as operating memory, buffer memory, cache memory, or the like. For example, memory 111 can be implemented as VM (such as DRAM and SRAM) or NVM (such as PRAM and flash memory). In some example embodiments, memory 111 may include VM, and some example embodiments implementing memory 111 using SRAM are primarily described. Memory recovery firmware FW may be loaded into memory 111, and processor 112 may access memory 111 and execute the memory recovery firmware FW. However, the inventive concept is not limited thereto, and the memory recovery firmware FW may be implemented in hardware. In some example embodiments, memory 111 may include static RAM (SRAM), and storage device 100 (e.g., memory controller 110) may be configured to, in response to determining that a progressive defect has occurred in the SRAM (e.g., memory 111), perform a repair operation on the SRAM based on executing at least a portion of the memory recovery firmware FW.

[0057] The ECC engine 113 may detect error bits in data and correct the detected error bits by performing an ECC operation on data received from the NVM 120 via the NVM IF 115. Thus, the ECC engine 113 may be configured to correct errors in data read from a memory (e.g., the NVM 120, the memory 111, and / or the VM 130). In addition, the ECC engine 113 may detect error bits in data and correct the detected error bits by performing an ECC operation on data received from the VM 130 via the VM IF 116. In some example embodiments, the ECC engine 113 may be implemented in hardware. In some example embodiments, the ECC engine 113 may be implemented in software or firmware and may be loaded into the memory 111.

[0058] The host IF 114 may provide an interface between the host 200 and the memory controller 110 (e.g., the host IF 114 may be configured to communicate with the host 200), and may provide an interface according to, for example, a Universal Serial Bus (USB), a MultiMediaCard (MMC), a Peripheral Component Interconnect (PCI) Express (PCIe), an Advanced Technology (AT) Attachment (ATA), a Serial ATA (SATA), a Parallel ATA (PATA), a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), an Enhanced Small Disk Interface (ESDI), or an Integrated Drive Electronics (IDE).

[0059] NVM IF 115 may provide an interface between memory controller 110 and NVM 120 (e.g., NVM IF 115 may be configured to communicate with NVM 120). For example, memory recovery firmware FW may be transmitted and received between memory controller 110 and NVM 120 via NVM IF 115. In addition, for example, mapping tables, write data, and read data may be transmitted and received between memory controller 110 and NVM 120 via NVM IF 115. For example, memory recovery firmware FW may be configured to be downloaded from NVM 120 by memory controller 110 via NVM IF 115.

[0060] The VM IF 116 may provide an interface between the memory controller 110 and the VM 130 (e.g., the VM IF 116 may be configured to communicate with the VM 130). For example, memory recovery firmware FW may be transmitted and received between the memory controller 110 and the VM 130 via the VM IF 116. In addition, for example, write data received from the host 200 may be buffered in the VM 130 via the VM IF 116, and read data received from the NVM 120 may be buffered in the VM 130 via the VM IF 116.

[0061] Either or both of NVM IF 115 and VM IF 116 may be referred to herein as a “memory interface” of memory controller 110 that is configured to transmit and receive data with memory (eg, NVM 120 and / or VM 130 ).

[0062] Figure 3 NVM 120A is shown according to some example embodiments.

[0063] Reference Figure 3NVM 120A may include NAND flash memory and may be implemented as a single chip. NVM 120A may include a first die 121A and a second die 122A. Each of the first die 121A and the second die 122A may include multiple planes PL (e.g., plane 0 (PL0), plane 1 (PL1), ..., plane n, where n is an integer greater than 1). Each plane PL may include multiple memory blocks BLK (e.g., block 0 (BLK0), block 1 (BLK1), ..., block n-1). Each memory block BLK may include multiple pages PG (e.g., page 0 to page n-1).

[0064] For example, when a defective page PG occurs (e.g., in response to a defective page PG), the memory device (e.g., the memory controller 110) executes the memory recovery firmware FW, and the defective page is replaced with a reserved page, so that the defective memory can be reused. For example, when a defective block occurs (e.g., in response to a defective block), the memory device (e.g., the memory controller 110) executes the memory recovery firmware FW, and the defective block is replaced with a reserved block, so that the defective memory can be reused. For example, when a defective plane occurs (e.g., in response to a defective plane), the memory device (e.g., the memory controller 110) executes the memory recovery firmware FW, and the defective plane is replaced with a reserved plane, so that the defective memory can be reused. For example, when a defective die occurs (e.g., in response to a defective die), the memory device (e.g., the memory controller 110) executes the memory recovery firmware FW, and the defective die is replaced with a reserved die, so that the defective memory can be reused.

[0065] Figure 4A VM 130 is shown according to some example embodiments.

[0066] Reference Figure 4A The VM 130 may include an MCA 131, a repair controller 132, a row decoder 133, and a column decoder 134. However, the configuration of the VM 130 is not limited thereto, and the VM 130 may further include a page buffer that temporarily stores data to be stored in the MCA 131 or temporarily stores data read from the MCA 131, a data I / O circuit that transmits and receives data stored in the page buffer to the outside, and a controller that receives commands from the outside and controls the overall operation of the VM 130 according to the commands.

[0067] The MCA 131 may include a normal region 131a in which a plurality of memory cells are arranged, and a redundant region 131b in which a plurality of redundant memory cells are arranged. In some example embodiments, the redundant region 131b may be arranged adjacent to the normal region 131a according to the extending direction of the bit lines BL. The normal region 131a may include a plurality of memory cells arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL, and the redundant region 131b may include a plurality of redundant memory cells arranged at intersections of a plurality of redundant word lines RWL and a plurality of bit lines BL.

[0068] A defect may occur in at least one of the plurality of memory cells in the normal region 131a. The defective cell may be referred to as a single bit, a weak cell, or a defective cell. The defective cell in the normal region 131a may be replaced with a redundant memory cell included in the redundant region 131b. This operation may be referred to as a "repair operation." Through the repair operation, data to be written to or read from the defective cell may be written to or read from the redundant memory cell. Therefore, it will be understood that the memory device 100 (e.g., the memory controller 110) may be configured to perform a repair operation based on executing memory recovery firmware FW by replacing at least one defective cell (e.g., a defective cell among the plurality of cells in the normal region 131a) among the plurality of memory cells in a defective memory (e.g., at least one of the NVM 120, VM 130, and memory 111 in which a progressive defect has occurred) with a redundant memory cell. The redundant memory cell is also referred to herein as a "redundant cell" (e.g., a cell among the plurality of cells in the redundant region 131b).

[0069] In some example embodiments, the repair operation may be performed according to a row repair method that replaces a row including a defective cell in the normal region 131a with a redundant row in the redundant region 131b. In some example embodiments, the repair unit may be a word line WL, and thus, the word line WL including a defective cell may be replaced with a redundant word line RWL. In some example embodiments, the repair unit may be a word line group, and thus, the word line group including a defective cell may be replaced with a redundant word line group. For example, a word line group may correspond to two, four, eight, or sixteen word lines. When the repair unit is two word lines WL, the two word lines WL including the defective cell included in the normal region 131a may be replaced with two redundant word lines RWL included in the redundant region 131b.

[0070] The repair controller 132 may control a repair operation for a defective cell among a plurality of memory cells according to the memory recovery firmware FW. The repair controller 132 may control the repair operation when an input address (e.g., a row address RA) of a memory cell to be accessed corresponds to a defective cell. The repair controller 132 may generate a row match signal RM when the row address RA corresponds to a defective cell, and may provide the generated row match signal RM to the row decoder 133. Therefore, the row decoder 133 may activate the redundant word line RWL in response to the row match signal RM.

[0071] The row decoder 133 may select some word lines WL from among a plurality of word lines WL in response to a row address RA and activate the selected word lines WL. Furthermore, the row decoder 133 may select some redundant word lines RWL from among a plurality of redundant word lines RWL in response to a row match signal RM and activate the selected redundant word lines RWL. The row decoder 133 may disable the row address RA in response to the row match signal RM and activate the redundant word lines RWL. The column decoder 134 may select some bit lines BL from among a plurality of bit lines BL in response to a column address CA.

[0072] Figure 4B VM 130' is shown according to some example embodiments.

[0073] Reference Figure 4B , the VM 130' may include an MCA 131', a repair controller 132', a row decoder 133', and a column decoder 134'. The VM 130' according to some example embodiments may be Figure 4A A modified example embodiment of the VM 130 is described, and duplicate descriptions given previously are omitted.

[0074] The MCA 131′ may include a normal region 131a′ in which a plurality of memory cells are arranged, and a redundant region 131b′ in which a plurality of redundant memory cells are arranged. In some example embodiments, the redundant region 131b′ may be arranged adjacent to the normal region 131a′ according to the extending direction of the word lines WL. The normal region 131a′ may include a plurality of memory cells arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL, and the redundant region 131b′ may include a plurality of redundant memory cells arranged at intersections of a plurality of word lines WL and a plurality of redundant bit lines RBL.

[0075] A defect may occur in at least one memory cell among the plurality of memory cells in the normal region 131a', and the defective cell occurring in the normal region 131a' may be replaced by a redundant memory cell included in the redundant region 131b' through a repair operation. Through the repair operation, data to be written to or read from the defective cell may be written to or read from the redundant memory cell.

[0076] In some example embodiments, the repair operation may be performed according to a column repair method that replaces a column including a defective cell in the normal region 131a' with a redundant column in the redundant region 131b'. In some example embodiments, the repair unit may be a bit line BL, and thus, the bit line BL including a defective cell may be replaced with a redundant bit line RBL. In some example embodiments, the repair unit may be a bit line group, and thus, the bit line group including a defective cell may be replaced with a redundant bit line group. For example, a bit line group may correspond to 2, 4, 8, or 16 bit lines. When the repair unit is two bit lines BL, the two bit lines BL including the defective cell included in the normal region 131a' may be replaced with two redundant bit lines RBL included in the redundant region 131b'.

[0077] The repair controller 132' can control a repair operation for a defective cell among a plurality of memory cells. The repair controller 132' can control the repair operation when an input address (e.g., column address CA) of a memory cell to be accessed corresponds to a defective cell (e.g., in response to determining that the input address corresponds to a defective cell). The repair controller 132' can generate a column match signal CM when the column address CA corresponds to a defective cell, and can provide the generated column match signal CM to the column decoder 134'. Therefore, the column decoder 134' can activate the redundant bit line RBL in response to the column match signal CM.

[0078] The row decoder 133' may select some word lines WL from among a plurality of word lines WL in response to a row address RA and activate the selected word lines WL. The column decoder 134' may select some bit lines BL from among a plurality of bit lines BL in response to a column address CA and activate the selected bit lines BL. Furthermore, the column decoder 134' may select some redundant bit lines RBL from among a plurality of redundant bit lines RBL in response to a column match signal CM and activate the selected redundant bit lines RBL. The column decoder 134' may disable the column address CA in response to the column match signal CM and activate the redundant bit lines RBL.

[0079] Figure 5 is a flow chart of a method of operating a storage device according to some example embodiments. The method may be performed by any portion of the storage device according to any example embodiment herein (including Figure 1 The operations described herein as being performed by the memory device 100 may be performed by any portion of the memory device 100 (including the memory controller 110).

[0080] Reference Figure 5, the operating method of a storage device according to some example embodiments may be performed during operation of the storage device after shipment of the storage device such as a disk (ie, SSD). For example, the operating method of a storage device according to some example embodiments may include Figure 1 In the following, reference is made to a plurality of operations performed in a time series in the storage device 100. Figure 1 、 Figure 2 and Figure 5 Give a description.

[0081] Memory device 100 (e.g., memory controller 110) may detect a progressive defect in a memory, which may be at least one of NVM 120, VM 130, and memory 111 (S110). To reiterate, memory device 100 (e.g., memory controller 110) may determine that a progressive defect has occurred in at least one of NVM 120, VM 130, and memory 111, such that the at least one memory is determined to be a defective memory. For example, memory controller 110 may detect a UECC in NVM 120, VM 130, or memory 111. For example, by performing an ECC operation on data received from NVM 120, VM 130, or memory 111, ECC engine 113 may detect erroneous bits in the data and correct the detected erroneous bits. In some example embodiments, when an uncorrected erroneous bit occurs in ECC engine 113 (e.g., in response to such occurrence), memory controller 110 may detect the progressive defect in the memory by determining that the uncorrected erroneous bit is an unrecoverable error. To reiterate, the memory controller 110 may determine that a progressive defect has occurred in the memory based on a determination by the memory controller 110 that an uncorrectable error has occurred in the memory, an uncorrectable error being an error that the ECC engine 113 is unable to correct.

[0082] As described herein, it will be understood that "detecting" or "sense" of an occurrence, event, state of one or more elements, etc., may be referred to interchangeably as "determining" or "determining that" the occurrence, event, state of one or more elements, etc., has occurred. For example, as described herein, detecting a progressive defect may be referred to interchangeably as "determining" that a progressive defect has occurred.

[0083] The memory device 100 (e.g., the memory controller 110) may enter a memory test mode (S130). The memory device 100 may enter the memory test mode in response to detecting a progressive defect at S110. In some example embodiments, the memory test mode may correspond to a firmware downloadable mode, and the memory controller 110 may enter the memory test mode or the firmware downloadable mode to download memory recovery firmware FW from the host 200, and then refer to Figure 6In some example embodiments, the memory test mode may correspond to a firmware downloadable mode, and the memory controller 110 may receive (eg, download) the memory recovery firmware FW from the NVM 120. Figures 11 to 13 Describe this.

[0084] The storage device 100 (e.g., the memory controller 110) may perform a repair operation on a memory device (e.g., a defective memory device) determined to have a progressive defect by executing memory recovery firmware FW (S150). The storage device 100 may perform the repair operation in response to detecting a progressive defect at S110, entering a memory test mode at S130, and / or receiving (e.g., downloading) the memory recovery firmware FW. For example, the storage device 100 (e.g., the memory controller 110) may perform a repair operation on the defective memory device by executing the memory recovery firmware FW in response to determining at S110 that a progressive defect has occurred in at least one of the NVM 120, VM 130, and memory 111, thereby determining that the at least one memory device is a defective memory device. For example, the memory controller 110 may regenerate the NVM 120, VM 130, or memory 111 by executing the memory recovery firmware FW. When performing the repair operation at S150, the memory controller 110 may be in the memory test mode entered at S130, so that "performing the repair operation at S150" includes executing the memory recovery firmware FW in the memory test mode. The memory controller 110 may perform tests on the NVM 120, VM 130, or memory 111, analyze defect attributes, and repair defective cells. Such execution of S150 may be performed in response to S110 being executed independently of S130.

[0085] In some example embodiments, the operating method described above may further include: when a progressive defect is detected (e.g., in response to determining that a progressive defect has occurred), the memory controller 110 marking a memory failure signature and resetting the operation of the memory device 100. In addition, in some example embodiments, the operating method described above may further include: when a repair operation is completed (e.g., in response to determining that the repair operation on the defective memory is completed), the memory controller 110 correcting the memory failure signature to a memory repair signature (e.g., changing the memory failure signature to a memory repair signature) and resetting the operation of the memory device 100. Figure 13 and Figure 14 This is described in more detail.

[0086] As described above, according to some example embodiments, when a defect occurs in a disk being used in a data center or server system (i.e., in the storage device 100) (e.g., in response to the occurrence of the defect), the storage device 100 may be regenerated by performing a test and repairing the memory. When the storage device 100 recognizes the UECC of the memory (e.g., in response to the storage device 100 recognizing the UECC of the memory), the storage device 100 may not enter a defect mode but may enter a memory test mode, in which memory recovery firmware FW may be received (e.g., downloaded).

[0087] Host 200 (i.e., a data center host) may transfer memory recovery firmware FW to storage device 100 to test the memory. The transfer may include storage device 100 (e.g., memory controller 110) downloading the memory recovery firmware FW from host 200. The transfer of the memory recovery firmware FW to storage device 100 may be performed in response to host 200 receiving information about a progressive defect from storage device 100, for example, by processing the information to determine a specific memory recovery firmware FW associated with the defect (e.g., a specific memory recovery firmware FW corresponding to a specific type or attribute of memory in which a progressive defect has occurred (i.e., defective memory), selecting the specific memory recovery firmware FW, and transferring the selected memory recovery firmware FW to storage device 100 and / or enabling storage device 100 to download the selected memory recovery firmware FW from host 200. In some example embodiments, host 200 may store a database of various separate memory recovery firmware FWs corresponding to different types or attributes of one or more memories. The host 200 may maintain a lookup table or other database storing relationships (e.g., empirically determined relationships) between specific types or attributes of defective memory and corresponding specific multiple memory recovery firmware FWs. The host 200 may process received information about progressive defects (including information associated with specific types or attributes of memory (e.g., defective memory) in which progressive defects have occurred) to determine the specific type or attribute, access the lookup table or other database to determine or select a corresponding specific memory recovery firmware FW from multiple memory recovery firmware FWs, and provide the corresponding specific memory recovery firmware FW to the storage device 100 (e.g., the memory controller 110). This may include, in response to the determination or selection of the corresponding memory recovery firmware FW, transmitting the specific memory recovery firmware FW and / or enabling the storage device 100 to download the specific memory recovery firmware FW from the host 200. After performing a memory test, the memory recovery firmware FW may identify defective cells, analyze the attributes, perform repairs, and return the test results along with an attribute defect analysis log to the host 200. In this way, by repairing the defective memory, the defective disk can be used as a normal disk. Therefore, data centers can reduce bad disks, and disk manufacturers can perform in-house level defect analysis in customer environments.

[0088] Figure 6 is a flowchart illustrating operations between the host 200 and the memory controller 110 according to some example embodiments.

[0089] Reference Figure 6, the memory controller 110 may detect a progressive defect in the memory (S210) (e.g., determine that a progressive defect has occurred in the memory, such that the memory is determined to be a defective memory). In response (e.g., in response to detecting the progressive defect at S210), the memory controller 110 may transmit information about the progressive defect (e.g., associated with the progressive defect) to the host 200 (S220), which may include information associated with a specific type or attribute of the defective memory in which the progressive defect has occurred. The memory controller 110 may then enter a firmware downloadable mode (S230) in response to S210 and / or S220 being executed, such that the memory controller 110 operates in the firmware downloadable mode. According to some example embodiments, the order of operations S220 and S230 may be changed. In some example embodiments, operations S220 and S230 may be performed substantially simultaneously.

[0090] The host 200 may, for example, transmit the memory recovery firmware FW to the memory controller 110 in response to receiving the transmitted information at S220 (S240). Therefore, at S240, the memory controller 110 may receive (e.g., download) the memory recovery firmware FW from the host 200 in the firmware downloadable mode, wherein the memory recovery firmware FW is received (e.g., downloaded) by the memory controller 110 at S240 (e.g., simultaneously with the firmware downloadable mode entered by the memory controller 110 at S230) based on the information associated with the progressive defect that was transmitted to the host at S220. The reception at S240 may be based on the host 200 receiving the information at S220 and processing the information. The host 200 may process the information received at S220 to determine the specific type or attribute of the memory in which a progressive defect has occurred, and in response, may determine or select, and subsequently transmit, at S240, a specific memory recovery firmware FW corresponding to the specific type or attribute of the memory in which a progressive defect has occurred. The specific corresponding memory recovery firmware FW may be determined or selected by the host 200 based on accessing a lookup table or database that associates the type or attribute of the memory in which a progressive defect may have occurred with a plurality of corresponding memory recovery firmware. The memory controller 110 may, for example, execute the memory recovery firmware FW for memory repair (e.g., the memory recovery firmware FW downloaded from the host at S240) in response to receiving (e.g., downloading) the memory recovery firmware FW at S240 (S250). Such execution may include downloading the received memory recovery firmware FW to, for example, the memory 111. For example, the memory controller 110 may repair the defective memory based on executing the memory recovery firmware FW downloaded to the memory 111. A test result may be generated based on the execution of the memory recovery firmware FW.

[0091] The memory controller 110 may, for example, transmit the test results to the host 200 (S260) in response to executing the memory recovery firmware FW at S250. For example, the memory controller 110 may obtain the test results of executing the memory recovery firmware FW and the results of analyzing the properties of the defective cells. In this case, the obtained results may correspond to a test result log. The memory controller 110 may provide the test result log to the host 200 as part of transmitting the test results at S260. After operation S260 (e.g., in response to executing the repair program based on the execution of the memory recovery firmware FW at S250), the memory device 100 may be formatted to reuse the defective memory.

[0092] Figure 7 is a flowchart illustrating operations among the memory controller 110 , the NVM 120 , and the VM 130 according to some example embodiments.

[0093] Reference Figure 7 , the memory controller 110 may detect a progressive defect in the memory, such that the memory is determined to be a defective memory (S310). For example, the memory controller 110 may detect the UECC in the NVM 120, VM 130, or memory 111. In response to the detection in S310, the memory controller 110 may enter a memory test mode (S320). In response to the detection in S310 and / or the entry into the memory test mode in S320, the memory controller 110 may execute memory recovery firmware FW for memory repair (S330).

[0094] The memory controller 110 may, for example, transmit a command CMD and an address ADDR for memory repair to the NVM 120 in response to executing the memory recovery firmware FW at S330 (S340). The NVM 120 may, for example, perform an NVM repair operation in response to receiving the command CMD and the address ADDR for memory repair at S340 (S345). The memory controller 110 may, for example, transmit a command CMD and an address ADDR for memory repair to the VM 130 in response to executing the memory recovery firmware FW at S330 (S350). The VM 130 may, for example, perform a VM repair operation in response to receiving the command CMD and the address ADDR for memory repair at S350 (S355). In some example embodiments, operations S350 and S355 may be performed before operations S340 and S345. In some example embodiments, the order of operations S340 and S350 may be changed, and operations S345 and S355 may be performed substantially simultaneously. In some example embodiments, operations S340 and S345 or operations S350 and S355 may be omitted according to the type of the defective memory.

[0095] The memory controller 110 may migrate the memory recovery firmware FW stored in the memory 111 to the VM 130 (S360). The memory controller 110 may, for example, access the VM 130 to perform an SRAM repair operation (S370) in response to migrating the memory recovery firmware FW to the VM 130 at S360. In some example embodiments, operations S360 and S370 may be omitted depending on the type of defective memory. In some example embodiments, operations S360 and S370 may be performed before operations S340 to S345. In some example embodiments, operations S345, S355, and S370 may be performed substantially simultaneously.

[0096] Figure 8 is a flowchart illustrating operations between the memory controller 110 and the memory MEM according to some example embodiments.

[0097] Reference Figure 8 , the memory MEM may perform a data read operation (S410). The memory MEM may correspond to, for example Figure 1 The NVM 120, VM 130 or memory 111 in the memory MEM may transmit the read data to the memory controller 110 (S420).

[0098] The memory controller 110 may, for example, determine whether the data is damaged (S430) in response to receiving the read data from the memory MEM at S420. The memory controller 110 may determine whether the data is recoverable (S440). As a result of the determination, when the data is recoverable (S440=Yes), the memory controller 110 may transmit the read data to the host 200 in response (S442). On the other hand, when the data is unrecoverable (S440=No), the memory controller 110 may enter a memory test mode in response. Figure 9 A description is provided regarding operations S430 and S440 .

[0099] The memory recovery firmware FW may be executed for memory repair, for example, in response to the memory controller 110 entering the memory test mode at S450 (S460). The memory controller 110 may, for example, transmit a command CMD and an address ADDR for memory repair to the memory MEM in response to executing the memory recovery firmware FW at S460 (S470). The memory MEM may, for example, perform a memory repair operation in response to receiving the command CMD and the address ADDR for memory repair on the memory MEM at S470 (S480).

[0100] Figure 9 ECC operation according to the number of error bits (also interchangeably referred to herein as "amount") in data is shown, according to some example embodiments.

[0101] Refer to it together Figure 2 、 Figure 8 and Figure 9 For example, the ECC allowable range of the ECC engine 113 may be one error bit. For example, the occurrence of a one-bit error in the physical address PPNa may cause the physical address PPNa to be changed to the first damaged physical address PPNa′. In some example embodiments, because the number of error bits is one, the ECC engine 113 may correct the one-bit error, and thus the first damaged physical address PPNA′ may be corrected back to the normal physical address PPNa.

[0102] On the other hand, as another example, the occurrence of a two-bit error in the physical address PPNa may cause the physical address PPNa to be changed to a second damaged physical address PPNa". In some example embodiments, because the number of error bits is two, the ECC engine 113 may not be able to correct the two-bit error and may only detect the two-bit error. Therefore, the second damaged physical address PPNa" may correspond to unrecoverable data.

[0103] Figure 10 is a block diagram illustrating a storage system 10 ′ according to some example embodiments.

[0104] Reference Figure 10 , the storage system 10' may include a storage device 100' and a host 200', and the storage device 100' may include a memory controller 110' and an NVM 120'. In addition, the storage device 100' may further include a VM 130'. For example, the VM 130' may include a DRAM. For example, the storage system 10' may include a plurality of storage devices 100'. The storage system 10' according to some example embodiments may correspond to Figure 1 A modified example of the storage system 10, referred to above Figure 1 and Figure 2 The given description may also apply to some example embodiments.

[0105] According to some example embodiments, the storage device 100' may pre-store multiple memory recovery firmware FWs. For example, multiple memory recovery firmware FWs may be stored in the memory controller 110' or the NVM 120' before the storage device 100' is shipped. For example, the MCA 121' of the NVM 120' may store multiple memory recovery firmware FWs. Therefore, when a defective memory occurs in the storage device 100' (for example, in response to determining that a defective memory has occurred in the storage device 100'), the storage device 100' may not receive the memory recovery firmware FW from the host 200', but may regenerate the defective memory based on executing one of the multiple memory recovery firmware FWs previously stored in the storage device 100'. However, the inventive concept is not limited to this, and the storage device 100' may pre-store one memory recovery firmware FW.

[0106] When (e.g., in response to) detecting a defective memory, the memory device 100' may enter a memory test mode. In some example embodiments, the memory test mode may be a mode in which the loaded memory recovery firmware FWa or FWb is executed by loading the memory recovery firmware FWa or FWb previously stored in the memory device 100'. For example, when the memory device 100' detects a UECC (e.g., in response to the memory device 100' detecting a UECC), the memory in which an unrecoverable error has occurred may be determined (e.g., by the memory device 100') as a defective memory.

[0107] In some example embodiments, the memory device 100' may select a specific memory recovery firmware FWa or FWb from among a plurality of pre-stored memory recovery firmware FWs based on the attributes or type of the defective memory, and may execute the selected specific memory recovery firmware FWa or FWb. However, the inventive concept is not limited thereto, and the memory device 100' may execute memory recovery firmware FW applicable to all kinds of memories. For example, in some example embodiments, the memory recovery firmware FW may include a first memory recovery firmware (e.g., FWa) applicable to the NVM 120' (e.g., the first memory recovery firmware may be configured to perform a repair operation on the NVM 120') and a second memory recovery firmware (e.g., FWb) applicable to the VM 130' that is different from FWa (e.g., the second memory recovery firmware may be configured to perform a separate repair operation on the VM 130'), so that the memory controller 110' may be configured to perform a repair operation based on executing the first memory recovery firmware (e.g., FWa) in response to determining that a progressive defect has occurred in the NVM 120', and the memory controller 110' may be configured to perform a repair operation based on executing the second memory recovery firmware (e.g., FWb) in response to determining that a progressive defect has occurred in the VM 130'. In some example embodiments, the first memory recovery firmware (e.g., FWa) may be applicable to both NVM 120′ and VM 130′ (i.e., the first memory recovery firmware may be configured to perform a repair operation on NVM 120′ and a repair operation on VM 130′), so that the memory controller 110′ may be configured to perform a repair operation based on executing the first memory recovery firmware (e.g., FWa) in response to determining that a progressive defect has occurred in VM 130′. In some example embodiments, the memory recovery firmware FW may include a third memory recovery firmware (e.g., FWc) applicable to memory 111′, which may include static RAM (SRAM), and the memory controller 110′ may be configured to perform a repair operation (e.g., a separate repair operation) on the SRAM based on executing the third memory recovery firmware (e.g., FWc) in response to determining that a progressive defect has occurred in the SRAM (e.g., a separate progressive defect has occurred in the SRAM).

[0108] In some example embodiments, the storage device 100' may load memory recovery firmware FW into the memory 111'. For example, the memory recovery firmware FW loaded into the memory 111' may include DRAM recovery firmware or NVM recovery firmware. However, the inventive concept is not limited thereto, and the memory recovery firmware FW loaded into the memory 111' may include memory recovery firmware FW applicable to various memories.

[0109] In some example embodiments, the storage device 100' may load the memory recovery firmware FWb into the VM 130'. For example, the memory recovery firmware FWb loaded into the VM 130' may include SRAM recovery firmware or NVM recovery firmware. However, the inventive concept is not limited thereto, and the memory recovery firmware FWb loaded into the memory VM 130' may include memory recovery firmware FW applicable to all kinds of memories.

[0110] The memory device 100' can test the defective memory by executing the loaded memory recovery firmware FWa or FWb. The memory device 100' can identify defective cells in the defective memory, analyze the defect attributes, and perform repair operations on the defective cells by executing the memory recovery firmware FWa or FWb. The memory device 100' can regenerate the defective memory by replacing the defective cells with redundant cells, thereby allowing the defective memory to be reused. Therefore, since the memory device 100' does not need to be replaced, costs can be reduced.

[0111] Figure 11 Shown included in Figure 10 The MCA 121' in the NVM 120'.

[0112] Reference Figure 11 , the MCA 121' may be divided into a meta area MA and a storage area SA. The meta area MA may store a plurality of memory recovery firmware FWa, FWb, and FWc (e.g., units, instances, products, etc.). In addition, the meta area MA may include a plurality of mapping tables that store mapping information about user data to be stored in the storage area SA. In addition, the storage area SA may be physically or logically divided into various units. For example, the storage area SA may include a plurality of planes PL1 and PL2, and each of the plurality of planes PL1 and PL2 may include a plurality of blocks BLK1 and BLK2. Each of the plurality of blocks BLK1 and BLK2 may be an erase unit of the NVM 120'.

[0113] Figure 12 is a flowchart illustrating operations between the memory controller 110 ′ and the NVM 120 ′ according to some example embodiments.

[0114] Refer to it together Figures 10 to 12, the memory controller 110' may detect a progressive defect in the memory (S510). To reiterate, the memory controller 110' may determine that a progressive defect has occurred in the memory, which is at least one of the NVM 120', the VM 130', and the memory 111'. For example, the memory controller 110' may detect the UECC in the NVM 120', the VM 130', or the memory 111'. The memory controller 110' may, for example, in response to the detection of S510, select memory recovery firmware FW according to the type of defective memory (S520). For example, the memory controller 110' may select one of a plurality of memory recovery firmware FWs stored in the NVM 120' according to the type of defective memory (e.g., select a specific memory recovery firmware FW among the plurality of memory recovery firmware FWs).

[0115] The memory controller 110' may, for example, in response to the detection of S510 and / or the selection of S520, transmit a read command RCMD and an address ADDR to the NVM 120' to read the memory recovery firmware FW (S530). Such a read command RCMD and address ADDR may indicate a specific memory recovery firmware FW based on the type or attribute of the memory in which a progressive defect has occurred (e.g., a defective memory). The NVM 120' may, for example, in response to the transmission of S530, perform a data read operation (S540). For example, the NVM 120' may read the selected (e.g., specific) memory recovery firmware FW by performing a read operation on the meta area MA of the MCA 121'.

[0116] NVM 120' may, for example, transmit the read (e.g., specific, selected) memory recovery firmware FW to memory controller 110' (S550) in response to performing a data read operation at S540. Therefore, memory controller 110' may receive the memory recovery firmware FW from NVM 120' in response to determining that a progressive defect has occurred at S510. Therefore, NVM 120' may be configured to transmit the memory recovery firmware FW to memory controller 110' in response to determining that a progressive defect has occurred at S510. If NVM 120' stores multiple memory recovery firmware FWs, as described above, the transmission at S550 may include transmitting the specific memory recovery firmware FW selected at S520, so that memory controller 110' receives (e.g., downloads) the specific memory recovery firmware FW from the multiple memory recovery firmware FWs based on the type or attributes of the memory in which the progressive defect has occurred. For example, memory controller 110' may load the received memory recovery firmware FW into memory 111' or VM 130'. The memory controller 110' may enter a memory test mode (S560), for example, in response to the transmission of S550, the detection of S510, and / or the selection of S520. For example, the memory test mode may correspond to a memory recoverable firmware loadable mode. In some example embodiments, operation S560 may be performed before operation S550.

[0117] The memory controller 110' may, for example, execute memory recovery firmware FW for memory repair in response to entering the memory test mode at S560, detecting at S510, transmitting at S550, and / or selecting at S520 (S570). For example, the memory controller 110' may repair a defective memory by executing the memory recovery firmware FW downloaded to the memory 111'.

[0118] Figure 13 is a flowchart illustrating operations between a host and a storage device according to some example embodiments.

[0119] Reference Figure 13 , the host may correspond to, for example Figure 1 In the host 200, the storage device may correspond to, for example Figure 1 The storage device 100 in the above reference Figures 1 to 12 The description given is also applicable to some example embodiments, and repeated descriptions are omitted. Hereinafter, an example of operations between a host and a storage device over time is described. The host may be in the process of performing a data input / output operation on the storage device (S600). For example, the host may transmit a write request or a read request to the storage device, and the storage device may write data or read data in response to the write request or the read request, respectively.

[0120] In the first interval 1331, a memory error may occur in the storage device (S611). For example, an ECC engine included in the storage device may detect a UECC in the NVM or VM. The storage device may, for example, record a memory failure address (i.e., a memory defect address) in response to the occurrence of the error in S611 (S612). For example, the memory failure address may include a physical address. However, the inventive concept is not limited thereto, and the memory failure address may include a logical address. Next, the storage device may, for example, mark a memory failure signature in response to the recording in S612 (S613). For example, the storage device may mark a memory failure signature on a specific area of ​​the NVM or a specific area of ​​the SRAM. Next, the storage device may, for example, be reset in response to the marking in S613 (S614). Therefore, the first interval 1331 may be referred to as a first reset interval or a first reset cycle. For example, the storage device may perform operations S611 to S614 based on executing the main firmware.

[0121] When the storage device is reset (e.g., in response to the storage device being reset at S614), a second interval 1332 may begin. In the second interval 1332, the storage device may enter a fault mode or a memory test mode. First, the storage device may check a memory fault signature (S621). Next, the storage device may transmit a memory fault notification to the host (S622), for example, in response to the check at S621, and the host may receive a memory fault notification from the storage device (S630), for example, in response to the transmission at S622. The storage device may download memory recovery firmware (S641). The downloading of S641 may be performed in response to any of the aforementioned operations S611 to S630. In some example embodiments, a memory controller (e.g., Figure 1 110) may receive memory recovery firmware FW from the host. In some example embodiments, a memory controller of the storage device (e.g., Figure 11 110') can be obtained from NVM (e.g., Figure 10 120') receives the memory recovery firmware FW.

[0122] The storage device may, for example, execute the memory recovery firmware FW to repair the memory error in response to the download at S641 (S640). The storage device may perform a test and repair operation on the memory (S642), return the result thereof (S643), and re-mark the memory repair signature (S644). For example, the memory repair signature indicates that the repair operation on the defective memory is complete. For example, the storage device may change the memory fault signature to a memory repair signature. For example, when the memory fault signature is logic "1" (for example, in response to the memory fault signature being logic "1"), the memory repair signature may be logic "0". Subsequently, the storage device may be reset (S645), for example, in response to the execution of the repair at S640. Therefore, the second interval 1332 may be referred to as a second reset interval or a second reset cycle. For example, the storage device may perform operations S621 to S645 based on executing the main firmware.

[0123] When the storage device is reset (e.g., in response to determining that the storage device is reset at S645), a third interval 1333 may begin. During third interval 1333, the storage device may enter a fault mode or a memory test mode. First, the storage device may check for a memory repair signature (S651). Next, the storage device may transmit a memory repair notification to the host (S653), for example, in response to the check at S651. The host may receive the memory repair notification from the storage device (S660), for example, in response to the transmission at S653. For example, the storage device may perform operations S651 to S653 based on executing host firmware. Next, the host may format the storage device (S670), for example, in response to the reception at S660, and reuse the storage device (S680).

[0124] It will be appreciated that performing an operation in response to a previous operation may include performing an operation in response to a result of the previous operation.

[0125] Figure 14 is a flowchart illustrating operations between a host and a storage device according to some example embodiments.

[0126] Reference Figure 14 , the host may correspond to, for example Figure 1 In the host 200, the storage device may correspond to, for example Figure 1 The operation between the host and the storage device according to some example embodiments may correspond to Figure 13 Therefore, the above reference Figure 13 The description given may also be applied to some example embodiments, and repeated descriptions are omitted. The host may be in the process of performing a data input / output operation on the storage device (S600). The operation of the storage device in the first interval 141 may be the same as Figure 13The operations of the storage devices in the first compartment 1331 are performed identically or substantially identically.

[0127] When the storage device is reset (e.g., in response to the storage device being reset at S614), the second interval 142 may begin. In the second interval 142, the storage device may enter a fault mode or a memory test mode. First, the storage device may check the memory fault signature (S621). As a result of checking the memory fault signature (e.g., in response to the result of the checking), in some example embodiments of the memory fault, the storage device may download memory recovery firmware FW (S641a). In some example embodiments, the memory controller of the storage device (e.g., Figure 10 110') can be obtained from NVM (e.g., Figure 10 The storage device receives the memory recovery firmware FW (see 120' in FIG). For example, the storage device may perform operations S621 and S641a based on executing the ROM code. The storage device may execute the memory recovery firmware FW to repair the memory error (S640). The storage device may perform a test and repair operation on the memory (S642), return the result (S643), and re-mark the memory repair signature. Subsequently, the storage device may be reset (S645).

[0128] When the storage device is reset (e.g., in response to the storage device being reset in S645), the third interval 143 may begin. During the third interval 143, the storage device may check the memory repair signature (S651). As a result of checking the memory repair signature, if the memory has been repaired (e.g., in response to the memory being repaired), the storage device may boot by receiving normal firmware from the NVM (S652). For example, the storage device may perform operations S651 and S652 based on executing ROM code. Next, the storage device may transmit a memory failure notification to the host (S654), and the host may receive the memory failure notification from the storage device (S665). For example, the storage device may perform operation S654 based on executing the host firmware. Next, the host may format the storage device (S670) and reuse the storage device (S680).

[0129] Figure 15 A network system 1000 is shown according to some example embodiments.

[0130] Reference Figure 15The network system 1000 may be a facility that collects various data and provides services, and may also be referred to as a data center or data storage center. The network system 1000 may include application servers 1100 to 1100n and storage servers 1200 to 1200n, which may be referred to as computing nodes. The number of application servers 1100 to 1100n and the number of storage servers 1200 to 1200n may be selected differently according to some example embodiments, and the number of application servers 1100 to 1100n and the number of storage servers 1200 to 1200n may be different from each other.

[0131] The application servers 1100 to 1100n and the storage servers 1200 to 1200n can communicate with each other via a network 1300. The network 1300 can be implemented using Fibre Channel (FC) or Ethernet, etc. In some example embodiments, FC can be a medium for high-speed data transmission, and an optical switch that provides high performance and high availability can be used. Depending on the access method of the network 1300, the storage servers 1200 to 1200n can be provided as file storage devices, block storage devices, or object storage devices.

[0132] In some example embodiments, the network 1300 may include a storage-specific network such as a storage area network (SAN). For example, the SAN may include a Fibre Channel (FC) SAN (FC-SAN) implemented using an FC network according to the FC protocol (PCP). In some example embodiments, the SAN may include an Internet Protocol (IP) SAN (IP_SAN) implemented using a TCP / IP network according to the Internet (i) Small Computer System Interface (SCSI) (iSCSI) (i.e., SCSI over Transmission Control Protocol (TCP) / IP (TCP / IP), or Internet SCSI) protocol. In some example embodiments, the network 1300 may include a general-purpose network such as a TCP / IP network. For example, the network 1300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or NVMe over Network (NVMe-oF).

[0133] Hereinafter, the application server 1100 and the storage server 1200 will be mainly described. The description of the application server 1100 is applicable to other application servers (eg, 1100n), and the description of the storage server 1200 is applicable to other storage servers (eg, 1200n).

[0134] Application server 1100 may include at least one of a processor 1110 and a memory 1120. Processor 1110 may control the overall operation of application server 1100 and access memory 1120 to execute commands and / or data loaded in memory 1120. According to some example embodiments, the number of processors 1110 and the number of memories 1120 included in application server 1100 may be selected differently. In some example embodiments, processor 1110 and memory 1120 may provide a processor-memory pair. In some example embodiments, the number of processors 1110 and the number of memories 1120 may be different from each other.

[0135] The application server 1100 may further include a storage device 1150. In some example embodiments, the number of storage devices 1150 included in the application server 1100 may be selected differently according to some example embodiments. The processor 1110 may provide a command to the storage device 1150, and the storage device 1150 may generate device information in response to the command received from the processor 1110 or by itself, and the generated device information may be provided to the processor 1110. However, the inventive concept is not limited thereto, and the application server 1100 may not include the storage device 1150.

[0136] Application server 1100 may further include a switch 1130 and a network interface card (NIC) 1140. Under the control of processor 1110, switch 1130 may selectively connect processor 1110 to storage device 1150, or selectively connect NIC 1140 to storage device 1150. NIC 1140 may include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. In some example embodiments, processor 1110 and NIC 1140 may be integrated into one. In some example embodiments, storage device 1150 and NIC 1140 may be integrated into one.

[0137] The application server 1100n may include at least one of a processor 1110n and a memory 1120n. The application server 1100n may also include a storage device 1150n. The application server 1100n may also include a switch 1130n and a network interface card (NIC) 1140n.

[0138] The application server 1100 may store data requested by a user or client in one of the storage servers 1200 to 1200n via the network 1300. In addition, the application server 1100 may obtain data requested to be read by a user or client from one of the storage servers 1200 to 1200n via the network 1300. For example, the application server 1100 may be implemented as a network server or a database management system (DBMS).

[0139] The application server 1100 can independently access the memory 1120n or storage device 1150n included in another application server 1100n via the network 1300, or access the memory 1220 to 1220n or storage devices 1250 to 1250n included in the storage servers 1200 to 1200n via the network 1300. Therefore, the application server 1100 can perform various operations on the data stored in the application servers 1100 to 1100n and / or the storage servers 1200 to 1200n. For example, the application server 1100 can execute a command for moving or copying data between the application servers 1100 to 1100n and / or the storage servers 1200 to 1200n.

[0140] The storage server 1200 may include at least one of a processor 1210 and a memory 1220. The processor 1210 may control the overall operation of the storage server 1200 and access the memory 1220 to execute commands and / or data loaded in the memory 1220. According to some example embodiments, the number of processors 1210 and the number of memories 1220 included in the storage server 1200 may be selected differently. In some example embodiments, the processor 1210 and the memory 1220 may include a processor-memory pair. In some example embodiments, the number of processors 1210 and the number of memories 1220 may be different from each other.

[0141] The processor 1210 may include a single-core processor or a multi-core processor. For example, the processor 1210 may include a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller (MCU), a microprocessor, a network processor, an embedded processor, a field programmable gate array (FPGA), an application-specific instruction set processor (ASIP), and an application-specific integrated circuit (ASIC) processor. For example, the processor 1210 may be packaged in a general processor package, a multi-core processor package, a system-on-chip (SoC) package, a system-in-package (SiP) package, a system-on-package (SOP) package, etc.

[0142] The storage server 1200 may further include at least one storage device 1250. The number of storage devices 1250 included in the storage server 1200 may be selected differently according to some example embodiments. The storage device 1250 may include a controller (CTRL) 1251, a NAND flash memory 1252, a DRAM 1253, and an interface (I / F) 1254. Hereinafter, the configuration and operation of the storage device 1250 will be described in detail. The following description of the storage device 1250 may be applied to the other storage devices 1150 to 1150n and 1250 to 1250n.

[0143] The interface 1254 may provide the controller 1251 with a physical connection between the processor 1210 and the controller 1251 and a physical connection between the NIC 1240 and the controller 1251. For example, the I / F 1254 may be implemented in a direct attached storage (DAS) method of directly connecting the storage device 1250 to a dedicated cable. In addition, for example, the I / F 1254 may be implemented in various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Node Version Manager (NVM) Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMediaCard (MMC), Embedded MultiMediaCard (eMMC), and Compact Flash (CF) card.

[0144] The controller 1251 may control the overall operation of the storage device 1250. In some example embodiments, the controller 1251 may include an SRAM. The controller 1251 may write data to the NAND flash memory 1252 in response to a write command, or may read data from the NAND flash memory 1252 in response to a read command. For example, the write command and / or the read command may be provided by the processor 1210 in the storage server 1200, the processor 1210n in another storage server 1200n, or the processors 1110 to 1110n in the application servers 1100 to 1100n, respectively.

[0145] The NAND flash memory 1252 may include a plurality of NAND flash memory cells. However, the inventive concept is not limited thereto, and the storage device 1250 may include other NVMs (e.g., resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM), or a magnetic storage medium or an optical storage medium, etc.) in addition to the NAND flash memory 1252.

[0146] The DRAM 1253 may be used as a buffer memory. For example, the DRAM 1253 may be a double data rate (DDR) SRAM (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a rambus DRAM (RDRAM), or a high bandwidth memory (HBM). However, the inventive concept is not limited thereto, and the storage device 1250 may use a VM other than DRAM or NVM as a buffer memory.

[0147] However, the configuration of the storage device 1250 is not limited to the description given above, and may include various memories (such as DRAM, SDRAM, hard disk drive (HDD), solid state drive (SSD), redundant array of independent disks (RAID) volume, non-volatile dual in-line memory module (NVDIMM), network attached storage (NAS), flash memory (such as planar NAND flash memory, three-dimensional (3D) NAND flash memory and NOR flash memory), 3D cross point memory, non-volatile MRAM (NVMRAM), ReRAM, PRAM, FRAM, ReRAM and memristor, or a combination thereof).

[0148] The storage server 1200 may further include a switch 1230 and a NIC 1240. Under the control of the processor 1210, the switch 1230 may selectively connect the processor 1210 to the storage device 1250, or selectively connect the NIC 1240 to the storage device 1250. In some example embodiments, the processor 1210 and the NIC 1240 may be integrated into one. In some example embodiments, the storage device 1250 and the NIC 1240 may be integrated into one.

[0149] The storage devices 1150 to 1150n and 1250 to 1250n may be configured according to the above references. Figures 1 to 14 According to some example embodiments of the inventive concept, the controller 1251 of the storage device 1250 may include an SRAM, and the storage device 1250 may detect a UECC in the SRAM, the NAND flash memory 1252, and / or the DRAM 1253. In some example embodiments, the storage device 1250 may provide information about the detected UECC to the application server 1100 via the network 1300. The application server 1100 may generate a recovery command based on the information about the detected UECC, so that the storage device 1250 enters a recovery mode, and provide the generated recovery command to the storage device 1250 via the network 1300. In some example embodiments, the application server 1100 may provide memory recovery firmware FW to the storage device 1250.

[0150] The storage device 1250 may execute the memory recovery firmware FW in response to the recovery command to regenerate defective memory in the SRAM, NAND flash memory 1252, and / or DRAM 1253. The storage device 1250 may identify defective cells in the SRAM, NAND flash memory 1252, and / or DRAM 1253, analyze the defect attributes, and perform repair operations on the defective cells. In some example embodiments, the storage device 1250 may execute the memory recovery firmware FW received from the application server 1100. However, the inventive concept is not limited thereto, and the storage device 1250 may execute the memory recovery firmware FW previously stored in the NAND flash memory 1252.

[0151] The storage server 1200n may include a processor 1210n and / or a memory 1220n, a switch 1230n, a storage device 1250n, and a NIC 1240n.

[0152] While the inventive concept has been particularly shown and described with reference to certain example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A storage device comprising: Non-volatile memory; Volatile memory; and a memory controller configured to control the nonvolatile memory and the volatile memory, The memory controller is further configured to: during operation of the memory device, in response to determining that a progressive defect has occurred in at least one of the non-volatile memory and the volatile memory, such that the at least one memory is determined to be a defective memory, download memory recovery firmware, and perform a repair operation on the defective memory based on executing the memory recovery firmware; The memory controller is configured as follows: In response to determining that a progressive defect has occurred, transmitting information associated with the progressive defect to a host and downloading memory recovery firmware from the host, or In response to determining that a progressive defect has occurred, memory recovery firmware is downloaded as a specific memory recovery firmware among a plurality of memory recovery firmwares stored in the nonvolatile memory according to a type or attribute of the defective memory.

2. The storage device according to claim 1, wherein The information associated with the progressive defect includes information associated with the type or attribute of the defective memory, and The memory controller is further configured to download the memory recovery firmware from the host based on the memory recovery firmware being specific memory recovery firmware corresponding to the type or attribute of the defective memory.

3. The storage device according to claim 1 or 2, wherein: The memory recovery firmware includes a first memory recovery firmware, and The memory controller is further configured to, in response to determining that a progressive defect has occurred in the non-volatile memory, perform a repair operation based on executing the first memory recovery firmware. The storage device according to claim 3 , wherein: The memory recovery firmware further includes a second memory recovery firmware different from the first memory recovery firmware, and The memory controller is further configured to, in response to determining that a progressive defect has occurred in the volatile memory, perform a repair operation based on executing the second memory recovery firmware.

5. The storage device according to claim 1 or 2, wherein: The memory recovery firmware includes a first memory recovery firmware, and The memory controller is configured to, in response to determining that a progressive defect has occurred in the volatile memory or the non-volatile memory, perform a repair operation based on executing the first memory recovery firmware.

6. The storage device according to claim 1 or 2, wherein: The memory controller is configured to perform a repair operation based on replacing at least one defective cell among a plurality of memory cells included in a defective memory with a redundant cell.

7. A method for operating a storage device, the storage device comprising a non-volatile memory, a volatile memory, and a memory controller, the method comprising: detecting, by a memory controller, a progressive defect in at least one of a non-volatile memory and a volatile memory, so that the memory in which the progressive defect is detected is determined to be a defective memory; entering, by the memory controller, a memory test mode in response to detecting a progressive defect; and The memory controller downloads memory recovery firmware in a memory test mode, and performs a repair operation on the defective memory based on executing the memory recovery firmware. The operation method further includes: In response to detecting a progressive defect, transmitting, by the memory controller, information associated with the progressive defect to a host; and memory recovery firmware received by the memory controller from the host, or In response to detecting a progressive defect, a memory recovery firmware is downloaded by the memory controller as a specific memory recovery firmware among a plurality of memory recovery firmwares stored in the nonvolatile memory according to a type or attribute of the defective memory.

8. The operating method according to claim 7, wherein: Memory recovery firmware is received by the memory controller based on information associated with the progressive defect having been transmitted to the host, The step of performing the repair operation includes executing memory recovery firmware received from the host.

9. The operating method according to claim 7, in, The step of performing a repair operation includes executing memory recovery firmware downloaded from the non-volatile memory.

10. The operating method according to any one of claims 7 to 9, wherein: The memory recovery firmware is configured to perform both repair operations on the non-volatile memory and repair operations on the volatile memory.

11. The operating method according to any one of claims 7 to 9, wherein: The memory recovery firmware includes: first memory recovery firmware configured to perform a first repair operation on the non-volatile memory; and The second memory recovery firmware is configured to perform a second repair operation on the volatile memory.

12. A memory controller configured to control a memory, the memory controller comprising: a memory interface configured to transmit and receive data to and from the memory; an error checking and correction engine configured to correct errors in data read from the memory; and memory recovery firmware configured to: perform a repair operation on the memory in response to a determination by the memory controller that an uncorrectable error has occurred in the memory, the uncorrectable error being an error that the error checking and correction engine is unable to correct, wherein the memory recovery firmware is configured to be downloaded to the memory controller in response to a determination by the memory controller that an uncorrectable error has occurred in the memory, The memory controller further includes a host interface configured to communicate with a host. The memory recovery firmware is configured to be downloaded from the host via a host interface, or a specific memory recovery firmware among multiple memory recovery firmwares stored in a non-volatile memory of the memory is downloaded as the memory recovery firmware according to the type or attribute of the memory.

13. The memory controller according to claim 12, wherein: The memory includes nonvolatile memory, and The memory recovery firmware is configured to perform a repair operation on the non-volatile memory.

14. The memory controller according to claim 13, wherein: The memory recovery firmware is configured to be downloaded by the memory controller from a non-volatile memory via a memory interface.

15. The memory controller according to claim 12, wherein: The memory includes volatile memory, and The memory recovery firmware is configured to perform repair operations on volatile memory.

16. The memory controller according to any one of claims 12 to 15, further comprising: internal memory, The memory recovery firmware is loaded into the internal memory.

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