A low-cost multi-chip high-speed and high-bandwidth interconnect structure

Abstract

The present invention discloses a low-cost multi-chip high-speed high-bandwidth interconnection structure, comprising: a plurality of active chips, an interconnection substrate and a flip-chip interconnection bump; the interconnection substrate is used to realize metal interconnection and mechanical support between each active chip; the active chips realize data exchange through an ultra-high-speed interface and jointly bear artificial intelligence computing power; the active chips are connected to the interconnection substrate in a flip-chip welding manner through the flip-chip interconnection bump. The present invention can not only greatly improve the computing power of the artificial intelligence system, but also greatly reduce the production cost of the artificial intelligence system.

Description

Technical Field

[0001] The invention discloses a low-cost multi-chip high-speed and high-bandwidth interconnection structure, and relates to the technical field of artificial intelligence module system-level integration. Background Art

[0002] Artificial Intelligence (AI) is a science and technology that studies and develops theories, methods, technologies and applications for simulating, extending and expanding human intelligence. With the continuous development of artificial intelligence technology in the fields of machine learning, high-performance computing, image recognition, genetic engineering, etc., the amount of data that artificial intelligence technology needs to process has exploded. In a certain AI training application, the bandwidth requirement of a single SoC may exceed several TB / s. Traditional chip and system integration methods can no longer meet the needs of artificial intelligence technology. At present, Silicon Interposer technology is a traditional technology for artificial intelligence system integration. The more well-known products include NVIDIA's Tesla A100 and Radeon VII, Google's chip TPU 3.0, etc.

[0003] Patent TW201826403A Methods of forming cowos structures discloses the manufacturing method of TSMC COWOS (Chip on Wafer on Substrate). In order to improve the integration, the SOC and HBM (High Bandwidth Memory) are integrated by using a silicon-based adapter board to form a high-bandwidth computing module. However, the technical process of the silicon-based adapter board is difficult and the production cost is high. Moreover, this integration method has an upper limit in theory, which is subject to the data processing capability of a single SOC.

[0004] Traditional AI system integration technology is overly dependent on the development of Moore's Law. It continuously improves the integration of transistors in a single chip, designs superchips with powerful computing power, and uses high-cost silicon-based adapter board technology, which is integrated with HBM and then packaged in a traditional way. However, as Moore's Law comes to an end, the size of transistors is getting closer and closer to the limit, and the corresponding production cost is also getting higher and higher. In addition, due to the material properties of silicon, silicon-based adapter boards are not naturally suitable for large-area integration. Summary of the invention

[0005] The technical problem to be solved by the present invention is: to provide a low-cost multi-chip high-speed and high-bandwidth interconnection structure in view of the defects of the prior art.

[0006] The present invention adopts the following technical solutions to solve the above technical problems:

[0007] A low-cost multi-chip high-speed and high-bandwidth interconnection structure, comprising: the interconnection structure comprises: a plurality of active chips, an interconnection substrate and flip-chip interconnection bumps, wherein the interconnection substrate is used to realize metal interconnection and mechanical support between each active chip; the active chips realize data exchange through an ultra-high-speed interface and jointly bear artificial intelligence computing power; the active chips are connected to the interconnection substrate in a flip-chip welding manner through the flip-chip interconnection bumps.

[0008] The multiple active chips are used to bear the computing power of the artificial intelligence system. If the computing requirements of the system exceed the data transmission volume and computing power of a single active chip, each active chip can collect external transmission data at the same time, and each active chip can exchange data through an ultra-high-speed interface, and jointly bear the computing power of artificial intelligence. The main advantage of this parallel computing is that it innovatively proposes the use of multiple identical active chips for parallel computing, which can reduce the computing power requirements of a single chip and greatly reduce the design and production costs of the chip.

[0009] As a preferred solution, the architecture and functions of each active chip are exactly the same. They are discrete small systems that can be independently interconnected with external data or integrated in an array. The number of integrated chips can be flexibly designed according to the computing power requirements of the system. Unlike the heterogeneous integration of different chips, this array integration method greatly reduces the difficulty of integration.

[0010] As a preferred solution, the ultra-high-speed interconnection interface between active chips includes other high-speed interconnection interfaces such as NRZ, PAM4, PAM8, etc. Currently, the commercial single-channel high-speed interface rate can reach 112Gbps, which can meet the high-speed and high-bandwidth interconnection requirements.

[0011] As a preferred embodiment, the metal interconnection includes horizontal interconnection and vertical interconnection; the horizontal electrical interconnection is mainly provided by metal wires and can be made by exposure and etching methods, and the vertical electrical interconnection is made by laser blind buried holes or mechanical through-hole methods.

[0012] In a specific embodiment, the available options for the flip chip interconnect bumps include C4 bumps, copper bumps, or other metal bumps.

[0013] As a preferred solution, the flip-chip interconnect bumps should have a specific bump arrangement: each pair of differential signal bumps are not adjacent, and are separated by a pair of ground bumps. While not affecting the interconnect performance of a single channel, the specific bump array can greatly reduce the crosstalk between different channels.

[0014] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: The present invention uses low-cost substrate technology to integrate multiple chips, realizes parallel computing of multiple chips, and greatly improves the computing power of the artificial intelligence system. The improvement of system performance is no longer solely dependent on the improvement of the computing power of a single SOC. Under the condition of the same computing power, the use of this unique multi-chip parallel architecture can greatly reduce the design difficulty and production cost compared with a single SOC chip architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a cross-sectional view of a packaging structure in a specific embodiment of the present invention;

[0016] Figure 2 is a top view of a package structure in a specific embodiment of the present invention, including a plurality of active chips and their interconnection methods;

[0017] Figure 3 In a specific embodiment of the present invention, a single active chip and its bump arrangement;

[0018] Figure 4 It is a simulation result diagram of a three-dimensional full-wave electromagnetic field simulation tool in the present invention;

[0019] Figure 5 This is the result diagram of the eye diagram simulated at the receiving end of the present invention;

[0020] Among them: 101-active chip, 102-chip flip-chip interconnection bumps, 103-metal interconnection between active chips, 104-substrate vertical electrical interconnection, 105-substrate horizontal electrical interconnection, 106-solder ball; 201-signal bump, 202-power bump. DETAILED DESCRIPTION

[0021] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0022] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0023] Combination Figure 1-Figure 2 The present invention describes in detail a low-cost multi-chip high-speed high-bandwidth interconnection structure suitable for artificial intelligence system integration, including multiple active chips, a low-cost interconnection substrate and a flip-chip interconnection bump, and its structural schematic diagram is shown in FIG. Figure 1 As shown, the top view is Figure 2As shown. Multiple active chips 101 are mounted on a low-cost interconnect substrate, and the low-cost interconnect substrate is used to provide metal interconnection and mechanical support between each active chip 101. The low-cost interconnect substrate includes an organic medium substrate or a low-temperature co-fired ceramic substrate or a high-temperature co-fired ceramic substrate. The metal interconnection 103 between the active chips can be realized on the interconnect substrate, and the metal interconnection includes a substrate horizontal electrical interconnection 105 in the horizontal direction and a substrate vertical electrical interconnection 104 in the vertical direction. Data exchange is achieved between each active chip through an ultra-high-speed interface, and the ultra-high-speed interface includes other high-speed interconnection interfaces such as NRZ, PAM4, PAM8, etc. The flip-chip interconnection bumps 102 of the chip include C4 bumps, copper bumps or other metal bumps, and the active chip is connected to the interconnection substrate through the flip-chip interconnection bumps. The flip-chip interconnection bumps should have a specific arrangement, such as Figure 2 As shown in the figure, each pair of differential signal bumps are not adjacent, and are separated by a pair of ground bumps. While not affecting the interconnection performance of a single channel, the specific bump array can greatly reduce the crosstalk between different channels. A single active chip and its bump arrangement are shown in the figure. Figure 3 As shown, the signal bumps 201 and the power bumps 202 are arranged at intervals.

[0024] The present invention uses a three-dimensional full-wave electromagnetic field simulation tool to model the passive interconnect structure, which can accurately compare the transmission characteristics of different structures based on traditional bump arrangements and specific bump arrangements. Figure 4 The simulation results show that at 2 times the Nyquist frequency, the crosstalk between different channels in the passive structure corresponding to the specific bump array is only below -40dB, which is much better than the isolation of -30dB based on the traditional bump array. The simulation results prove that the specific bump arrangement is conducive to the interconnection between active chips.

[0025] The present invention uses the time domain eye diagram simulation tool ADS to cascade the chip active model IBIS AMI model and the S parameter models of all passive channels to simulate the eye diagram results at the receiving end. Figure 5 The simulation results shown in the figure show that when the transmission speed of a single channel is 112Gbps (only one differential pair transmits data; when the channel contains multiple differential pairs, the channel transmission data is doubled), the eye diagram at the receiving end is still clearly open, proving the possibility of high-speed and high-bandwidth transmission between active chips.

[0026] The above is a detailed description of the implementation mode of the present invention in conjunction with the accompanying drawings, but the present invention is not limited to the above implementation mode. Various changes can be made within the knowledge scope of ordinary technicians in the field without departing from the purpose of the present invention. The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical content disclosed above to an equivalent embodiment of equivalent changes without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principle of the present invention, still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A low-cost multi-chip high-speed high-bandwidth interconnect structure, characterized in that: The interconnect structure comprises: a plurality of active chips, an interconnect substrate and flip-chip interconnect bumps, wherein: The interconnection substrate is used to realize metal interconnection and mechanical support between various active chips; The metal interconnection includes horizontal interconnection and vertical interconnection; In the horizontal direction, metal wires are made by exposure and etching to achieve electrical interconnection; Make laser blind buried vias or mechanical through holes in the vertical direction to achieve electrical interconnection; The active chips exchange data through ultra-high-speed interfaces and jointly undertake artificial intelligence computing power; Multiple active chips, each with the same architecture and functions, each independently interconnects with external data, independently undertakes artificial intelligence computing power, and transmits and calculates in parallel through ultra-high-speed interfaces; The active chip is connected to the interconnection substrate in a flip-chip soldering manner through the flip-chip interconnection bumps; The arrangement of the flip-chip interconnect bumps is as follows: each pair of differential signal bumps are not adjacent to each other and are separated by a pair of ground bumps; In a single active chip, signal bumps and power bumps are arranged alternately.

2. A low-cost multi-chip high-speed high-bandwidth interconnect structure as claimed in claim 1, characterized in that: The interconnect substrate includes an organic medium substrate, a low temperature co-fired ceramic substrate or a high temperature co-fired ceramic substrate.

3. A low-cost multi-chip high-speed high-bandwidth interconnect structure as claimed in claim 1, characterized in that: The flip-chip interconnect bumps include C4 bumps, copper bumps or other metal bumps.

4. A low-cost multi-chip high-speed high-bandwidth interconnect structure as claimed in claim 1, characterized in that: The ultra-high-speed interface includes an NRZ interface, a PAM4 interface or a PAM8 interface, and other PAMN interfaces, where N is an integer.

Images