A chip resetting method and device for ultrasonic equipment and ultrasonic system

Abstract

The present invention discloses a chip resetting method and device for ultrasonic equipment and an ultrasonic system. The method comprises: a reset control chip of the ultrasonic equipment performs power-on reset according to an acquired power-on reset signal; after the reset is completed, a reset instruction of a target chip is acquired; wherein the target chip comprises a main control chip in the ultrasonic equipment, and the main control chip comprises functional modules that are reset by different reset modes; according to the reset instruction, a reset sequence is generated according to the reset mode corresponding to each functional module, and the main control chip is controlled to perform a reset operation according to the reset sequence sequence; the present invention adopts a reset control chip to sequentially control the main control chip to reset according to the reset mode of each functional module in the main control chip, thereby ensuring the reliable reset of each functional module in the main control chip and avoiding the situation where the reset fan-out of the main control chip is large; and the independent reset control chip is set, so that the design of chip reset can be flexible.

Description

Technical Field

[0001] The present invention relates to the field of ultrasonic technology, and in particular to a chip resetting method and device for ultrasonic equipment and an ultrasonic system. Background Art

[0002] Ultrasound equipment contains a variety of control chips and front-end chips (i.e. peripheral chips), all of which need certain power-on and reset timing requirements to ensure the correctness, stability and reliability of the ultrasound equipment after power-on. Since the reset control signal needs to be reset after the power supply is stable, a power-on delay chip is usually used. After the last power supply is powered on, the reset level is pulled high for a period of time to reset the chip, and the power supply is released after a certain period of time.

[0003] At present, the reset timing of the front-end chip is mostly controlled by the main control chip (mostly FPGA chip in ultrasound equipment); and although the FPGA (Field Programmable Gate Array) chip can flexibly generate the reset control timing according to the timing requirements of the front-end chip; however, whether the FPGA chip adopts the external hardware reset method or the soft reset method, it will cause a large reset fan-out, affecting the timing (timing analysis) of the FPGA chip; and the reset of the FPGA chip itself needs to wait until the FPGA is loaded and the clock is stable. If the resources of the FPGA chip are large and the loading time is long, a power-on delay chip needs to be controlled. The delay time has high requirements.

[0004] Therefore, how to avoid the impact of the chip reset of the ultrasonic equipment on the timing analysis of the main control chip and reduce the requirements for the power-on delay chip is an urgent problem that needs to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a chip reset method, device and ultrasonic system for ultrasonic equipment, so as to improve the design flexibility of chip reset of ultrasonic equipment and avoid the influence of chip reset on the timing analysis of main control chip.

[0006] In order to solve the above technical problems, the present invention provides a chip resetting method of an ultrasonic device, comprising:

[0007] The reset control chip of the ultrasound device performs power-on reset according to the acquired power-on reset signal;

[0008] After the reset is completed, a reset instruction of the target chip is obtained; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules that are reset by different reset modes;

[0009] According to the reset instruction, a reset sequence is generated according to the reset mode corresponding to each of the functional modules, and the main control chip is controlled to perform a reset operation according to the reset sequence.

[0010] Optionally, when the target chip further includes a peripheral chip, after obtaining the reset instruction of the target chip, the method further includes:

[0011] According to the reset clock of the peripheral chip, the peripheral chip is controlled to perform a reset operation.

[0012] Optionally, controlling the main control chip to perform a reset operation according to the reset timing sequence includes:

[0013] According to the reset timing, a handshake mechanism is used to sequentially control the functional modules of the main control chip to perform a reset operation.

[0014] Optionally, when the reset mode includes synchronous reset and asynchronous reset, the reset operation of each functional module of the main control chip is sequentially controlled by a handshake mechanism according to the reset timing, including:

[0015] Controlling the main control chip to enter a synchronous reset state to reset the synchronous reset function module;

[0016] Control the main control chip to enter an asynchronous reset state, so that the asynchronous reset function module is reset and the synchronous reset function module exits reset;

[0017] Controlling the clock output enable signal to remain in an invalid state so that the reset signal of the main control chip exits the reset state;

[0018] After the reset signal of the main control chip exits the reset state, the clock output enable signal is set to a valid state.

[0019] Optionally, when the main control chip is specifically an FPGA, the reset operation of each functional module of the main control chip is sequentially controlled by a handshake mechanism according to the reset timing, including:

[0020] Controlling a loading control signal of the FPGA so that the FPGA loads a configuration file;

[0021] Monitor the working signal of the FPGA and wait for the loading of the FPGA to be completed;

[0022] After determining that the FPGA is loaded, a PLL phase-locked loop reset signal and an FPGA reset signal of the FPGA are controlled to remain in a valid state, and a clock output enable signal of the FPGA is controlled to remain in an invalid state, so as to control the PLL reset of the FPGA;

[0023] Setting the PLL phase-locked loop reset signal to an invalid state, monitoring the PLL lock signal of the FPGA, and waiting for the PLL of the FPGA to be locked;

[0024] After determining that the PLL of the FPGA is locked, setting the clock output enable signal to a valid state so as to reset the synchronous reset register of the FPGA to zero;

[0025] Setting the clock output enable signal to an invalid state so that the asynchronous reset register of the FPGA is reset to zero and the synchronous reset register exits reset;

[0026] Setting the FPGA reset signal to an invalid state to cause the asynchronous reset register to exit reset;

[0027] The clock output enable signal is set to a valid state, so that the FPGA enters a normal working state and completes the reset.

[0028] Optionally, the loading control signal for controlling the FPGA includes:

[0029] After controlling the loading control signal to be at a low level for a preset time, the loading control signal is then controlled to be at a high level.

[0030] The present invention also provides a chip reset device for ultrasonic equipment, which is applied to a reset control chip of ultrasonic equipment, comprising:

[0031] A power-on reset module, used for performing a power-on reset according to an acquired power-on reset signal;

[0032] An acquisition module, used for acquiring a reset instruction of a target chip after the reset is completed; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules that are reset by different reset modes;

[0033] The reset control module is used to generate a reset sequence according to the reset instruction and the reset mode corresponding to each functional module, and control the main control chip to perform a reset operation according to the reset sequence.

[0034] The present invention also provides an ultrasound system, comprising: a host, a main control chip and a reset control chip; wherein the main control chip is connected to the host and the reset control chip respectively;

[0035] A computer program is stored in the reset control chip, and the reset control chip implements the steps of the chip reset method of the ultrasound device as described above when executing the computer program.

[0036] Optionally, the system further includes:

[0037] The peripheral chip connected to the host and the reset control chip is used to perform a reset operation according to the control of the reset control chip.

[0038] Optionally, the main control chip is specifically FPGA.

[0039] A chip reset method for an ultrasonic device provided by the present invention comprises: a reset control chip of the ultrasonic device performs a power-on reset according to an acquired power-on reset signal; after the reset is completed, a reset instruction of a target chip is acquired; wherein the target chip comprises a main control chip in the ultrasonic device, and the main control chip comprises functional modules reset by different reset modes; according to the reset instruction, a reset sequence is generated according to the reset mode corresponding to each functional module, and the main control chip is controlled to perform a reset operation according to the reset sequence sequence;

[0040] It can be seen that the present invention uses the reset control chip to sequentially control the main control chip to reset according to the respective reset modes of each functional module in the main control chip, thereby ensuring the reliable reset of each functional module in the main control chip and avoiding the situation where the reset fan-out of the main control chip is large; and the independent reset control chip setting can improve the design flexibility of the chip reset of the ultrasonic equipment and reduce the requirements for the power-on delay chip. In addition, the present invention also provides a chip reset device and an ultrasonic system for ultrasonic equipment, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0042] Figure 1 A flowchart of a chip resetting method for an ultrasonic device provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the structure of an ultrasound system provided by an embodiment of the present invention;

[0044] Figure 3 A schematic flow chart of another chip resetting method for an ultrasonic device provided by an embodiment of the present invention;

[0045] Figure 4 A diagram showing the reset timing of a main control chip provided by an embodiment of the present invention;

[0046] Figure 5 A flowchart of a reset control method for a main control chip of an ultrasound device provided by an embodiment of the present invention;

[0047] Figure 6 This is a structural block diagram of a chip resetting device for ultrasonic equipment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Please refer to Figure 1 , Figure 1 This is a flow chart of a chip resetting method for an ultrasound device provided by an embodiment of the present invention. The method may include:

[0050] Step 101: The reset control chip of the ultrasound device performs a power-on reset according to the acquired power-on reset signal.

[0051] The reset control chip in this embodiment may be a chip provided in the ultrasound device for controlling the reset of the main control chip and the peripheral chip in the ultrasound device, such as Figure 2 MCU (Micro Control Unit) in the device; that is, the reset control chip in this step can be a chip that is independent of the existing main control chip and peripheral chip set in the ultrasound device.

[0052] Specifically, the specific chip type of the reset control chip in this step can be set by the designer according to the practical scenario and user needs. For example, the reset control chip can be an MCU such as CPLD (Complex Programmable Logic Device), or other MCUs such as single-chip microcomputers and ARM (Advanced RISC Machines, a type of microprocessor), or FPGA. This embodiment does not limit this.

[0053] It is understandable that the power-on reset signal in this step can be a signal for controlling the reset control chip to perform power-on reset after the power supply of the ultrasound device is powered on and stabilized. The purpose of this step is to perform power-on reset on the reset control chip to complete its own power-on reset.

[0054] Correspondingly, this step may also include a step in which the reset control chip obtains a power-on reset signal. The specific method for the reset control chip to obtain the power-on reset signal can be set by the designer according to practical scenarios and user needs, such as Figure 2 As shown, the reset control chip (i.e., MCU) can receive the power-on reset signal sent by the reset delay chip (i.e., power-on reset delay chip) after the power supply is powered on and stabilized; that is, even if the reset control chip adopts FPGA, compared with the main control chip, the reset control chip has very few resources, and the time for loading the configuration file during its reset process is very short, and the delay control requirements for the reset delay chip are not high; and if the reset control chip adopts an MCU such as ARM or CPLD, the configuration file loading process such as FPGA is not required during the reset process, and the control requirements for the reset delay chip are lower. The reset control chip can also generate a power-on reset signal according to the detected power supply conditions. As long as the reset control chip can obtain the power-on reset signal after the power supply of the ultrasonic device is powered on and stabilized, thereby completing its own power-on reset, this embodiment does not limit this.

[0055] Specifically, the specific method for the reset control chip to perform power-on reset according to the obtained power-on reset signal in this step can be set by the designer. For example, according to the specific chip type of the reset control chip, it can be implemented in the same or similar manner as the power-on reset method of the corresponding type of chip in the prior art. This embodiment does not impose any restrictions on this.

[0056] Step 102: After the reset is completed, a reset instruction of the target chip is obtained; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules that are reset by different reset modes.

[0057] It is understandable that the reset instruction in this step may be an instruction for controlling the target chip to reset. The target chip in this step may be a chip set in the ultrasound device that can be controlled to reset by the reset control chip, such as a main control chip. The purpose of this step is for the reset control chip to determine the chip (i.e., the target chip) that needs to be controlled to reset this time by obtaining the reset instruction of the target chip after completing the power-on reset.

[0058] Specifically, the specific method for the reset control chip in this step to obtain the reset instruction of the target chip after completing the power-on reset can be set by the designer according to practical scenarios and user needs. For example, the reset control chip can generate a reset instruction for the target chip after completing the power-on reset; that is, the reset instruction can be a reset instruction generated by the reset control chip itself to control the target chip to reset. The reset control chip can automatically control the target chip in the ultrasound device to complete the reset by generating the reset instruction of the target chip after its own power-on reset is completed; for example, the reset control chip can generate reset instructions for the main control chip and the peripheral chip after the power-on reset is completed, so that the reset control chip can control the main control chip and all peripheral chips to complete the reset, thereby realizing the automatic reset of the chips in the ultrasound device. The reset control chip can also obtain the host of the ultrasound system (such as Figure 2 The reset control instruction of the target chip sent by the host computer (PC, personal computer); that is, the reset instruction can be a reset control instruction received by the reset control chip for controlling the target chip to reset. After the reset control chip completes its own power-on reset, it can receive the reset control instruction sent by the host computer of the ultrasound system, so as to reset the target chip according to the control of the host computer. After completing the power-on reset, the reset control chip can also obtain the reset control instruction of the target chip sent by the host control chip. This embodiment does not limit this.

[0059] Correspondingly, this embodiment does not limit the specific manner in which the reset control chip obtains the reset control instruction of the target chip sent by the host of the ultrasound system, such as Figure 2 As shown, when the reset control chip (ie, MCU) in the ultrasound device is connected to the host (ie, PC) through the main control chip, the reset control chip can receive the reset control instruction sent by the host through the main control chip.

[0060] Specifically, the main control chip in this step may include functional modules that are reset by different reset methods, that is, the main control chip is provided with multiple functional modules that need to be reset according to their respective corresponding reset methods, such as the FPGA includes multiple register modules, such as a synchronous reset register that needs to be reset synchronously and an asynchronous reset register that needs to be reset asynchronously.

[0061] Step 103: According to the reset instruction, a reset sequence is generated according to the reset mode corresponding to each functional module, and the main control chip is controlled to perform a reset operation according to the reset sequence.

[0062] Among them, the reset timing in this step can be the timing generated by the reset control chip according to the reset mode corresponding to each functional module in the main control chip, so as to output the corresponding signal to the main control chip according to the timing, sequentially control the functional modules of the main control chip to perform the reset operation, and complete the reset of the main control chip. That is to say, in this step, the reset control chip can generate the reset timing of the main control chip according to the reset mode corresponding to each functional module in the main control chip according to the reset instruction of the main control chip obtained, and sequentially output the corresponding signal to the main control chip according to the reset timing, sequentially control the functional modules of the main control chip to reset, and complete the reset of the main control chip.

[0063] It can be understood that this embodiment demonstrates the reset control of the main control chip by the reset control chip as an example. The reset control chip can also perform reset control on the peripheral chip in the ultrasound equipment, that is, when the target chip also includes a peripheral chip, the reset control chip can also control the peripheral chip to perform a reset operation according to the reset clock of the peripheral chip; wherein, the reset control chip can store a reset clock of each peripheral chip that is pre-set or self-generated, such as a reset timing or a reset signal, so that after obtaining the reset instruction of the peripheral chip, the stored reset clock of the peripheral chip is used to control the peripheral chip to perform a reset operation.

[0064] Furthermore, in this step, the reset control chip can use a handshake mechanism to sequentially control the reset operation of each functional module of the main control chip according to the reset timing of the generated main control chip; that is, the reset scheme of the reset control chip controlling the main control chip to reset in this embodiment can use a handshake mechanism to further improve the reliability of the reset. Among them, handshake means waiting for the other party to give feedback before proceeding to the next step. Figure 3 As shown, during the process of the reset control chip controlling the reset of the main control chip (i.e., FPGA chip), it first sends an instruction to the FPGA, gives feedback after the FPGA operation is completed, and then proceeds to the next step to ensure that all links of the reset sequence are at a stable and reliable moment, and the reset is sufficient, thereby improving the stability and reliability of the reset. Correspondingly, when the target chip also includes a peripheral chip, the reset control chip can use a handshake mechanism to control the peripheral chip to perform a reset operation according to the reset clock of the peripheral chip.

[0065] Correspondingly, the specific content of the reset timing generated by the reset control chip in this step according to the reset mode corresponding to each functional module, that is, the sequential control mode corresponding to the reset timing, can be set by the designer according to practical scenarios and user needs. For example, when the main control chip includes a functional module of synchronous reset and a functional module of asynchronous reset, the reset control chip can control the main control chip to enter the synchronous reset state according to the reset timing of the main control chip, so that the functional module of synchronous reset is reset; then control the main control chip to enter the asynchronous reset state, so that the functional module of asynchronous reset is reset, and the functional module of synchronous reset exits the reset; then control the clock output enable signal to remain in the invalid state, so that the reset signal of the main control chip exits the reset state; after the reset signal of the main control chip exits the reset state, the clock output enable signal is set to the valid state, so that the handshake mechanism is used to sequentially control the functional module of synchronous reset and the functional module of asynchronous reset in the main control chip to perform reset operations in sequence, thereby completing the reset of the main control chip.

[0066] Specifically, Figure 3 and Figure 4 As shown, when the main control chip of the ultrasound device is specifically an FPGA chip, the reset control chip can be as follows Figure 4 The reset timing of the FPGA chip shown in the figure goes through 8 steps from STEP1 to STEP8, namely, triggering the FPGA loading stage, waiting for the FPGA loading completion stage, the PLL (phase-locked loop) reset stage, the PLL lock waiting stage, the synchronous clearing stage, the asynchronous clearing stage, the reset release stage and the normal working state stage. The handshake mechanism is used to control the FPGA chip to perform the reset operation to complete the reset of the main control chip.

[0067] It should be noted that, in this embodiment, after obtaining the reset instruction of the main control chip for the first time, the reset control chip can generate and store the reset timing according to the reset mode corresponding to each functional module in the main control chip, and control the main control chip to perform the reset operation according to the generated reset timing sequence, and then directly control the main control chip to perform the reset operation according to the stored reset timing sequence after obtaining the reset instruction of the main control chip again. The embodiment of the present invention uses the reset control chip to sequentially control the main control chip to reset according to the reset mode of each functional module in the main control chip, thereby ensuring the reliable reset of each functional module in the main control chip and avoiding the situation where the reset fan-out of the main control chip is large; and the independent reset control chip setting can improve the design flexibility of the chip reset of the ultrasound equipment and reduce the requirements for the power-on delay chip.

[0068] Based on the above embodiments, the present invention provides a reset solution in which a reset control chip uses a handshake mechanism to sequentially control the master chip to reset, so as to improve the reliability of the master chip reset. Figure 5 , Figure 5This is a flow chart of a reset control method for a main control chip of an ultrasound device provided by an embodiment of the present invention. The method may include:

[0069] Step 201: The reset control chip controls the loading control signal of the FPGA to enable the FPGA to load the configuration file.

[0070] It can be understood that this embodiment takes the main control chip of the ultrasonic device as FPGA (i.e., FPGA chip) as an example, and the reset control chip shown adopts a handshake mechanism to control the main control chip to reset, that is, the reset control chip in the previous embodiment uses a handshake mechanism to sequentially control the various functional modules of the main control chip to perform reset operations according to the reset instruction of the main control chip and the reset timing corresponding to the generated main control chip. For the reset scheme of the ultrasonic device whose main control chip is other types of chips and the reset scheme of the peripheral chip of the ultrasonic device, the same or similar method as the method provided in this embodiment can be used for corresponding settings, so as to realize the reset scheme of using a handshake mechanism to control the chip reset of the ultrasonic device.

[0071] Specifically, in this step, the reset control chip can trigger the FPGA to load the configuration file (such as a bitstream file) by controlling the loading control signal of the FPGA. Specifically, the specific method for the reset control chip to control the loading control signal of the FPGA in this step can be set by the designer, such as Figure 4 As shown, after the reset control chip controls the loading control signal (FPGA_PROG_B signal) to be at a low level for a preset time, it controls the loading control signal to be at a high level so that the FPGA loads the configuration file. The preset time can be greater than or equal to 1ms to ensure that the FPGA can accurately trigger the loading of the configuration file.

[0072] That is to say, Figure 3 and Figure 4 As shown, this step can be a trigger FPGA loading phase controlled by the reset control chip (such as Figure 4 At this stage, the reset control chip (such as MCU) can pull the FPGA_PROG_B signal (i.e., the loading control signal) low and then high to enable the FPGA to start loading the configuration file.

[0073] Step 202: Monitor the working signal of the FPGA and wait for the FPGA to be loaded.

[0074] The purpose of this step is to reset the control chip by monitoring the working signal of the FPGA (such as Figure 4 FPGA_DONE signal in the middle), wait for the FPGA to load the configuration file to complete, and then enter step 203 after confirming that the FPGA loading is completed, to ensure the reliability of FPGA reset.

[0075] Specifically, Figure 3 and Figure 4 As shown, this step can be the stage of waiting for FPGA loading to be completed controlled by the reset control chip (such as Figure 4 At this stage, the reset control chip (such as MCU) can monitor and wait for the FPGA_DONE signal (i.e., the working signal) to be pulled high, indicating that the FPGA configuration file loading is completed.

[0076] Step 203: After determining that the FPGA loading is completed, the PLL phase-locked loop reset signal and the FPGA reset signal of the FPGA are controlled to remain valid, and the clock output enable signal of the FPGA is controlled to remain invalid, so as to control the PLL reset of the FPGA.

[0077] Specifically, Figure 3 and Figure 4 As shown, this step can be the PLL reset stage controlled by the reset control chip. In this stage (such as Figure 4 In STEP3), the reset control chip (such as MCU) can control the PLL_RESET signal (i.e., PLL phase-locked loop reset signal) and FPGA_RESET signal (FPGA reset signal) to be in a valid set state, and the FPGA_CLKEN signal (clock output enable signal) to be in an invalid state; the internal clock of the FPGA stops flipping, the internal reset signal is in a valid state, and the asynchronous clear circuit inside the FPGA enters the reset state from this time.

[0078] Among them, the FPGA clock output enable signal (such as Figure 4 FPGA_CLKEN signal) indicates clock output when it is at a high level, and no clock output when it is at a low level. It is used to control the clock output of PLL. This clock is used to control the synchronous reset clock or the normal working clock.

[0079] Step 204: Set the PLL phase-locked loop reset signal to an invalid state, monitor the PLL lock signal of the FPGA, and wait for the PLL of the FPGA to be locked.

[0080] Specifically, Figure 3 and Figure 4 As shown, this step can be the PLL lock waiting stage controlled by the reset control chip. In this stage (such as Figure 4 STEP4), the reset control chip (such as MCU) can release the PLL_RESET signal (i.e., the PLL phase-locked loop reset signal), such as Figure 3In the PLL release phase, wait for the PLL to be in a locked state; under normal circumstances, the PLL of the FPGA can be reliably locked within 500us, and the reset control chip can wait for a preset time (such as more than 1ms) to ensure that the PLL is normally locked. In this step, the reset control chip can further determine whether the PLL is locked by monitoring whether the PLL lock signal (such as the PLL_LOCK signal) is at a high level, so as to ensure the reliability of the FPGA reset.

[0081] Correspondingly, in the PLL lock waiting stage corresponding to this step, the internal clock of the FPGA can stop flipping, and the internal reset signal is in a valid state.

[0082] Step 205: After determining that the PLL of the FPGA is locked, the clock output enable signal is set to a valid state to reset the synchronous reset register of the FPGA to zero.

[0083] Specifically, Figure 3 and Figure 4 As shown, this step can be the synchronous clearing stage controlled by the reset control chip. In this stage (such as Figure 4 STEP5), the reset control chip (such as MCU) can output the clock enable signal (such as Figure 4 FPGA_CLKEN signal) is set to valid, and the FPGA reset signal (such as Figure 4 The FPGA_RESET signal in the FPGA is still in a valid state; the internal clock of the FPGA flips normally, the internal reset signal is in a valid state, and the registers without reset terminals and the synchronous reset registers inside the FPGA will be cleared in this state.

[0084] Step 206: Set the clock output enable signal to an invalid state to reset the asynchronous reset register of the FPGA to zero and to exit the reset of the synchronous reset register.

[0085] Specifically, Figure 3 and Figure 4 As shown, this step can be the asynchronous clearing stage controlled by the reset control chip. In this stage (such as Figure 4 STEP6), the reset control chip (such as MCU) can output the clock enable signal (such as Figure 4 FPGA_CLKEN signal) is set to invalid, and the FPGA reset signal (such as Figure 4 The FPGA_RESET signal in the FPGA is still in a valid state; the internal clock of the FPGA stops flipping, and the internal reset signal is in a valid state. This state allows the synchronous reset register inside the FPGA to exit reset normally.

[0086] Accordingly, in the asynchronous clearing phase corresponding to this step, the clock output enable signal (such as Figure 4 The FPGA_CLKEN signal in the FPGA is pulled low, so that there is no clock inversion inside the FPGA. At this moment, it is in an asynchronous reset state. Since there is no clock and it is in a reset state, the metastable state caused by the release of the reset signal near the clock edge is avoided. In the next stage (such as Figure 4 STEP7) is in the no-clock state. At this time, the asynchronous reset exits the reset and will not affect the control of the synchronous reset part. The synchronous reset register can exit normally.

[0087] Step 207: Set the FPGA reset signal to an invalid state to make the asynchronous reset register exit the reset state.

[0088] Specifically, Figure 3 and Figure 4 As shown, this step may be the reset release stage controlled by the reset control chip. In this stage (such as Figure 4 STEP7), the reset control chip (such as MCU) can release the FPGA reset signal (such as Figure 4 FPGA_RESET signal), clock output enable signal (such as Figure 4 The FPGA_CLKEN signal in the FPGA remains in an invalid state; the internal clock of the FPGA stops flipping, and the internal reset signal exits the reset state, allowing the asynchronous reset register to exit the reset state normally.

[0089] Step 208: Set the clock output enable signal to a valid state, so that the FPGA enters a normal working state and completes the reset.

[0090] Specifically, Figure 3 and Figure 4 As shown, this step can be the normal working state of the reset control chip control. At this stage (such as Figure 4 STEP8), the reset control chip (such as MCU) can clock out an enable signal (such as Figure 4 The FPGA_CLKEN signal in the FPGA is set to be valid, allowing the entire FPGA to enter normal working state and completing the reset control of the FPGA.

[0091] It is understandable that, since the registers of the asynchronous reset and synchronous reset of the FPGA have exited the reset in step 206 and step 207, the registers in the same clock domain will not have inconsistent exit reset times in the FPGA during normal operation, and the process can ensure that the reset path will not become a critical path, and the reset path can be set as a false path during FPGA layout and routing, and will no longer affect the timing constraints of the FPGA. Accordingly, asynchronous reset can be used inside the FPGA, and a BUFG (global buffer) can be set on the reset input pin to enhance the fan-out capability, use a dedicated routing channel, and reduce ordinary wiring resources. In the system of a relatively large ultrasound device, the layout and routing are optimized, so that the timing constraints of the system are easier to pass, and the reliability of the system is guaranteed.

[0092] That is to say, in this embodiment, all synchronous reset and asynchronous reset operations have been completed during clock recovery, and under normal circumstances, there will be no problem of inconsistent reset release time. The critical path of timing analysis means the one with the largest combinational logic delay between two registers. When setting the timing constraint, it is set as a false path, which will not affect the timing constraint.

[0093] In this embodiment, the embodiment of the present invention adopts a handshake mechanism to control the reset of the main control chip, thereby ensuring the reset reliability of the main control chip and avoiding the occurrence of a metastable state caused by the release of the reset signal near the clock edge, thereby improving the reset stability of the main control chip.

[0094] Please refer to Figure 6 , Figure 6 This is a structural block diagram of a chip reset device for an ultrasound device provided by an embodiment of the present invention. The device is applied to a reset control chip of an ultrasound device and may include:

[0095] A power-on reset module 10, used for performing a power-on reset according to an acquired power-on reset signal;

[0096] The acquisition module 20 is used to acquire the reset instruction of the target chip after the reset is completed; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules reset by different reset modes;

[0097] The reset control module 30 is used to generate a reset sequence according to the reset instruction and the reset mode corresponding to each functional module, and control the main control chip to perform a reset operation according to the reset sequence.

[0098] Optionally, when the target chip further includes a peripheral chip, the device may further include:

[0099] The peripheral reset module is used to control the peripheral chip to perform a reset operation according to the reset clock of the peripheral chip.

[0100] Optionally, the reset control module 30 may include:

[0101] The handshake reset submodule is used to control the reset operation of each functional module of the main control chip in sequence according to the reset timing and adopt the handshake mechanism.

[0102] Optionally, when the reset mode includes synchronous reset and asynchronous reset, the handshake reset submodule may include:

[0103] A synchronous reset unit is used to control the main control chip to enter a synchronous reset state, so as to reset the synchronous reset function module;

[0104] An asynchronous reset unit is used to control the main control chip to enter an asynchronous reset state, so that the asynchronous reset function module is reset and the synchronous reset function module exits reset;

[0105] An exit reset unit, used to control the clock output enable signal to remain in an invalid state, so that the reset signal of the main control chip exits the reset state;

[0106] The recovery unit is used to set the clock output enable signal to a valid state after the reset signal of the main control chip exits the reset state.

[0107] Optionally, when the main control chip is specifically an FPGA, the handshake reset submodule may include:

[0108] A loading trigger unit is used to control the loading control signal of the FPGA so that the FPGA loads the configuration file;

[0109] The loading waiting unit is used to monitor the working signal of the FPGA and wait for the FPGA loading to be completed;

[0110] A PLL reset unit is used to ensure that after the FPGA is loaded, the PLL phase-locked loop reset signal and the FPGA reset signal of the FPGA are kept valid, and the clock output enable signal of the FPGA is kept invalid, so as to control the PLL reset of the FPGA;

[0111] A PLL lock waiting unit is used to set a PLL phase-locked loop reset signal to an invalid state, monitor a PLL lock signal of the FPGA, and wait for the PLL of the FPGA to lock;

[0112] A synchronous reset unit, used to set the clock output enable signal to a valid state after determining that the PLL of the FPGA is locked, so as to reset and clear the synchronous reset register of the FPGA;

[0113] An asynchronous reset unit, used to set the clock output enable signal to an invalid state, so that the asynchronous reset register of the FPGA is reset and cleared and the synchronous reset register exits reset;

[0114] A reset release unit, used to set the FPGA reset signal to an invalid state so that the asynchronous reset register exits reset;

[0115] The normal working unit is used to set the clock output enable signal to a valid state, so that the FPGA enters a normal working state and completes the reset.

[0116] Optionally, the loading trigger unit may be specifically configured to control the loading control signal to be at a low level for a preset time, and then control the loading control signal to be at a high level.

[0117] In this embodiment, the reset control chip of the present invention sequentially controls the reset of the main control chip according to the reset mode of each functional module in the main control chip, thereby ensuring the reliable reset of each functional module in the main control chip and avoiding the situation where the reset fan-out of the main control chip is large; and the independent reset control chip is set, which can improve the design flexibility of the chip reset of the ultrasound equipment and reduce the requirements for the power-on delay chip.

[0118] The embodiment of the present invention further provides an ultrasound system, comprising: a host, a main control chip and a reset control chip; wherein the main control chip is connected to the host and the reset control chip respectively;

[0119] A computer program is stored in the reset control chip, and when the reset control chip executes the computer program, the steps of the chip reset method of the ultrasound device provided in the above embodiment are implemented.

[0120] Optionally, the ultrasound system provided in this embodiment may further include:

[0121] The peripheral chip connected to the host and the reset control chip is used to perform reset operations according to the control of the reset control chip.

[0122] Specifically, the reset control chip in this embodiment may be specifically an MCU, such as a CPLD, a single-chip microcomputer or an ARM.

[0123] Optional, such as Figure 2 As shown, the ultrasound system in this embodiment may further include a power-on reset delay chip connected to the reset control chip (ie, MCU), so that the reset control chip can perform a power-on reset according to a power-on reset signal sent by the power-on reset delay chip.

[0124] In addition, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed, the steps of the chip reset method of the ultrasound device provided in any of the above embodiments can be implemented. The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0125] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. As for the device, ultrasound system and computer-readable storage medium disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0126] The above is a detailed introduction to a chip resetting method, device and ultrasonic system of an ultrasonic device provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A chip resetting method for ultrasonic equipment, characterized in that: include: The reset control chip of the ultrasound device performs power-on reset according to the acquired power-on reset signal; the reset control chip is a chip provided in the ultrasound device and is independent of the existing main control chip and peripheral chip, and is used to control the reset of the main control chip and peripheral chip in the ultrasound device; After the reset is completed, a reset instruction of the target chip is obtained; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules that are reset by different reset modes; According to the reset instruction, a reset sequence is generated according to the reset mode corresponding to each of the functional modules, and according to the reset sequence, a handshake mechanism is used to sequentially control the functional modules of the main control chip to perform a reset operation; Wherein, when the reset mode includes synchronous reset and asynchronous reset, the reset operation of each functional module of the main control chip is sequentially controlled by a handshake mechanism according to the reset timing, including: Controlling the main control chip to enter a synchronous reset state to reset the synchronous reset function module; Control the main control chip to enter an asynchronous reset state, so that the asynchronous reset function module is reset and the synchronous reset function module exits reset; Controlling the clock output enable signal to remain in an invalid state so that the reset signal of the main control chip exits the reset state; After the reset signal of the main control chip exits the reset state, the clock output enable signal is set to a valid state.

2. The chip resetting method of ultrasonic equipment according to claim 1, characterized in that: When the target chip also includes a peripheral chip, after obtaining the reset instruction of the target chip, the method further includes: According to the reset clock of the peripheral chip, the peripheral chip is controlled to perform a reset operation.

3. The chip resetting method of ultrasonic equipment according to claim 1, characterized in that: When the main control chip is specifically an FPGA, the reset operation of each functional module of the main control chip is sequentially controlled by a handshake mechanism according to the reset timing, including: Controlling a loading control signal of the FPGA so that the FPGA loads a configuration file; Monitor the working signal of the FPGA and wait for the loading of the FPGA to be completed; After determining that the FPGA is loaded, a PLL phase-locked loop reset signal and an FPGA reset signal of the FPGA are controlled to remain in a valid state, and a clock output enable signal of the FPGA is controlled to remain in an invalid state, so as to control the PLL reset of the FPGA; Setting the PLL phase-locked loop reset signal to an invalid state, monitoring the PLL lock signal of the FPGA, and waiting for the PLL of the FPGA to be locked; After determining that the PLL of the FPGA is locked, setting the clock output enable signal to a valid state so as to reset the synchronous reset register of the FPGA to zero; Setting the clock output enable signal to an invalid state so that the asynchronous reset register of the FPGA is reset to zero and the synchronous reset register exits reset; Setting the FPGA reset signal to an invalid state to cause the asynchronous reset register to exit reset; The clock output enable signal is set to a valid state, so that the FPGA enters a normal working state and completes the reset.

4. The chip resetting method of ultrasonic equipment according to claim 3, characterized in that: The loading control signal for controlling the FPGA includes: After controlling the loading control signal to be at a low level for a preset time, the loading control signal is then controlled to be at a high level.

5. A chip resetting device for ultrasonic equipment, characterized in that: Reset control chips used in ultrasound equipment include: A power-on reset module, used for performing a power-on reset according to an acquired power-on reset signal; the reset control chip is a chip provided in the ultrasound device and is independent of the existing main control chip and peripheral chip, and is used for controlling the reset of the main control chip and peripheral chip in the ultrasound device; An acquisition module, used for acquiring a reset instruction of a target chip after the reset is completed; wherein the target chip includes a main control chip in the ultrasound device, and the main control chip includes functional modules that are reset by different reset modes; A reset control module, used to generate a reset sequence according to the reset instruction and the reset mode corresponding to each functional module, and control the main control chip to perform a reset operation according to the reset sequence sequence; Wherein, the reset control module includes: A handshake reset submodule, used to control the functional modules of the main control chip to perform reset operations in sequence according to the reset timing using a handshake mechanism; When the reset mode includes synchronous reset and asynchronous reset, the handshake reset submodule includes: A synchronous reset unit, used to control the main control chip to enter a synchronous reset state, so as to reset the synchronous reset function module; An asynchronous reset unit, used to control the main control chip to enter an asynchronous reset state, so that the asynchronous reset function module is reset and the synchronous reset function module exits reset; An exit reset unit, used for controlling the clock output enable signal to remain in an invalid state, so that the reset signal of the main control chip exits the reset state; The recovery unit is used to set the clock output enable signal to a valid state after the reset signal of the main control chip exits the reset state.

6. An ultrasound system, characterized in that: include: A host, a main control chip and a reset control chip; wherein the main control chip is connected to the host and the reset control chip respectively; A computer program is stored in the reset control chip, and the reset control chip implements the steps of the chip reset method of the ultrasound device according to any one of claims 1 to 4 when executing the computer program.

7. The ultrasound system according to claim 6, characterized in that Also includes: The peripheral chip connected to the host and the reset control chip is used to perform a reset operation according to the control of the reset control chip.

8. The ultrasound system according to claim 6, characterized in that The main control chip is specifically FPGA.

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