DUT clock signal recovery method and system based on multi-FPGA interconnection

Abstract

The present invention provides a DUT clock signal recovery method and system based on multi-FPGA interconnection. The method comprises: using a PLL feedback mode to lock the phase of CLK_IN and CLK_OUT inside each interconnected FPGA; dividing the clock source into multiple paths through clk_buffer, inputting into the dedicated clock pin of each FPGA through the same routing length as the input of the PLL, and outputting the DUT clock signal; judging whether the DUT clock signals output by each FPGA are in phase, and when the output DUT clock signals are in different phases, resetting the PLL of each FPGA until the DUT clock signals output by each FPGA are in phase. The present invention has no special requirements for the split point of large synchronous logic RTL, and is particularly suitable for the real function and performance verification of large synchronous logic on multiple FPGAs; it can ensure the data throughput efficiency of the original design RTL, does not increase any additional clock level delay, and the FPGA has a relatively fast running speed; when used with SelectIO, a large number of signals can be transmitted across FPGAs, and the timing of the post-FPGA project can be easily converged.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a DUT clock signal recovery method and system based on multi-FPGA interconnection. Background Art

[0002] When verifying SOC prototypes with FPGA, the scale of logic IP is very large, especially image and video related IP, which cannot be realized by one FPGA resource and requires multiple FPGAs.

[0003] The FPGA-based emulator system also needs to split the entire DUT into multiple FPGAs for operation. Large synchronous RTL often has a DUT_CLK tight logic design inside. In order to ensure the consistency of RTL verification, the logic on multiple FPGAs must run on the same frequency clock, and no DUT_CLK level delay can be inserted.

[0004] In the prior art, multiple FPGAs generally run in asynchronous mode, and the RTL split point is generally selected at the ready / valid or req / ack boundary. This is achieved by adding extra cycle latency between the split boundary blocks, which cannot guarantee the data throughput efficiency of the original IP design and has special requirements for the RTL split point. It is not suitable for large synchronous logic IP, especially the split implementation and verification of this type of logic with a tight coupling of one cycle in the signal path. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a DUT clock signal recovery method and system based on multi-FPGA interconnection, to solve the technical problem of splitting a large synchronous RTL into multiple FPGAs and recovering the same DUT_CLK, and to exemplify the implementation in a multi-FPGA verification system interconnected based on Xilinx FPGA selectIO.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present invention provides a DUT clock signal recovery method based on multi-FPGA interconnection, including: using the PLL feedback mode to lock the phase of CLK_IN and CLK_OUT inside each interconnected FPGA; dividing the clock source into multiple paths through the clk_buffer, inputting them to the dedicated clock pin of each FPGA through the same routing length as the input of the PLL, and outputting the DUT clock signal; judging whether the DUT clock signals output by each FPGA are in phase, and if the output DUT clock signals are in different phases, resetting the PLL of each FPGA until the DUT clock signals output by each FPGA are in phase.

[0007] In some embodiments of the first aspect of the present invention, the method for determining whether the clock signals output by each FPGA are in phase includes: combining each FPGA in the interconnected multiple FPGAs with the remaining FPGAs in pairs, each group including a first FPGA and a second FPGA; inputting the DUT clock signal output by the first FPGA into the second FPGA, and performing an XOR operation with the DUT clock signal output by the second FPGA, and sampling the operation result; if the sampling result is a high level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are out of phase; if the sampling result is a low level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are in phase.

[0008] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present invention provides a system for interconnecting multiple FPGAs, and the system executes the DUT clock signal recovery method based on interconnecting multiple FPGAs.

[0009] As described above, the DUT clock signal recovery method and system based on multi-FPGA interconnection involved in the present invention have the following beneficial effects: after the large synchronous RTL is divided, each interconnected FPGA runs based on the DUT clock signal of the same frequency and phase, and there is no special requirement for the division point of the large synchronous logic RTL. It is particularly suitable for the real function and performance verification of large synchronous logic in multiple FPGAs, especially the division implementation and verification of this type of logic with tight coupling of signal links (data paths); it can ensure the data throughput efficiency of the original design RTL without adding any additional clock-level delay (cycle latency), and the FPGA has a very fast running speed; when used with SelectIO, a large number of signals can be transmitted across FPGAs, and the post-FPGA engineering timing (timing) can be easily converged. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Shown is a flow chart of a DUT clock signal recovery method based on multi-FPGA interconnection according to an embodiment of the present invention.

[0011] Figure 2 Shown is a schematic diagram of a board-level clock source design in an embodiment of the present invention.

[0012] Figure 3 Shown is a schematic diagram of the PLL settings in each FPGA in an embodiment of the present invention.

[0013] Figure 4 Shown is a schematic diagram of the clock structure of a multi-FPGA interconnected system in one embodiment of the present invention.

[0014] Figure 5Shown is a schematic diagram of a 5 MHz in-phase DUT_CLK generated in multiple interconnected FPGAs in one embodiment of the present invention.

[0015] Figure 6 Shown is a schematic diagram of 5 MHz DUT_CLK with different phases generated in an interconnected FPGA in one embodiment of the present invention.

[0016] Figure 7 Shown is a schematic diagram of monitoring and processing of 5 MHz different phase DUT_CLK in an interconnected FPGA in one embodiment of the present invention.

[0017] Figure 8 Shown is a schematic diagram of the interconnection between the internal PLL of an FPGA and multiple SelectIO clocks in one embodiment of the present invention.

[0018] Fig. 9 Shown is a schematic diagram of signal transmission and receiving channels of two interconnected FPGAs in one embodiment of the present invention.

[0019] Fig.10 Shown is a schematic diagram of a system structure of multiple FPGA interconnection in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0021] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0022] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "hold" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] Furthermore, as used in this article, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0024] The purpose of the present invention is to provide a DUT clock signal recovery method and system based on multiple FPGA interconnection, so as to solve the technical problem of stable clock signal recovery when a large synchronous RTL is divided into multiple FPGAs in the prior art.

[0025] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0026] Embodiment 1

[0027] Figure 1 The flowchart of the DUT clock signal recovery method based on multiple FPGA interconnection according to an embodiment of the present invention is shown as follows:

[0028] Step S11: Use the PLL feedback mode to lock the phase of CLK_IN and CLK_OUT inside each interconnected FPGA.

[0029] Step S12: divide the clock source into multiple paths through clk_buffer, input them into the dedicated clock pin of each FPGA through the same routing length as the input of the PLL, and output the DUT clock signal.

[0030] Step S13. Determine whether the DUT clock signals output by each FPGA are in phase. If the output DUT clock signals are in different phases, reset the PLL of each FPGA until the DUT clock signals output by each FPGA are in phase.

[0031] In a preferred implementation manner of this embodiment, the method for determining whether the clock signals output by each FPGA are in phase includes: combining each FPGA in the interconnected multiple FPGAs with the remaining FPGAs in pairs, each group including a first FPGA and a second FPGA; inputting the DUT clock signal output by the first FPGA into the second FPGA, and performing an XOR operation with the DUT clock signal output by the second FPGA, and sampling the operation result; if the sampling result is a high level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are out of phase; if the sampling result is a low level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are in phase.

[0032] In a preferred implementation of this embodiment, the same clock signal is input from the pin at the same position of each FPGA. It should be noted that FPGA has many clock input pins, and the input at the same pin position is to reduce the slight difference of the PLL input clocks inside multiple FPGAs. Clock pins at different positions can also be used for input.

[0033] In order to conveniently explain the implementation principle of the above steps 11 to 13, let the board-level common_clk be a 10Mhz clock source, and take SelectIO running at 1Gbps as an example for technical explanation. CLK_10MHz_In is the clock input to the clock pin of each FPGA. 5Mhz and 125Mhz are based on the current 10Mhz as an example. The newly generated clock frequency after PLL frequency division and multiplication, 5Mhz is the actual running DUT_CLK clock after RTL is divided into multiple FPGAs. The above is for the convenience of describing the technical principles, and the present invention is not limited to the above frequency and speed definitions.

[0034] The specific implementation steps of taking the 10Mhz clock source as an example include: dividing the 10Mhz clock source into multiple clocks of the same frequency and phase through the clk buffer, and inputting them into the clock input pins of each FPGA in the FPGA verification system with the same routing length and width. After inputting into the PLL of each FPGA, the PLL outputs 5Mhz and the high frequency 125Mhz required by the SelectIO module, and they all have the same phase. The PLL inside the SelectIO module will generate a 1Gbps clock and the corresponding parallel data sampling clock pll0_clkout0 based on the 125MHz clock input (this frequency is also the same frequency and phase as the 125Mhz input frequency).

[0035] This embodiment takes a 10Mhz clock source as an example. Figure 2 to Figure 8 To further elaborate:

[0036] Step 21. Figure 2 The schematic diagram of the board-level clock source design in one embodiment of the present invention is shown as follows: Figure 2 Design the multi-FPGA system clock source common_clk, and ensure that the routing width and length of each clk after the clk_buffer to the clock input pin of each FPGA are the same.

[0037] Step 22. Figure 3 It is shown as a schematic diagram of the PLL setting in each FPGA in an embodiment of the present invention. The PLL inside each FPGA is configured to the internal feedback mode, so that the frequency locking phase characteristic of the PLL can be used to ensure that the 5Mhz and 125Mhz output after the PLL is locked and the input CLK_10Mhz_in are in phase. Figure 4 Shown is a schematic diagram of the clock structure of a multi-FPGA interconnection system in one embodiment of the present invention.

[0038] Step 23. Determine whether the DUT clock signals output by each FPGA are in phase. Since large RTL consumes a lot of FPGA resources, the frequency of DUT_CLK is generally not fast, so the DUT_CLK clock signal is generally one-Nth of CLK_10Mhz_in. In the current example, it is one-half 5Mhz, so after PLL is locked, the PLL of each FPGA actually outputs a 5Mhz clock signal.

[0039] Step 24. The PLL inside each FPGA outputs different 5Mhz clocks based on the same CLK_10Mhz_in. Figure 5 Shown is a schematic diagram of the 5 MHz (DUT_CLK) in-phase signal generated in the interconnected FPGA in one embodiment of the present invention, which is the expected output. Figure 6The display is a schematic diagram of different phases of 5MHz (DUT_CLK) generated in the interconnected FPGAs in one embodiment of the present invention, which is an unexpected output. In this case, the 5Mhz generated inside one of the interconnected FPGAs is input to another FPGA for logical processing and judgment, such as Figure 7 , Figure 7 The figure shows a schematic diagram of monitoring and processing different phases of 5MHz (DUT_CLK) in interconnected FPGAs in one embodiment of the present invention. If they are found to be out of phase, the PLL of the current FPGA can be logically reset and re-locked until the 5Mhz clocks generated by the two FPGAs are of the same frequency and phase.

[0040] Step 25. Figure 8 It shows a schematic diagram of the interconnection between the internal PLL and multiple SelectIO clocks of the FPGA in one embodiment of the present invention, which is a clock structure diagram with multiple SelectIO added inside the FPGA (SelectIO can perform 8-to-1 serial-to-parallel conversion, so that more cross-border signals after RTL segmentation can be transmitted between FPGAs). So far, the 5Mhz clock inside each interconnected FPGA, the 125Mhz clock and the clock pll0_clkout0 for sampling parallel port data of SelectIO are all of the same frequency and phase. After the large RTL with the same frequency is segmented to each FPGA, it runs at the 5Mhz DUT_CLK, and the segmentation boundary signal is sampled and restored using the pll0_clkout0 of the selectIO, and is sent or received at 1Gbps. Since the 5Mhz DUT_CLK and the pll0_clkout0 of each selectIO have a phase relationship, and the entire clock domain is interconnected inside the FPGA, the FPGA implementation timing is easy to converge.

[0041] Step 26. Figure 7 It also shows the method for processing different phases of the 5Mhz clock signal between interconnected FPGAs. Specifically, FPGA 1 and FPGA 2 are interconnected, and the 5Mhz clock signal generated in FPGA 1 is output to FPGA 2, and is XORed with the 5Mhz clock signal generated in FPGA 2, and sampled with CLK_10MHz_in of FPGA 2. If the high level is sampled, it means that the phase is different, and the current FPGA 2 needs to reset the PLL to relock.

[0042] Fig. 9 Shown is a schematic diagram of the signal transmission and reception channels of two interconnected FPGAs. Fig. 9Taking the interconnection of two FPGAs as an example, it shows the signal transmission channel when a large RTL is implemented on two FPGAs, one FPGA sends a signal and the other FPGA receives a signal. Specifically, CLK_10MHz_in is input into the PLLs of FPGA1 and FPGA2 respectively. Based on the method described above, FPGA1 and FPGA2 obtain the 5MHz DUT_CLK signal with the same frequency and phase. After the large RTL with the same frequency is split into FPGA1 and FPGA2, it runs with the 5Mhz DUT_CLK. The SelectIO in FPGA1 samples the split boundary signal based on pll0_clkout0, converts parallel to serial and sends it to FPGA2. The SelectIO in FPGA2 recovers the data parallel port with pll0_clkout0, and the split boundary signal is recovered, and the serial is converted to parallel.

[0043] In summary, this embodiment provides a DUT clock signal recovery method based on multi-FPGA interconnection, which has the following beneficial effects: after the large synchronous RTL is split, each interconnected FPGA runs based on the DUT clock signal of the same frequency and phase, and there is no special requirement for the split point of the large synchronous logic RTL. It is particularly suitable for the real function and performance verification of large synchronous logic in multiple FPGAs, especially the split implementation and verification of this type of logic with tight coupling of signal links (data paths); it can ensure the data throughput efficiency of the original design RTL without adding any additional clock-level delay (cycle latency), and the FPGA has a very fast running speed; when used with SelectIO, a large number of signals can be transmitted across FPGAs, and the post-FPGA engineering timing can be easily converged.

[0044] Embodiment 2

[0045] Fig.10 The system structure diagram of a multi-FPGA interconnection provided by an embodiment of the present invention is shown. The system executes the DUT clock signal recovery method based on multi-FPGA interconnection. The system includes a DUT clock signal recovery device 101. The DUT clock signal recovery device 101 also includes: a phase locking module 1011, which uses the PLL feedback mode to lock the phase of CLK_IN and CLK_OUT inside each interconnected FPGA; a clock signal processing module 1012, which divides the clock source into multiple paths through clk_buffer, and inputs it to the dedicated clock pin of each FPGA through the same routing length as the input of the PLL, and outputs the DUT clock signal; a phase judgment module 1013, which judges whether the DUT clock signals output by each FPGA are in phase, and when the output DUT clock signals are in different phases, resets the PLL of each FPGA until the DUT clock signals output by each FPGA are in phase. This embodiment is similar to the method described above, so it will not be repeated here.

[0046] The system bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface is used to realize the communication between the database access device and other devices (such as clients, read-write libraries, and read-only libraries). The memory may include random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage.

[0047] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0048] In summary, the present invention provides a DUT clock signal recovery method and system based on multiple FPGA interconnection, which is particularly suitable for verifying the SOC prototype stage with FPGA or the emulator system based on FPGA. After the large synchronous RTL is divided, each interconnected FPGA runs based on the DUT clock signal of the same frequency and phase. There is no special requirement for the division point of the large synchronous logic RTL. It is particularly suitable for the real function and performance verification of large synchronous logic in multiple FPGAs, especially the division realization and verification of this type of logic with tight coupling of signal links (data paths); it can ensure the data throughput efficiency of the original design RTL, without adding any additional clock level delay (cycle latency), and the FPGA has a very fast running speed; when used with SelectIO, a large number of signals can be transmitted across FPGAs, and the timing of the post-FPGA engineering can be easily converged. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A DUT clock signal recovery method based on multiple FPGA interconnection, characterized in that: include: Use the feedback mode within the PLL to lock the phase of the CLK_IN and CLK_OUT inside each interconnected FPGA; The clock source is divided into multiple paths through clk_buffer, and input to the dedicated clock pin of each FPGA through the same routing width and length as the input of the PLL, and the DUT clock signal is output; Determine whether the DUT clock signals output by each FPGA are in the same phase. If the output DUT clock signals are in different phases, reset the PLL of each FPGA until the DUT clock signals output by each FPGA are in the same frequency and phase. The method of determining whether the clock signals output by each FPGA are in phase includes: Each FPGA in the interconnected plurality of FPGAs is combined with the remaining FPGAs in pairs, each group including a first FPGA and a second FPGA; The DUT clock signal output by the first FPGA is input into the second FPGA, and an XOR operation is performed with the DUT clock signal output by the second FPGA, and the operation result is sampled; if the sampling result is a high level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are in different phases; if the sampling result is a low level, it is determined that the DUT clock signal output by the first FPGA and the DUT clock signal output by the second FPGA are in the same phase.

2. A system for interconnecting multiple FPGAs, characterized in that: The system executes the DUT clock signal recovery method based on multi-FPGA interconnection as described in claim 1, and the system includes a DUT clock signal recovery device, and the DUT clock signal recovery device includes: a phase locking module, which uses the feedback mode in the PLL to lock the phase of CLK_IN and CLK_OUT inside each interconnected FPGA; a clock signal processing module, which divides the clock source into multiple paths through clk_buffer, inputs them to the dedicated clock pin of each FPGA through the same routing width and length as the input of the PLL, and outputs the DUT clock signal; a phase judgment module, which judges whether the DUT clock signals output by each FPGA are in the same phase. When the output DUT clock signals are in different phases, the PLL of each FPGA is reset until the DUT clock signals output by each FPGA are in the same frequency and phase.

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