Voltage multiplexing selection circuit for eeprom port and eeprom system including the same

Abstract

The application provides a voltage multiplexing selection circuit for an EEPROM port and an EEPROM system comprising the same. The circuit comprises a control line end voltage multiplexing module and a bit line end voltage multiplexing module. The control line end voltage multiplexing module comprises a first latch, a first latch signal input unit, a first output switch tube and a second output switch tube. The gates of the first and second output switch tubes are connected to the output end of the first latch, the drains of the first and second output switch tubes are used for receiving first and second input voltages respectively, and the sources of the first and second output switch tubes are connected to the control line ends of different storage units. The bit line end voltage multiplexing module comprises a second latch, a second latch signal input unit, a third output switch tube and a fourth output switch tube. The gates of the third and fourth output switch tubes are connected to the output end of the second latch, the drains of the third and fourth output switch tubes are used for receiving third and fourth input voltages respectively, and the sources of the third and fourth output switch tubes are connected to the bit line ends of different storage units. The application can solve the problems of complex structure and many analog devices of the EEPROM port voltage multiplexing selection circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more particularly to a voltage multiplexing selection circuit for an EEPROM port and an EEPROM system including the circuit. Background Technology

[0002] With the development of integrated circuit technology, electrically erasable programmable read-only memory (EEPROM) has been widely used, and manufacturers are gradually shifting their design and production focus towards cost reduction and efficiency improvement.

[0003] The structure of an EEPROM is generally as follows: Figure 1 As shown, the system includes a first memory cell 1 and a second memory cell 2. The first memory cell 1 includes: a memory transistor M0, a select transistor M2 (denoted as drain select transistor M2) connected to the drain of memory transistor M0, and a select transistor M4 (denoted as gate select transistor M4) connected to the gate of memory transistor M0. The second memory cell 2 includes: a memory transistor M1, a select transistor M3 (denoted as drain select transistor M3) connected to the drain of memory transistor M1, and a select transistor M5 (denoted as gate select transistor M5) connected to the gates of memory transistors M0 and M1. The drains of drain select transistors M2 and M3 are connected to the bit line terminals BL0 and BL1 of their respective memory cells; the drains of gate select transistors M4 and M5 are connected to the control line terminals CL0 and CL1 of their respective memory cells; the gates of drain select transistors M2 and M3 and gate select transistors M4 and M5 are connected to the same word line terminal WL; and the sources of memory transistors M0 and M1 are connected to the VGD port.

[0004] Data erasure, writing, and reading operations in each memory cell of the EEPROM are achieved by applying different voltages to the three ports of each memory cell, as shown in Table 1 below:

[0005] Table 1

[0006]

[0007]

[0008] In Table 1, FLOAT indicates floating, HV indicates high voltage, ROUT indicates readout, LV indicates low voltage, and VB indicates bias voltage.

[0009] Existing technologies typically use voltage multiplexing selection circuits to provide different voltages to different ports of each memory cell. However, existing EEPROM port voltage multiplexing selection circuits are complex in structure, contain many analog components, and occupy a large area. Summary of the Invention

[0010] To address the problems of complex structure, numerous analog components, and large area occupation of existing EEPROM port voltage multiplexing selection circuits, this invention provides an improved voltage multiplexing selection circuit for EEPROM ports and an EEPROM system including this circuit.

[0011] To achieve the above objectives, the present invention provides a voltage multiplexing selection circuit for an EEPROM port, including a control line voltage multiplexing module and a bit line voltage multiplexing module;

[0012] The control line voltage multiplexing module includes: a first latch, a first latch signal input unit, a first output switch transistor, and a second output switch transistor. The first latch signal input unit is connected to the input terminal of the first latch. The gates of the first output switch transistor and the second output switch transistor are respectively connected to the output terminal of the first latch. The drains are respectively used to receive the first input voltage and the second input voltage. The sources are respectively used to connect to the control line terminals of different memory cells in the EEPROM.

[0013] The bit line voltage multiplexing module includes: a second latch, a second latch signal input unit, a third output switch, and a fourth output switch. The second latch signal input unit is connected to the input terminal of the second latch. The gates of the third and fourth output switches are respectively connected to different output terminals of the second latch. The drains are respectively used to receive the third input voltage and the fourth input voltage, and the sources are respectively used to connect to the bit line terminals of different memory cells in the EEPROM.

[0014] In a preferred embodiment of the present invention, the first latch includes a first inverter and a second inverter connected end to end; the second latch includes a third inverter and a fourth inverter connected end to end.

[0015] In a preferred embodiment of the present invention, the first inverter includes a first PMOS transistor and a first NMOS transistor. The drain of the first PMOS transistor is used to receive the programming voltage, the source is connected to the drain of the first NMOS transistor, the gate is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is grounded.

[0016] The second inverter includes a second PMOS transistor and a second NMOS transistor. The drain of the second PMOS transistor is used to receive the programming voltage. The source is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor. The gate is connected to the gate of the second NMOS transistor and the drain of the first NMOS transistor. The source of the second NMOS transistor is grounded.

[0017] In a preferred embodiment of the present invention, the third inverter includes a third PMOS transistor and a third NMOS transistor. The drain of the third PMOS transistor is used to receive the programming voltage, the source is connected to the drain of the third NMOS transistor, and the gate is connected to the gate of the third NMOS transistor. The source of the third NMOS transistor is grounded; and / or

[0018] The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor. The drain of the fourth PMOS transistor is used to receive the programming voltage. The source is connected to the drain of the fourth NMOS transistor and the gate of the third NMOS transistor. The gate is connected to the gate of the fourth NMOS transistor and the drain of the third NMOS transistor. The source of the fourth NMOS transistor is grounded.

[0019] In a preferred embodiment of the present invention, the first latch signal input unit includes: a first input switch transistor and a second input switch transistor, the gate of the first input switch transistor and the gate of the second input switch transistor are connected and used to receive a switch signal, the drain of the first input switch transistor and the drain of the second input switch transistor are used to receive signals with opposite levels, and the source of the first input switch transistor and the source of the second input switch transistor are respectively connected to different input terminals of the first latch.

[0020] In a preferred embodiment of the present invention, the second latch signal input unit includes a third input switch and a fourth input switch. The gates of the third input switch and the fourth input switch are connected and used to receive a switch signal. The drains of the third input switch and the fourth input switch are used to receive signals with opposite levels. The sources of the third input switch and the fourth input switch are respectively connected to different input terminals of the second latch.

[0021] To achieve the above objectives, the present invention also provides an EEPROM system, including a first memory unit and a second memory unit. The first memory unit and the second memory unit respectively include a memory transistor, a drain select transistor connected to the drain of the memory transistor, and a gate select transistor connected to the gate of the memory transistor. The drain of the drain select transistor is connected to the bit line terminal of the corresponding memory unit, the drain of the gate select transistor is connected to the control line terminal of the corresponding memory unit, and the gate of the drain select transistor and the gate level of the gate select transistor are connected to the word line terminal. The EEPROM system further includes the voltage multiplexing selection circuit as described above.

[0022] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides voltage to the control line terminals and bit line terminals of different memory cells in EEPROM through a simple control line terminal voltage multiplexing module and a bit line terminal voltage multiplexing module. While realizing the multiplexing of the voltage selection path of different memory cell ports, it effectively reduces the number of analog devices used and the area occupied. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a conventional EEPROM.

[0024] Figure 2 This is a circuit diagram of the control line terminal voltage multiplexing module in Embodiment 1 of the present invention;

[0025] Figure 3 This is a circuit diagram of the bit line terminal voltage multiplexing module in Embodiment 1 of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0027] It should be noted that the terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The singular forms “a,” “the,” and “the” used in this invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0028] Example 1

[0029] This embodiment provides a voltage multiplexing selection circuit for an EEPROM port, suitable for... Figure 1 The EEPROM shown. In this embodiment, the circuit includes... Figure 2 The control line terminal voltage multiplexing module shown and Figure 3 The bit line terminal voltage multiplexing module is shown.

[0030] See Figure 2 The control line voltage multiplexing module includes: a first latch 11, a first latch signal input unit 12, a first output switch Mo1, and a second output switch Mo2. The first latch signal input unit 12 is connected to the input terminal of the first latch 11. The gates of the first output switch Mo1 and the second output switch Mo2 are respectively connected to the same output terminal of the first latch 11. The drains of Mo1 and Mo2 are used to receive the first input voltage VPPE0_VS and the second input voltage VPPE1_VS, respectively. The sources of Mo1 and Mo2 are respectively connected to the control line terminals CL0 and CL1 of the first storage cell 1 and the second storage cell 2 in the EEPROM.

[0031] In this embodiment, the first latch 11 includes a first inverter and a second inverter connected end-to-end. The first inverter includes a first PMOS transistor MP1 and a first NMOS transistor MN1. The drain of the first PMOS transistor MP1 is used to receive the programming voltage VPP, the source is connected to the drain of the first NMOS transistor MN1, and the gate is connected to the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded. The second inverter includes a second PMOS transistor MP2 and a second NMOS transistor MN2. The drain of the second PMOS transistor MP2 is used to receive the programming voltage VPP, the source is connected to the drain of the second NMOS transistor MN2 and the gate of the first NMOS transistor MN1, and the gate is connected to the gate of the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1; the source of the second NMOS transistor MN2 is grounded.

[0032] The first latch signal input unit 12 includes: a first input switch Mi1 and a second input switch Mi2. The gate of the first input switch Mi2 and the gate of the second input switch Mi2 are connected and used to receive a switch signal SW. The drain of the first input switch Mi1 and the drain of the second input switch Mi2 are used to receive signals CIN and CINB with opposite levels. The source of the first input switch Mi1 and the source of the second input switch Mi2 are respectively connected to different input terminals of the first latch 11.

[0033] See Figure 3 The bit line voltage multiplexing module includes: a second latch 21, a second latch signal input unit 22, a third output switch Mo3, and a fourth output switch Mo4. The second latch signal input unit 22 is connected to the input terminal of the second latch 21. The gates of the third output switch Mo3 and the fourth output switch Mo4 are respectively connected to different output terminals of the second latch 21. Their drains are used to receive the third input voltage VPPW0_RO and the fourth input voltage VPPW1_RO, respectively, and their sources are used to connect to the bit line terminals BL0 and BL1 of the first storage cell 1 and the second storage cell 2 in the EEPROM, respectively.

[0034] The second latch 21 includes a third inverter and a fourth inverter connected end-to-end. The third inverter includes a third PMOS transistor MP3 and a third NMOS transistor MN3. The drain of the third PMOS transistor MP3 is used to receive the programming voltage VPP, the source is connected to the drain of the third NMOS transistor MN3, the gate is connected to the gate of the third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is grounded. The fourth inverter includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4. The drain of the fourth PMOS transistor MP4 is used to receive the programming voltage VPP, the source is connected to the drain of the fourth NMOS transistor MN4 and the gate of the third NMOS transistor MN3, the gate is connected to the gate of the fourth NMOS transistor MN4 and the drain of the third NMOS transistor MN3, and the source of the fourth NMOS transistor MN4 is grounded.

[0035] The second latch signal input unit 22 includes a third input switch transistor Mi3 and a fourth input switch transistor Mi4. The gates of the third input switch transistor Mi3 and the fourth input switch transistor Mi4 are connected and used to receive a switch signal SW. The drains of the third input switch transistor Mi3 and the fourth input switch transistor Mi4 are used to receive signals DIN and BINB with opposite levels. The sources of the third input switch transistor Mi3 and the fourth input switch transistor Mi4 are respectively connected to different input terminals of the second latch 21.

[0036] This embodiment provides voltage to the control line terminals and bit line terminals of different memory cells in the EEPROM through a simple control line terminal voltage multiplexing module and a bit line terminal voltage multiplexing module. While realizing the multiplexing of the voltage selection path of different memory cell ports, it effectively reduces the number of analog devices used and the area occupied.

[0037] based on Figure 2 and Figure 3 The voltage multiplexing selection circuit structure shown is used when it is necessary to select the voltage multiplexing selection circuit. Figure 1 When performing erase, write, and read operations on M0, the method is as follows (the erase operation on M1 is similar):

[0038] According to Table 1, during the erase operation, the WL voltage is HV and the CL voltage is HV. Based on this, if an erase operation needs to be performed on M0, the following steps should be executed:

[0039] S11, let CIN = 1 / CINB = 0 and SW = 1, such that a = 1.

[0040] S12 applies high voltage to VPP and VPPE0_VS, but does not apply high voltage to VPPE1_VS, so that CL0 outputs high voltage.

[0041] S13, no high voltage is applied to VPPW0_RO and VPPW1_RO.

[0042] S14, WL defaults to loading high voltage to open the selection tube of the first storage unit 1.

[0043] S15, the high voltage at the CL0 terminal is transmitted to the gate terminal of the storage tube M0 through the selector tube to start the erase operation, while M1 retains its original data because no high voltage is applied to its gate terminal.

[0044] Conversely, when an erase operation is performed on M1, M0 retains its original data.

[0045] According to Table 1, during a write operation, the BL voltage should be HV, the WL voltage should be HV, and the CL voltage should be 0. Based on this, if a write operation needs to be performed on M0, the following steps should be executed (similar to the erase operation on M1):

[0046] S21, let DIN = 1 / DINB = 0 and SW = 1, such that b = 1 and c = 0.

[0047] S22, apply high voltage to VPP and VPPW0_RO, but do not apply high voltage to VPPW1_RO.

[0048] S23, let CIN = 1 / CINB = 0 and SW = 1, such that a = 1.

[0049] S24, let VPPE0_VS / VPPE1_VS=0.

[0050] S25, WL defaults to high voltage to enable the selection tube of the storage cell.

[0051] S26, because b=1, the high voltage at the BL0 terminal is transmitted to the drain of the storage tube M0 through the selector to start the write operation; because c=0, M1 retains its original data because no high voltage is applied to the drain.

[0052] Conversely, when writing to M1, M0 retains its original data.

[0053] According to Table 1, during a read operation, BL is the data read channel, WL voltage is LV, and CL voltage is VB. Based on this, if a read operation needs to be performed on M0, the following steps are performed (the steps are similar when performing a read operation on M1):

[0054] S31, let CIN = 1 / CINB = 0 and SW = 1, such that a = 1.

[0055] S32 applies a low voltage to VPP, and VPPE0_VS / VPPE1_VS applies the bias voltage VB required for the read operation.

[0056] S33, read data operation, WL defaults to loading low voltage to select the memory cell selection tube.

[0057] S34, set DIN=1 / DINB=0 and SW=1, so that b=1 / c=0 to open the data read channel of BL0 and close the data read channel of BL1 to avoid mutual interference between different cell currents when reading cell current. Conversely, the same applies when reading M1.

[0058] Example 2

[0059] This embodiment provides an EEPROM system, including Figure 1 The EEPROM shown includes a first storage unit 1 and a second storage unit 2, and also includes the voltage multiplexing selection circuit described in Embodiment 1, which includes a control line voltage multiplexing module and a bit line voltage multiplexing module.

[0060] This embodiment effectively reduces the number of analog devices and their footprint by reusing the storage unit port voltage selection path.

[0061] It should be understood that each voltage multiplexing selection circuit controls a maximum of two memory cells, operating on one memory cell at a time. When the EEPROM contains more than two memory cells, more voltage multiplexing selection circuits as described in Embodiment 1 can be used to achieve voltage multiplexing.

[0062] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of the present invention.

Claims

1. A voltage multiplexing selection circuit for an EEPROM port, characterized in that, Includes a control line voltage multiplexing module and a bit line voltage multiplexing module; The control line voltage multiplexing module includes: a first latch, a first latch signal input unit, a first output switch transistor, and a second output switch transistor. The first latch signal input unit is connected to the input terminal of the first latch. The gates of the first output switch transistor and the second output switch transistor are respectively connected to the output terminal of the first latch transistor, the drains are respectively used to receive the first input voltage and the second input voltage, and the sources are respectively connected to the control line terminals of different memory cells in the EEPROM. The bit line voltage multiplexing module includes: a second latch, a second latch signal input unit, a third output switch, and a fourth output switch. The second latch signal input unit is connected to the input terminal of the second latch. The gates of the third and fourth output switches are respectively connected to different output terminals of the second latch, the drains are respectively used to receive the third and fourth input voltages, and the sources are respectively connected to the bit lines of different memory cells in the EEPROM.

2. The voltage multiplexing selection circuit according to claim 1, characterized in that, The first latch includes a first inverter and a second inverter connected end to end; The second latch includes a third inverter and a fourth inverter connected end to end.

3. The voltage multiplexing selection circuit according to claim 2, characterized in that, The first inverter includes a first PMOS transistor and a first NMOS transistor. The drain of the first PMOS transistor is used to receive the programming voltage, the source is connected to the drain of the first NMOS transistor, the gate is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The second inverter includes a second PMOS transistor and a second NMOS transistor. The drain of the second PMOS transistor is used to receive the programming voltage. The source is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor. The gate is connected to the gate of the second NMOS transistor and the drain of the first NMOS transistor. The source of the second NMOS transistor is grounded.

4. The voltage multiplexing selection circuit according to claim 2, characterized in that, The third inverter includes a third PMOS transistor and a third NMOS transistor. The drain of the third PMOS transistor is used to receive the programming voltage, the source is connected to the drain of the third NMOS transistor, the gate is connected to the gate of the third NMOS transistor, and the source of the third NMOS transistor is grounded. The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor. The drain of the fourth PMOS transistor is used to receive the programming voltage. The source is connected to the drain of the fourth NMOS transistor and the gate of the third NMOS transistor. The gate is connected to the gate of the fourth NMOS transistor and the drain of the third NMOS transistor. The source of the fourth NMOS transistor is grounded.

5. The voltage multiplexing selection circuit according to claim 1, characterized in that, The first latch signal input unit includes: a first input switch transistor and a second input switch transistor. The gates of the first input switch transistor and the second input switch transistor are connected and used to receive a switch signal. The drains of the first input switch transistor and the second input switch transistor are used to receive signals with opposite levels. The sources of the first input switch transistor and the second input switch transistor are respectively connected to different input terminals of the first latch.

6. The voltage multiplexing selection circuit according to claim 1, characterized in that, The second latch signal input unit includes a third input switch and a fourth input switch. The gates of the third input switch and the fourth input switch are connected and used to receive a switch signal. The drains of the third input switch and the fourth input switch are used to receive signals with opposite levels. The sources of the third input switch and the fourth input switch are respectively connected to different input terminals of the second latch.

7. An EEPROM system, comprising a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell respectively include a memory transistor, a drain select transistor connected to the drain of the memory transistor, and a gate select transistor connected to the gate of the memory transistor, wherein, The drain of the drain select transistor is connected to the bit line terminal of the corresponding memory cell, the drain of the gate select transistor is connected to the control line terminal of the corresponding memory cell, and the gate of the drain select transistor and the gate of the gate select transistor are respectively connected to the word line terminal. The feature is that it further includes: The voltage multiplexing selection circuit according to any one of claims 1-6.

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