Metal-containing structures and methods of treating metal-containing materials to increase grain size and / or reduce contaminant concentrations

Abstract

The present application relates to metal-containing structures, and methods of treating metal-containing materials to increase grain size and / or reduce contaminant concentrations. Some embodiments include methods of forming a conductive structure. A metal-containing conductive material is formed on a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and at least one oxidant. The exposure changes at least a portion of the metal-containing conductive material to form at least a portion of the conductive structure. Some embodiments include a conductive structure having a metal-containing conductive material, the conductive material having a first region adjacent to a second region. The first region has a higher concentration of one or both of fluorine and boron relative to the second region.

Description

Technical Field

[0001] Integrated assemblies. Metal-containing structures (e.g., word lines and bit lines). Methods of processing metal-containing materials to increase grain size and / or reduce contaminant concentrations. Background Art

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is common in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to obtain enhanced features.

[0003] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0004] Before describing NAND in detail, it may be helpful to more generally describe the relationship of the memory array within the integrated arrangement. FIG. 1 shows a block diagram of a prior art device 1000 including a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns and access lines 1004 (e.g., word lines that conduct signals WL0 to WLm) and first data lines 1006 (e.g., bit lines that conduct signals BL0 to BLn). The access lines 1004 and the first data lines 1006 may be used to transfer information to and from the memory cells 1003. The row decoder 1007 and the column decoder 1008 decode the address signals A0 to AX on the address lines 1009 to determine which memory cells 1003 are to be accessed. The sense amplifier circuit 1015 operates to determine the value of the information read from the memory cells 1003. The I / O circuit 1017 transmits the value of information between the memory array 1002 and the input / output (I / O) line 1005. The signals DQ0 to DQN on the I / O line 1005 can represent the value of information read from the memory cell 1003 or to be written to the memory cell 1003. Other devices can communicate with the device 1000 through the I / O line 1005, the address line 1009, or the control line 1020. The memory control unit 1018 is used to control the memory operation to be performed on the memory cell 1003 and utilizes the signal on the control line 1020. The device 1000 can receive power supply voltage signals Vcc and Vss on the first power supply line 1030 and the second power supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input / output (I / O) circuit 1017. The selection circuit 1040 can respond to the signals CSEL1 to CSELn via the I / O circuit 1017 to select the signals on the first data line 1006 and the second data line 1013, which can represent the value of the information to be read from the memory cell 1003 or to be programmed into the memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address lines 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 in FIG. 1 may be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that may be used for the memory array 1002 in FIG. 1 . The device 200 includes a plurality of charge storage device strings. In a first direction (Z-Z'), each charge storage device string may include, for example, thirty-two charge storage devices stacked on top of each other, wherein each charge storage device corresponds to, for example, one of thirty-two layers (e.g., layer 0 to layer 31). The charge storage devices of the corresponding strings may share a common channel region, such as a common channel region formed in a corresponding pillar of semiconductor material (e.g., polysilicon), wherein the charge storage device string is formed around the pillar. In a second direction (XX'), each of, for example, sixteen first groups of the plurality of strings may include, for example, eight strings that share a plurality (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines", also referred to as word lines WL). Each access line may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), for example, each of the eight second groups of multiple strings can include sixteen strings coupled by a corresponding one of the eight data lines. The size of the memory block can include 1,024 pages and a total of approximately 16MB (e.g., 16 WLs×32 layers×2 bits=1,024 pages / block, block size=1,024 pages×16KB / page=16MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages can be greater or less than the number shown in FIG. 2.

[0006] 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, which includes fifteen charge storage device strings in one of the sixteen first groups of strings described with respect to FIG. 2. The plurality of strings of the memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as I , Tile Column j and tile columns K, where each subset (e.g., tile column) contains a "partial block" of the memory block 300. The global drain-side select gate (SGD) line 340 can be coupled to the SGD of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via a corresponding one of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 can simultaneously couple or cut off the SGD of the string of the corresponding partial block (e.g., tile column) independently of the SGD of other partial blocks. The global source-side select gate (SGS) line 360 ​​can be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​can be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 can simultaneously couple or cut off the SGS of the string of the corresponding partial block (e.g., a tile column) independently of the SGS of other partial blocks. The global access line (e.g., a global CG line) 350 can couple the charge storage device of the corresponding layer of each of the plurality of strings. Each global CG line (e.g., a global CG line 350) can be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314, and 316. Each sub-string driver can simultaneously couple or cut off the charge storage device corresponding to the corresponding partial block and / or layer independently of the charge storage device of other partial blocks and / or other layers. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and the respective layers may include a "partial layer" (e.g., a single "tile") of the charge storage devices. The strings corresponding to the respective subsets (e.g., partial blocks) may be coupled to respective ones of the sub-sources 372, 374, and 376 (e.g., "tile sources"), each of which is coupled to a respective power source.

[0007] NAND memory device 200 is optionally described with reference to the schematic diagram of FIG. 4 .

[0008] The memory array 200 includes word lines 202 1 To 202 N and bit line 228 1 To 228 M .

[0009] The memory array 200 also includes NAND strings 206. 1 To 206 M Each NAND string includes a charge storage transistor 208 1To 208 N The charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0010] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 206 of each NAND string 208 is connected in series from source to drain between a source select device (e.g., source side select gate, SGS) 210 and a drain select device (e.g., drain side select gate, SGD) 212. Each source select device 210 is located at the intersection of the string 206 and the source select line 214, and each drain select device 212 is located at the intersection of the string 206 and the drain select line 215. The select devices 210 and 212 can be any suitable access devices and are generally shown as boxes in Figure 4.

[0011] The source of each source selection device 210 is connected to the common source line 216. The drain of each source selection device 210 is connected to the source of the corresponding NAND string 206 of the first charge storage transistor 208. For example, the source selection device 210 1 The drain of the charge storage transistor 208 is connected to 1 The corresponding NAND string 206 1 The source selection device 210 is connected to the source selection line 214.

[0012] The drain of each drain select device 212 is connected to a bit line (ie, digit line) 228 at a drain contact. 1 The drain is connected to the bit line 228 1 The source of each drain selection device 212 is connected to the drain of the corresponding NAND string 206 of the previous charge storage transistor 208. For example, the drain selection device 212 1 The source of the charge storage transistor 208 is connected to N The corresponding NAND string 206 1 of the drain.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 has its control gate 236 coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are commonly coupled to a given word line 202.

[0014] It is desirable to have high conductivity (low resistance) within various conductive structures (e.g., word lines and bit lines) of a three-dimensional NAND assembly (arrangement, device). It is desirable to develop methods for increasing conductivity within such conductive structures. It is also desirable that such methods be generally applicable to conductive structures (e.g., word lines and bit lines) of integrated circuits (e.g., logic, memory, sensors, etc.). Summary of the invention

[0015] In one aspect, the present application is directed to a method for forming a conductive structure, comprising: forming a metal-containing conductive material on a supporting substrate; and exposing a surface of the metal-containing conductive material to at least one free radical form of hydrogen and at least one oxidant; the exposure changes at least a portion of the metal-containing conductive material, thereby forming at least a portion of the conductive structure.

[0016] In another aspect, the present application is directed to an assembly comprising a metal-containing conductive material having a first region adjacent to a second region; the first region having a smaller average grain size per unit area relative to the second region; the conductive structure is located within a conductive layer; the conductive layer is one of a plurality of substantially identical conductive layers within a stack having insulating layers alternating with the conductive layers.

[0017] In another aspect, the present application is directed to a conductive structure comprising a metal-containing conductive material having a first region adjacent to a second region; the first region having a higher concentration of one or both of fluorine and boron relative to the second region.

[0018] In another aspect, the present application is directed to an integrated assembly comprising: a conductive structure supported by a semiconductor substrate; and the conductive structure comprising a metal-containing conductive material having a first region adjacent to a second region; the first region having a different crystallinity relative to the second region and having a higher concentration of one or both of fluorine and boron relative to the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0020] FIG. 2 is a schematic diagram showing a prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0021] FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device in FIG. 2 along the XX′ direction.

[0022] FIG. 4 is a schematic diagram of a NAND memory array in the prior art.

[0023] Figure 5A schematic cross-sectional side view of a portion of an integrated assembly processed according to an example embodiment is shown.

[0024] Figure 6 is a schematic cross-sectional side view of a portion of an integrated assembly according to an example embodiment.

[0025] Figure 7 is a schematic cross-sectional side view of a portion of an integrated assembly according to an example embodiment.

[0026] Figure 8 A schematic cross-sectional side view of a portion of an integrated assembly processed according to an example embodiment is shown.

[0027] Fig. 9 is a schematic cross-sectional side view of a portion of an integrated assembly.

[0028] Fig.10 yes Fig. 9 Part of the integrated assembly in Fig. 9 Schematic cross-sectional side view of a process stage following the process stage in .

[0029] Fig.11 yes Fig. 9 Part of the integrated assembly in Fig.10 Schematic cross-sectional side view of a process stage following the process stage in .

[0030] Fig.12 yes Fig. 9 Part of the integrated assembly in Fig.11 Schematic cross-sectional side view of a process stage following the process stage in .

[0031] Fig.13 yes Fig. 9 Part of the integrated assembly in Fig.10 Schematic cross-sectional side view of a process stage following the process stage in .

[0032] Fig.14 yes Fig. 9 Part of the integrated assembly in Fig.13 Schematic cross-sectional side view of a process stage following the process stage in .

[0033] Fig.15 yes Fig. 9 Part of the integrated assembly in Fig.14 Schematic cross-sectional side view of a process stage following the process stage in .

[0034] Fig.16 yes Fig. 9 Part of the integrated assembly in Fig.11Schematic cross-sectional side view of a process stage following the process stage in .

[0035] Fig.17 is a diagrammatic schematic of a portion of an example integrated memory array. DETAILED DESCRIPTION

[0036] Some embodiments include a metal-containing structure (e.g., word lines, bit lines, etc.) having at least two regions that differ from one another with respect to crystallinity and / or contaminant concentration. Some embodiments include methods of exposing a metal-containing material to at least one oxidant and at least one form of hydrogen radicals. The exposure may increase the grain size of the metal-containing material region, and / or may reduce the contaminant concentration (e.g., fluorine concentration, boron concentration, chlorine concentration, carbon concentration, silicon concentration, germanium concentration, oxygen concentration, etc.) within the metal-containing material region. Reference Figure 5-17 Example embodiments are described.

[0037] Figure 5 An integrated assembly (structure, construction, device, arrangement, etc.) 10 is shown that is transformed from a first process stage (A) to a second process stage (B) through a process (T).

[0038] Referring to the first process stage (A), the assembly 10 includes a metal-containing conductive material 12 on a supporting substrate 14 .

[0039] The metal-containing conductive material 12 may include one or more of tungsten, titanium, cobalt, nickel, molybdenum, niobium, ruthenium, tantalum, copper and aluminum. In some embodiments, the metal-containing material 12 may be substantially composed of metal or composed of metal. The metal may be an element (pure, single element metal), or may be a mixture of two or more metals (e.g., an alloy). In some embodiments, the metal-containing material may include a mixture of a metal and one or more non-metallic elements. The non-metallic elements may include, for example, one or more of nitrogen, silicon, boron, carbon and germanium. Therefore, in some embodiments, the metal-containing material 12 may include one or more of metal nitrides, metal silicides, metal borides, metal carbides and metal germanides. In some embodiments, the metal-containing material may include one or more trace contaminants (e.g., one or both of fluorine and boron may be included). It should be noted that boron is listed as a potential non-metallic component and potential contaminant of the conductive material 12. Determining whether boron is a component or a contaminant of the conductive material 12 depends on whether the boron is expected to reach the concentration present in the material within the material 12.

[0040] The support structure 14 may include a semiconductor substrate and may include an insulating material (e.g., silicon nitride, silicon dioxide, etc.) directly adjacent to the metal-containing material 12. Specifically, the support structure 14 may include an insulating material (e.g., silicon dioxide) on a semiconductor material (e.g., silicon). The term "semiconductor substrate" refers to any structure including a semiconductive material, including but not limited to bulk semiconductive materials, such as a semiconductive wafer (alone or in an assembly including other materials) and a semiconductive material layer (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the above-mentioned semiconductor substrate. In some applications, the support structure (base) 14 may correspond to a semiconductor substrate containing one or more materials related to integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0041] Process stage (A) treats the metal-containing material 12 as a single region 16. The metal-containing material 12 has a substantially uniform composition throughout the single region 16.

[0042] The assembly 10 is treated (T) to change at least a portion of the metal-containing material 12, thereby transferring the assembly 10 to a second process stage (B). In the illustrated embodiment, an upper region 18 of the metal-containing material 12 is changed. A dashed line 17 is provided to schematically illustrate the approximate boundary between regions 16 and 18. The boundary represented by dashed line 17 may be an abrupt boundary or may be a gradient boundary.

[0043] Modified region 18 may include a reduced concentration of one or more contaminants compared to region 16. For example, modified region 18 may include a lower concentration of one or both of fluorine and boron relative to region 16. Additionally or optionally, modified region 18 may include a different degree of crystallinity than region 16. For example, modified region 18 may include a larger grain size than region 16.

[0044] Regions 16 and 18 may be considered together to form conductive structure 24 .

[0045] Figure 6The configuration of assembly 10 is schematically illustrated, wherein region 18 includes a larger grain size than region 16. Specifically, grains 20 (only one of which is labeled) are schematically illustrated within region 16, and grains 22 (only one of which is labeled) are schematically illustrated within region 18. Grains 22 are larger than grains 20. In some embodiments, grains 22 may be at least about 10% larger than grains 20, at least about 50% larger than grains 20, at least about two times larger than grains 20, at least about 10 times larger than grains 20, and so on. One of ordinary skill in the art will recognize that grain size may be quantified as an average grain size per unit area. To simplify the drawings, Figure 6 The cross-hatching of the conductive material 12 is not shown.

[0046] Figure 7 The configuration of the assembly 10 is schematically shown, wherein the region 18 has a lower concentration of pollutants (X) than the region 16. To simplify the drawings, Figure 7 The cross-hatching of the conductive material 12 is not shown.

[0047] Shows the pollutant concentration (in Figure 7 The contaminants (denoted as [X] in FIG. 1 ) increase from boundary 17 to region 16. The contaminants may include, for example, one or both of fluorine and boron. The contaminant concentration in region 16 may be at least about 10% higher than in region 18, at least about 50% higher than in region 18, at least about two times higher than in region 18, at least about 10 times higher than in region 18, etc. The contaminant concentration may be expressed as the amount of contaminant per unit volume; and in some embodiments may be expressed as an atomic percentage. In some embodiments, the contaminant concentration in region 18 may be so low as to be undetectable.

[0048] In some embodiments, the contaminant may include fluorine and may be present in the unaltered region 16 at a concentration of at least about 1 atomic percent, 2 atomic percent, 10 atomic percent, 20 atomic percent, etc.; and may be present in the altered region 18 at a concentration less than or equal to about 1 atomic percent, less than or equal to about 0.5 atomic percent, less than or equal to about 0.25 atomic percent, etc.

[0049] In some embodiments, the contaminant may include boron and may be present in the unaltered region 16 at a concentration of at least about 1 atomic percent, 2 atomic percent, 10 atomic percent, 20 atomic percent, etc.; and may be present in the altered region 18 at a concentration less than or equal to about 1 atomic percent, less than or equal to about 0.5 atomic percent, less than or equal to about 0.25 atomic percent, or even substantially undetectable.

[0050] The reduction in the contaminant concentration within region 18 and / or the increase in the grain size within region 18 can improve the overall conductivity of conductive structure 24. This can improve the operating characteristics of conductive structure 24 of the integrated architecture. For example, conductive structure 24 can be incorporated into wiring, interconnects, components, etc. of an integrated assembly. In some embodiments, conductive structure 24 can be incorporated into bit lines and / or word lines.

[0051] Figure 5 The treatment (T) in may include exposing the metal-containing material 12 to an oxidizing agent and a reducing agent. The oxidizing agent converts regions of the metal-containing material 12 into metal oxides, and then the reducing agent converts the metal oxides back into a non-oxidized form of the metal-containing material. Repeated oxidation and reduction may result in grain growth within the metal-containing material, and / or may result in the removal of contaminants from the metal-containing material.

[0052] In some embodiments, the reducing agent used to treat (T) may include at least one hydrogen in the form of a free radical (e.g., may include H·, H 2 + and H 2 - and in some embodiments, the reducing agent may comprise, consist essentially of, or consist of H·. Free radical forms of hydrogen may be generated by the plasma. The plasma may be remote from the assembly 10. In other words, the plasma may be operated under conditions where the assembly 10 is not directly exposed to the plasma, but hydrogen radicals generated by the plasma are transported from the plasma to the assembly 10.

[0053] In some embodiments, the oxidizing agent used to treat (T) may include O 2 (diatomic oxygen), O 3 (Ozone), H 2 O 2 (hydrogen peroxide) and perchlorate ions; and in some embodiments, the oxidant may comprise O 2 and O 3 One or two of 2 and O 3 One or two of or consisting of O 2 and O 3 One or two of the components.

[0054] Treatment (T) exposes the upper surface 13 of the assembly 10 to a reducing agent and an oxidizing agent. In some embodiments, such upper surface can be maintained at a temperature in the range of about 100° C. to about 1000° C. for a time of about 10 seconds to about 100 minutes during such treatment. The treated surface can be in an environment with a pressure less than or equal to atmospheric pressure (i.e., a pressure less than or equal to about one atmosphere).

[0055] In some embodiments, the conductive structure 24 may include a plurality of conductive materials, one or more of which have been Figure 5 The processing conditions (T) in are processed. For example, Figure 8 An integrated assembly 10 is shown, the integrated assembly 10 including a conductive material 12 as a first conductive material, and including a second conductive material 26 formed on the first conductive material. The first conductive material 12 is transferred from a first process stage (A) to a second process stage (B) by a treatment (T); such treatment is similar to that described above with reference to Figure 5 Conductive material 12 comprises first and second regions 16 and 18 at process stage (B), wherein region 18 is altered relative to region 16 (eg, comprises fewer contaminants than region 16 and / or comprises a different degree of crystallinity than region 16).

[0056] Process stage (B) transitions to process stage (C) by forming second conductive material 26 on conductive structure 24. Second conductive material 26 may be considered to represent second conductive structure 28 formed directly against altered region 18 of first conductive structure 24. In some embodiments, first and second conductive structures 24 and 28 may be considered together to form third conductive structure 30.

[0057] Second conductive material 26 may be a second metal-containing material; and may include one or more of the substances described above as suitable for use in first metal-containing material 12. Second metal-containing material 26 may be different in composition from first metal-containing material 12, or may be the same in composition as first metal-containing material 12.

[0058] The second metal-containing material 26 is treated (T) to form an altered upper region 32 of the second metal-containing material 26 on an unaltered lower region 34 of the second metal-containing material 26. A dashed line 27 is provided to illustrate the approximate boundary between regions 32 and 34. The altered region 32 may include a different degree of crystallinity (e.g., a larger grain size) than the unaltered region 34 and / or may include a lower concentration of contaminants (e.g., a lower concentration of one or both of fluorine and boron) relative to the unaltered region 34.

[0059] Consider Figure 830. Specifically, process stages (A) and (B) illustrate a first iteration for forming a first portion of conductive structure 30, and process stages (C) and (D) illustrate a second iteration for forming a second portion of the conductive structure. Each iteration includes a process (T). Although two iterations are shown, it should be understood that the process may include any suitable number of iterations to form a conductive structure having any suitable thickness and composition combination. Therefore, in other embodiments, three or more of the illustrated iterations may be used to form a conductive structure.

[0060] Figure 5-8 The method may be used to form conductive components (eg, word lines, bit lines, etc.) of an integrated assembly. Figure 9-16 An example application is shown in which the method is utilized to form conductive components of a three-dimensional NAND.

[0061] Reference Fig. 9 , assembly 40 includes an arrangement 42 supported on a base 44. Base 44 may include a semiconductor substrate. A gap is provided between arrangement 42 and base 44 to indicate that other materials and structures may be provided between arrangement 42 and base 44.

[0062] Arrangement 42 includes alternating layers 46 and 48 .

[0063] Layer 46 may be referred to as an insulating layer, and includes insulating material 50 .

[0064] exist Fig. 9 At the process stage in , layer 48 includes voids 52. These voids are lined with high-k dielectric material 54 (eg, aluminum oxide). The term high-k refers to a dielectric constant that is greater than the dielectric constant of silicon dioxide. Dielectric material 54 may be referred to as a dielectric barrier material.

[0065] Channel material 56 extends through layers 46 and 48. Channel material 56 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; the term III / V semiconductor material refers to semiconductor materials containing elements selected from Group III and Group V of the periodic table (Group III and Group V are old nomenclatures, now referred to as Group 13 and Group 15).

[0066] Although the channel material appears to be arranged along Fig. 9 The cross-section of the channel material 56 may be two spaced-apart segments, but it should be understood that these segments may be part of a single structure. For example, when viewed from above, the channel material 56 may be configured as an annular ring.

[0067] Dielectric material 58 fills the "cavities" between the illustrated segments of channel material 56. The illustrated embodiment may be considered a hollow channel structure. In other embodiments, channel material 56 may be a solid pillar rather than an annular ring.

[0068] Region 60 is outside of channel material 56. This region may contain tunneling material (gate dielectric material), charge storage material, and charge blocking material (in Fig. 9 The tunneling material, charge storage material, and charge blocking material may comprise any configuration suitable for incorporation into a NAND memory cell.

[0069] Fig. 9 Arrangement 42 in can be formed by any suitable process. For example, sacrificial material (not shown) can be initially provided in layer 48 and can be removed after forming channel material 56 to form voids 52. These voids can then be lined with dielectric barrier material 54.

[0070] Reference Fig.10 , a first conductive material 62 is provided within the void 52 to narrow the void. The first conductive material 62 may be a metal-containing material and may be referred to as a first metal-containing material. The conductive material 62 may include any suitable composition. In some embodiments, the first conductive material 62 may be a metal nitride; and may, for example, include, consist essentially of, or consist of titanium nitride, tungsten nitride, or the like.

[0071] Reference Fig.11 , the first metal-containing material 62 is exposed to the above reference Figure 5 The processing conditions described as conditions (T) are described. Specifically, the conductive material 62 is exposed to a reducing agent (e.g., hydrogen radicals) and an oxidizing agent (e.g., one or both of diatomic oxygen and ozone). The exposure forms the modified regions 18 of the conductive material 62, while leaving the unmodified regions 16. The modified regions 18 may contain a lower contaminant concentration and / or a larger grain size than the unmodified regions, as described above with reference to Figure 5-7 as described.

[0072] Reference Fig.12 , in the gap 52( Fig.11) to fill the void. The second conductive material 64 may be a metal-containing material and may be referred to as a second metal-containing material. The second conductive material 64 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more metals (e.g., may include, consist essentially of, or consist of tungsten). In some embodiments, the first metal-containing material 62 may be used as a seed material to promote the growth of the second metal-containing material 64, and / or may be used to provide adhesion to both the second metal-containing material 64 and the dielectric barrier material 54.

[0073] Conductive materials 62 and 64 together form conductive structure 66. This conductive structure may be considered to include a control gate region 68 adjacent to channel material 56, and to include a word line region 70 adjacent to control gate region 68. Word line region 70 may be considered to consist of word lines of a three-dimensional NAND configuration.

[0074] The NAND memory cell 72 may include a control gate region 68 along with portions of the channel material 56 and the materials within the region 60 (i.e., gate dielectric material, charge blocking material, and charge storage material). The NAND memory cells 72 are stacked vertically one above the other. Although two NAND memory cells are shown, it should be understood that there may be more than two memory cells in the vertical stack. For example, there may be 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. in the vertical stack. The vertical stack of memory cells shown may represent a large number of vertical stacks formed across a NAND memory array.

[0075] In some embodiments, Fig.12 At this stage in the process, level 48 may be considered a conductive layer (e.g., a NAND word line layer). Such conductive layers may be considered to alternate with insulating layers 46 within stack 74. Conductive layers 48 may be considered to be substantially identical to one another; where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement.

[0076] In some embodiments, the conductive material 64 can be considered to correspond to a metal-containing core 76 of the conductive structure 66, and such a core can be considered to be at least partially surrounded by the first metal-containing material 62. Each metal-containing core 76 can be considered to be directly adjacent to the first metal-containing material 62 and connected to the first metal-containing material 62 along an interface (interface region) 77. The metal-containing material 62 includes a surface 79 (which can be referred to as a second surface) that is offset from the interface 77. The concentration of contaminants (e.g., contaminants including one or both of fluorine and boron) within the material 62 can decrease in region 18 relative to region 16. In some embodiments, the gradient of the contaminant concentration can increase in the direction from the interface 77 toward the second surface 79, and this increase is similar to the above reference to Figure 7 The increased contaminant concentration [X] described above. In some embodiments, the grain size within the metal-containing material 62 along the interface 77 can be greater than the grain size along the second surface 79; this difference in grain size is similar to the above reference to Figure 6 The differences in grain size described with respect to regions 16 and 18. In some embodiments, altered region 18 may have a larger grain size than unaltered region 16 of metallic material 62 and / or may have a lower contaminant concentration (e.g., a lower concentration of one or both of fluorine and boron) than unaltered region 16.

[0077] Fig.10 and 11 The embodiment in shows that first metal-containing material 62 is exposed to a processing condition (T) to form region 18. In other embodiments, second metal-containing material 64 may be exposed to a processing condition.

[0078] Fig.13 Shown in Fig.10 The assembly 40 at the process stage after the process stage of FIG. A first portion of the conductive material 64 is formed within the void 52 to partially fill the void. The first portion has an exposed surface 65 within the void 52.

[0079] Reference Fig.14 , the exposed surface 65 is exposed to the above reference Figure 5 The processing conditions (T) are described to form modified regions 80 while leaving unmodified regions 82. Dashed lines 81 are provided to schematically illustrate the approximate boundary between modified regions 80 and unmodified regions 82.

[0080] Reference Fig.15 , in the gap 52( Fig.14 ) to fill the voids, thereby forming a conductive core 76. Dashed lines 83 are provided to schematically illustrate the area where the second portion of the conductive material 64 is connected to the first portion of the conductive material 64 ( Fig.14 The first part of this is shown in ).

[0081] Conductive core 76 is connected to first metal-containing material 62 along interface 77. In some embodiments, conductive core 76 includes contaminants, and the concentration of the contaminants increases in a direction toward interface 77 (i.e., is higher in unaltered region 82 than in altered region 80). In some embodiments, conductive core 76 includes a larger grain size in regions away from interface 77 relative to regions directly adjacent to interface 77 (i.e., includes a larger grain size in region 80 than in region 82). Fig.14 The portion of conductive material 64 provided after processing shown in the process stage (the second portion of conductive material 64) can have a grain size approximately the same as the grain size of the unaltered region 82 and / or can have a contaminant concentration approximately the same as the contaminant concentration of the unaltered region 82.

[0082] Fig.15 The configuration in includes similar to the above reference Fig.12 A conductive structure 66 is depicted. Such a conductive structure has a control gate region 68 and a word line region 70 and may comprise a NAND word line of a three-dimensional NAND configuration. Fig.15 The assembly 40 in the embodiment also includes a Fig.12 Vertically stacked NAND memory cells 72 are depicted.

[0083] In some embodiments, both the outer conductive material 62 and the core conductive material 64 may be made of the same material as described above. Figure 5 The treatment process (T) described. In other words, Fig.14 The process stage can be Fig.11 In such an embodiment, Fig.11 The treatment in can be considered as the first exposure to the treatment process (T), Fig.14 The treatment in can be considered as a second exposure to this condition. Fig.16 Assembly 40 is shown in a configuration in which first metalliferous material 62 and second metalliferous material 64 have been subjected to a treatment process (T). Material 62 includes altered regions 18 and unaltered regions 16, and material 64 includes altered regions 80 and unaltered regions 82.

[0084] Fig.16 The assembly 40 comprises a similar Fig.12 The NAND memory cells 72 are depicted as being stacked vertically, and may be considered another example of a three dimensional NAND arrangement.

[0085] Modified conductive structures (e.g. Figure 5 and Figure 8 The conductive structure 24, and Fig.12 , 15 The conductive structures 66 in FIG. 16 may be considered example conductive structures that may be used within an integrated circuit. The conductive structures may be used in many conductive components of an integrated circuit and may be incorporated into word lines and / or bit lines in some embodiments. The word lines and / or bit lines may be used in a NAND memory array of the type described with reference to FIGS. 1-4; an example of a NAND memory array is Fig.12 , 15 and the three-dimensional array shown in 16. Word lines and / or bit lines may also be used in other types of memory arrays; for example, DRAM (dynamic random access memory) arrays. Fig.17 An example DRAM array 90 is schematically shown in FIG. Memory array 90 includes a plurality of memory cells 92. The memory cells shown are representative of a large number of memory cells that may be provided within a memory array. In practice, a memory array may contain hundreds, thousands, millions, hundreds of millions, etc. of memory cells. Memory cell 92 may be a single transistor single capacitor (1T-1C) memory cell, or may be any other suitable memory cell.

[0086] The memory array 90 includes a series of word lines WL1-WL4 and a series of bit lines (digit lines) DL1-DL4. In the illustrated embodiment, each memory cell 92 is uniquely addressed with one of the word lines (WL1-WL4) and one of the bit lines (DL1-DL4). In some embodiments, the word lines may be coupled to driver circuits (e.g., word line driver circuits) and the digit lines (bit lines) may be coupled to sense amplifier circuits.

[0087] In some applications, the word lines (WL1-WL4) and / or the digit lines (DL1-DL4) may include a plurality of digital lines (e.g., as described above with reference to FIG. Figure 5-8 A treated metal-containing material formed by the method described herein.

[0088] The above-described assemblies and structures may be used in integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0089] Unless otherwise stated, the various materials, substances, components, etc. described herein may be formed by any suitable method, which is now known or still to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0090] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes in this disclosure to simplify the premise basis in the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0091] The terms "electrically connected" and "electrically coupled" may both be used in the present disclosure. These terms are considered synonymous. The use of one term in some cases and the other in other cases may provide language variations in the present disclosure to simplify the premise basis in the appended claims.

[0092] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the subsequent claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to the described orientation.

[0093] To simplify the drawings, the cross-sectional views of the drawings only show features within the plane of the cross-section and do not show material behind the plane of the cross-section unless otherwise indicated.

[0094] When a structure is referred to above as being "on," "adjacent," or "against" another structure, it can be directly on the other structure, or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly over," and the like do not denote direct physical contact (unless expressly stated otherwise), but rather denote vertical alignment.

[0095] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying base (e.g., substrate). The vertically extending structure may extend generally orthogonally relative to the upper surface of the base, or may extend non-orthogonally.

[0096] Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed on a support substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and at least one oxidant. The exposure changes at least a portion of the metal-containing conductive material to form at least a portion of the conductive structure.

[0097] Some embodiments include an assembly comprising a metal-containing conductive material having a first region adjacent to a second region. The first region has a smaller average grain size per unit area relative to the second region. The conductive structure is located within a conductive layer. The conductive layer is one of a plurality of substantially identical conductive layers in a stack having insulating layers alternating with the conductive layers.

[0098] Some embodiments include a conductive structure having a metal-containing conductive material having a first region adjacent to a second region. The first region has a higher concentration of one or both of fluorine and boron relative to the second region.

[0099] Some embodiments include an integrated assembly having a conductive structure supported by a semiconductor substrate. The conductive structure includes a metal-containing conductive material having a first region adjacent to a second region. The first region has a different crystallinity relative to the second region and has a higher concentration of one or both of fluorine and boron relative to the second region.

[0100] In compliance with the statute, the subject matter disclosed herein has been described in more or less specific language with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, since the methods disclosed herein include example embodiments. Therefore, the claims are to be given the full scope of the literal wording and are appropriately interpreted according to the doctrine of equivalents.

Claims

1. A method for forming a conductive structure, comprising: forming a metal-containing conductive material on a supporting substrate; and exposing the surface of the metal-containing conductive material to at least one radical form of hydrogen and at least one oxidizing agent; the exposing altering at least a portion of the metal-containing conductive material to form at least a portion of the conductive structure; Wherein the conductive structure further comprises a metal-containing core at least partially surrounded by the metal-containing conductive material, and the metal-containing conductive material is configured to promote growth of the metal-containing core.

2. The method of claim 1, wherein the altering comprises reducing a concentration of at least one contaminant within the metal-containing conductive material.

3. The method of claim 2, wherein the at least one contaminant comprises one or more of chlorine, carbon, silicon, germanium, boron, oxygen, and fluorine. The method of claim 2 , wherein the at least one contaminant comprises fluorine.

5. The method of claim 2, wherein the at least one contaminant comprises boron. The method of claim 1 , wherein the change comprises a change in crystallinity of the metal-containing conductive material.

7. The method of claim 1, wherein the altering comprises increasing a grain size of the metal-containing conductive material. The method of claim 1 , wherein the conductive structure is a bit line.

9. The method of claim 1, wherein the conductive structure is a word line.

10. The method of claim 1, wherein the at least one free radical form of hydrogen comprises H·.

11. The method of claim 1, wherein the at least one free radical form of hydrogen comprises H·, H 2 + and H 2 - One or more of .

12. The method of claim 1, wherein the at least one radical form of hydrogen is generated by a plasma.

13. The method of claim 1, wherein the at least one oxidizing agent comprises O 2 and O 3 One or both of the following.

14. The method of claim 1, wherein the at least one oxidizing agent comprises O 2 , O 3 , hydrogen peroxide and perchlorate ion or more.

15. The method of claim 1, wherein the exposing is performed while the surface is at a temperature in the range of 100°C to 1000°C and in an environment maintained at a pressure less than or equal to atmospheric pressure.

16. The method of claim 1, wherein the conductive material is a first conductive material, and the method further comprises forming a second conductive material directly against the surface after the exposing.

17. A method of forming a conductive structure, include: forming a metal-containing conductive material on a supporting substrate; as well as exposing the surface of the metal-containing conductive material to at least one radical form of hydrogen and at least one oxidizing agent; the exposing altering at least a portion of the metal-containing conductive material to form at least a portion of the conductive structure; wherein the metal-containing conductive material is a first conductive material, and wherein the exposing is a first exposure; and The method further comprises: forming a second conductive material against the surface directly after the first exposing; as well as The surface of the second conductive material is exposed to the at least one radical form of hydrogen and the at least one oxidizing agent to alter at least a portion of the second conductive material.

18. The method of claim 17, wherein the first conductive material comprises titanium and nitrogen, and wherein the second conductive material comprises tungsten.

19. The method of claim 17, wherein the metal-containing conductive material comprises one or more of tungsten, titanium, cobalt, nickel, molybdenum, niobium, ruthenium, tantalum, copper, and aluminum.

20. The method of claim 19, wherein the metal-containing conductive material comprises one or more non-metallic components selected from the group consisting of nitrogen, silicon, germanium, boron, and carbon.

21. An assembly comprising a metal-containing conductive material having a first region adjacent to a second region; the first region having a smaller average grain size per unit area relative to the second region; a conductive structure located within a conductive layer; the conductive layer being one of a plurality of substantially identical conductive layers within a stack having insulating layers alternating with the conductive layer; wherein the conductive structure comprises a metal-containing core at least partially surrounded by the metal-containing conductive material, and the metal-containing conductive material is used to promote growth of the metal-containing core, and wherein the conductive structure comprises the metal-containing conductive material and the metal-containing core.

22. The assembly of claim 21, wherein the average grain size per unit area of ​​the second region is at least 50% greater than the average grain size per unit area of ​​the first region.

23. The assembly of claim 21, wherein the average grain size per unit area of ​​the second region is at least twice the average grain size per unit area of ​​the first region.

24. The assembly of claim 21, wherein the average grain size per unit area of ​​the second region is at least ten times the average grain size per unit area of ​​the first region.

25. The assembly of claim 21, wherein the first region has a higher concentration of one or both of fluorine and boron relative to the second region.

26. A conductive structure comprising a metal-containing conductive material having a first region adjacent to a second region; the first region having a higher concentration of one or both of fluorine and boron relative to the second region; wherein the conductive structure further comprises a metal-containing core at least partially surrounded by the metal-containing conductive material, and the metal-containing conductive material is configured to promote growth of the metal-containing core.

27. The conductive structure of claim 26, wherein the boron concentration in the first region is greater than the boron concentration in the second region.

28. The conductive structure of claim 26, wherein the fluorine concentration in the first region is greater than the fluorine concentration in the second region.

29. The conductive structure of claim 26, wherein the fluorine concentration and the boron concentration in the first region are greater than the fluorine concentration and the boron concentration in the second region.

30. The conductive structure according to claim 26, in: One or both of the fluorine and boron are contained in a pollutant, and the concentration of one or both of the fluorine and boron is a pollutant concentration; The metal-containing conductive material is directly adjacent to the metal-containing core at an interface; The metal-containing conductive material includes a second surface offset from the interface; as well as The gradient of the contaminant concentration increases in a direction from the interface toward the second surface.

31. The conductive structure of claim 30, wherein a gradient of the contaminant concentration within the metal-containing core increases in a direction toward the interface.

32. The conductive structure of claim 31, wherein the metal-containing conductive material comprises titanium nitride, and wherein the metal-containing core comprises tungsten.

33. The conductive structure of claim 31 comprising a word line of a three-dimensional NAND configuration.

34. The conductive structure of claim 26, configured to include the metal-containing conductive material as a metal-containing core, the metal-containing core being at least partially surrounded by a second metal-containing conductive material, and in: The second metal-containing conductive material comprises a metal nitride; The metal-containing core consists essentially of metal; One or both of the fluorine and boron are contained in a pollutant, and the concentration of one or both of the fluorine and boron is a pollutant concentration; the second metal-containing conductive material is directly adjacent to the metal-containing core at an interface; and The gradient of the contaminant concentration within the metal-containing core increases in a direction toward the interface.

35. The conductive structure of claim 34 configured as a region of conductive layers within a stack of alternating conductive and insulating layers.

36. The conductive structure of claim 26 coupled to a driver circuit.

37. The conductive structure of claim 26 coupled to a sense amplifier circuit.

38. An integrated assembly comprising: a conductive structure supported by a semiconductor substrate; and The conductive structure includes a metal-containing conductive material having a first region adjacent to a second region; the first region has a different crystallinity relative to the second region and has a higher concentration of one or both of fluorine and boron relative to the second region, wherein the conductive structure further includes a metal-containing core at least partially surrounded by the metal-containing conductive material, and the metal-containing conductive material is configured to promote growth of the metal-containing core.

39. The integrated assembly of claim 38, wherein the second region has a larger grain size than the first region.

40. The integrated assembly of claim 38, wherein the conductive structure is coupled to a driver circuit.

41. The integrated assembly of claim 38, wherein the conductive structure is coupled with a sense amplifier circuit.

42. The integrated assembly of claim 38, wherein the conductive structures are configured as regions of conductive layers within a stack of alternating conductive and insulating layers.

43. The integrated assembly of claim 42, wherein the metal-containing conductive material comprises one or both of titanium and tungsten.

44. The integrated assembly of claim 43, wherein the metal-containing conductive material comprises nitrogen.

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