Fingerprint recognition module, display panel

Abstract

The present disclosure relates to the field of display technology, and proposes a fingerprint recognition module and a display panel, wherein the fingerprint recognition module includes a pixel sensing circuit, and the pixel sensing circuit includes a driving transistor, a first transistor, a second transistor, and a photodiode. The fingerprint recognition module also includes: a base substrate, a first conductive layer, and a third conductive layer stacked in sequence. The first conductive layer includes: a first signal line and a second signal line. The first signal line extends along a first direction and is connected to the gate of the first transistor; the second signal line extends along a first direction and is connected to the gate of the second transistor; the third conductive layer includes a first conductive portion, and the first conductive portion is used to form a first electrode of the photodiode, and the orthographic projection of the first conductive portion on the base substrate does not intersect with the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate. The fingerprint recognition module has less noise.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a fingerprint recognition module and a display panel. Background Art

[0002] The existing display panel usually integrates a fingerprint recognition module, which can be used to recognize fingerprint images. In the related art, the fingerprint recognition module may include an active pixel sensing circuit, which can convert optical signals into electrical signals, thereby reflecting the fingerprint image according to the electrical signals.

[0003] However, in the related art, the active pixel sensing circuit has more transistors and signal lines, and more parasitic capacitance will be generated between more transistors and signal lines. The parasitic capacitance will cause the fingerprint recognition module to have greater noise when working.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] According to one aspect of the present disclosure, a fingerprint recognition module is provided, which includes a pixel sensing circuit, the pixel sensing circuit includes a driving transistor, a first transistor, a second transistor, and a photodiode, the first electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the first electrode of the driving transistor, and the first electrode of the photodiode is connected to the gate of the driving transistor. The fingerprint recognition module also includes: a substrate, a first conductive layer, and a third conductive layer. The first conductive layer is located on one side of the substrate, and the first conductive layer includes: a first signal line and a second signal line. The first signal line extends along a first direction in the orthogonal projection of the substrate and is connected to the gate of the first transistor; the second signal line extends along the first direction in the orthogonal projection of the substrate, and the second signal line is spaced apart from the first signal line in the orthogonal projection of the substrate and in the second direction of the orthogonal projection of the substrate, the first direction intersects with the second direction, and the second signal line is connected to the gate of the second transistor. A third conductive layer is located on a side of the first conductive layer away from the substrate, the third conductive layer includes a first conductive portion, the first conductive portion is used to form a first electrode of the photodiode, the orthographic projection of the first conductive portion on the substrate does not intersect with the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate, and the orthographic projection of the first conductive portion on the substrate is located between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

[0007] In an exemplary embodiment of the present disclosure, the fingerprint recognition module further includes a second conductive layer, and the second conductive layer is located between the first conductive layer and the third conductive layer. The second conductive layer includes: a third signal line and a fourth signal line, the third signal line extending along the second direction in the orthographic projection of the substrate, and the third signal line is used to connect the second electrode of the first transistor; the fourth signal line extending along the second direction in the orthographic projection of the substrate, and the fourth signal line is used to connect the second electrode of the driving transistor. The third conductive layer also includes a fifth signal line, the fifth signal line extending along the second direction in the orthographic projection of the substrate, and the fifth signal line is used to connect the second electrode of the second transistor.

[0008] In an exemplary embodiment of the present disclosure, the orthographic projection of the fourth signal line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third signal line on the base substrate.

[0009] In an exemplary embodiment of the present disclosure, the orthographic projection of the fifth signal line on the substrate is located between the orthographic projection of the third signal line on the substrate and the orthographic projection of the fourth signal line on the substrate.

[0010] In an exemplary embodiment of the present disclosure, the fingerprint recognition module further includes an active layer, the active layer is located between the base substrate and the first conductive layer, and the active layer includes: a first active portion and a second active portion. The orthographic projection of the first active portion on the base substrate is located between the orthographic projection of the third signal line on the base substrate and the orthographic projection of the fourth signal line on the base substrate, and a portion of the first active portion is used to form a channel region of the first transistor. The orthographic projection of the second active portion on the base substrate is located between the orthographic projection of the third signal line on the base substrate and the orthographic projection of the fourth signal line on the base substrate, and a portion of the second active portion is used to form a channel region of the second transistor and the driving transistor.

[0011] In an exemplary embodiment of the present disclosure, the orthographic projection of the first active portion on the substrate substrate is located between the orthographic projection of the first signal line on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate; the orthographic projection of the second active portion on the substrate substrate is located between the orthographic projection of the first active portion on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate.

[0012] In an exemplary embodiment of the present disclosure, the first active portion includes: a first sub-active portion and a second sub-active portion, the first sub-active portion is used to form the first channel region of the first transistor; the second sub-active portion is used to form the second channel region of the first transistor, and the orthographic projection of the first sub-active portion on the substrate and the orthographic projection of the second sub-active portion on the substrate are spaced apart in the first direction. The first conductive layer also includes: a second conductive portion and a third conductive portion, the second conductive portion is connected to the first signal line, the orthographic projection of the second conductive portion on the substrate covers the orthographic projection of the first sub-active portion on the substrate, and the second conductive portion is used to form the first gate of the first transistor; the third conductive portion is connected to the first signal line, the orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the second sub-active portion on the substrate, and the third conductive portion is used to form the second gate of the first transistor.

[0013] In an exemplary embodiment of the present disclosure, the second active portion includes: a third sub-active portion, a fourth sub-active portion, and a fifth sub-active portion. The third sub-active portion is used to form the first channel region of the second transistor; the fourth sub-active portion is used to form the second channel region of the second transistor; the fifth sub-active portion is used to form the channel region of the driving transistor, and the orthographic projection of the third sub-active portion on the substrate substrate, the orthographic projection of the fourth sub-active portion on the substrate substrate, and the orthographic projection of the fifth sub-active portion on the substrate substrate are sequentially spaced in the first direction, and the orthographic projection of the fifth sub-active portion on the substrate substrate is located between the orthographic projection of the fourth signal line on the substrate substrate and the orthographic projection of the fourth sub-active portion on the substrate substrate. The first conductive layer also includes: a fourth conductive portion, a fifth conductive portion, and a sixth conductive portion. The fourth conductive portion is connected to the second signal line, and the orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the third sub-active portion on the substrate, and the fourth conductive portion is used to form the first gate of the second transistor; the fifth conductive portion is connected to the second signal line, and the orthographic projection of the fifth conductive portion on the substrate covers the orthographic projection of the fourth sub-active portion on the substrate, and the fifth conductive portion is used to form the second gate of the second transistor; the orthographic projection of the sixth conductive portion on the substrate covers the orthographic projection of the fifth sub-active portion on the substrate, and the sixth conductive portion is used to form the gate of the driving transistor.

[0014] In an exemplary embodiment of the present disclosure, the first active portion further includes: a sixth sub-active portion, the sixth sub-active portion being located on the side of the first sub-active portion being away from the second sub-active portion being projected on the substrate substrate in the orthogonal projection on the substrate substrate. The second conductive layer further includes a seventh conductive portion, the seventh conductive portion being located on the orthogonal projection on the substrate substrate between the third signal line being projected on the substrate substrate and the fourth signal line being projected on the substrate substrate; wherein the seventh conductive portion is connected to the sixth conductive portion and the sixth sub-active portion through vias, respectively.

[0015] In an exemplary embodiment of the present disclosure, the second active portion further includes a seventh sub-active portion, the orthographic projection of the seventh sub-active portion on the substrate substrate is located on the side of the orthographic projection of the third sub-active portion on the substrate substrate away from the orthographic projection of the fourth sub-active portion on the substrate substrate. The second conductive layer further includes an eighth conductive portion, the orthographic projection of the eighth conductive portion on the substrate substrate at least partially overlaps with the orthographic projection of the seventh sub-active portion on the substrate substrate, and the eighth conductive portion is connected to the seventh sub-active portion through a via. The fifth signal line is connected to the eighth conductive portion through a via.

[0016] In an exemplary embodiment of the present disclosure, the area of ​​the orthographic projection of the first conductive portion on the substrate is 13-16 times the area of ​​the orthographic projection of the sixth conductive portion on the substrate.

[0017] According to one aspect of the present disclosure, a display panel is provided, comprising: the above-mentioned fingerprint recognition module.

[0018] In an exemplary embodiment of the present disclosure, the display panel further comprises: a substrate, a filter module, a collimating layer, and an array substrate. The fingerprint recognition module is located on one side of the substrate; the filter module is located on the side of the fingerprint recognition module away from the substrate; the collimating layer is located on the side of the filter module away from the substrate; and the array substrate is located on the side of the collimating layer away from the substrate.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0021] Figure 1 A schematic structural diagram of an exemplary embodiment of a pixel sensing circuit in the related art;

[0022] Figure 2 A timing diagram of each node in a driving method of a pixel sensing circuit in the related art;

[0023] Figure 3 It is the structural layout of the fingerprint recognition module in the related technology;

[0024] Figure 4 for Figure 3 The structural layout of the active layer in the

[0025] Figure 5 for Figure 3 A structural layout of the first conductive layer;

[0026] Figure 6 for Figure 3 The structural layout of the second conductive layer;

[0027] Figure 7 for Figure 3 The structural layout of the third conductive layer;

[0028] Figure 8 for Figure 3 The structural layout of the fourth conductive layer;

[0029] Fig. 9 for Figure 3 The structural layout of the fifth conductive layer;

[0030] Fig.10 is the influence curve of parasitic capacitance on the output voltage of the driving transistor;

[0031] Fig.11 is a curve showing the influence of parasitic capacitance on the output voltage of the second transistor;

[0032] Fig.12 This is a structural diagram of an exemplary embodiment of the fingerprint recognition module disclosed in the present invention;

[0033] Fig.13 for Fig.12 The structural layout of the active layer in the

[0034] Fig.14 for Fig.12 A structural layout of the first conductive layer;

[0035] Fig.15 for Fig.12 The structural layout of the second conductive layer;

[0036] Fig.16 for Fig.12 The structural layout of the third conductive layer;

[0037] Fig.17 for Fig.12 The structural layout of the fourth conductive layer;

[0038] Fig.18 for Fig.12 The structural layout of the fifth conductive layer;

[0039] Fig.19 is a graph showing the relationship between the measured area of ​​the first conductive portion and the output current of the driving transistor;

[0040] Fig. 20 for Fig.12 A cross-sectional view along the dashed line AA;

[0041] Fig.21 is a cross-sectional view of another exemplary embodiment of the fingerprint recognition module disclosed herein;

[0042] Fig. 22 It is a schematic structural diagram of an exemplary embodiment of a display panel disclosed in the present invention. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0044] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0045] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0046] The fingerprint recognition module can be used to recognize fingerprint images. In the related art, the fingerprint recognition module may include a pixel sensing circuit, which can convert optical signals into electrical signals, thereby reflecting the fingerprint image according to the electrical signals. Figure 1 , 2 As shown, Figure 1 is a structural schematic diagram of an exemplary embodiment of a pixel sensing circuit in the related art, Figure 2 FIG. 1 is a timing diagram of each node in a driving method of a pixel sensing circuit in the related art. Figure 1As shown, the pixel sensing circuit may include a driving transistor DT, a first transistor T1, a second transistor T2, and a photodiode PD. Among them, the gate of the driving transistor is connected to the node N, the first electrode is connected to the first electrode of the second transistor T2, and the second electrode is connected to the first power supply terminal VDD. The first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Reset. The second electrode of the second transistor T2 is connected to the read signal terminal Read, and the gate is connected to the gate drive signal terminal Gate. The first electrode of the photodiode is connected to the node N, and the second electrode is connected to the bias voltage terminal Vbias. Among them, the driving transistor DT, the first transistor T1, and the second transistor T2 can all be N-type transistors. As Figure 2 As shown, the driving method of the pixel sensing circuit may include three stages: a reset stage t1, a sensing stage t2, and a reading stage t3. In the reset stage t1, the reset signal terminal Reset outputs a high-level signal, the first transistor T1 is turned on, and the initial signal terminal Vinit inputs an initial signal to the node N to reset the node N; in the sensing stage t2, the photodiode PD collects incident light and generates a corresponding electrical signal to charge the node N; in the reading stage t3, the gate drive signal terminal Gate outputs a high level, the second transistor T2 is turned on, and the driving transistor DT outputs a current to the reading signal terminal Read under the action of the node N. Among them, in the reading stage t3, the driving transistor operates in the saturation region, and the formula for the output current of the driving transistor DT is: I = (μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The image processor can determine the intensity of the incident light based on the electrical signal of the read signal terminal Read.

[0047] like Figure 3 , 4 , 5, 6, 7, 8, 9, Figure 3 It is the structural layout of the fingerprint recognition module in the related technology. Figure 4 for Figure 3 The structural layout of the active layer, Figure 5 for Figure 3 The structural layout of the first conductive layer in Figure 6 for Figure 3 The structural layout of the second conductive layer; Figure 7 for Figure 3 The structural layout of the third conductive layer; Figure 8 for Figure 3 The structural layout of the fourth conductive layer; Fig. 9 for Figure 3The structure of the fifth conductive layer in the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be stacked in sequence, and an insulating layer is provided between the adjacent structural layers. The fingerprint recognition module may include Figure 1 The pixel sensing circuit shown.

[0048] like Figure 3 , 4 As shown, the active layer may include an active portion 011 and an active portion 012. Part of the active portion 011 may be used to form a channel region of the first transistor T1; and part of the active portion 012 may be used to form a channel region of the second transistor T2 and the driving transistor DT. Figure 3 , 5 As shown, the first conductive layer may include a signal line 021, a signal line 022, a conductive portion 023, a conductive portion 024, and a conductive portion 025. The conductive portion 023 may be used to form the gate of the driving transistor; the conductive portion 024 may be used to form the gate of the first transistor T1; the conductive portion 025 may be used to form the gate of the second transistor T2; the signal line 021 may be used to provide Figure 1 The reset signal terminal Reset in the signal line 022 can be used to form Figure 1 The gate drive signal terminal Gate in. Figure 3 , 6 As shown, the second conductive layer may include a signal line 031, a signal line 032, a signal line 033, and a conductive portion 034. The signal line 031 may be used to provide Figure 1 The initial signal terminal Vinit in the signal line 032 can be used to provide Figure 1 The signal line 033 can be used to provide Figure 1 The first power supply terminal VDD in. Among them, the signal line 031 can be connected to the active part 011 through a via 071 to connect the second electrode of the first transistor T1 and the initial signal terminal Vinit. The conductive part 034 can be connected to the active part 011 through a via 072, and connected to the conductive part 023 through a via 073 to connect the first electrode of the first transistor T1 and the gate of the driving transistor DT. The signal line 033 is connected to the active part 012 through a via 075 to connect the second electrode of the driving transistor and the first power supply terminal VDD. The signal line 032 can be connected to the active part 012 through a via 076 to connect the second electrode of the second transistor and the read signal terminal. Figure 3 , 7 As shown, the third conductive layer may include a conductive portion 04. The conductive portion 04 may be used to form a first electrode of a photodiode, wherein the conductive portion 04 is connected to the conductive portion 034 through a via 074 to connect the first electrode of the photodiode and the gate of the driving transistor. Figure 3 , 8As shown, the fourth conductive layer may include a conductive portion 05. The conductive portion 05 may be used to form a second electrode of the photodiode. Figure 3 , 9 As shown, the fifth conductive layer may include a signal line 06, which may be used to provide Figure 1 The bias voltage terminal Vbias in the signal line 06 can be connected to the conductive part 05 through the via 077.

[0049] based on Figure 3-9 The fingerprint recognition module shown can be calculated using EDA software Figure 3-9 As shown in Table 1, the capacitance values ​​of parasitic capacitors formed between different conductive parts are shown.

[0050] Table 1

[0051]

[0052] This embodiment simulates the influence of parasitic capacitance on the output of each level of pixels. Fig.10 , 11 As shown, Fig.10 : is the influence curve of parasitic capacitance on the output voltage of the driving transistor, the horizontal axis is the system time, and the vertical axis is the simulation value of the output voltage of the driving transistor; Fig.11 is a curve of the influence of parasitic capacitance on the output voltage of the second transistor, the horizontal axis is system time, and the vertical axis is the simulation value of the output voltage of the second transistor.

[0053] like Fig.10 As shown, 82 represents the curve of the output voltage of the driving transistor changing with time when there is no parasitic capacitance; 81 represents the curve of the output voltage of the driving transistor changing with time when there are other capacitances other than capacitance C2 and no capacitance C2; ​​83 represents the curve of the output voltage of the driving transistor changing with time when there are all parasitic capacitances; 84 represents the curve of the output voltage of the driving transistor changing with time when there is only capacitance C2. Fig.10 It can be seen that the presence of capacitor C2 can make the output voltage curve of the driving transistor drift from 81 to 83, and the influence of other parasitic capacitances other than capacitor C2 makes the output voltage curve of the driving transistor drift from 84 to 83. Therefore, the influence weight of capacitor C2 on the output voltage of the driving transistor is greater than the influence weight of other parasitic capacitances other than capacitor C2 on the output voltage of the driving transistor.

[0054] like Fig.11As shown, 92 represents the variation curve of the output voltage of the second transistor over time without any parasitic capacitance; 93 represents the variation curve of the output voltage of the second transistor over time with other capacitances other than capacitance C7 and without capacitance C7; 91 represents the variation curve of the output voltage of the second transistor over time with all parasitic capacitances; 94 represents the variation curve of the output voltage of the second transistor over time with only capacitance C2. Fig.11 It can be seen that the presence of capacitor C7 can make the output voltage curve of the second transistor drift from 93 to 91, and the influence of other parasitic capacitances other than capacitor C7 makes the output voltage curve of the driving transistor drift from 94 to 91. Therefore, the weight of the influence of capacitor C7 on the output voltage of the second transistor is greater than the weight of the influence of other parasitic capacitances other than capacitor C7 on the output voltage of the second transistor.

[0055] Therefore, the parasitic capacitance C2 formed between the signal line 021 and the conductive part 04 and the parasitic capacitance C7 formed between the signal line 022 and the conductive part 04 in the related art will seriously affect the normal driving of the pixel sensing circuit, thereby affecting the accuracy of the fingerprint recognition module in recognizing fingerprints.

[0056] Based on this, this exemplary embodiment provides a fingerprint recognition module, such as Fig.12 , 14 , as shown in 16, Fig.12 This is a structural diagram of an exemplary embodiment of the fingerprint recognition module disclosed in the present invention. Fig.14 for Fig.12 The structural layout of the first conductive layer in Fig.16 for Fig.12 The fingerprint recognition module includes a pixel sensing circuit, which can be as follows: Figure 1 As shown. Fig.12 , 14As shown in Figures 1 and 16, the fingerprint recognition module further includes: a base substrate 0, a first conductive layer, and a third conductive layer. The first conductive layer is located on one side of the base substrate 1, and the first conductive layer may include: a first signal line 21 and a second signal line 22. The first signal line 21 may extend along the first direction X in the orthographic projection of the base substrate, and may be connected to the gate of the first transistor T1; the second signal line 22 may extend along the first direction X in the orthographic projection of the base substrate, and the second signal line 22 may be spaced apart from the first signal line 21 in the orthographic projection of the base substrate in the second direction Y, and the first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular. The second signal line 22 may be connected to the gate of the second transistor T2. The third conductive layer may be located on the side of the first conductive layer away from the substrate 0, and the third conductive layer may include a first conductive portion 41, which may be used to form the first electrode of the photodiode PD, and the orthographic projection of the first conductive portion 41 on the substrate may not intersect with the orthographic projection of the first signal line 21 on the substrate and the orthographic projection of the second signal line 22 on the substrate, and the orthographic projection of the first conductive portion 41 on the substrate may be located between the orthographic projection of the first signal line 21 on the substrate and the orthographic projection of the second signal line 22 on the substrate. The first signal line 21 may be used to provide Figure 1 The second signal line 22 can be used to provide a reset signal terminal. Figure 1 The gate drive signal terminal in.

[0057] The fingerprint recognition module provided by this exemplary embodiment reduces the parasitic capacitance between the second signal line 22 and the first conductive portion 41, and reduces the parasitic capacitance between the first signal line 21 and the first conductive portion 41, by setting the first conductive portion 41 on the substrate substrate to not intersect with the first signal line 21 on the substrate substrate and the second signal line 22 on the substrate substrate, thereby reducing the influence of the above parasitic capacitance on the output voltage of the driving transistor and the second transistor, reducing the noise when the fingerprint recognition module is working, and improving the fingerprint detection accuracy of the fingerprint recognition module. In addition, the first conductive portion 41 is set on the substrate substrate between the first signal line 21 on the substrate substrate and the second signal line 22 on the substrate substrate, which can improve the integration of the pixel sensing circuit.

[0058] like Figure 3 , 6As shown, the signal line 032 is bent and extended, and has a plurality of right angles. The right angles are prone to strong signal reflection. Meanwhile, the bent and extended signal line 032 is prone to generate large parasitic capacitance with other structures (eg, the first conductive portion 41).

[0059] In this exemplary embodiment, Fig.15 As shown, Fig.12 The fingerprint recognition module may further include a second conductive layer, and the second conductive layer may be located between the first conductive layer and the third conductive layer. The second conductive layer may include: a third signal line 33 and a fourth signal line 34, wherein the orthographic projection of the third signal line 33 on the substrate extends along the second direction Y, and the third signal line 33 is used to connect the second electrode of the first transistor T1; the orthographic projection of the fourth signal line 34 on the substrate may extend along the second direction Y, and the fourth signal line 34 may be used to connect the second electrode of the driving transistor DT. Fig.12 , 16 As shown, the third conductive layer may further include a fifth signal line 45, the orthographic projection of the fifth signal line 45 on the substrate may extend along the second direction Y, and the fifth signal line 45 may be used to connect the second electrode of the second transistor T2. Figure 1 The initial signal terminal Vinit in the fourth signal line 34 can be used to provide Figure 1 The first power supply terminal VDD in the fifth signal line 45 can be used to provide Figure 1 The read signal terminal Read in the third conductive layer. In this exemplary embodiment, the fifth signal line 45 is arranged in the third conductive layer, so that the positive projection of the fifth signal line 45 on the substrate can extend in a straight line along the second direction Y. On the one hand, this arrangement can reduce the above-mentioned signal reflection phenomenon; on the other hand, this arrangement can also reduce the parasitic capacitance between the fifth signal line 45 and other structures; on the other hand, arranging the fifth signal line 45 in the third conductive layer can increase the distance between the fifth signal line 45 and the second signal line 22 in the stacking direction, thereby reducing the parasitic capacitance between the fifth signal line 45 and the second signal line 22, thereby reducing the signal interference between the fifth signal line 45 and the second signal line 22, and improving the performance of the pixel sensing circuit; on the other hand, the fifth signal line 45 extending in a straight line has a shorter length, so that the voltage drop of the fifth signal line 45 itself can be reduced.

[0060] In this exemplary embodiment, Fig.12 , 15 As shown, the orthographic projection of the fourth signal line 34 on the substrate can be located between the orthographic projection of the first conductive portion 41 on the substrate and the orthographic projection of the third signal line 33 on the substrate. Fig.15 and Figure 7 As shown, Fig.15 The first conductive portion 41 in the Figure 7 The conductive portion 4 has a smaller area, Fig.15 The area of ​​the first conductive portion 41 in can be Figure 7 60% of the area of ​​the conductive part 4 in the photodiode. The photodiode PD can be equivalent to an ideal photosensor and an equivalent capacitor, and the first electrode of the photodiode PD (i.e., the first conductive part 41) can be an electrode of the equivalent capacitor. Under certain lighting conditions, the photodiode PD can accumulate a certain amount of charge, where the charge accumulated by the photodiode PD is Q=CU, where C is the capacitance value of the equivalent capacitance of the photodiode PD, and the voltage U is the change in the potential of the node N during the reading phase. Theoretically, under the same conditions, Q∝S, S is the area of ​​the first conductive part 41. The equivalent capacitance of the photodiode can be calculated according to the parallel plate model, and its capacitance value is Where ε0 is the dielectric constant of vacuum, ε r is the relative dielectric constant, and d is the distance between the two electrodes. Under the premise of only considering the influence of S on C, C∝S is satisfied. According to U=Q / C, Q∝S, and C∝S, it can be known that, under the condition that other conditions remain unchanged, the area S of the first conductive portion 41 does not affect the voltage of the N node during the reading phase. Fig.19 As shown in FIG. 1 , it is a graph showing the relationship between the measured area of ​​the first conductive portion and the output current of the driving transistor. The measurement was carried out under 0.5 nit illumination and 100 ms integration time (i.e., the duration of the sensing phase). Fig.19 As shown, the horizontal axis represents the area of ​​the first conductive portion, and the vertical axis represents the output current of the driving transistor. Fig.19 The solid and dotted lines in the figure represent two samples, respectively. Fig.19 It can be seen that under a certain light intensity, the area S of the first conductive portion 41 does not affect the output current of the driving transistor end, that is, the area S of the first conductive portion 41 does not affect the voltage of the node N in the reading stage. Therefore, although the exemplary embodiment reduces the area of ​​the first conductive portion 41 compared to the related art, it does not affect the output current of the driving transistor DT in the reading stage.

[0061] In this exemplary embodiment, the fingerprint recognition module further includes an active layer, such as Fig.13 As shown, Fig.12The active layer in the substrate may be located between the substrate and the first conductive layer, and the active layer may include: a first active portion 11 and a second active portion 12. The orthographic projection of the first active portion 11 on the substrate may be located between the orthographic projection of the third signal line 33 on the substrate and the orthographic projection of the fourth signal line 34 on the substrate, and part of the first active portion 11 may be used to form the channel region of the first transistor T1. The orthographic projection of the second active portion 12 on the substrate may be located between the orthographic projection of the third signal line 33 on the substrate and the orthographic projection of the fourth signal line 34 on the substrate, and part of the second active portion 12 may be used to form the channel region of the second transistor T2 and the driving transistor DT. At the same time, the orthographic projection of the first active portion 11 on the substrate may be located between the orthographic projection of the first signal line 21 on the substrate and the orthographic projection of the second signal line 22 on the substrate; the orthographic projection of the second active portion 12 on the substrate may be located between the orthographic projection of the first active portion 11 on the substrate and the orthographic projection of the second signal line 22 on the substrate. In this exemplary embodiment, Fig.12 , 15 As shown, the orthographic projection of the fifth signal line 15 on the substrate can be located between the orthographic projection of the third signal line 33 on the substrate and the orthographic projection of the fourth signal line 34 on the substrate. This arrangement can make the pixel sensing circuit have a higher degree of integration.

[0062] In this exemplary embodiment, Fig.13 As shown, the first active portion may include: a first sub-active portion 111 and a second sub-active portion 112. The first sub-active portion 111 may be used to form a first channel region of the first transistor T1; the second sub-active portion 112 may be used to form a second channel region of the first transistor T1. The orthographic projection of the first sub-active portion 111 on the substrate and the orthographic projection of the second sub-active portion 112 on the substrate may be spaced apart in the first direction. Fig.14As shown, the first conductive layer further includes: a second conductive portion 23 and a third conductive portion 24, wherein the second conductive portion 23 is connected to the first signal line 21, and the orthographic projection of the second conductive portion 23 on the substrate can cover the orthographic projection of the first sub-active portion 111 on the substrate, and the second conductive portion 23 can be used to form the first gate of the first transistor T1; the third conductive portion 24 can be connected to the first signal line 21, and the orthographic projection of the third conductive portion 24 on the substrate can cover the orthographic projection of the second sub-active portion 112 on the substrate, and the third conductive portion 24 can be used to form the second gate of the first transistor. In this exemplary embodiment, the first transistor T1 is a dual-gate structure, so that the leakage current of the first transistor T1 can be reduced.

[0063] In this exemplary embodiment, Fig.13 As shown, the second active portion may include: a third sub-active portion 123, a fourth sub-active portion 124, and a fifth sub-active portion 125. The third sub-active portion 123 may be used to form the first channel region of the second transistor T2; the fourth sub-active portion 124 may be used to form the second channel region of the second transistor T2; the fifth sub-active portion 125 may be used to form the channel region of the driving transistor DT, and the orthographic projection of the third sub-active portion 123 on the substrate, the orthographic projection of the fourth sub-active portion 124 on the substrate, and the orthographic projection of the fifth sub-active portion 125 on the substrate may be distributed in sequence in the first direction X, and the orthographic projection of the fifth sub-active portion 125 on the substrate may be located between the orthographic projection of the fourth signal line 34 on the substrate and the orthographic projection of the fourth sub-active portion 124 on the substrate. Fig.14 As shown, the first conductive layer may further include: a fourth conductive portion 25, a fifth conductive portion 26, and a sixth conductive portion 27. The fourth conductive portion 25 may be connected to the second signal line 22, and the orthographic projection of the fourth conductive portion 25 on the substrate may cover the orthographic projection of the third sub-active portion 123 on the substrate, and the fourth conductive portion 25 may be used to form the first gate of the second transistor T2; the fifth conductive portion 26 may be connected to the second signal line 22, and the orthographic projection of the fifth conductive portion 26 on the substrate may cover the orthographic projection of the fourth sub-active portion 124 on the substrate, and the fifth conductive portion 26 may be used to form the second gate of the second transistor T2; the orthographic projection of the sixth conductive portion 27 on the substrate may cover the orthographic projection of the fifth sub-active portion 125 on the substrate, and the sixth conductive portion 27 may be used to form the gate of the driving transistor DT. In this exemplary embodiment, the area of ​​the first conductive portion 41 may be 13-16 times the area of ​​the sixth conductive portion 27, for example, 13 times, 14 times, 15 times, or 16 times.

[0064] In this exemplary embodiment, Fig.12 , 13 As shown, the first active portion may further include: a sixth sub-active portion 116, the sixth sub-active portion 116 may be located on the side of the first sub-active portion 111 on the substrate substrate away from the second sub-active portion 112 on the substrate substrate. The second conductive layer may further include a seventh conductive portion 37, the seventh conductive portion 37 may be located between the third signal line 33 on the substrate substrate and the fourth signal line 34 on the substrate substrate; wherein the seventh conductive portion 37 may be connected to the sixth conductive portion 27 through a via 71, and connected to the sixth sub-active portion 116 through a via 72, thereby connecting the first electrode of the first transistor T1 and the gate of the driving transistor DT.

[0065] In this exemplary embodiment, Fig.13 As shown, the second active portion may further include a seventh sub-active portion 127, and the seventh sub-active portion 127 may be located on the side of the orthographic projection of the third sub-active portion 123 on the substrate away from the orthographic projection of the fourth sub-active portion 124 on the substrate. Fig.15 As shown, the second conductive layer may further include an eighth conductive portion 38, the orthographic projection of the eighth conductive portion 38 on the substrate may at least partially overlap with the orthographic projection of the seventh sub-active portion 127 on the substrate, and the eighth conductive portion 38 may be connected to the seventh sub-active portion 127 through a via 73. The fifth signal line 45 may be connected to the eighth conductive portion 38 through a via 74, thereby realizing that the read signal terminal is connected to the second electrode of the second transistor T2. It should be understood that in other exemplary embodiments, the fifth signal line 45 and the seventh sub-active portion 127 may also be directly connected through a via. Compared with the fifth signal line 45 and the seventh sub-active portion 127 being directly connected through a via, this exemplary embodiment transfers the seventh sub-active portion 127 located in the active layer and the fifth signal line 45 located in the third conductive layer through the eighth conductive portion 38 located in the second conductive layer, and the via 73 and the via 74 may have a lower depth, thereby improving the yield rate of the via connection.

[0066] like Fig.13 As shown, the first active portion may further include an eighth sub-active portion 118, the orthographic projection of the eighth sub-active portion 118 on the substrate substrate is located on a side of the orthographic projection of the second sub-active portion 112 on the substrate substrate away from the orthographic projection of the first sub-active portion on the substrate substrate. The third signal line 33 may be connected to the eighth sub-active portion 118 through a via 75 to connect Figure 1The second active portion may further include a ninth sub-active portion 129, the orthographic projection of the ninth sub-active portion 129 on the substrate substrate may be located on a side of the orthographic projection of the fifth sub-active portion 125 on the substrate substrate away from the orthographic projection of the fourth sub-active portion 124 on the substrate substrate. The fourth signal line 34 may be connected to the ninth sub-active portion 129 through the via 76 to connect Figure 1 The second electrode of the middle driving transistor DT and the first power supply terminal.

[0067] In this exemplary embodiment, Fig.12 As shown, the fingerprint recognition module may further include a fourth conductive layer and a fifth conductive layer, wherein the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate. Fig.17 , 18 As shown, Fig.17 for Fig.12 The structural layout of the fourth conductive layer in Fig.18 for Fig.12 The fourth conductive layer may further include a conductive portion 51, the orthographic projection of the conductive portion 51 on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion 41 on the base substrate, and the conductive portion 51 may be used to form a second electrode of the photodiode. Fig.12 As shown, the conductive portion 51 can be connected to the seventh conductive portion 37 through the via 78 to connect the first electrode of the photodiode and the gate of the driving transistor. The fifth conductive layer may include a signal line 61, the orthographic projection of the signal line 61 on the substrate is located on the side of the orthographic projection of the first conductive portion 41 on the substrate away from the orthographic projection of the fourth signal line 34 on the substrate, and the signal line 61 can be used to provide Figure 1 The bias voltage terminal in the photodiode, the signal line 61 can be connected to the conductive portion 51 through the via 77, thereby connecting the bias voltage terminal and the second electrode of the photodiode.

[0068] It should be understood that in other exemplary embodiments, the pixel sensing circuit in the fingerprint recognition module can also be other structures. For example, the first transistor, the second transistor, and the driving transistor can all be P-type transistors. For another example, the pixel sensing circuit can also be an internal compensation circuit.

[0069] like Fig.12 As shown, in the fingerprint recognition module, a blank area may be provided between the first transistor T1 and the second transistor T2 in the second direction Y, and other electrical components may be integrated in the blank area. For example, when the pixel sensing circuit is an internal compensation circuit, the pixel sensing circuit has more transistors, and the extra transistors may be arranged in the blank area.

[0070] In this exemplary embodiment, Fig. 20 As shown, Fig.12 The cross-sectional view along the AA dotted line in FIG. The fingerprint recognition module may also include a buffer layer 101, an insulating layer 102, a dielectric layer 103, a passivation layer 104, a flat layer 105, a passivation layer 106, a protective layer 107, a flat layer 108, a passivation layer 109, and a photoelectric functional layer 110. Among them, the substrate 0, the buffer layer 101, the active layer, the insulating layer 102, the first conductive layer, the dielectric layer 103, the second conductive layer, the passivation layer 104, the flat layer 105, the passivation layer 106, the third conductive layer, the photoelectric functional layer 110, the fourth conductive layer, the protective layer 107, the flat layer 108, the passivation layer 109, and the fifth conductive layer are stacked in sequence. Among them, the photoelectric functional layer 110 can be used to form a photodiode, and the photoelectric functional layer 110 may include a PIN stacked structure.

[0071] In this exemplary embodiment, the materials of the protective layer, the dielectric layer, and the passivation layer may be inorganic materials, such as at least one of silicon nitride, silicon oxide, and silicon oxynitride, or a combination thereof; or organic materials, such as transparent polyimide (CPI), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and the like. The material of the conductive layer may be at least one of copper, molybdenum, titanium, aluminum, nickel, silver, indium tin oxide (ITO), or a combination thereof, or an alloy material of the above materials, or a stack, such as a titanium / aluminum / titanium triple stack. The buffer layer may be made of inorganic materials, such as at least one of silicon nitride, silicon oxide, and silicon oxynitride, or a combination thereof. The material of the planar layer may be an organic material, such as transparent polyimide (CPI), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), a silicon-glass bonding structure (SOG), and the like. The material of the insulating layer may be an inorganic material, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The active layer may be formed of a low temperature polysilicon material or an indium gallium zinc oxide material. The fourth conductive layer may be formed of an indium tin oxide (ITO) material.

[0072] like Fig.21 , which is a cross-sectional view of another exemplary embodiment of the fingerprint recognition module disclosed herein. The fingerprint recognition module may also include a passivation layer 191 located on the side of the fifth conductive layer away from the base substrate, a light shielding layer 193 located on the side of the passivation layer 191 away from the base substrate, an insulating layer 192 located on the side of the light shielding layer 193 away from the base substrate, and a transparent conductive layer 194 located on the side of the insulating layer 192 away from the base substrate. The light shielding layer 193 may be used to shield some of the multiple photodiodes in the fingerprint recognition module.

[0073] This exemplary embodiment also provides a display panel, which includes the above-mentioned fingerprint recognition module.

[0074] like Fig. 22 , which is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel may further include: a substrate 201, a filter module 203, a collimating layer 204, and an array substrate 205. The fingerprint recognition module 202 is located on one side of the substrate 201; the filter module 203 is located on the side of the fingerprint recognition module 202 away from the substrate 201; the collimating layer 204 is located on the side of the filter module 203 away from the substrate; and the array substrate 205 is located on the side of the collimating layer 204 away from the substrate 201. There may be an air gap between the array substrate 205 and the collimating layer 204.

[0075] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered merely exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0076] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A fingerprint recognition module, characterized in that: The pixel sensing circuit includes a driving transistor, a first transistor, a second transistor, and a photodiode, wherein the first electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the first electrode of the driving transistor, and the first electrode of the photodiode is connected to the gate of the driving transistor. The fingerprint recognition module also includes: substrate substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer includes: A first signal line extending along a first direction in an orthographic projection of the substrate and connected to a gate of the first transistor; A second signal line, extending along the first direction in the orthogonal projection of the substrate, and the second signal line is spaced apart from the first signal line in the orthogonal projection of the substrate in the second direction, the first direction intersects the second direction, and the second signal line is connected to the gate of the second transistor; The third conductive layer is located on a side of the first conductive layer away from the substrate, and the third conductive layer includes: The first conductive portion is used to form the first electrode of the photodiode, the orthographic projection of the first conductive portion on the substrate does not intersect with the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate, and the orthographic projection of the first conductive portion on the substrate is located between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.

2. The fingerprint recognition module according to claim 1, characterized in that: The fingerprint recognition module also includes: A second conductive layer is located between the first conductive layer and the third conductive layer, and the second conductive layer includes: A third signal line, the orthographic projection of the substrate extending along the second direction, the third signal line being used to connect the second electrode of the first transistor; a fourth signal line, the orthographic projection of the substrate extending along the second direction, the fourth signal line being used to connect the second electrode of the driving transistor; The third conductive layer further comprises: A fifth signal line extends along the second direction in an orthographic projection of the substrate, and the fifth signal line is used to connect the second electrode of the second transistor.

3. The fingerprint recognition module according to claim 2, characterized in that: The orthographic projection of the fourth signal line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third signal line on the base substrate.

4. The fingerprint recognition module according to claim 3, characterized in that: The orthographic projection of the fifth signal line on the base substrate is located between the orthographic projection of the third signal line on the base substrate and the orthographic projection of the fourth signal line on the base substrate.

5. The fingerprint recognition module according to claim 3, characterized in that: The fingerprint recognition module further includes an active layer, which is located between the base substrate and the first conductive layer, and includes: A first active portion, the orthographic projection of which on the substrate is located between the orthographic projection of the third signal line on the substrate and the orthographic projection of the fourth signal line on the substrate, and a portion of the first active portion is used to form a channel region of the first transistor; The second active portion has an orthographic projection on the substrate between the orthographic projection of the third signal line and the orthographic projection of the fourth signal line on the substrate, and part of the second active portion is used to form the channel regions of the second transistor and the driving transistor.

6. The fingerprint recognition module according to claim 5, characterized in that: The orthographic projection of the first active portion on the base substrate is located between the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate; The orthographic projection of the second active portion on the base substrate is located between the orthographic projection of the first active portion on the base substrate and the orthographic projection of the second signal line on the base substrate.

7. The fingerprint recognition module according to claim 5, characterized in that: The first active portion comprises: a first sub-active portion, used to form a first channel region of the first transistor; A second sub-active portion, used to form a second channel region of the first transistor, wherein an orthographic projection of the first sub-active portion on the substrate and an orthographic projection of the second sub-active portion on the substrate are spaced apart in the first direction; The first conductive layer further comprises: a second conductive portion, connected to the first signal line, the orthographic projection of the second conductive portion on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate, and the second conductive portion is used to form a first gate of the first transistor; A third conductive portion is connected to the first signal line, the orthographic projection of the third conductive portion on the base substrate covers the orthographic projection of the second sub-active portion on the base substrate, and the third conductive portion is used to form a second gate of the first transistor.

8. The fingerprint recognition module according to claim 7, characterized in that: The second active portion includes: a third sub-active portion, used to form a first channel region of the second transistor; a fourth sub-active portion, used to form a second channel region of the second transistor; a fifth sub-active portion, used to form a channel region of the driving transistor, wherein the orthographic projection of the third sub-active portion on the substrate, the orthographic projection of the fourth sub-active portion on the substrate, and the orthographic projection of the fifth sub-active portion on the substrate are sequentially spaced apart in the first direction; and the orthographic projection of the fifth sub-active portion on the base substrate is located between the orthographic projection of the fourth signal line on the base substrate and the orthographic projection of the fourth sub-active portion on the base substrate; The first conductive layer further comprises: a fourth conductive portion connected to the second signal line, wherein an orthographic projection of the fourth conductive portion on the base substrate covers an orthographic projection of the third sub-active portion on the base substrate, and the fourth conductive portion is used to form a first gate of the second transistor; a fifth conductive portion connected to the second signal line, wherein an orthographic projection of the fifth conductive portion on the base substrate covers an orthographic projection of the fourth sub-active portion on the base substrate, and the fifth conductive portion is used to form a second gate of the second transistor; The sixth conductive portion has an orthographic projection on the base substrate covering the orthographic projection of the fifth sub-active portion on the base substrate, and the sixth conductive portion is used to form a gate of the driving transistor.

9. The fingerprint recognition module according to claim 8, characterized in that: The first active portion further comprises: The sixth sub-active portion is located on a side of the orthogonal projection of the first sub-active portion on the substrate substrate away from the orthogonal projection of the second sub-active portion on the substrate substrate; The second conductive layer further comprises: A seventh conductive portion, located between the orthographic projection of the third signal line on the base substrate and the orthographic projection of the fourth signal line on the base substrate in the orthographic projection of the base substrate; The seventh conductive portion is connected to the sixth conductive portion and the sixth sub-active portion through vias respectively.

10. The fingerprint recognition module according to claim 8, characterized in that: The second active portion further comprises: The seventh sub-active portion is located on a side of the orthogonal projection of the third sub-active portion on the substrate substrate away from the orthogonal projection of the fourth sub-active portion on the substrate substrate; The second conductive layer further comprises: an eighth conductive portion, the orthographic projection of which on the base substrate at least partially overlaps with the orthographic projection of the seventh sub-active portion on the base substrate, and the eighth conductive portion is connected to the seventh sub-active portion through a via hole; Wherein, the fifth signal line is connected to the eighth conductive part through a via hole.

11. The fingerprint recognition module according to claim 8, characterized in that: The area of ​​the first conductive part projected on the base substrate is 13-16 times the area of ​​the sixth conductive part projected on the base substrate.

12. A display panel, characterized in that: include: The fingerprint recognition module according to any one of claims 1 to 11.

13. The display panel according to claim 12, characterized in that: The display panel further includes: A substrate, wherein the fingerprint recognition module is located on one side of the substrate; A filter module, located on a side of the fingerprint recognition module away from the substrate; A collimating layer, located on a side of the filter module facing away from the substrate; The array substrate is located on a side of the alignment layer away from the substrate.

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