A writing depth test system and method for storage chip

Abstract

The present invention discloses a writing depth test system for a memory chip, comprising: a voltage regulating circuit, the input end of which is connected to the first output end of a main control chip, the first output end of which is connected to the first input end of a level conversion chip, and the second output end of which is connected to the first input end of a memory chip to be tested; the second input end of the level conversion chip is connected to the second output end of the main control chip, the first output end of which is connected to the second input end of the memory chip, and the third input end of which is connected to the output end of the memory chip; a digital analog converter, the input end of which is connected to the third output end of the main control chip, and the output end of which is connected to the third input end of the memory chip. This invention solves the problem that traditional ATE cannot be operated offline and has poor convenience, adopts dual power supplies and high-precision DAC, realizes VT board-level testing in an offline state, reduces testing costs, facilitates testing operations, and meets the flexible application requirements of various application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a writing depth testing system and method for a storage chip. Background Art

[0002] For the FLASH memory chips and EEPROM memory chips developed by PUYA Semiconductor, the traditional write depth (VT margin) test requires the use of an integrated circuit automatic test machine (ATE) machine.

[0003] When testing the write depth of FLASH memory chips and EEPROM memory chips developed by PUYA, in addition to completing laboratory tests, on-site tests are also required at the test factory and by field technical support engineers (FAE). However, currently a dedicated ATE machine is required, which is expensive, large, inconvenient, not easy to carry, and cannot be operated offline, and cannot meet the needs of on-site applications. Summary of the invention

[0004] The purpose of the present invention is to provide a write depth test system and method for storage chips. This system and method aims to solve the problem that traditional ATE cannot be operated offline and has poor convenience. It adopts dual power supplies and high-precision DAC to realize VT board-level testing in an offline state, reduce test costs, facilitate test operations, and meet the flexible application of various application scenarios.

[0005] To achieve the above object, the present invention provides a write depth test system for a memory chip, comprising:

[0006] Main control chip, generating test digital signals;

[0007] A voltage regulating circuit, wherein the input end is connected to the first output end of the main control chip, the first output end is connected to the first input end of a level conversion chip, and the second output end is connected to the first input end of the memory chip to be tested, and provides a first voltage and a second voltage to the level conversion chip and the memory chip respectively according to the test digital signal;

[0008] The second input end of the level conversion chip is connected to the second output end of the main control chip, and the first output end of the level conversion chip is connected to the second input end of the memory chip. The test digital signal is level-converted according to the first voltage to obtain a processed test digital signal, and the processed test digital signal is applied to the memory chip together with the second voltage.

[0009] A digital-to-analog converter, whose input end is connected to the third output end of the main control chip and whose output end is connected to the third input end of the storage chip, performs digital-to-analog conversion on the test digital signal to obtain a test analog signal;

[0010] The third input terminal of the level conversion chip is connected to the output terminal of the memory chip, and the memory chip is tested under the joint action of the test analog signal, the second voltage and the processed test digital signal to obtain test data of the memory chip and complete the write depth test of the memory chip.

[0011] Most preferably, the write depth test system also includes a host computer, an output end of which is connected to the first input end of the main control chip, for the test personnel to manually input the test instruction information of the write depth test and transmit it to the main control chip to generate a test digital signal.

[0012] Most preferably, the second output terminal of the level conversion chip is connected to the input terminal of the host computer through the main control chip, so as to transmit the test data back to the host computer through the main control chip in real time for the tester to read in real time.

[0013] Most preferably, the processed test digital signal is a variable voltage in different voltage ranges.

[0014] Most preferably, the size of the writing depth test system is 15 cm x 10 cm.

[0015] The present invention also provides a write depth test method for a memory chip. The write depth test method is implemented based on the above-mentioned write depth test system for a memory chip. The write depth test method comprises the following steps:

[0016] Step 1: The tester inputs the test instruction information of the write depth test and transmits it to the main control chip to generate a test digital signal; the test digital signal is divided into three paths;

[0017] Step 2: transmitting the first test digital signal to the voltage regulating circuit, and the voltage regulating circuit provides a first voltage and a second voltage to the level conversion chip and the memory chip to be tested respectively according to the first test digital signal;

[0018] Step 3: Transmitting the second test digital signal to the level conversion chip, the level conversion chip performs level conversion on the second test digital signal according to the first voltage, obtains a processed test digital signal, and applies it together with the second voltage to the storage chip;

[0019] Step 4: Transmit the third test digital signal to the digital-to-analog converter for digital-to-analog conversion to obtain a test analog signal;

[0020] Step 5: Test the memory chip under the combined action of the test analog signal second voltage and the processed test digital signal to obtain test data, and complete the write depth test of the memory chip to be tested.

[0021] Most preferably, the test instruction information is input in real time via the host computer.

[0022] Most preferably, the test data is also transmitted back to the host computer in real time through the main control chip for real-time reading by the tester.

[0023] The invention solves the problem that traditional ATE cannot be operated offline and has poor convenience. By adopting dual power supplies and high-precision DAC, VT board-level testing in an offline state is realized, which reduces the testing cost, facilitates the testing operation, and satisfies the flexible application in various application scenarios.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The write depth test system provided by the present invention solves the problem that traditional ATE cannot be operated offline and has poor convenience. It adopts dual power supplies and high-precision DAC to realize VT board-level testing in an offline state, reduces testing costs, facilitates testing operations, and meets the flexible use of various application scenarios.

[0026] 2. The write depth test system provided by the present invention adopts a highly integrated board-level design, which achieves miniaturization and portability, and reduces the test cost.

[0027] 3. The write depth test system provided by the present invention adopts a high-precision DAC to realize operation in both online and offline states. It is easy to operate, does not require programming and sample importing, realizes fast test operation, facilitates test operation, and meets the flexible use of various application scenarios.

[0028] 4. The write depth test system provided by the present invention adopts the working function of the voltage regulating circuit and the level conversion chip, satisfies the wide voltage test, and realizes high-speed application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a write depth test system provided by the present invention;

[0030] Figure 2 This is a flow chart of the write depth testing method provided by the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings. These embodiments are only used to illustrate the present invention and are not intended to limit the protection scope of the present invention.

[0032] The present invention provides a write depth test system for a memory chip. The write depth test system adopts a highly integrated board-level design. In this embodiment, the size of the write depth test system is 15 cm×10 cm. Figure 1As shown, it includes: a main control chip 1, a host computer 2, a voltage regulation circuit 3, a level conversion chip 4 and a digital-to-analog converter (DAC) 5.

[0033] Among them, the tester inputs the test instruction information of the write depth test in real time through the host computer 2; the first input end of the main control chip 1 is connected to the output end of the host computer 2, and generates a test digital signal according to the test instruction information of the write depth test generated by the host computer 2.

[0034] The input end of the voltage regulating circuit 3 is connected to the first output end of the main control chip 1, the first output end of the voltage regulating circuit 3 is connected to the first input end of the level conversion chip 4, and the second output end of the voltage regulating circuit 3 is connected to the test pin of the first input end of the storage chip K to be tested. According to the test digital signal, the first voltage and the second voltage are provided to the level conversion chip 4 and the storage chip K to be tested respectively.

[0035] The second input end of the level conversion chip 4 is connected to the second output end of the main control chip 1, and the first output end is connected to the test pin of the second input end of the storage chip K to be tested. According to the first voltage output by the voltage regulating circuit 3, the test digital signal is level-converted to obtain a processed test digital signal; wherein the processed test digital signal is a test digital signal in a different voltage range.

[0036] The processed test digital signals of different voltage ranges and the second voltage output by the voltage regulating circuit 3 are applied together to the memory chip K to be tested to broaden the testable voltage range of the write depth test system, meet the test requirements under different voltages, and ensure level compatibility under different voltages.

[0037] In this embodiment, the communication rate of the processed test digital signal can reach 100Mhz at a voltage of 1.2V, and the communication rate of the processed test digital signal can reach 140Mhz at a voltage of 3.6V.

[0038] The input end of the digital-to-analog converter 5 is connected to the third output end of the main control chip 1, and the output end of the digital-to-analog converter 5 is connected to the test pin of the third input end of the memory chip K to be tested, and the test digital signal is converted into a digital-to-analog signal to obtain a test analog signal.

[0039] The third input terminal of the level conversion chip 4 is connected to the output terminal of the memory chip K to be tested, and the test analog signal, the test digital signal processed in different voltage ranges and the data stored inside the memory chip K to be tested under the joint application of the second voltage are tested to obtain the test data of the memory chip K under different applied voltages; the second output terminal of the level conversion chip 4 is connected to the second input terminal of the main control chip 1, and the test data of the memory chip K under different applied voltages are transmitted back to the main control chip 1; the fourth output terminal of the main control chip 1 is connected to the input terminal of the host computer 2, and the test data of the memory chip K under different applied voltages are transmitted back to the host computer 2 in real time for the test personnel to read in real time.

[0040] In this embodiment, the digital-to-analog converter is a high-precision 24-bit DAC, which effectively improves the test accuracy of the write depth test system.

[0041] The present invention also provides a write depth test method for a memory chip, characterized in that the write depth test method is implemented based on the above-mentioned write depth test system for a memory chip, such as Figure 2 As shown, the write depth test method includes the following steps:

[0042] Step 1: The tester inputs the test instruction information of the write depth test, and transmits the test instruction information of the write depth test to the main control chip 1 to generate a test digital signal; the test digital signal generated by the main control chip 1 is divided into three paths; among which, the test instruction information of the write depth test is input by the tester in real time through the host computer 2.

[0043] Step 2: Transmit the first test digital signal to the voltage regulating circuit 3, and the voltage regulating circuit 3 provides the first voltage and the second voltage to the level conversion chip 4 and the memory chip K to be tested respectively according to the first test digital signal.

[0044] Step 3: Transmit the second test digital signal to the level conversion chip 4, and the level conversion chip 4 performs level conversion on the second test digital signal according to the first voltage output by the voltage regulation circuit 3 to obtain processed test digital signals in different voltage ranges.

[0045] The processed test digital signals of different voltage ranges and the second voltage output by the voltage regulating circuit 3 are applied to the memory chip K to be tested, so as to broaden the testable voltage range of the write depth test system, meet the test requirements under different voltages, and ensure level compatibility under different voltages;

[0046] Step 4: Transmit the third test digital signal to the digital-to-analog converter 5 for digital-to-analog conversion to obtain a test analog signal.

[0047] Step 5: Test the data stored in the memory chip K to be tested under the combined application of the test analog signal, the processed test digital signal in different voltage ranges and the second voltage to obtain test data of the memory chip K under different applied voltages.

[0048] The test data of the memory chip K under different applied voltages are transmitted back to the host computer 2 in real time through the main control chip 1 for real-time reading by the tester, thereby completing the write depth test of the memory chip K to be tested.

[0049] In this embodiment, the write depth test system reads the voltage at the test pin (TP) end of the memory chip K at the critical point of the verification data (Pass / Fail, P / F); the voltage is added through the TP end, the full-chip data is read and verified, and the critical voltage value of the P / F critical point is found. The critical voltage value reflects the write depth of the memory chip.

[0050] Working principle of the present invention:

[0051] The test personnel input the test instruction information of the write depth test in real time through the host computer, and transmit the test instruction information of the write depth test to the main control chip to generate a test digital signal; the test digital signal generated by the main control chip is divided into three paths; the first test digital signal is transmitted to the voltage regulating circuit, and the voltage regulating circuit provides the first voltage and the second voltage to the level conversion chip and the storage chip to be tested respectively according to the first test digital signal; the second test digital signal is transmitted to the level conversion chip, and the level conversion chip performs level conversion on the second test digital signal according to the first voltage output by the voltage regulating circuit to obtain different voltage ranges. A processed test digital signal; applying the processed test digital signal of different voltage ranges and the second voltage together on the memory chip to be tested; transmitting the third test digital signal to the digital-to-analog converter for digital-to-analog conversion to obtain a test analog signal; testing the data stored inside the memory chip to be tested under the combined application of the test analog signal, the processed test digital signal of different voltage ranges and the second voltage to obtain test data of the memory chip under different applied voltages; transmitting the test data back to the host computer in real time through the main control chip for real-time reading by the tester, thereby completing the write depth test of the memory chip to be tested.

[0052] In summary, the present invention provides a write depth test system and method for storage chips, which solves the problem that traditional ATE cannot be operated offline and has poor convenience. It adopts dual power supplies and high-precision DAC to realize VT board-level testing in an offline state, reduces testing costs, facilitates testing operations, and satisfies flexible use in various application scenarios.

[0053] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A write depth test system for a memory chip, characterized in that: include: Main control chip, generating test digital signals; A voltage regulating circuit, wherein the input end is connected to the first output end of the main control chip, the first output end is connected to the first input end of a level conversion chip, and the second output end is connected to the first input end of the memory chip to be tested, and according to the test digital signal, the first voltage and the second voltage are respectively provided to the level conversion chip and the memory chip; The second input end of the level conversion chip is connected to the second output end of the main control chip, and the first output end of the level conversion chip is connected to the second input end of the storage chip. According to the first voltage, the test digital signal is level-converted to obtain a processed test digital signal, and the processed test digital signal is applied to the storage chip together with the second voltage; A digital-to-analog converter, whose input end is connected to the third output end of the main control chip, whose output end is connected to the third input end of the storage chip, performs digital-to-analog conversion on the test digital signal to obtain a test analog signal; The third input terminal of the level conversion chip is connected to the output terminal of the storage chip, and the storage chip is tested under the joint application of the test analog signal, the second voltage and the processed test digital signal to obtain test data and complete the write depth test of the storage chip.

2. The write depth test system for a memory chip according to claim 1, wherein: The write depth test system also includes a host computer, an output end of which is connected to the first input end of the main control chip, and is used for test personnel to manually input test instruction information of the write depth test and transmit it to the main control chip to generate the test digital signal.

3. The write depth test system for a memory chip as claimed in claim 2, characterized in that: The second output end of the level conversion chip is connected to the input end of the host computer through the main control chip, and is used to transmit the test data back to the host computer through the main control chip in real time for the tester to read in real time.

4. The write depth test system for a memory chip according to claim 1, characterized in that: The processed test digital signal is a variable voltage in different voltage ranges.

5. The write depth test system for a memory chip as claimed in claim 1, characterized in that: The size of the writing depth test system is 15cm×10cm.

6. A write depth test method for a storage chip, characterized in that: The write depth test method is implemented based on the write depth test system for a memory chip according to any one of claims 1 to 5, and the write depth test method comprises the following steps: Step 1: The tester inputs the test instruction information of the write depth test and transmits it to the main control chip to generate a test digital signal; the test digital signal is divided into three paths; Step 2: transmitting the first test digital signal to the voltage regulating circuit, and the voltage regulating circuit provides a first voltage and a second voltage to the level conversion chip and the memory chip to be tested respectively according to the first test digital signal; Step 3: transmitting the second test digital signal to the level conversion chip, the level conversion chip performs level conversion on the second test digital signal according to the first voltage, obtains a processed test digital signal, and applies the processed test digital signal together with the second voltage to the storage chip; Step 4: Transmit the third test digital signal to the digital-to-analog converter for digital-to-analog conversion to obtain a test analog signal; Step 5: Testing the memory chip under the combined action of the test analog signal, the second voltage and the processed test digital signal to obtain test data and complete the write depth test of the memory chip to be tested.

7. The write depth test method for a memory chip according to claim 6, characterized in that: The test instruction information is input in real time through the host computer.

8. The write depth test method for a memory chip according to claim 6, wherein: The test data is also transmitted back to the host computer in real time through the main control chip for real-time reading by the tester.

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