FINFET doping structure

Abstract

An embodiment of the present invention provides a semiconductor device, comprising: a doped semiconductor material layer, disposed on a substrate; an undoped semiconductor material layer, disposed on the doped semiconductor material layer, the undoped semiconductor material layer comprising a top surface facing away from the substrate; a gate structure, disposed on the undoped semiconductor material layer, the gate structure comprising a gate electrode and a gate dielectric layer; a lightly doped drain (LDD) region, disposed in the substrate and directly interfacing with the undoped semiconductor material layer; and a sidewall spacer, disposed along the sidewall of the gate structure and extending to the top surface of the undoped semiconductor material layer, so that the sidewall spacer physically contacts the top surface of the undoped semiconductor material layer, the sidewall spacer being disposed on at least a portion of the lightly doped drain region.

Description

[0001] Divisional application

[0002] This application is a divisional application of the Chinese patent application numbered 201410770301.2 filed on December 15, 2014 and entitled “FINFET doping method and structure thereof”. Technical Field

[0003] The present invention relates generally to the field of semiconductors, and more particularly to FINFET devices. Background Art

[0004] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). These goals have been largely achieved by scaling down semiconductor IC sizes (e.g., minimum feature sizes) and thereby improving production efficiency and reducing associated costs. However, this reduction has also introduced increased complexity into semiconductor manufacturing processes. Therefore, the realization of continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technology.

[0005] Recently, efforts have been made to introduce multi-gate devices to improve gate control through gate-channel coupling, reduce cutoff current, and reduce short channel effect (SCE). One such multi-gate device that has been introduced is the fin field effect transistor (FinFET). The name of the FinFET comes from the fin-shaped structure extending from the substrate, which is formed on the substrate and used to form the FET channel. FinFETs are compatible with traditional complementary metal oxide semiconductor (CMOS) processes, and their three-dimensional structure allows them to be strongly scaled down while maintaining gate control and mitigating SCE. However, ion implantation of dopants through FinFET devices (as performed by current manufacturing methods) directly contributes to the formation of defects in the FinFET channel region and the introduction of impurities. Such channel defects and impurities can cause scattering of carriers flowing through the FinFET channel, thereby reducing channel mobility and adversely affecting device performance. Injection of dopants through the FinFET fins can also produce non-uniform doping distributions, which can cause changes in FinFET device parameters and some other problems. Therefore, the prior art is not completely satisfactory in all aspects. Summary of the invention

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate having a fin extending from the substrate; forming an in-situ doped layer on the fin; and after forming the in-situ doped layer on the fin, forming an undoped layer on the in-situ doped layer.

[0007] Preferably, forming an in-situ doped layer on the fin further comprises epitaxially growing an in-situ doped well region on the fin.

[0008] Preferably, forming the undoped layer on the in-situ doped layer further comprises epitaxially growing an undoped channel region on the in-situ doped layer.

[0009] Preferably, the thickness of the in-situ doping layer is between about 10 nm and 40 nm.

[0010] Preferably, the thickness of the undoped layer is between about 10 nm and 40 nm.

[0011] Preferably, the dopant concentration of the undoped layer is less than about 1×10 17 cm -3 .

[0012] Preferably, the method further comprises: forming a source region and a drain region adjacent to the undoped channel region and located on both sides of the undoped channel region.

[0013] Preferably, the method also includes: depositing a dielectric layer above the substrate before forming the in-situ doping layer on the fin; and performing a first dielectric patterning step to expose a first fin extending from the substrate; wherein, forming the in-situ doping layer on the fin also includes: forming the in-situ doping layer on the exposed first fin; and forming an undoped layer on the in-situ doping layer also includes: forming an undoped layer on the in-situ doping layer formed on the exposed first fin.

[0014] Preferably, the method also includes: performing a second dielectric patterning step to expose a second fin extending from the substrate; wherein forming an in-situ doped layer on the fin also includes: forming an in-situ doped layer on the exposed second fin; and forming an undoped layer on the in-situ doped layer also includes: forming an undoped layer on the in-situ doped layer formed on the exposed second fin.

[0015] Preferably, the in-situ doping layer includes one of an N-type well region and a P-type well region.

[0016] According to another aspect of the present invention, a method is provided, comprising: providing a substrate, the substrate comprising a plurality of fins extending from the substrate; forming an isolation region that isolates each of the plurality of fins from each other; forming an in-situ doped N-well region on a first group of fins of the plurality of fins; and after forming the in-situ doped N-well region on the first group of fins, forming an undoped channel region on the in-situ doped N-well region.

[0017] Preferably, the method further comprises: forming an in-situ doped P-well region on a second group of fins of the plurality of fins; and after forming the in-situ doped P-well region on the second group of fins, forming an undoped channel region on the in-situ doped P-well region.

[0018] Preferably, the in-situ doped N-well region includes at least one dopant selected from the group consisting of arsenic, phosphorus and antimony.

[0019] Preferably, the in-situ doped P-well region includes at least one dopant selected from the group consisting of boron, aluminum, gallium and indium.

[0020] Preferably, the method further comprises: depositing a dielectric layer over the substrate before forming the in-situ doped N-well region on the first group of fins of the plurality of fins; and performing a dielectric patterning step to expose the first group of fins of the plurality of fins.

[0021] Preferably, the method further comprises: depositing a dielectric layer over the substrate before forming the in-situ doped P-well region on the second group of fins of the plurality of fins; and performing a dielectric patterning step to expose the second group of fins of the plurality of fins.

[0022] Preferably, the dopant concentration of the undoped channel region is less than about 1×10 17 cm -3 .

[0023] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate having a fin; an in-situ doped layer formed above the fin; an undoped layer formed above the in-situ doped layer; and a gate stack formed above the undoped layer; wherein the in-situ doped layer includes a well region; and the undoped layer includes a channel region.

[0024] Preferably, the thickness of the in-situ doped layer and the undoped layer is between about 10 nm and 40 nm.

[0025] Preferably, the semiconductor device further comprises: a source region adjacent to the channel region and located on a first side of the channel region; and a drain region adjacent to the channel region and located on a second side of the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0027] Figure 1 is a flow chart of a method of manufacturing a FinFET device or a portion thereof according to one or more aspects of the present invention;

[0028] Figures 2 to 7 Shown according to Figure 1 isometric view of an embodiment of a device 200 having fins fabricated in accordance with one or more aspects of a method of; and

[0029] Figure 8 A perspective view of an embodiment of a device 200 is shown. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0032] It should also be noted that the present invention presents embodiments in the form of multi-gate transistors or fin-type multi-gate transistors referred to herein as FinFET devices. Such devices may include P-type metal oxide semiconductor FinFET devices or N-type metal oxide semiconductor FinFET devices. FinFET devices may be dual-gate devices, tri-gate devices, bulk devices, silicon-on-insulator (SOI) devices, and / or other structures. Those of ordinary skill in the art will recognize other examples of semiconductor devices that may benefit from various aspects of the present invention. For example, some embodiments described herein may also be applied to full-ring gate (GAA) devices, Omega-gate (Ω gate) devices, or Pi-gate (Π gate) devices.

[0033] Figure 1 A method 100 of semiconductor fabrication is shown, the method comprising fabricating a fin having a channel disposed on a substrate and free of dopants. As used herein, the term "dopant-free" material is used to describe a material having a dopant content from about 0 cm -3 To about 1×10 17 cm -3A material (e.g., a semiconductor material) having a non-intrinsic dopant concentration. As discussed below, the presence of dopants in the device channel can cause carrier scattering in the active device channel, which can significantly reduce device performance. As described below, a device (such as a FinFET device) having an undoped channel region that is substantially free of dopants and epitaxially grown can significantly improve device performance (e.g., increase the on-current of the device). As used herein, "dopant" or "non-intrinsic dopant" is used to describe impurities (e.g., B, P, As, etc.) that can be introduced into the semiconductor lattice in order to change the electrical properties of the semiconductor. For example, N-type impurities can be introduced into a semiconductor to form an N-type material, and P-type impurities can be introduced into a semiconductor to form a P-type material. It should be understood that method 100 includes steps that have the characteristics of a complementary metal oxide semiconductor (CMOS) technology process flow, and is therefore only briefly described herein. Additional steps may be implemented before, after, and / or during the method.

[0034] Figures 2 to 7 and Figure 8 According to Figure 1 Isometric and perspective views of an embodiment of a semiconductor device 200 at various stages of method 100 are provided. It should be understood that the various portions of the semiconductor device 200 may be manufactured using a complementary metal oxide semiconductor (CMOS) technology process flow, and therefore only some processes are briefly described herein. Furthermore, the semiconductor device 200 may include a plurality of other devices and components such as other types of devices (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, etc.), but are simplified to facilitate a better understanding of the inventive concepts of the present invention. In some embodiments, the semiconductor device 200 includes a plurality of semiconductor devices (e.g., transistors) that may be interconnected, including PFETs, NFETs, etc. Additionally, it should be noted that the process steps of method 100 (including reference Figures 2 to 8 Any description given is illustrative only and is not intended to be limiting beyond what is specifically recited in the following claims.

[0035] Method 100 begins at box 102, where a substrate is provided. In some embodiments, the substrate may be a semiconductor substrate such as a silicon substrate. The substrate may include multiple layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. As is known in the art, depending on design requirements, the substrate may include multiple doping structures. The substrate may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, the substrate may include a compound semiconductor and / or an alloy semiconductor. Moreover, the substrate may optionally include an epitaxial layer (epi layer), the substrate may be strained to enhance performance, the substrate may include a silicon-on-insulator (SOI) structure, and / or the substrate may have other suitable enhancement features.

[0036] In various embodiments, the substrate includes a plurality of fins extending from the substrate. As with the substrate, the fins may include: silicon or another element semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or a combination thereof. The fins may be manufactured using a suitable process including a lithography and etching process. The lithography process may include: forming a photoresist layer (resist) on a substrate (e.g., on a silicon layer), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a masking element including the photoresist. In some embodiments, patterning the photoresist to form a masking element may be implemented using an electron beam (e-beam) lithography process. Then, while the etching process forms recesses in the silicon layer, the masking element may be used to protect regions of the substrate, thereby forming an extended fin. The recesses may be etched using dry etching (eg, reactive ion etching), wet etching, and / or other suitable processes.Many other embodiments of methods of forming fins on a substrate may also be used.

[0037] In an embodiment, the channel of the device will be formed in a first fin or a first group of fins (e.g., a channel of an N-type field effect transistor (NFET)). Such a fin or a group of fins may be referred to as an N-type fin in the present invention. Moreover, as described below, an N-type fin or an N-type fin group may include a P-type well. In an embodiment, a second fin or a second group of fins is associated with a p-type device (e.g., including a channel of a P-type FET or PFET). Such a fin or a group of fins may be referred to as a P-type fin in the present invention. Moreover, as described below, a P-type fin or a P-type fin may include an N-type well.

[0038] Reference Figure 2In an example, a FinFET device 200 is shown. The FinFET device 200 includes one or more fin-based, multi-gate field effect transistors (FETs). The FinFET device 200 includes a substrate 202, a plurality of fin elements 204 extending from the substrate 202, and an isolation region 206. In some embodiments, the isolation region 206 may include one or more shallow trench isolation (STI) features. As described above, the plurality of fin elements 204 may be patterned by photolithography or electron beam lithography, followed by dry etching (e.g., RIE), wet etching, or other suitable process etching. The etching process defines a plurality of fins 204 extending from the substrate 202 and trenches disposed between the plurality of fins 204. In some embodiments, a dielectric is deposited over the substrate 202, thereby filling the trenches with the dielectric and forming the isolation region 206. In some embodiments, the dielectric used to form the isolation region 206 includes SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, other suitable materials, combinations thereof, and / or other suitable materials known in the art. The dielectric used to form the isolation region 206 can be deposited by CVD, ALD, PVD or other suitable processes. In some embodiments, the dielectric forming the isolation region 206 is annealed to improve the quality of the dielectric. In some embodiments, field oxides, LOCOS components and / or other suitable isolation components can be implemented on and / or within the substrate. However, other embodiments are possible. For example, in some embodiments, the isolation region 206 may include a multilayer structure, for example, with one or more liner layers.

[0039] like Figure 2 As shown in the example of , each of the plurality of fin elements 204 may include a dielectric 208 formed above the fin element 204. In some embodiments, the dielectric 208 includes a first dielectric layer formed above the fin element 204 and a second dielectric layer formed above the first dielectric layer. In some embodiments, the first dielectric layer includes a pad oxide layer (e.g., SiO2) that can be used as a buffer layer between adjacent layers. In some embodiments, the first dielectric layer includes a thermally grown oxide, a CVD deposited oxide, and / or an ALD deposited oxide. For example, the thickness of the first dielectric layer may be between about 5 nm and about 40 nm. In some embodiments, the second dielectric layer includes a pad nitride layer (e.g., Si3N4). The second dielectric layer may be deposited by CVD or other suitable techniques, and in some instances, the thickness of the second dielectric layer may be between about 20 nm and about 160 nm.

[0040] The method 100 then proceeds to block 104 where the isolation region 206 is thinned and planarized, for example, by a CMP process. Figure 3 , shows an example of block 104. Specifically, Figure 3 The example of FIG. 2 shows the device 200 at an intermediate processing stage, wherein a CMP process has been performed to remove excess dielectric material (for forming the isolation region 206) and planarize the top surface of the semiconductor device 200. In some embodiments, the isolation region 206 is configured to isolate each fin active region (e.g., fin 204). In some embodiments, the isolation region 206 between each fin 204 may include a multi-layer structure, for example, with one or more liner layers.

[0041] The method 100 then proceeds to block 106 where the isolation region is recessed. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and / or a combination thereof. For example, the recessing process may include a dry plasma-free process using a reactive gas, a reactive gas combination such as HF+NH3, NF3+NH3, and / or other suitable reactive gases. In some embodiments, the recessing process may include a dry plasma-free process using a reactive gas such as HF+NH3, NF3+NH3, and / or other suitable reactive gases. A dry plasma-free recess process is performed using a gas chemical etching system (available from Tokyo Electron Co., Ltd., Tokyo, Japan). A dry plasma-free recess process is performed using an ATTACH system (available from Applied Materials, Inc., Santa Clara, California). In some examples, the recess process can include a wet etch performed using a dilute mixture of HF (e.g., 49% HF in H2O by weight) and deionized (DI) H2O, wherein the HF:H2O ratio is about 1:50 or about 1:100. Figure 4 In an example, the isolation region 206 around the fin 204 is recessed to laterally expose the upper portion 204A. In some embodiments, the recess depth is controlled (e.g., by controlling the etching time) to produce a desired height 'H' of the exposed upper portion 204A. In an embodiment, the exposed upper portion 204A of the fin may include at least a portion of the dielectric 208 formed above the fin element 204.

[0042] The method 100 then proceeds to block 108 where the dielectric 208 formed over the fin element 204 is removed. In some embodiments, the removal of the dielectric 208 includes removal of a pad nitride. In some embodiments, the removal of the dielectric 208 includes removal of a pad nitride and a pad oxide. The removal of the dielectric 208 (including one or both of the pad nitride and the pad oxide) may be performed using a suitable etching process (e.g., dry etching or wet etching). In some embodiments, a CMP process may be performed to remove the dielectric 208 (including one or both of the pad nitride and the pad oxide) and planarize the top surface of the semiconductor device 200. As an example of block 108, Figure 5 The semiconductor device 200 is shown wherein the dielectric 208 has been removed from the top of each fin element 204 , thereby exposing the underlying fin element 204 .

[0043] In the existing semiconductor process flow, after removing the pad nitride and before removing the pad oxide, an ion implantation process is used and a suitable N-type or P-type dopant is used to implement well implantation. Optionally, in the existing process flow, after removing the dielectric 208, an oxide layer can be regrown above the fin element 204, followed by well implantation by an ion implantation process. In some embodiments, the fin element 204 includes N-type and P-type fins, wherein each N-type fin and P-type fin are implemented using process steps, respectively. For example, in some embodiments, the regrown oxide can be used as a masking layer, and the masking layer can be patterned to expose one fin type (N-type or P-type) while the other fin type is implanted. In some embodiments, other layers can be used as masking layers, such as resists, nitrides, etc. For example, the N-type dopant can include arsenic, phosphorus, antimony, or other N-type donor materials. In other examples, the P-type dopant can include boron, aluminum, gallium, indium, or other P-type acceptor materials. Traditionally, N-type or P-type dopants can be used to implement anti-punch-through (APT) ion implantation through the fin 204. In some examples, other ion implantation processes may also be performed, such as threshold voltage (V t ) adjustment injection, halo injection or other suitable injection.

[0044] Although such ion implantation methods are commonly used in existing semiconductor process flows, there are some disadvantages. For example, it is known that the energy ion beam used in the ion implantation process will damage the substrate material implanted or passed by the ion beam. In the above example, the ion implantation process through the fin element 204 can cause damage to the fin element 204, including damage to the FinFET channel region, which can cause carrier scattering and thus reduce device performance. Although high temperature annealing can be used to try to remove such defects (and for dopant activation), it is impossible to completely remove all defects introduced by ion implantation, so the substrate (or fin element 204) may not be completely restored to the state before ion implantation. In addition, the ion implantation process can produce non-uniform doping distribution. In some examples, implanting dopants through the fin element 204 can produce a non-uniform doping distribution including dopants distributed in the FinFET channel region. As is known in the art, due to ionized impurity scattering, an increase in doping concentration in the device channel can cause a decrease in device mobility. Therefore, due to the non-uniform ion implantation doping distribution, the ion implantation process causes device performance degradation by, for example, ion implantation damage and unwanted channel dopants.

[0045] Embodiments of the present invention provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all advantages need to be discussed herein, and no particular advantage is required by all embodiments. For example, the embodiments discussed herein include methods and structures for avoiding degradation (including defect formation and channel impurity introduction) of semiconductor devices that may occur due to ion implantation processes. In some embodiments, an in-situ doped epitaxial growth layer is used instead of an ion implantation process to form a device well region (N well or P well), thereby avoiding such degradation caused by ion implantation. In some embodiments, an epitaxially grown undoped layer is formed above the in-situ doped epitaxial growth layer. The epitaxially grown undoped layer is used as an active device channel, and because the epitaxially grown undoped layer is substantially free of dopants, carrier channel scattering is reduced, thereby improving device mobility and drive current. In various embodiments, the undoped layer (i.e., the active device channel) has a thickness of less than about 1×10 17 cm -3 In some embodiments, the thickness of the in-situ doped layer and the undoped layer is between about 10 nm and 40 nm. As described below, the methods and structures described herein can be applied to NFET or PFET devices. In addition, although the discussion herein is primarily directed to FinFET devices, it will be understood by those skilled in the art that the methods and structures described herein can be equally applicable to other types of devices without departing from the scope of the present invention.

[0046] Returning to method 100, method 100 proceeds to block 110 where a doped layer is grown. In some embodiments, the doped layer includes a doped well grown by in-situ doping during an epitaxial growth process as discussed below. For example, Figure 5 As shown, after removing the dielectric 208, an oxide layer may be regrown over the fin structure 204. In some embodiments, the oxide layer includes a silicon dioxide (SiO2) layer deposited over the fin element 204. Thereafter, a first photolithography (light) step is performed to pattern the oxide layer (e.g., SiO2 layer) to expose a first set of fins in the fin element 204 that will be formed as an N-type or P-type FinFET, while a second set of fins in the fin element 204 is still masked by the oxide layer. For example, the first photolithography step may include an N-well or P-well photolithography step. In some embodiments, the first photolithography step may include: forming a photoresist layer (resist) over the substrate, exposing the photoresist to a pattern (e.g., defined by an N-well or P-well mask), performing a post-exposure bake process, and developing the photoresist to form a masking element including the photoresist. In some embodiments, the exposed oxide may be etched after photoresist development to expose a first set of fins to be formed as N-type or P-type FinFETs in fin element 204 , corresponding to the mask (N-well mask or P-well mask) used for the first photolithography step.

[0047] As an example of box 110, a doped well is formed by one or more epitaxial growth processes. In various embodiments, the epitaxial growth process may include a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the doped well may be grown above the first set of fins exposed in the fin element 204 by a first photolithography step and subsequent etching. In addition, the doped well is in-situ doped during the epitaxial growth process. In some embodiments, the epitaxially grown doped well includes the same material as the substrate 202. In some embodiments, the epitaxially grown doped well includes a material different from the substrate 202. In various embodiments, the epitaxially grown doped well may include: silicon, germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In addition, in various embodiments and depending on the type of well to be formed (N-well or P-well), the epitaxially grown doped well can be in-situ doped with N-type dopants such as arsenic, phosphorus, antimony or other N-type dopants, or can be in-situ doped with P-type dopants such as boron, aluminum, gallium, indium or other P-type dopants. As just one example, the epitaxially grown Si can be in-situ doped with boron for P-well growth and subsequent NFET formation. In another example, the epitaxially grown Si can be in-situ doped with phosphorus for N-well growth and subsequent PFET formation. In some embodiments, the thickness of the epitaxially grown doped well is in the range of about 10nm to 40nm. Moreover, since the N-well or P-well is in-situ doped during the epitaxial growth process, the dopant distribution within the N-well or P-well is substantially uniform throughout the well. In various embodiments, the epitaxially grown doped well (rather than the ion implantation process discussed above) is used to form an in-situ doped APT layer, an in-situ doped threshold voltage (V t ) adjustment layer, an in-situ doped halo layer, or other suitable in-situ doped layer. In some embodiments, the doped N-well or P-well includes an in-situ dopant concentration of N-type or P-type dopant in the range of about 1×10 17 cm -3 Up to 5×10 18 cm -3 within the range.

[0048] After forming the epitaxially grown doped well, method 100 proceeds to block 112 where an undoped layer is grown. In some embodiments, the undoped layer includes an undoped channel region formed directly on top of the epitaxially grown doped well by an epitaxial growth process. In some embodiments, the epitaxially grown undoped channel region is substantially free of dopants (i.e., the dopant concentration is equal to about 0 cm -3In some embodiments, the dopant concentration of the epitaxially grown undoped channel region is less than about 1×10 17 cm -3 In some embodiments, the thickness of the epitaxially grown undoped channel region is in the range of about 10 nm to 40 nm. In various embodiments, as described in more detail below, the epitaxially grown undoped channel region is used as an active FinFET channel. Therefore, for a FinFET device including an epitaxially grown undoped channel region substantially free of dopants as described herein, carrier scattering through the active FinFET channel will be significantly reduced. In some embodiments, the formation of a substantially dopant-free channel region using one or more of the methods described herein can enable the device to conduct an on-current (I ON ) increases by about 7%. As an example of blocks 110 and 112, and referring to Figure 6 , where a doped layer / undoped layer stack 604 is shown, for example, a stack including a doped well / undoped channel. In some embodiments, the doped layer / undoped layer stack 604 corresponds to the fin type (N-type or P-type) of the first set of fins 608 of the fin element 204. For example, as described above with respect to blocks 110 and 112 of method 100, the doped layer / undoped layer stack 604 may be formed in the fin element 204 as the first set of fins ( Figure 5 ) above.

[0049] After the doped well / undoped channel stack 604 corresponding to the fin type (N-type or P-type) of the first set of fins is formed, the method 100 may substantially repeat blocks 110 and 112 for the formation of a second doped layer / undoped layer stack 605 corresponding to the fin type (N-type or P-type) of the second set of fins 610. For example, a second photolithography step may be performed to pattern and etch an oxide layer (e.g., a SiO2 layer) to expose the second set of fins of the fin element 204 while the first set of fins is still masked by the photoresist layer. In some embodiments, the second photolithography step may include an N-well or P-well photolithography step. In some embodiments, the second photolithography step may include: forming a photoresist layer (resist) over the substrate, exposing the photoresist to a pattern (e.g., defined by an N-well or P-well mask), performing a post-exposure bake process, and developing the photoresist to form a masking element including the photoresist. For example, the exposed oxide may be etched after developing the photoresist to expose a second set of fins to be formed as N-type or P-type FinFETs in the underlying fin element 204 , corresponding to the mask (N-well or P-well mask) used for the second photolithography step.

[0050] Thus, similar to the doped / undoped layer stack 604, the doped / undoped layer stack 605 may be formed over the second set of fins exposed in the fin element 204 by the second lithography step and subsequent etching. The doped layers in the doped / undoped layer stack 605 may be formed over the exposed second set of fins by one or more in-situ doping epitaxial growth processes. In various embodiments and depending on the type of well to be formed (N-well or P-well), the epitaxially grown doped layers may be in-situ doped with N-type dopants or P-type dopants, as described above. In some embodiments, the thickness of the epitaxially grown doped layers grown over the exposed second set of fins is in the range of about 10 nm to 40 nm. Thereafter, the undoped layers (i.e., undoped channel regions) in the doped / undoped layer stack 605 are formed directly on top of the epitaxially grown doped layers in the doped / undoped layer stack 605 by an epitaxial growth process. As described above, the epitaxially grown undoped channel regions serve as active FinFET channels and are substantially free of dopants (i.e., dopant concentration equal to about 0 cm -3 In some embodiments, the dopant concentration of the epitaxially grown undoped channel region is less than about 1×10 17 cm -3 In some embodiments, the thickness of the epitaxially grown undoped channel region is in a range of about 10 nm to 40 nm.

[0051] The method 100 then proceeds to block 114 where a gate stack and sidewall spacers disposed on sidewalls of the gate stack are formed. In an embodiment, the gate stack is a dummy gate stack. In other embodiments of the method 100, the gate stack may be a high-k / metal gate stack. Although the method 100 is described below with reference to a replacement gate process, those skilled in the art will readily appreciate that the methods and structures disclosed herein may be equally applicable to a gate-first process.

[0052] In an embodiment using a gate-last process, the gate stack is a dummy gate stack and will be replaced by a final gate stack at a subsequent processing stage of the semiconductor device 200. Specifically, the gate stack can be replaced by a high-K dielectric layer (HK) and a metal gate electrode (MG) at a later processing stage. In some embodiments, the gate stack is formed over the substrate 202 and is at least partially disposed over the fin element 204. In one embodiment, the gate stack includes a dielectric layer, an electrode layer, and a hard mask. For illustration purposes only, after forming the doped layer / undoped layer stack 604, 605, Figure 7A semiconductor device 200 is shown that further includes a dielectric layer 702. In some embodiments, the dielectric layer 702 includes a gate stack dielectric layer. In some embodiments, the dielectric layer 702 includes an input / output (I / O) oxide layer. In some instances, the I / O oxide layer includes an oxide layer configured to prevent electrostatic discharge (ESD) events. In some embodiments, the gate stack is formed by multiple process steps such as layer deposition, patterning, etching, and other suitable processing steps. In some instances, the layer deposition process includes CVD (including low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques or combinations thereof. In some embodiments, the patterning process includes a lithography process (e.g., photolithography or electron beam lithography), and the lithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., dehydration drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (eg, RIE etching), wet etching, and / or other etching methods.

[0053] In some embodiments, the dielectric layer of the gate stack includes silicon oxide. Alternatively or additionally, the dielectric layer of the gate stack may include silicon nitride, a high-K dielectric material, or other suitable material. In some embodiments, the electrode layer of the gate stack may include polycrystalline silicon (polysilicon). In some embodiments, the hard mask of the gate stack includes a suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbide.

[0054] In various embodiments, the sidewall spacer is disposed on the sidewall of the gate stack. The sidewall spacer may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. In some embodiments, the sidewall spacer includes a plurality of layers, such as a main spacer wall, a liner layer, and the like. For example, the sidewall spacer may be formed by depositing a dielectric material over the gate stack and anisotropically etching back the dielectric material. In some embodiments, the etch-back process (e.g., for spacer formation) may include a multi-step etching process to improve etching selectivity and provide over-etching control. In some embodiments, before forming the sidewall spacer, an ion implantation process may be performed to form a lightly doped drain (LDD) component in the semiconductor device 200. In other examples, such an LDD component may be formed by epitaxial growth of an in-situ doping layer before forming the sidewall spacer. In some examples, a plasma doping (PLAD) process may be used to form an LDD component. In yet other embodiments, an ion implantation process may be performed to form an LDD component after forming the sidewall spacer 1202. Similar to the separate processing of the doped layer / undoped layer stacks 604, 605 corresponding to each set of fins of the first set of fins and the second set of fins described above, the formation of the LDD components can be implemented separately in a processing sequence for each of the N-type and P-type LDD regions. In some embodiments, after forming the LDD components, the semiconductor device 200 can be subjected to a high thermal budget process (annealing) to remove defects and activate dopants (i.e., place dopants at substitution sites).

[0055] Referring again to method 100, method 100 proceeds to frame 116, wherein a source / drain component is formed in the source / drain region. In some embodiments, the source / drain component is formed by epitaxially growing a semiconductor material layer in the source / drain region. In some instances, a pseudo sidewall spacer may be formed before the epitaxial source / drain growth, and the pseudo sidewall spacer may be removed after the epitaxial source / drain growth. In addition, as described above, a main sidewall spacer may be formed after the epitaxial source / drain growth. In various embodiments, the semiconductor material layer grown in the source / drain region includes Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain component may be formed by one or more epitaxial (epi) processes. In some embodiments, the source / drain component may be in-situ doped during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain component may be doped with boron. In other examples, the epitaxially grown Si epitaxial source / drain components may be doped with carbon to form Si:C source / drain components, the epitaxially grown Si epitaxial source / drain components may be doped with phosphorus to form Si:P source / drain components, or the epitaxially grown Si epitaxial source / drain components may be doped with boron and phosphorus to form SiCP source / drain components. In some embodiments, the source / drain components are not doped in situ, but an implantation process is performed to dope the source / drain components. In various embodiments, the doping dose for doping the source / drain components is greater than the doping dose for doping the LDD components. Similar to the separate processing of the doped layer / undoped layer stacks 604, 605 corresponding to each set of fins of the first set of fins and the second set of fins described above, the formation of the source / drain components may be performed separately in the processing order for the N-type and P-type source / drain components. In some embodiments, after forming the source / drain components, a double epitaxial annealing process may be performed, wherein the semiconductor device 200 is subjected to a high thermal budget process.

[0056] In some examples, after forming the source / drain features (block 116), an etch stop layer and a dielectric layer may be formed on the substrate 202. For example, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer may be formed over the substrate 202. In some examples, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL may be formed by a plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer, the semiconductor device 200 may be subjected to a high thermal budget process to anneal the ILD layer. In some examples, a planarization process may be performed to expose the top surface of the dummy gate stack. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the CESL and ILD layers located above the dummy gate stack and planarizes the top surface of the semiconductor device 200. In addition, the CMP process removes the hard mask above the dummy gate stack to expose an electrode layer (such as a polysilicon electrode layer).

[0057] In an embodiment, the method 100 then proceeds to block 118 where a replacement gate stack is formed. In some embodiments, a previously formed gate stack component (e.g., a dummy gate stack) is removed from the substrate. Removing the gate stack component (e.g., a dielectric layer and / or an electrode layer) from the gate stack may create a trench whereby a final gate structure (e.g., including a high-K dielectric layer and a metal gate electrode) may subsequently be formed in the trench. Removal of the dummy gate stack component may include a selective etching process including a selective wet etching process or a selective dry etching process.

[0058] Thereafter, a high-K / metal gate stack is formed on the device 200. The high-K / metal gate stack includes an interface layer formed above the substantially dopant-free channel material of the fin, a high-K gate dielectric layer formed above the interface layer, and a metal layer formed above the high-K gate dielectric layer. As used and described herein, the high-K gate dielectric includes a dielectric material with a high dielectric constant (e.g., a dielectric constant greater than that of thermal silicon oxide (approximately 3.9)). The metal layer used in the high-K / metal gate stack may include a metal, a metal alloy, or a metal silicide. In addition, the formation of the high-K / metal gate stack includes multiple depositions to form various gate materials and one or more CMP processes to remove excess gate material to planarize the top surface of the semiconductor device 200.

[0059] The interface layer may include a dielectric material such as silicon dioxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer of the high-K / metal gate stack may include a high-K dielectric layer such as hafnium dioxide (HfO2). Alternatively, the gate dielectric layer of the high-K / metal gate stack may include other high-K dielectrics (such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof) or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The metal layer of the high-K / metal gate stack may include a single layer or optionally include a multilayer structure (such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides). For example, the metal layer of the high-K / metal gate stack may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or combinations thereof. In addition, the metal layer may provide an N-type or P-type work function, may be used as a transistor (e.g., FinFET) gate electrode, and in at least some embodiments, the metal layer may include a polysilicon layer. In various embodiments, the metal layer of the high-K / metal gate stack may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. Moreover, the metal layers of the high-K / metal gate stack in N-FET and P-FET transistors using different metal layers may be formed separately. In various embodiments, a CMP process may be performed to remove excess metal from the metal layer of the high-K / metal gate stack and thereby provide a substantially planar top surface of the metal layer of the high-K / metal gate stack.

[0060] The semiconductor device 200 may be further processed to form various components and regions known in the art. For example, subsequent processing may form an interlayer dielectric (ILD) layer, contact openings, contact metals, and various contacts / vias / lines and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on the substrate 202, which are configured to connect various components to form a functional circuit including one or more FinFET devices. In another example, the multilayer interconnects may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. Various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, inlay and / or dual inlay processes are used to form a copper-containing multilayer interconnect structure. In addition, additional process steps may be implemented before, during, and after the method 100, and some of the process steps described above may be replaced or deleted according to various embodiments of the method 100.

[0061] Now refer to Figure 8 , Figure 8 A FinFET device 800 manufactured according to one or more steps of method 100 is shown. FinFET device 800 is formed on a substrate (e.g., substrate 202) having one or more fin elements (e.g., fin element 204). Specifically, device 800 includes an in-situ doped epitaxial growth layer 803 formed above the fin element (e.g., fin element 204), and an epitaxial growth undoped layer 805 formed above the in-situ doped epitaxial growth layer 803. In various embodiments, the in-situ doped epitaxial growth layer 803 includes an N-type well or a P-type well, for example, the N-type well or the P-type well can be used to form an in-situ doped APT layer, an in-situ doped threshold voltage (V t ) adjustment layer, in-situ doped halo layer or other suitable in-situ doped layer. In various embodiments, the epitaxially grown undoped layer 805 includes an undoped device channel 807, which effectively mitigates carrier channel scattering, thereby producing improved device mobility and drive current. In various embodiments, the dopant concentration of the undoped layer 805 (i.e., the active device channel 807) is less than about 1×10 17 cm -3 In some embodiments, the thickness of the in-situ doped layer and the undoped layer is between about 10 nm and 40 nm. In some embodiments, the device 800 includes an N-type FinFET. In some embodiments, the device 800 includes a P-type FinFET.

[0062] The device 800 also includes a source region 810 and a drain region 812 and an LDD region 814. In some embodiments, the source region 810 and the drain region 812 are adjacent to the undoped device channel 807 and on both sides of the undoped device channel 807. In some embodiments, the source region 810 and the drain region 812 can be epitaxially grown. In addition, the device 800 includes a gate structure 808 formed above the undoped device channel 807. In some examples, the undoped layer 805 (i.e., the active device channel 807) includes silicon. In other examples, the undoped layer 805 (i.e., the active device channel 807) includes a high mobility material such as germanium and any semiconductor and / or combinations thereof of the compound semiconductors or alloy semiconductors discussed above.

[0063] The gate structure 808 includes a gate stack having an interface layer formed above the undoped device channel 807, a gate dielectric layer 809 formed above the interface layer, and a metal layer 811 formed above the gate dielectric layer 809. The interface layer may include a dielectric material, such as a silicon dioxide layer (SiO2) or a silicon oxynitride (SiON). The gate dielectric layer 809 may include a high-k dielectric layer, silicon dioxide or other suitable dielectric. The metal layer 811 may include one or more of the multiple conductive layers described above or a combination thereof. The interface layer, the gate dielectric layer 809 and the metal layer 811 may all be formed by one or more of the methods described above. In some embodiments, sidewall spacers 815, 817 are formed on the sidewalls of the gate structure 808. The sidewall spacers 815, 817 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or a combination thereof, and may be formed as previously described.

[0064] According to the description provided herein, the present invention provides methods and structures for avoiding degradation of semiconductor devices (which may occur due to ion implantation processes), the degradation of semiconductor devices including defect formation and introduction of channel impurities (i.e., unwanted channel dopants). In some instances, an in-situ doped epitaxial growth layer is used instead of an ion implantation process to form a device well region (N-well or P-well), thereby avoiding degradation caused by ion implants. An epitaxially grown undoped layer is formed above the in-situ doped epitaxial growth layer, wherein the epitaxially grown undoped layer is used as an active device channel. Therefore, embodiments of the present invention provide a FinFET device channel that is substantially free of dopants, which directly improves device mobility and drive current. Those skilled in the art will readily appreciate that the methods and structures described herein can be applied to various other semiconductor devices to advantageously achieve similar benefits from these other devices without departing from the scope of the present invention.

[0065] Thus, one embodiment of the present invention describes a method for manufacturing a semiconductor device (e.g., a FinFET device) having a substantially undoped channel region. In some embodiments, the method includes providing a substrate having a fin extending from the substrate. In various embodiments, an in-situ doped layer is formed on the fin. For example, the in-situ doped layer may include an in-situ doped well region formed by an epitaxial growth process. After the in-situ doped layer is formed on the fin, an undoped layer is formed on the in-situ doped layer. For example, the undoped layer may include an undoped channel region formed by an epitaxial growth process.

[0066] In another embodiment, a method is discussed, wherein a substrate is provided, the substrate comprising a plurality of fins extending from the substrate. In various embodiments, an isolation region is formed to isolate each of the plurality of fins from each other. In some instances, an in-situ doped N-well region is formed on a first group of fins of the plurality of fins, and thereafter, an undoped channel region is formed on the in-situ doped N-well region. Additionally, in some embodiments, an in-situ doped P-well region is formed on a second group of fins of the plurality of fins, and thereafter, an undoped channel region is formed on the in-situ doped P-well region.

[0067] In yet another embodiment, a semiconductor device is discussed, the semiconductor device comprising a substrate having a fin, an in-situ doped layer formed above the fin, an undoped layer formed above the in-situ doped layer, and a gate stack formed above the undoped layer. In some embodiments, the in-situ doped layer comprises a well region, and the undoped layer comprises a channel region. In some instances, the thickness of the in-situ doped layer and the undoped layer is between about 10 nm and 40 nm. In addition, various embodiments include a source region and a drain region adjacent to the undoped channel region and located on both sides of the undoped channel region.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a doped semiconductor material layer disposed on a substrate; an undoped semiconductor material layer, disposed on the doped semiconductor material layer, the undoped semiconductor material layer comprising a top surface facing away from the substrate, the undoped semiconductor material layer further comprising an undoped device channel, and the undoped device channel being located in the undoped semiconductor material layer; A gate structure, disposed on the undoped semiconductor material layer, the gate structure comprising a gate electrode and a gate dielectric layer; A source region and a drain region, located on both sides of the undoped device channel; A lightly doped drain region, the lightly doped drain region is located between the undoped semiconductor material layer and the source / drain region, and between the doped semiconductor material layer and the source / drain region, and directly borders the undoped semiconductor material layer and the doped semiconductor material layer; as well as A sidewall spacer is arranged along the sidewall of the gate structure and extends to the top surface of the undoped semiconductor material layer so that the sidewall spacer physically contacts the top surface of the undoped semiconductor material layer, and the sidewall spacer is arranged on at least a portion of the lightly doped drain region.

2. The device according to claim 1, further comprising: A fin structure is disposed above the substrate, and wherein the doped semiconductor material layer is disposed above the fin structure.

3. The device according to claim 2, wherein The fin structure is formed of a first semiconductor material, and the doped semiconductor material layer is formed of the first semiconductor material.

4. The device according to claim 2, wherein The fin structure is formed of a first semiconductor material, and the doped semiconductor material layer is formed of a second semiconductor material different from the first semiconductor material.

5. The device according to claim 1, wherein A metal layer is disposed on the gate dielectric layer.

6. The device according to claim 1, wherein The gate dielectric layer physically contacts a top surface of the undoped semiconductor material layer.

7. The device according to claim 1, wherein The undoped semiconductor material layer has a value less than 1×10 17 cm -3 of doping concentration.

8. The device according to claim 1, wherein The undoped semiconductor material layer includes a material selected from the group consisting of silicon and germanium.

9. A semiconductor device comprising: a doped semiconductor material layer disposed on a substrate; an undoped semiconductor material layer, directly disposed on the doped semiconductor material layer so that the undoped semiconductor material layer is in physical contact with the doped semiconductor material layer, the undoped semiconductor material layer comprising a first sidewall surface and an opposite second sidewall surface and a top surface extending from the first sidewall surface to the second sidewall surface, wherein the undoped semiconductor material layer comprises an upper portion having a first width and a lower portion having a second width different from the first width, the undoped semiconductor material layer further comprising an undoped device channel, the undoped device channel being located in the undoped semiconductor material layer; A source region and a drain region, located on both sides of the undoped device channel; A gate structure, disposed on the undoped semiconductor material layer, the gate structure comprising a gate electrode and a gate dielectric layer; a first lightly doped drain region, the first lightly doped drain region being located between the undoped semiconductor material layer and the source / drain region, and between the doped semiconductor material layer and the source / drain region, and being in physical contact with a first sidewall surface of the undoped semiconductor material layer; and A sidewall spacer is arranged along the sidewall of the gate structure and extends to the top surface of the undoped semiconductor material layer so that the sidewall spacer physically contacts the top surface of the undoped semiconductor material layer, and the sidewall spacer is arranged on at least a portion of the lightly doped drain region.

10. The device according to claim 9, wherein The first sidewall surface and the second sidewall surface of the undoped semiconductor material layer are curved.

11. The device according to claim 9, wherein The first width is greater than the second width.

12. The device according to claim 9, wherein The first lightly doped drain region physically contacts an entire first sidewall surface of the undoped semiconductor material layer.

13. The device according to claim 9, wherein The first lightly doped drain region physically contacts the doped semiconductor material layer.

14. The device according to claim 9, further comprising: A contact feature is disposed above the substrate and interfaces with the top surface of the undoped semiconductor material layer.

15. The device according to claim 9, further comprising: The second lightly doped drain region is in physical contact with the second sidewall surface of the undoped semiconductor material layer.

16. A semiconductor device comprising: A first doping material layer, disposed above the substrate, the first doping material layer comprising a first dopant having a first conductivity type; a first undoped material layer, disposed on the first doped material layer, the first undoped material layer further comprising a first undoped device channel, and the first undoped device channel is located in the first undoped material layer; A first source region and a first drain region, located on both sides of the first undoped device channel; A second doping material layer, disposed on the substrate, the second doping material layer comprising a second dopant having a second conductivity type opposite to the first conductivity type; A second undoped material layer, disposed above the second doped material layer; A first gate structure, disposed above the first undoped material layer; A second gate structure is disposed above the second undoped material layer; A first lightly doped drain region is arranged along an edge of the first undoped material layer, so that the first lightly doped drain region is in direct contact with the first undoped material layer, and the first lightly doped drain region is located between the first undoped material layer and the first source region / first drain region, and between the first doped material layer and the first source region / first drain region; as well as A first sidewall spacer is disposed along a sidewall of the first gate structure and in physical contact with the first undoped material layer, wherein the first sidewall spacer is disposed on at least a portion of the first lightly doped drain region.

17. The semiconductor device according to claim 16, further comprising: a second lightly doped drain region, disposed along an edge of the second undoped material layer, such that the second lightly doped drain region is in direct contact with the second undoped material layer; as well as A second sidewall spacer is disposed along a sidewall of the second gate structure and in physical contact with the second undoped material layer, and the second sidewall spacer is disposed on at least a portion of the second lightly doped drain region.

18. The device according to claim 16, wherein The first lightly doped drain region covers the entire edge of the first undoped material layer.

19. The device according to claim 16, wherein At least one of the first doped material layer and the first undoped material layer includes a semiconductor material.

20. The device according to claim 16, wherein The first doping material layer includes silicon, and the second doping material layer includes germanium.

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