A Run-length Decoding Digital Circuit

Abstract

The present invention provides a run-length decoding digital circuit, including a decoding control module and two decoders, wherein the decoding control module is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder according to a first preset logic, and the decoder is used to decode the obtained compressed data into picture stream data of a preset format and output it according to a second preset logic. With such a configuration, decoding is performed in a hardware manner, which is real-time; at the same time, the two decoders are buffered with each other, and each has enough time to decode the received compressed data, thereby avoiding the interruption and delay that are easy to occur in the picture stream data output by the ordinary hardware decoding circuit, and meeting the requirements for the picture stream data to be superimposed in the OSD function.

Description

Technical Field

[0001] The invention relates to the field of digital circuit design, and in particular to a run-length decoding digital circuit. Background Art

[0002] Run-length encoding is a common compression algorithm. Its basic idea is to describe characters that are repeated and appear multiple times in succession using the format of {number of consecutive occurrences, a certain character}. In the process of run-length encoding, there are two types of data, one is the original data (also called data to be compressed or encoded), and the other is the compressed data (or encoded data). In this specification, picture stream data, decoded data, unencoded data, data in ordinary format and similar descriptions all refer to original data; data in run-length encoding format, compressed data and similar descriptions all refer to compressed data; the process of obtaining compressed data from original data is called run-length encoding; the process of obtaining original data from compressed data is called run-length decoding. A run-length decoding digital circuit provided by the present invention refers to a circuit that decodes compressed data into original picture stream data.

[0003] Run-length encoding is a solution for loading overlay images or characters to implement the OSD (picture-in-picture) function. Implementing the OSD function includes the following five steps: 1. Obtaining overlay data in run-length encoding format; 2. Obtaining the image data to be overlaid in ordinary format; 3. Decoding the overlay data in run-length encoding format to obtain decoded overlay data; 4. Superimposing the overlay data in ordinary format on the image data to be overlaid in ordinary format to obtain combined image stream data; 5. Outputting the combined image stream data.

[0004] In the prior art, the above process is implemented by MCU (Microcontroller Unit, micro control unit or microcontroller). Specifically, the MCU accesses the overlay coding information and the data to be overlaid stored in the external memory or internal cache (i.e., the above steps 1 and 2), then decodes the overlay coding information by software and combines the decoded overlay data with the data to be overlaid to complete the OSD overlay function (i.e., the above steps 3 and 4), and then writes the overlay result back to the data memory (i.e., the above step 5).

[0005] There are the following problems with decoding through MCU: Since the data reading, decoding and overlaying processes are completely based on MCU, the reading encoding and decoding speeds are limited by the MCU performance. On a lower-performance MCU, the OSD overlay frame rate may be low. Figure 1 This is a schematic diagram of an overlay error caused by MCU decoding. Figure 1It shows that there are multiple erroneous data in the YUV format image stream data finally generated by the image stream data output by the ordinary decoding circuit, which affects the final overlay effect.

[0006] In summary, in the prior art, the circuit that implements the OSD function through software has high requirements on the MCU performance, and is prone to low frame rate, inability to output picture stream data in real time, and delays, breakpoints or errors when outputting picture stream data in real time. Summary of the invention

[0007] The purpose of the present invention is to provide a run-length decoding digital circuit to solve the problems in the prior art that the circuit that realizes the OSD function by software has high requirements on MCU performance and is prone to low frame rate, inability to output picture stream data in real time, and delays, breakpoints or errors when outputting picture stream data in real time.

[0008] In order to solve the above technical problems, the present invention provides a run-length decoding digital circuit, which includes a decoding control module and two decoders. The decoding control module is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder according to a first preset logic. The decoder is used to decode the obtained compressed data into picture stream data in a preset format and output it according to a second preset logic; the compressed data is picture stream data in a run-length encoding format.

[0009] Optionally, the first preset logic includes sending the compressed data to the two decoders alternately, and sending the compressed data to only one decoder at the same time.

[0010] Optionally, the first preset logic also includes sending only the compressed data of the same data type before switching the sending object.

[0011] Optionally, the second preset logic includes the two decoders outputting picture stream data alternately and uninterruptedly, and only one decoder outputs data at the same time.

[0012] Optionally, the run-length decoding digital circuit also includes a storage control module and a picture stream data storage device, wherein the storage control module is used to directly splice the picture stream data output by the decoder in the order of reception time, and write the combined picture stream data into the picture stream data storage device.

[0013] Optionally, the data processing mode of the image stream data storage device is first-in-first-out.

[0014] Optionally, the storage control module is also used to read the picture stream data stored in the picture stream data storage device and output it to an external circuit.

[0015] Optionally, when the available storage space of the picture stream data storage is less than or equal to a preset ratio, the storage control module suspends writing data to the picture stream data storage.

[0016] Optionally, the preset ratio is 1 / 2.

[0017] Optionally, the run-length decoding digital circuit further includes a memory, wherein the memory is used to store the compressed data to be decoded, and the decoding control module obtains the compressed data from the memory.

[0018] Compared with the prior art, the run-length decoding digital circuit provided by the present invention includes a decoding control module and two decoders, wherein the decoding control module is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder according to a first preset logic, and the decoder is used to decode the obtained compressed data into picture stream data of a preset format and output it according to a second preset logic. With such a configuration, decoding is performed in hardware, which is real-time, and the decoding speed is completely consistent with the input clock. The overlay operation can be completed while ensuring the output picture stream frame rate, which solves the problem that the circuit that realizes the OSD function by software has high requirements on MCU performance, and is prone to low frame rate, inability to output picture stream data in real time, and delays, breakpoints or errors when outputting picture stream data in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0020] Figure 1 Schematic diagram of the error caused by overlay when the OSD function is implemented for MCU;

[0021] Figure 2 A schematic diagram of the structure of a run-length decoding digital circuit according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of data types of part of compressed data according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of correct superimposed data obtained by an OSD circuit according to an embodiment of the present invention.

[0024] In the attached figure:

[0025] 1-decoding control module; 2-decoder; 3-storage control module; 4-picture stream data storage; 5-storage; 6-storage control module. DETAILED DESCRIPTION

[0026] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0027] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] The core idea of ​​the present invention is to provide a run-length decoding digital circuit to solve the problems in the prior art that the circuit that realizes the OSD function by software has high requirements on MCU performance, is prone to low frame rate, cannot output picture stream data in real time, and is prone to delays, breakpoints or errors when outputting picture stream data in real time.

[0029] In the background technology section, the disadvantages of implementing the OSD function through MCU have been analyzed in detail. Furthermore, the inventors found that since the run-length coded data contains multiple data types, and the lengths of the run-length coded data of different data types are also different, it is possible that multiple digital clocks will be occupied during the decoding process to obtain the complete and accurate pixel information contained in the run-length coded data. In order to realize the OSD function, a decoding circuit is required to output the picture stream to be superimposed, and the picture stream output by the decoding circuit and the picture stream input data of another channel must be strictly superimposed according to the user's configuration, the size of the superimposed area and other requirements, and there must be no signal interruption and delay of the picture stream data in the middle. The hardware decoding circuit with simple settings cannot meet the above requirements. Therefore, the inventors further thought that the above difficulties can be solved by the run-length decoding digital circuit in this embodiment.

[0030] The following description is given with reference to the accompanying drawings.

[0031] Please refer to Figures 2 to 4 ,in, Figure 2 A schematic diagram of the structure of a run-length decoding digital circuit according to an embodiment of the present invention; Figure 3 A schematic diagram of data types of part of compressed data according to an embodiment of the present invention; Figure 4 It is a schematic diagram of correct superimposed data obtained by an OSD circuit according to an embodiment of the present invention.

[0032] like Figure 2 As shown, this embodiment provides a run-length decoding digital circuit, which includes a decoding control module 1 and two decoders 2. The decoding control module 1 is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder 2 according to a first preset logic. The decoder 2 is used to decode the obtained compressed data into picture stream data in a preset format and output it according to a second preset logic; the compressed data is picture stream data in a run-length encoding format.

[0033] With such configuration, on the one hand, decoding is performed in hardware, which is real-time, and the decoding speed is completely consistent with the input clock. The overlay operation can be completed while ensuring the frame rate of the output picture stream, which solves the problem that the circuit that implements the OSD function by software has high requirements on MCU performance and is prone to low frame rate, inability to output picture stream data in real time, and delays, breakpoints or errors when outputting picture stream data in real time. On the other hand, in combination with the first preset logic and the second preset logic, the effect of the two decoders 2 working alternately can be achieved. When one of the decoders 2 has not completed the decoding task, the other decoder 2 can be used as a buffer to output the decoded picture stream data, thereby eliminating the interruption and delay of the picture stream data when a single decoder 2 outputs the decoded picture stream, and meeting the requirements for the picture stream data to be superimposed in the OSD function.

[0034] It should be understood that the preset format may be any data format that is convenient for subsequent image overlay implementation, and those skilled in the art may set it according to common knowledge, which will not be described in detail here.

[0035] It should be understood that the first preset logic can be any logic that enables the above effect to be achieved. For example, data can be sent to one of the decoders 2 first, and when the sending process is not completed, other data can be sent to the other decoder 2. From the perspective of time scale, the time for sending data to both decoders 2 at the same time accounts for 10%, the time for sending data to one of the decoders 2 alone accounts for 80%, and the time for not sending data accounts for 10%. The above effect can also be achieved. However, preferably, the first preset logic includes sending the compressed data to the two decoders 2 alternately, and sending compressed data to only one decoder 2 at the same time. Such a configuration is conducive to the design and implementation of the decoding control module 1. On the other hand, the decoded picture stream data ultimately needs to be overlaid with the picture stream data of another channel to output the final image. Therefore, the run-length decoding digital circuit does not need to output the picture stream data at a faster speed (compared to the picture stream data of another channel), and the design of sending data to the two decoders 2 at the same time in part of the time is not necessary. Of course, under some other working conditions, the expected effect can be achieved by other forms of the first preset logic.

[0036] Preferably, the first preset logic also includes sending only the compressed data of the same data type before switching the sending object. That is, in each continuous process of sending compressed data, only the compressed data of the same type is output. Figure 3 , Figure 3 FIG. 1 is a schematic diagram of data types of part of compressed data according to an embodiment of the present invention. Figure 3It can be seen that the data types of the compressed data are multiple, and the total length of the compressed data of each data type is not all equal. If the time length or data length is used as the logic for switching the sending object, the workload of each decoder 2 is increased. On the other hand, if the compressed data of the same data type is switched before it is completely sent, the other decoder 2 receives the subsequent data without the data header, which is not conducive to its decoding of the data.

[0037] It should be understood that the second preset logic can also be diverse. For example, when each of the decoders 2 receives the compressed data, it immediately decodes and outputs the decoded picture stream data as soon as the decoding is completed, which can also achieve the above effect. However, such a scheme brings inconvenience to the subsequent circuit module processing. In a preferred embodiment, the second preset logic includes two decoders 2 outputting picture stream data alternately and uninterruptedly, and only one decoder 2 outputs data at the same time. It should be understood that how each decoder 2 determines whether another decoder 2 has completed the data output this time can be implemented through a variety of schemes, for example, the two decoders 2 communicate with each other, or by setting a module to send information to each decoder 2 that the data of another decoder 2 has been sent, or other implementation schemes. This specification does not limit the above scheme, and those skilled in the art can design and implement it according to actual needs and common knowledge.

[0038] In one embodiment, the run-length decoding digital circuit further includes a storage control module 3 and a picture stream data memory 4, and the storage control module 3 is used to directly splice the picture stream data output by the decoder in the order of receiving time, and write the combined picture stream data into the picture stream data memory 4. With such a configuration, firstly, the picture stream data to be outputted can be formed through the splicing process, and no further processing by other circuits is required. Secondly, the buffering link is increased by the setting of the picture stream data memory 4, so that the picture stream data outputted finally is smoother, and the possibility of interruption or delay is further reduced. It should be understood that the "direct splicing" here should be understood as a simple splicing process, such as directly combining two copies of data, or deleting some data at the end of the first copy of data and / or deleting some data at the header of the second copy of data, and then directly combining the processed two copies of data. Any splicing process that requires at least one of decoding, reordering, and data conversion should not be understood as "direct splicing".

[0039] Furthermore, the data processing mode of the picture stream data memory 4 is first-in-first-out. With such configuration, the picture stream data memory 4 can match the timing of the run-length decoding digital circuit outputting data to the external circuit when storing and deleting data, and no additional conversion is required.

[0040] In one embodiment, the storage control module 3 is further used to read the picture stream data stored in the picture stream data storage 4 and output it to the external circuit. With such configuration, the entire function of the run-length decoding digital circuit can be fully realized.

[0041] In a preferred embodiment, when the available storage space of the picture stream data memory 4 is less than or equal to a preset ratio, the storage control module 3 suspends writing data to the picture stream data memory 4. This configuration prevents the loss of excess picture stream data after the picture stream data memory 4 is full under special circumstances, thereby causing errors in the entire run-length decoding digital circuit. The preset ratio can be set according to actual conditions, and a preferred solution is that the preset ratio is 1 / 2. This configuration can take into account both security and storage space utilization. It should be understood that when the storage control module 3 suspends writing data, the operating logic of other modules can be set according to actual conditions, for example, temporarily storing data on the storage control module 3, or the decoder 2 synchronously suspends outputting data, or the decoding control module suspends outputting compressed data, etc. The communication and trigger logic between the modules can also be configured according to actual conditions, which will not be described in detail here.

[0042] In one embodiment, the run-length decoding digital circuit further includes a memory 5, the memory 5 is used to store the compressed data to be decoded, and the decoding control module 1 obtains the compressed data from the memory 5. The decoding control module 1 can be connected to the memory 5 through a memory control module 6 to better read the data inside the memory 5. The control logic of the memory control module 6 can be configured by those skilled in the art according to actual needs and common knowledge, and will not be described in detail here. Preferably, the memory 5 is a static random access memory (i.e., SRAM), and the memory control module 6 is an SRAM control module. In other embodiments, as long as it can ensure that the compressed data can be read continuously, other forms of memory and memory control modules can also be selected, such as ROM (Read-Only Memory) and its control module.

[0043] As described in the background art, the realization of the OSD function includes five steps. The run-length decoding digital circuit disclosed in this embodiment optimizes step 3 of the five steps and realizes the functions of step 1 and step 3.

[0044] This embodiment also provides an OSD circuit to realize a complete OSD function, wherein the OSD circuit includes the above-mentioned run-length decoding digital circuit and overlay module, wherein the overlay module is configured to receive first picture stream data in a preset format sent by the run-length decoding digital circuit, and receive second picture stream data in the preset format, and superimpose the first picture stream data and the second picture stream data according to the overlay logic to obtain the overlaid picture stream data. Other modules of the OSD circuit, the internal specific implementation of the overlay module, and the connection relationship between the modules of the OSD circuit can be set by those skilled in the art according to common knowledge, and will not be described in detail here. Please refer to Figure 4 In one embodiment, the video data in YUV format output by the OSD circuit is as follows: Figure 4 As shown, it can be seen that the OSD circuit overcomes the problems of interruption and delay that are prone to occur in ordinary decoding circuits.

[0045] In summary, the run-length decoding digital circuit provided by the present invention includes a decoding control module 1 and two decoders 2. The decoding control module 1 is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder 2 according to a first preset logic. The decoder 2 is used to decode the obtained compressed data into picture stream data of a preset format and output it according to a second preset logic. With such a configuration, decoding is performed in hardware, which is real-time; at the same time, the two decoders 2 buffer each other, and each has enough time to decode the received compressed data, thereby avoiding the interruption and delay that are easy to occur in the picture stream data output by the ordinary hardware decoding circuit, and meeting the requirements of the OSD function for the picture stream data to be superimposed.

[0046] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A run-length decoding digital circuit, characterized in that: The run-length decoding digital circuit is applied to an OSD circuit, and the OSD circuit includes the run-length decoding digital circuit and an overlay module, and the overlay module is configured to receive the first picture stream data sent by the run-length decoding digital circuit, and receive the second picture stream data, and superimpose the first picture stream data and the second picture stream data according to the overlay logic to obtain the overlay picture stream data; the run-length decoding digital circuit includes a decoding control module and two decoders, the decoding control module is used to obtain compressed data of different data types, and send the obtained compressed data to the decoder according to the first preset logic, and the decoder is used to decode the obtained compressed data into picture stream data in a preset format and output it according to the second preset logic; the compressed data is picture stream data in a run-length encoding format; The first preset logic includes sending the compressed data to the two decoders alternately and sending the compressed data to only one decoder at a time; The second preset logic includes the two decoders outputting picture stream data alternately and continuously, with only one decoder outputting data at the same time; the first preset logic also includes only sending the compressed data of the same data type before switching the sending object.

2. The run-length decoding digital circuit according to claim 1, characterized in that: The run-length decoding digital circuit also includes a storage control module and a picture stream data storage device. The storage control module is used to directly splice the picture stream data output by the decoder in the order of receiving time, and write the combined picture stream data into the picture stream data storage device.

3. The run-length decoding digital circuit according to claim 2, characterized in that: The data processing mode of the picture stream data storage device is first-in-first-out.

4. The run-length decoding digital circuit according to claim 2, characterized in that: The storage control module is also used to read the picture stream data stored in the picture stream data storage device and output it to an external circuit.

5. The run-length decoding digital circuit according to claim 2, characterized in that: When the available storage space of the picture stream data storage is less than or equal to a preset ratio, the storage control module suspends writing data to the picture stream data storage.

6. The run-length decoding digital circuit according to claim 5, characterized in that: The preset ratio is 1 / 2.

7. The run-length decoding digital circuit according to claim 1, characterized in that: The run-length decoding digital circuit also includes a memory, which is used to store the compressed data to be decoded, and the decoding control module obtains the compressed data from the memory.

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