Method for forming capacitor receiving plate, semiconductor memory and method for forming the same

Abstract

The present invention provides a method for forming a capacitor receiving plate, a semiconductor memory and a method for forming the same. The method for forming the capacitor receiving plate comprises the following steps: providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on the surface of the substrate, the substrate having a plurality of word lines; forming a conductive layer on the surface of the substrate; forming a first mask structure on the surface of the conductive layer, the first mask structure having a first etching pattern; forming a second mask structure on the first mask structure, the second mask structure having a second etching pattern; using the portion where the projections of the first etching pattern and the second etching pattern intersect in a direction perpendicular to the substrate as a capacitor receiving plate pattern, etching the conductive layer, and forming a capacitor receiving plate tilted at a preset angle relative to the word line. The present invention can effectively control the size of the capacitor receiving plate and the spacing between adjacent capacitor receiving plates.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a capacitor receiving plate, a semiconductor memory and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, which is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] In semiconductor memories such as DRAM, if the bit line is a curved structure, the active area contact point can be directly connected to the upper layer capacitor without the need for an additional switching structure; however, for a straight bit line structure, a hexagonal capacitor structure is formed to meet the needs of tight stacking. In this case, a capacitor receiving plate must be provided between the active area contact point and the capacitor as a switching structure.

[0004] In the prior art, the design shape of the capacitor receiving plate is generally obtained by exposure on the photoresist, and then transferred downward to the top of the contact point of the active area through multiple mask layers to form a capacitor receiving plate pattern, and finally the capacitor receiving plate structure is formed by filling the capacitor receiving plate pattern with metal material. However, this process method is not suitable for small-sized integrated circuit structures. For example, if the structure of the capacitor receiving plate is too dense and small in size, it will be more difficult to expose the spacing, and the uniformity of the distribution of the capacitor receiving plate is not easy to control.

[0005] Therefore, how to improve the formation process of the capacitor receiving plate and enhance the electrical performance of the semiconductor memory is a technical problem that needs to be solved urgently. Summary of the invention

[0006] The present invention provides a method for forming a capacitor receiving plate, a semiconductor memory and a method for forming the same, which are used to solve the problem that the existing capacitor receiving plate is not suitable for a compact integrated circuit structure, so as to improve the electrical performance of the semiconductor memory.

[0007] In order to solve the above problems, the present invention provides a method for forming a capacitor receiving plate, comprising the following steps:

[0008] Providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines;

[0009] forming a conductive layer on the surface of the substrate;

[0010] Forming a first mask structure on the surface of the conductive layer, wherein the first mask structure has a first etching pattern extending along a first direction;

[0011] Forming a second mask structure on the first mask structure, wherein the second mask structure has a second etching pattern extending along a second direction, and the first direction and the second direction obliquely intersect;

[0012] The intersecting portion of the projections of the first etched pattern and the second etched pattern in a direction perpendicular to the substrate is used as a capacitor receiving plate pattern, and the conductive layer is etched to form a plurality of capacitor receiving plates corresponding to a plurality of capacitor contacts one by one, and the capacitor receiving plates are tilted at a preset angle relative to the word line.

[0013] Optionally, the specific steps of forming a conductive layer on the surface of the substrate include:

[0014] forming an isolation layer covering the surface of the substrate, wherein the isolation layer has a plurality of contact windows exposing the capacitor contacts;

[0015] A conductive layer is formed to fill the contact window and cover the top surface of the isolation layer.

[0016] Optionally, the specific step of forming a first mask structure on the surface of the conductive layer includes:

[0017] forming a first mask layer covering the surface of the conductive layer;

[0018] forming a second mask layer covering a surface of the first mask layer;

[0019] The second mask layer is etched to form a first trench that exposes the first mask layer and extends along a first direction, and the first trench is used as a first etching pattern.

[0020] Optionally, the specific step of forming a first trench that exposes the first mask layer and extends along the first direction includes:

[0021] forming a third mask layer covering a surface of the second mask layer;

[0022] forming a fourth mask layer covering the surface of the third mask layer;

[0023] Forming a first photoresist layer on the surface of the fourth mask layer, wherein the first photoresist layer has a first opening that exposes the fourth mask layer and extends along a first direction;

[0024] forming a first side wall covering the side wall of the first opening;

[0025] The fourth mask layer, the third mask layer and the second mask layer are etched using the first sidewall as a mask to form the first trench.

[0026] Optionally, the material of the first mask layer is a nitride material, and the material of the second mask layer is a polysilicon material.

[0027] Optionally, the specific steps of forming the second mask structure on the first mask structure include:

[0028] forming a fifth mask layer that fills the first etching structure and covers the top surface of the second mask layer;

[0029] forming a sixth mask layer covering the fifth mask layer;

[0030] forming a second photoresist layer on the surface of the sixth mask layer, wherein the second photoresist layer has a second opening exposing the sixth mask layer and extending along a second direction;

[0031] forming a second side wall covering the side wall of the second opening;

[0032] The second photoresist layer is removed, and a second groove extending along a second direction is formed between adjacent second sidewalls, and the second groove is used as a second etching pattern.

[0033] Optionally, the specific step of etching the conductive layer includes:

[0034] Removing the portion of the second mask layer other than the overlapping area with the projection of the second sidewall, the fifth mask layer, the sixth mask layer and the second sidewall, a capacitor receiving plate pattern is formed on the surface of the first mask layer;

[0035] The conductive layer is etched using the capacitor receiving plate pattern as a mask pattern.

[0036] Optionally, the surface of the conductive layer further includes a seventh mask layer, and the first mask structure is located on the surface of the seventh mask layer; and the specific step of etching the conductive layer using the capacitor receiving plate pattern as a mask pattern further includes:

[0037] Using the capacitor receiving plate pattern as a mask pattern and the isolation layer as an etching stop layer, the first mask layer, the seventh mask layer and the conductive layer are etched to form a plurality of capacitor receiving plates corresponding to a plurality of capacitor contacts.

[0038] Optionally, the seventh mask layer is an organic mask layer.

[0039] Optionally, the first direction is parallel to the word line, and the second direction is inclined by the preset angle relative to the word line direction; or,

[0040] The first direction is a direction inclined by the preset angle relative to the word line direction, and the second direction is a direction parallel to the word line.

[0041] Optionally, the preset angle is 60°.

[0042] In order to solve the above problem, the present invention also provides a method for forming a semiconductor memory, comprising the following steps:

[0043] Providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines;

[0044] A plurality of capacitor receiving plates are formed on the surface of the substrate and are connected to the plurality of capacitor contacts in a one-to-one correspondence, wherein the capacitor receiving plates are formed by any of the above-mentioned methods for forming a capacitor receiving plate;

[0045] A plurality of capacitors are formed and connected to the plurality of capacitor receiving plates in a one-to-one correspondence.

[0046] Optionally, a plurality of the capacitor receiving plates are arranged in a hexagonal array.

[0047] In order to solve the above problem, the present invention further provides a semiconductor memory, comprising:

[0048] A substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines;

[0049] A plurality of capacitor receiving plates are located on the surface of the substrate, the plurality of capacitor receiving plates are connected to the plurality of capacitor contacts in a one-to-one correspondence, and the capacitor receiving plates are inclined at a preset angle relative to the word line.

[0050] Optionally, a plurality of the capacitor receiving plates are arranged in a hexagonal array.

[0051] Optionally, the preset angle is 60°.

[0052] Optionally, also include:

[0053] An isolation layer, located on the surface of the substrate, wherein the isolation layer has a plurality of contact windows exposing the capacitor contacts;

[0054] The capacitor receiving plate fully fills the contact window, and the height of the capacitor receiving plate is greater than that of the isolation layer.

[0055] Optionally, the cross-section of the capacitor receiving plate along a direction parallel to the substrate is elliptical.

[0056] Optionally, also include:

[0057] A plurality of capacitors are electrically connected to the plurality of capacitor receiving plates in a one-to-one correspondence.

[0058] Optionally, also include:

[0059] A plurality of bit lines are in a straight line shape, and the extending direction of the bit lines is perpendicular to the extending direction of the word lines.

[0060] The present invention provides a method for forming a capacitor receiving plate, a semiconductor memory and a method for forming the same. By forming a first mask structure having a first etched pattern extending along a first direction and a second mask structure having a second etched pattern extending along a second direction, and controlling the first direction to intersect with the second direction at an angle, a capacitor receiving plate is formed by using the intersecting portion of the projections of the first etched pattern and the second etched pattern in a direction perpendicular to the substrate as a capacitor receiving plate pattern, so that the finally formed capacitor receiving plate is inclined relative to the word line, and the size of the capacitor receiving plate and the spacing between adjacent capacitor receiving plates can be effectively controlled, so that the capacitor receiving plate can be suitable for a compact integrated circuit structure, thereby improving the performance of the semiconductor memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Attached Figure 1 is a flow chart of a method for forming a capacitor receiving plate in a specific embodiment of the present invention;

[0062] Attached Figure 2 It is a schematic diagram of the distribution of the capacitor receiving plate inside the semiconductor memory in a specific implementation mode of the present invention;

[0063] Attached Figure 3A-3P It is a schematic diagram of the main process structure of the capacitor receiving plate during the formation process in the specific implementation mode of the present invention. DETAILED DESCRIPTION

[0064] The following is a detailed description of the method for forming a capacitor receiving plate, a semiconductor memory and a specific implementation method of the method for forming the capacitor receiving plate provided by the present invention in conjunction with the accompanying drawings.

[0065] This specific embodiment provides a method for forming a capacitor receiving plate, Figure 1 is a flow chart of a method for forming a capacitor receiving plate in a specific embodiment of the present invention, Figure 2 Schematic diagram of the distribution of the capacitor receiving plate inside the semiconductor memory in a specific embodiment of the present invention, Figure 3A-3P FIG. 1 is a schematic diagram of the main process structure of the capacitor receiving plate in the process of forming the capacitor receiving plate in the specific embodiment of the present invention. Figure 1 , Figure 2 , Figure 3A-Figure 3P As shown, the method for forming the capacitor receiving plate provided in this specific embodiment includes the following steps:

[0066] Step S11, providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts 22 located on the surface of the substrate, the substrate having a plurality of word lines 21, such as Figure 2 shown.

[0067] Specifically, the substrate may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc. In this embodiment, the substrate is preferably a Si substrate. Figure 2 As shown, the plurality of capacitor contacts on the surface of the substrate are arranged in an array, for example, in a hexagonal array; the plurality of straight word lines 21 inside the substrate are arranged in parallel. In this specific embodiment, the substrate also has a plurality of parallel arranged bit lines 20, the bit lines are straight, and the extension direction of the bit lines 20 (for example Figure 2 The X-axis direction in FIG. 1 ) and the extension direction of the word line 21 (eg Figure 2 The Y-axis direction in the image is perpendicular to the Y-axis direction.

[0068] Step S12, forming a conductive layer 30 on the surface of the substrate, such as Figure 3A shown.

[0069] Optionally, the specific steps of forming the conductive layer 30 on the surface of the substrate include:

[0070] An isolation layer 31 is formed covering the surface of the substrate, wherein the isolation layer has a plurality of contact windows 311 exposing the capacitor contacts 22;

[0071] A conductive layer 30 is formed to fill the contact window 311 and cover the top surface of the isolation layer 31 .

[0072] Specifically, after the capacitor contact 22 is formed on the substrate surface, the isolation layer 31 having the contact window 311 is first formed on the substrate surface to avoid interference between adjacent memory cells; then, a conductive material such as metal is deposited on the surface of the isolation layer 31 to fill the contact window 311. The material of the isolation layer 31 may be, but is not limited to, a nitride material, and the material of the conductive layer 30 may be tungsten and / or tungsten nitride.

[0073] Step S13, forming a first mask structure on the surface of the conductive layer 30, wherein the first mask structure has a first etching pattern 42 extending along a first direction, such as Figure 3F , 3G shown.

[0074] Optionally, the specific steps of forming the first mask structure on the surface of the conductive layer 30 include:

[0075] forming a first mask layer 33 covering the surface of the conductive layer 30;

[0076] forming a second mask layer 34 covering the surface of the first mask layer 33;

[0077] The second mask layer 34 is etched to form a first trench that exposes the first mask layer 33 and extends along a first direction, and the first trench is used as a first etched pattern 42 .

[0078] Optionally, the specific step of forming a first trench that exposes the first mask layer 33 and extends along the first direction includes:

[0079] forming a third mask layer 35 covering the surface of the second mask layer 34;

[0080] forming a fourth mask layer 36 covering the surface of the third mask layer 35;

[0081] A first photoresist layer 37 is formed on the surface of the fourth mask layer 36. The first photoresist layer 37 has a first opening 38 that exposes the fourth mask layer 36 and extends along a first direction. Figure 3A As shown;

[0082] A first sidewall 40 is formed to cover the sidewall of the first opening 38. Figure 3C As shown;

[0083] The fourth mask layer 36 , the third mask layer 35 and the second mask layer 34 are etched using the first sidewall 40 as a mask to form the first trench.

[0084] Optionally, the first direction is parallel to the word line 21, and the second direction is inclined at a preset angle relative to the direction of the word line 21; or,

[0085] The first direction is a direction inclined by the preset angle relative to the direction of the word line 21 , and the second direction is a direction parallel to the word line 21 .

[0086] The following description is made by taking the first direction as a direction parallel to the word line 21 (i.e., the Y-axis direction) and the second direction as an example inclined at the preset angle relative to the word line 21. Specifically, after forming the conductive layer 30, first, the first mask layer 33, the second mask layer 34, the third mask layer 35, and the fourth mask layer 36 are sequentially deposited on the surface of the conductive layer 30; then, the first photoresist layer 37 is deposited on the surface of the fourth mask layer 36, and the first opening 38 is defined in the first photoresist layer 37, wherein the first opening 38 exposes the fourth mask layer 36 and extends along the Y-axis direction; then, the first dielectric layer 39 is formed to fill the first opening 38 and cover the surface of the first photoresist layer 37, as shown in FIG. Figure 3B As shown; then, the first dielectric layer 39 is etched to remove the first dielectric layer 39 covering the top surface of the first photoresist layer 37 and the bottom of the first opening 38, forming a first etching window 41 exposing the fourth mask layer 36, and the first dielectric layer 39 remaining on the side wall surface of the first opening 38 forms the first sidewall 40, as shown Figure 3C Then, the first photoresist layer 37 is removed by ashing or other processes, as shown in FIG. Figure 3D Next, a first pitch doubling etching process is performed, that is, the fourth mask layer 36, the third mask layer 35 and the second mask layer 34 are etched downward using the first sidewall 40 as a mask to form a first trench exposing the first mask layer 33, as shown. Figure 3E As shown; Finally, through the ashing process area Figure 3E The third mask layer 35 remaining in the Figure 3F , Figure 3G The structure shown.

[0087] The material of the first sidewall 40 may be, but is not limited to, an oxide material, such as a silicon oxide material. In this specific embodiment, by adjusting the thickness of the first sidewall 40 remaining after the first spacing multiplication process etching, the critical size of the finally formed capacitor receiving plate and the spacing between adjacent capacitor receiving plates can be adjusted, thereby increasing the controllability of forming the capacitor receiving plate.

[0088] In order to increase the etching selectivity ratio between the first mask layer 33 and the second mask layer 34 so as to better control the shape of the capacitor receiving plate finally formed and the interval between adjacent capacitor receiving plates, optionally, the material of the first mask layer 33 is nitride material and the material of the second mask layer 34 is polysilicon material.

[0089] The material of the third mask layer 35 may be an organic mask material, such as a carbon-containing organic material; the material of the fourth mask layer 36 may be a hard mask material, such as a silicon oxynitride material having anti-reflection properties.

[0090] Step S14, forming a second mask structure on the first mask structure, wherein the second mask structure has a second etching pattern 49 extending along a second direction, and the first direction and the second direction intersect obliquely, such as Figure 3L shown.

[0091] Optionally, the specific steps of forming the second mask structure on the first mask structure include:

[0092] forming a fifth mask layer 43 that fills the first etching structure and covers the top surface of the second mask layer 34;

[0093] forming a sixth mask layer 44 covering the fifth mask layer 43;

[0094] A second photoresist layer 45 is formed on the surface of the sixth mask layer 44. The second photoresist layer 45 has a second opening 46 that exposes the sixth mask layer 44 and extends along a second direction. Figure 3H , Fig. 3I As shown;

[0095] A second sidewall 48 is formed to cover the sidewall of the second opening 46. Figure 3K As shown;

[0096] The second photoresist layer 45 is removed, and a second trench extending along a second direction is formed between adjacent second sidewalls 48 , and the second trench is used as a second etched pattern 49 .

[0097] Specifically, in the formation of Figure 3F , Figure 3G After the first mask structure shown in FIG. 1 , first, the fifth mask layer 43, the sixth mask layer 44 and the second photoresist layer 45 are sequentially deposited on the surface of the first mask structure, and a second opening 46 extending along the second direction is defined in the second photoresist layer 45, wherein the second direction refers to a direction inclined at a preset angle relative to the word line 21, such as Figure 3H , Fig. 3I Then, the second dielectric layer 47 is formed to fill the second opening 46 and cover the surface of the second photoresist layer 45, as shown in FIG. Figure 3J Afterwards, the second dielectric layer 47 is etched to remove the second dielectric layer 47 covering the top surface of the second photoresist layer 45 and the bottom of the second opening 46, forming a second groove exposing the sixth mask layer 44, as shown Figure 3KFinally, the second photoresist layer 45 is removed by ashing or other processes to obtain Figure 3L The structure shown.

[0098] The material of the second sidewall 48 may be the same as that of the first sidewall 40, for example, may also be a silicon oxide material. In this specific embodiment, by adjusting the thickness of the first sidewall 40 remaining after the first spacing multiplication process etching and / or the second sidewall 48 covering the sidewall of the second opening 46, the critical size of the finally formed capacitor receiving plate and the spacing between adjacent capacitor receiving plates can be better adjusted.

[0099] Step S15, using the intersection of the projections of the first etched pattern 42 and the second etched pattern 49 in the direction perpendicular to the substrate as a capacitor receiving plate pattern, etching the conductive layer 30 to form a plurality of capacitor receiving plates 23 corresponding to the plurality of capacitor contacts 22, wherein the capacitor receiving plates 23 are inclined at a preset angle relative to the word line 21, such as Figure 2 , Figure 3P shown.

[0100] Optionally, the specific steps of etching the conductive layer 30 include:

[0101] The portion of the second mask layer 34 outside the overlapped area with the projection of the second sidewall 48, the fifth mask layer 43, the sixth mask layer 44 and the second sidewall 48 are removed, and a capacitor receiving plate pattern 50 is formed on the surface of the first mask layer 33, as shown in FIG. Figure 3M , Figure 3N As shown;

[0102] The conductive layer 30 is etched using the capacitor receiving plate pattern 50 as a mask pattern.

[0103] Optionally, the surface of the conductive layer 30 further includes a seventh mask layer 32, and the first mask structure is located on the surface of the seventh mask layer 32; the specific step of etching the conductive layer 30 using the capacitor receiving plate pattern 50 as a mask pattern also includes:

[0104] The first mask layer 33 , the seventh mask layer 32 and the conductive layer 30 are etched using the capacitor receiving plate pattern 50 as a mask pattern and the isolation layer 31 as an etching stop layer to form a plurality of capacitor receiving plates 23 corresponding to a plurality of capacitor contacts 22 .

[0105] Specifically, after forming the second mask structure, a second pitch doubling etching process is performed, that is, the sixth mask layer 44, the fifth mask layer 43 and part of the second mask layer 34 are etched downward with the first mask layer 33 as the etching stop layer and the second side wall 48 as the mask, and the part of the second mask layer 34 outside the overlapping area with the projection of the second side wall 48, all of the fifth mask layer 43, all of the sixth mask layer 44 and all of the second side wall 48 are removed, and the capacitor receiving plate pattern 50 is formed on the surface of the first mask layer 33, as shown in FIG. Figure 3M , Figure 3N Afterwards, the isolation layer 31 is used as the etching stop layer, the capacitor receiving plate pattern 50 is used as the mask pattern to continue etching the seventh mask layer 32 and the conductive layer 30 downward to form a gap 51 exposing the isolation layer 31, as shown Fig.3O Finally, the seventh mask layer 32 is removed by ashing or other processes to form a Figure 2 , Figure 3P The capacitor receiving plate 23 is shown.

[0106] Optionally, the seventh mask layer 32 is an organic mask layer. The seventh mask layer 32 serves as a barrier layer in the etching process of the two pitch multiplication processes to ensure the shape of the capacitor receiving plate 23 that is finally formed.

[0107] Optionally, the preset angle is 60°.

[0108] The capacitor receiving plate 23 finally formed in this specific embodiment is elliptical along the interface parallel to the substrate direction, and the capacitor receiving plate 23 is inclined 60° relative to the word line 21, that is, the major axis of the ellipse is inclined 60° relative to the extension direction of the word line 21. This specific embodiment uses two pitch multiplication etching processes to make the final formed plurality of capacitor receiving plates 23 arranged in a hexagonal array, which can meet the electrical transmission requirements between the capacitor 24 and the capacitor contact 22 while also matching the hexagonal closely stacked structure of the capacitor 24. At the same time, by adjusting the thickness of the first side wall 40 and the second side wall 48 during the two pitch multiplication etching processes, the critical dimensions of a single capacitor receiving plate 23 and the uniformity of the spacing between any adjacent capacitor receiving plates can be well controlled.

[0109] In addition, this embodiment also provides a method for forming a semiconductor memory. The structure and forming method of the capacitor receiving plate in this embodiment can be found in Figure 1-Figure 2 , Figure 3A-Figure 3P .like Figure 1-Figure 2 , Figure 3A-Figure 3P As shown, the method for forming the semiconductor memory comprises the following steps:

[0110] Providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines;

[0111] A plurality of capacitor receiving plates 23 are formed on the surface of the substrate and are connected to the plurality of capacitor contacts in a one-to-one correspondence manner. The capacitor receiving plates 23 are formed by any of the above-mentioned methods for forming a capacitor receiving plate;

[0112] A plurality of capacitors 24 are formed, which are connected to the plurality of capacitor receiving plates 23 in a one-to-one correspondence.

[0113] Optionally, a plurality of the capacitor receiving plates 23 are arranged in a hexagonal array.

[0114] In addition, this specific embodiment also provides a semiconductor memory. The structure and formation method of the capacitor receiving plate in the semiconductor memory can be found in Figure 1-Figure 2 , Figure 3A-Figure 3P .like Figure 1-Figure 2 , Figure 3A-Figure 3P As shown, the semiconductor memory comprises:

[0115] A substrate, the substrate comprising a substrate and a plurality of capacitor contacts 22 located on a surface of the substrate, wherein the substrate has a plurality of word lines 21;

[0116] A plurality of capacitor receiving plates 23 are located on the surface of the substrate. The plurality of capacitor receiving plates 23 are connected to the plurality of capacitor contacts 22 in a one-to-one correspondence, and the capacitor receiving plates 23 are inclined at a preset angle relative to the word line 21 .

[0117] Optionally, a plurality of the capacitor receiving plates 23 are arranged in a hexagonal array.

[0118] Optionally, the preset angle is 60°.

[0119] Optionally, the semiconductor memory further includes:

[0120] An isolation layer 31, located on the surface of the substrate, wherein the isolation layer 31 has a plurality of contact windows 311 exposing the capacitor contacts;

[0121] The capacitor receiving plate 23 completely fills the contact window 311 , and the height of the capacitor receiving plate 23 is greater than that of the isolation layer 23 .

[0122] Optionally, the cross-section of the capacitor receiving plate 23 along a direction parallel to the substrate is elliptical.

[0123] Optionally, the semiconductor memory further includes:

[0124] A plurality of capacitors 24 are electrically connected to the plurality of capacitor receiving plates 23 in a one-to-one correspondence.

[0125] Optionally, the semiconductor memory further includes:

[0126] A plurality of bit lines 20 are in a straight line shape, and an extending direction of the bit lines 20 is perpendicular to an extending direction of the word lines 21 .

[0127] The method for forming a capacitor receiving plate, a semiconductor memory and the method for forming the same provided in this specific embodiment form a first mask structure having a first etched pattern extending along a first direction and a second mask structure having a second etched pattern extending along a second direction, and control the first direction and the second direction to intersect at an angle, and use the intersecting portion of the projections of the first etched pattern and the second etched pattern in a direction perpendicular to the substrate as a capacitor receiving plate pattern to form a capacitor receiving plate, so that the finally formed capacitor receiving plate is inclined relative to the word line, and the size of the capacitor receiving plate and the spacing between adjacent capacitor receiving plates can be effectively controlled, so that the capacitor receiving plate can be suitable for a compact integrated circuit structure, thereby improving the performance of the semiconductor memory.

[0128] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a capacitor receiving plate, characterized in that: The steps include: Providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines; forming a conductive layer on the surface of the substrate; Forming a first mask structure on the surface of the conductive layer, wherein the first mask structure has a first etching pattern extending along a first direction; Forming a second mask structure on the first mask structure, wherein the second mask structure has a second etching pattern extending along a second direction, and the first direction and the second direction obliquely intersect; The intersecting portion of the projections of the first etched pattern and the second etched pattern in a direction perpendicular to the substrate is used as a capacitor receiving plate pattern, and the conductive layer is etched to form a plurality of capacitor receiving plates corresponding to a plurality of capacitor contacts one by one, and the capacitor receiving plates are tilted at a preset angle relative to the word line.

2. The method for forming a capacitor receiving plate according to claim 1, characterized in that: The specific steps of forming a conductive layer on the surface of the substrate include: forming an isolation layer covering the surface of the substrate, wherein the isolation layer has a plurality of contact windows exposing the capacitor contacts; A conductive layer is formed to fill the contact window and cover the top surface of the isolation layer.

3. The method for forming a capacitor receiving plate according to claim 2, characterized in that: The specific steps of forming a first mask structure on the surface of the conductive layer include: forming a first mask layer covering the surface of the conductive layer; forming a second mask layer covering a surface of the first mask layer; The second mask layer is etched to form a first trench that exposes the first mask layer and extends along a first direction, and the first trench is used as a first etching pattern.

4. The method for forming a capacitor receiving plate according to claim 3, characterized in that: The specific steps of forming a first trench exposing the first mask layer and extending along a first direction include: forming a third mask layer covering a surface of the second mask layer; forming a fourth mask layer covering the surface of the third mask layer; Forming a first photoresist layer on the surface of the fourth mask layer, wherein the first photoresist layer has a first opening that exposes the fourth mask layer and extends along a first direction; forming a first side wall covering the side wall of the first opening; The fourth mask layer, the third mask layer and the second mask layer are etched using the first sidewall as a mask to form the first trench.

5. The method for forming a capacitor receiving plate according to claim 3, characterized in that: The material of the first mask layer is nitride material, and the material of the second mask layer is polysilicon material.

6. The method for forming a capacitor receiving plate according to claim 3, characterized in that: The specific steps of forming the second mask structure on the first mask structure include: forming a fifth mask layer that fills the first etching structure and covers the top surface of the second mask layer; forming a sixth mask layer covering the fifth mask layer; forming a second photoresist layer on the surface of the sixth mask layer, wherein the second photoresist layer has a second opening exposing the sixth mask layer and extending along a second direction; forming a second side wall covering the side wall of the second opening; The second photoresist layer is removed, and a second groove extending along a second direction is formed between adjacent second sidewalls, and the second groove is used as a second etching pattern.

7. The method for forming a capacitor receiving plate according to claim 6, characterized in that: The specific steps of etching the conductive layer include: Removing the portion of the second mask layer other than the overlapping area with the projection of the second sidewall, the fifth mask layer, the sixth mask layer and the second sidewall, a capacitor receiving plate pattern is formed on the surface of the first mask layer; The conductive layer is etched using the capacitor receiving plate pattern as a mask pattern.

8. The method for forming a capacitor receiving plate according to claim 7, characterized in that: The surface of the conductive layer further includes a seventh mask layer, and the first mask structure is located on the surface of the seventh mask layer; the specific step of etching the conductive layer using the capacitor receiving plate pattern as a mask pattern also includes: Using the capacitor receiving plate pattern as a mask pattern and the isolation layer as an etching stop layer, the first mask layer, the seventh mask layer and the conductive layer are etched to form a plurality of capacitor receiving plates corresponding to a plurality of capacitor contacts.

9. The method for forming a capacitor receiving plate according to claim 8, characterized in that: The seventh mask layer is an organic mask layer.

10. The method for forming a capacitor receiving plate according to claim 1, characterized in that: The first direction is parallel to the word line, and the second direction is inclined by the preset angle relative to the word line direction; or, The first direction is a direction inclined by the preset angle relative to the word line direction, and the second direction is a direction parallel to the word line.

11. The method for forming a capacitor receiving plate according to claim 10, characterized in that: The preset angle is 60°.

12. A method for forming a semiconductor memory, characterized in that: The steps include: Providing a substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines; A plurality of capacitor receiving plates connected to the plurality of capacitor contacts in one-to-one correspondence are formed on the surface of the substrate, wherein the capacitor receiving plates are formed by the method for forming a capacitor receiving plate according to any one of claims 1 to 11; A plurality of capacitors are formed and connected to the plurality of capacitor receiving plates in a one-to-one correspondence.

13. The method for forming a semiconductor memory according to claim 12, wherein: The plurality of capacitor receiving plates are arranged in a hexagonal array.

14. A semiconductor memory, characterized in that: include: A substrate, the substrate comprising a substrate and a plurality of capacitor contacts located on a surface of the substrate, wherein the substrate has a plurality of word lines; A plurality of capacitor receiving plates are located on the surface of the substrate, the plurality of capacitor receiving plates are connected to the plurality of capacitor contacts in a one-to-one correspondence, and the capacitor receiving plates are inclined at a preset angle relative to the word lines; The substrate is one of a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) or a GOI (Germanium On Insulator).

15. The semiconductor memory according to claim 14, wherein: The plurality of capacitor receiving plates are arranged in a hexagonal array.

16. The semiconductor memory according to claim 14, wherein: The preset angle is 60°.

17. The semiconductor memory according to claim 14, wherein: Also includes: An isolation layer, located on the surface of the substrate, wherein the isolation layer has a plurality of contact windows exposing the capacitor contacts; The capacitor receiving plate fully fills the contact window, and the height of the capacitor receiving plate is greater than that of the isolation layer.

18. The semiconductor memory according to claim 14, wherein: The cross section of the capacitor receiving plate along a direction parallel to the base is elliptical.

19. The semiconductor memory according to claim 14, wherein: Also includes: A plurality of capacitors are electrically connected to the plurality of capacitor receiving plates in a one-to-one correspondence.

20. The semiconductor memory according to claim 14, wherein: Also includes: A plurality of bit lines are in a straight line shape, and the extending direction of the bit lines is perpendicular to the extending direction of the word lines.

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