Optoelectronic chip and method for preparing optoelectronic chip

Abstract

The present invention relates to the technical field of chip testing, and discloses an optoelectronic chip and a preparation method thereof. The optoelectronic chip includes: a first region, a second region, and a third region; wherein, the first region includes a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region includes a substrate, an epitaxial structure disposed on the substrate, and a first diffusion doping layer disposed on the epitaxial structure; the third region includes a substrate, an epitaxial structure disposed on the substrate, and a second diffusion doping layer disposed on the epitaxial structure; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other. By forming the first diffusion doping layer and the second diffusion doping layer, the performance and parameters of the optoelectronic chip are tested on the first diffusion doping layer, avoiding the inconvenience of detecting the performance of the optoelectronic chip due to the too large tip diameter of the probe or the probe being unable to directly detect the second diffusion region; improving the yield of the optoelectronic chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular, to an optoelectronic chip and a method for preparing the optoelectronic chip. Background Art

[0002] In the manufacturing process of optoelectronic detector chips, the diffusion process, as a key link directly affecting the performance of optoelectronic detector chips, usually requires measuring the diffusion depth of optoelectronic detector chips after diffusion. However, the operation of measuring the diffusion depth of optoelectronic detector chips is relatively complex and the accuracy is limited. Generally, other parameters are tested, for example, the diffusion depth of optoelectronic detector chips is determined by testing the magnitude of the breakdown voltage.

[0003] However, for high-speed optoelectronic detector chips with a rate above 25 Gbps, single-photon detector chips, or other optoelectronic chips with special requirements, usually due to their very small diffusion regions, after the optoelectronic chips are diffusion-doped, the probe test station cannot directly test the performance of the optoelectronic chips, such as the breakdown voltage, dark current, etc. In this case, there is often a great risk in proceeding with the next process for the optoelectronic chips, resulting in a low yield. Summary of the Invention

[0004] In order to solve the technical problems of inconvenient performance testing and low yield of optoelectronic chips in related technologies, the present invention provides an optoelectronic chip and a method for preparing the optoelectronic chip.

[0005] In a first aspect, the present invention provides an optoelectronic chip, including: a first region, a second region, and a third region; wherein, the first region includes a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region includes the substrate, the epitaxial structure disposed on the substrate, and a first diffusion doping layer disposed on the epitaxial structure; the third region includes the substrate, the epitaxial structure disposed on the substrate, and a second diffusion doping layer disposed on the epitaxial structure; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other.

[0006] Optionally, the number of the second regions is one or more; the number of the third regions is one.

[0007] Optionally, the second regions and the third region are distributed at intervals, and the shortest interval distance between the second regions and the third region is greater than 10 um.

[0008] Optionally, the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same.

[0009] Optionally, the surface area of the second region is larger than the surface area of the third region.

[0010] Optionally, the outer contour of the first diffusion doping layer is circular, and the outer contour of the second diffusion doping layer is circular; the diameter of the first diffusion doping layer is larger than the diameter of the second diffusion doping layer.

[0011] Optionally, the value range of the diameter of the first diffusion doping layer is 30 um to 50 um.

[0012] In a second aspect, the present invention further provides a method for manufacturing an optoelectronic chip, including:

[0013] Forming an epitaxial structure on a substrate;

[0014] Forming a masking film on the epitaxial structure;

[0015] Removing partial regions on the masking film to respectively form a first preset region and a second preset region;

[0016] Simultaneously performing diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, and the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other;

[0017] The substrate, the epitaxial structure, and the masking film constitute a first region, the substrate, the epitaxial structure, and the first diffusion doping layer constitute a second region, and the substrate, the epitaxial structure, and the second diffusion doping layer constitute a third region.

[0018] Optionally, the diffusion concentration of the first diffusion doping layer and the second diffusion doping layer is the same, and the diffusion depth of the first diffusion doping layer and the second diffusion doping layer is the same.

[0019] Optionally, the removing partial regions on the masking film includes removing partial regions on the masking film by photolithography.

[0020] The above technical solutions provided by the embodiments of the present invention have the following advantages compared with the prior art:

[0021] The embodiments of the present invention provide an optoelectronic chip and a method for testing the optoelectronic chip. By forming a first diffusion doping layer and a second diffusion doping layer, the performance and parameters of the optoelectronic chip are tested on the first diffusion doping layer, avoiding the inconvenience of detecting the performance of the optoelectronic chip due to the too large tip diameter of the probe or the probe being unable to directly detect the second diffusion region; and it can also reduce the risk caused by poor diffusion of the second diffusion doping layer and improve the yield of the optoelectronic chip. Description of the Drawings

[0022] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present invention and, together with the specification, used to explain the principles of the present invention.

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] In the accompanying drawings:

[0025] Figure 1 is a schematic structural diagram of an optoelectronic chip provided by an embodiment of the present invention;

[0026] Figure 2 is another schematic structural diagram of an optoelectronic chip provided by an embodiment of the present invention. Description of the drawings:

[0028] 100, optoelectronic chip; 110, first region; 120, second region; 130, third region. Detailed implementation manners

[0029] To have a clearer understanding of the technical features, objectives, and effects of the present invention, the following will now describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings. In the following description, it should be understood that the orientation or positional relationships indicated by "front", "rear", "upper", "lower", "left", "right", "longitudinal", "transverse", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail", etc. are based on the orientation or positional relationships shown in the accompanying drawings, with a specific orientation structure and operation, and are only for the convenience of describing the present technical solution, rather than indicating that the device or element referred to must have a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0030] It should also be noted that, unless otherwise clearly specified and limited, terms such as "installation", "connection", "linkage", "fixation", "setting" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. When a component is referred to as being "on" or "under" another component, the component can be "directly" or "indirectly" located above the other component, or there may also be one or more intermediate components. Terms such as "first", "second", "third", etc. are only for the convenience of describing the present technical solution, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third", etc. can explicitly or implicitly include one or more of such features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures, technologies, etc. are proposed to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0032] Referring to Figure 1 and Figure 2 , an optoelectronic chip 100 according to an embodiment of the present invention includes: a first region 110, a second region 120, and a third region 130; wherein, the first region 110 includes a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region 120 includes a substrate, an epitaxial structure disposed on the substrate, and a first diffusion doping layer disposed on the epitaxial structure; the third region 130 includes a substrate, an epitaxial structure, and a second diffusion doping layer; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other.

[0033] By forming the first diffusion doping layer and the second diffusion doping layer on the optoelectronic chip 100, the performance and parameters of the optoelectronic chip 100 are tested on the first diffusion doping layer, avoiding the influence on the performance detection of the optoelectronic chip 100 due to the too large tip diameter of the probe or the probe being unable to directly detect the second diffusion doping layer, which is not conducive to detecting the performance of the optoelectronic chip 100; and it can also reduce the risk caused by the poor diffusion of the second diffusion doping layer and improve the yield rate of the optoelectronic chip 100.

[0034] The first diffusion doping layer is a non-functional region and does not possess the performance of the optoelectronic chip 100. The second diffusion doping layer is a functional region and possesses the performance of the optoelectronic chip 100. Therefore, the larger the diameter of the second diffusion doping region, the greater the impact on the performance of the optoelectronic chip 100. The larger the diameter of the second diffusion doping region, the lower the performance of the optoelectronic chip 100. Therefore, generally, the diameter of the second diffusion doping region is less than 30 um. In this way, when testing the second diffusion doping region with a probe, due to the small diameter of the second diffusion doping region, it is difficult for the probe to detect the second diffusion doping layer, and thus the performance and parameters of the optoelectronic chip 100 cannot be measured. By using the first diffusion doping layer for detection, it is possible to avoid detecting the second diffusion doping region, thereby avoiding affecting the performance of the optoelectronic chip 100, and it is also possible to indirectly measure the relevant performance and parameters of the optoelectronic chip 100, reducing the risk caused by poor diffusion of the second diffusion doping region.

[0035] The diffusion concentration of the first diffusion doping layer and the second diffusion doping layer is the same, and the diffusion depth of the first diffusion doping layer and the second diffusion doping layer is the same. In this way, the performance and parameters of the optoelectronic chip 100 can be indirectly detected by detecting the first diffusion doping layer.

[0036] The number of the second regions 120 is one or more, and the number of the third regions 130 is one. Generally, only one third region 130 is provided, and the number of the second regions 120 can be one or more. The performance and parameters of the optoelectronic chip 100 can be measured through one second region 120.

[0037] The second regions 120 and the third regions 130 are spaced apart, and the shortest spacing between the second regions 120 and the third regions 130 is greater than 10 um. The greater the spacing between the first diffusion doping layer and the second diffusion doping layer, the better the performance of the optoelectronic chip 100. Generally, the first diffusion doping layer is provided at the four corners of the optoelectronic chip 100, so that electrodes or other patterns can be made near the second diffusion doping layer. If the spacing between the first diffusion doping layer and the second diffusion doping layer is less than 10 um, the first diffusion doping layer will affect the performance of the optoelectronic chip 100.

[0038] The substrate is an InP substrate. The masking film includes one or more of a SiO2 masking film or a SiN masking film. In a specific embodiment, the masking film includes a SiO2 masking film and a SiN masking film, and the combination of these two masking films makes the performance of the optoelectronic chip 100 better.

[0039] The epitaxial structure includes a buffer layer, an absorption layer, and a top layer arranged in sequence. The buffer layer is provided on the substrate, and the masking film is provided on the top layer. This can improve the performance of the optoelectronic chip 100.

[0040] The buffer layer is an N-type InP buffer layer, the absorption layer is an InGaAs absorption layer, and the top layer is an InP top layer.

[0041] The surface area of the second region 120 is larger than that of the third region 130. The second region 120 can test the parameters and performance of the optoelectronic chip 100. The larger surface area of the second region 120 than that of the third region 130 can make the probe test more convenient.

[0042] The outer contour of the first diffusion doping layer is circular, and the outer contour of the second diffusion doping layer is circular. Setting the outer contour of the first diffusion doping layer to be circular makes the outer contour of the first diffusion doping layer close to the true shape of the second diffusion doping layer, so that the measured parameters of the optoelectronic chip 100 will be closer and more real. The diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer, which is convenient for probing with a probe. The probe can more easily contact the first diffusion doping layer, and then detect the performance of the optoelectronic chip 100.

[0043] The first diffusion doping layer has a circular hole structure. The first diffusion doping layer can also be a rectangular structure. Usually, the outer contour of the tip of the probe is cylindrical or conical. In order to match the outer contour of the tip of the probe, the structure of the first diffusion doping layer can be set to a circular hole structure, so that the test effect of the optoelectronic chip 100 is better.

[0044] The diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer. The value range of the diameter of the first diffusion doping layer is 30um to 50um. Generally, the diameter of the tip of the probe is 30um. Setting the diameter of the first diffusion doping layer to be larger than the diameter of the tip of the probe can make the probe more easily detect the first diffusion doping layer and improve the yield of the optoelectronic chip 100.

[0045] Reference Figure 1 , Figure 1 is a schematic structural diagram of the optoelectronic chip 100 provided by a specific embodiment of the present invention. In the figure, the first region 110 is masked by a masking film and will not be diffused. The masking films of the second region 120 and the third region 130 are both etched. In the figure, the diameter of the second diffusion doping layer is very small, usually less than 20um, and it is difficult for the tip of the probe to detect the second diffusion region.

[0046] Reference Figure 2 , Figure 2It is a schematic structural diagram of the optoelectronic chip 100 provided by another specific embodiment of the present invention. The second diffusion doping layer is annular, and the tip of the probe cannot detect inside the second diffusion doping layer. Therefore, by providing a first diffusion doping layer with a diameter of 30 um to 50 um outside the second diffusion doping layer, the parameters and performance of the optoelectronic chip 100 are tested using the first diffusion doping layer. Of course, the diameter size of the first diffusion doping layer is not particularly limited, generally just larger than the diameter of the tip of the probe.

[0047] For the optoelectronic chip 100 provided by the embodiment of the present invention, the performance and parameters of the optoelectronic chip 100 are tested by detecting the first diffusion doping layer with a probe, and then the values of the dark current magnitude and breakdown voltage of the optoelectronic chip 100 are obtained, improving the yield of the optoelectronic chip 100.

[0048] The embodiment of the present invention also provides a preparation method of an optoelectronic chip 100, including the following steps:

[0049] Form an epitaxial structure on the substrate;

[0050] Form a masking film on the epitaxial structure;

[0051] Remove partial regions on the masking film to respectively form a first preset region and a second preset region;

[0052] Simultaneously perform diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, and the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other;

[0053] The substrate, the epitaxial structure, and the masking film constitute a first region 110, the substrate, the epitaxial structure, and the first diffusion doping layer constitute a second region 120, and the substrate, the epitaxial structure, and the second diffusion doping layer constitute a third region 130.

[0054] In the prior art when preparing the optoelectronic chip 100, generally only a second preset region is formed on the masking film by photolithography, and then diffusion doping is performed on the second preset region to form a second diffusion doping layer, and then the third region 130 is formed. After the optoelectronic chip 100 is prepared in this way, it is necessary to test the formed optoelectronic chip 100 to obtain the performance and parameters of the optoelectronic chip 100. However, it is very difficult to directly test the optoelectronic chip 100 with a probe after diffusion doping, while the preparation method of the optoelectronic chip 100 provided by the embodiment of the present invention can indirectly test and obtain the relevant performance and parameters of the optoelectronic chip 100 through the first diffusion doping layer.

[0055] Specifically, removing partial regions on the masking film includes removing partial regions on the masking film by photolithography. Photolithography is a conventional process, and the prepared optoelectronic chip 100 has good effects.

[0056] The substrate and the epitaxial structure are wafers for fabricating the optoelectronic chip 100 in the optoelectronic detector. The epitaxial structure is prepared by sequentially growing an N-type InP buffer layer, an InGaAs absorption layer, and an InP top layer on the InP substrate.

[0057] Specifically, the steps of lithography on the masking film generally include coating photoresist, exposure, development, and etching. Etching removes the parts not protected by the photoresist, and the areas protected by the photoresist cannot be etched. Thus, after removing the masking film on the second region 120 and the third region 130 by lithography, diffusion doping is simultaneously performed on the second region 120 and the third region 130 to form the first diffusion doping layer and the third diffusion doping layer.

[0058] The diffusion concentration of the first diffusion doping layer and the second diffusion doping layer is the same, and the diffusion depth of the first diffusion doping layer and the second diffusion doping layer is the same. In this way, the performance and parameters of the optoelectronic chip 100 can be indirectly detected by detecting the first diffusion doping layer.

[0059] The diameter of the first diffusion doping layer ranges from 30 um to 50 um, which facilitates the detection of the first diffusion doping layer by the probe.

[0060] It can be understood that the above embodiments only represent the preferred embodiments of the present invention, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention; it should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can also be made, which all belong to the protection scope of the present invention; therefore, all equivalent transformations and modifications made to the scope of the claims of the present invention shall fall within the scope covered by the claims of the present invention.

Claims

1. An optoelectronic chip, characterized in that, Including: A first region, a second region, and a third region; wherein, the first region includes a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region includes the substrate, the epitaxial structure disposed on the substrate, and a first diffusion doping layer disposed on the epitaxial structure; the third region includes the substrate, the epitaxial structure disposed on the substrate, and a second diffusion doping layer disposed on the epitaxial structure; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other; Wherein, the first diffusion doping layer is a non-functional region, the second diffusion doping layer is a functional region, the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same, and the diameter of the second diffusion doping layer is less than 30um.

2. The optoelectronic chip according to claim 1, wherein, The number of the second regions is one or more; the number of the third regions is one.

3. The optoelectronic chip according to claim 1, characterized in that, The second region and the third region are distributed at intervals, and the shortest interval distance between the second region and the third region is greater than 10um.

4. The optoelectronic chip according to claim 1, characterized in that, The surface area of the second region is greater than the surface area of the third region.

5. The optoelectronic chip according to claim 1, characterized in that, The outer contour of the first diffusion doping layer is circular, and the outer contour of the second diffusion doping layer is circular; the diameter of the first diffusion doping layer is greater than the diameter of the second diffusion doping layer.

6. The optoelectronic chip according to claim 5, wherein The value range of the diameter of the first diffusion doping layer is 30um to 50um.

7. A method for preparing an optoelectronic chip, characterized in that, Including: Forming an epitaxial structure on a substrate; Forming a masking film on the epitaxial structure; Removing partial regions on the masking film to respectively form a first preset region and a second preset region; Simultaneously performing diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, and the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other; The substrate, the epitaxial structure and the masking film constitute the first region, the substrate, the epitaxial structure, the first diffusion doping layer constitute the second region, and the substrate, the epitaxial structure and the second diffusion doping layer constitute the third region; Wherein, the first diffusion doping layer is a non-functional region, the second diffusion doping layer is a functional region, the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same, and the diameter of the second diffusion doping layer is less than 30um.

8. The manufacturing method of the optoelectronic chip according to claim 7, characterized in that, The removing partial regions on the masking film includes removing partial regions on the masking film by photolithography.

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