Data transmission circuit

Abstract

A data transmission circuit is improved to support a data transmission mode suitable for an interface or an application according to selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential drive signal, a second differential drive signal, and a pre-emphasis control signal by using a first differential data signal, a second differential data signal, and an option signal; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential drive signal and the second differential drive signal; and a pre-emphasis driver configured to perform pre-emphasis of different amplification degrees on the first differential transmission signal and the second differential transmission signal in a first mode and a second mode by the pre-emphasis control signal.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to a data transmission circuit, and more particularly, to a data transmission circuit improved to support a data transmission mode suitable for an interface or an application according to selection of options. BACKGROUND

[0002] Generally, a display device includes a data transmission circuit such as a timing controller and a data reception circuit such as a source driver.

[0003] A data transmission scheme therebetween can be implemented in various ways according to an interface or an application. As a data transmission scheme, a low voltage differential signaling (LVDS) scheme and a current mode logic (CML) scheme can be exemplified.

[0004] The data transmission circuit should output transmission data in a scheme in which the data reception circuit can receive the transmission data. For example, in a case where a driver as the data reception circuit is capable of receiving transmission data of an LVDS scheme, the transmission data should be output from the data transmission circuit in the LVDS scheme. Also, in a case where the driver is capable of receiving transmission data of a CML scheme, the transmission data should be output from the data transmission circuit in the CML scheme.

[0005] The data transmission circuit needs to have a combined function compatible with an interface or an application, needs to be designed to be capable of supporting a plurality of data transmission schemes through the combined function, and to output transmission data in a selected data transmission scheme. SUMMARY

[0006] Various embodiments relate to a data transmission circuit capable of outputting transmission signals in a data transmission scheme according to selected options, thereby having compatibility with an interface or an application.

[0007] In one embodiment, the data transmission circuit can include a pre-driver configured to output first and second differential drive signals by using first and second differential data signals, and a main driver configured to output first and second differential transmission signals by using the first and second differential drive signals, wherein the main driver performs high-level output and low-level output corresponding to a first mode by using first high-level output circuitry and low-level output circuitry operated by the first and second differential drive signals, wherein the main driver performs high-level output and low-level output corresponding to a second mode by using second high-level output circuitry using an internal termination resistor and low-level output circuitry operated by the first and second differential drive signals, and wherein the main driver includes a current source that provides current paths having different current capacities to the low-level output circuitry shared by the first and second high-level output circuitry according to the modes.

[0008] In one embodiment, the data transmission circuit can include a pre-driver configured to output first and second differential drive signals, and a pre-emphasis control signal by using first and second differential data signals and an option signal, a main driver configured to output first and second differential transmission signals by using the first and second differential drive signals, and a pre-emphasis driver configured to perform pre-emphasis of different amplification degrees on the first and second differential transmission signals in first and second modes by the pre-emphasis control signal, wherein the main driver performs high-level output and low-level output corresponding to the first mode by using first high-level output circuitry and low-level output circuitry operated by the first and second differential drive signals, wherein the main driver performs high-level output and low-level output corresponding to the second mode by using second high-level output circuitry using an internal termination resistor and low-level output circuitry operated by the first and second differential drive signals, and wherein the main driver includes a current source that provides current paths having different current capacities to the low-level output circuitry shared by the first and second high-level output circuitry according to the modes.

[0009] According to embodiments of the present disclosure, an option can be selected in consideration of an interface or an application, and a combined function for outputting transmission signals in a mode according to the option can be provided.

[0010] Therefore, the data transmission circuit according to embodiments of the present disclosure can be compatible with an interface or an application.

[0011] Further, according to embodiments of the present disclosure, LVDS mode and CML mode can be supported by selection, the size of a chip can be reduced by sharing some circuits, and current paths having different current capacities can be provided according to a change in mode and whether pre-emphasis is applied. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example of a data transmission circuit according to embodiments of the present disclosure.

[0013] Figure 2 is a detailed circuit diagram illustrating an example of a pre-driver shown in Figure 1

[0014] Figure 3 is a detailed circuit diagram of Figure 2

[0015] Figure 4 is a detailed circuit diagram illustrating an example of a combination state of a main driver and a pre-emphasis circuit shown in Figure 1

[0016] Figure 5 is a detailed circuit diagram illustrating an example of a combination state of a main driver and a pre-emphasis circuit shown in Figure 1

[0017] Figure 6 is a detailed circuit diagram illustrating an example of a state in which a data transmission circuit according to embodiments of the present disclosure operates in an LVDS mode.

[0018] Figure 7 is a detailed circuit diagram illustrating an example of a state in which a data transmission circuit according to embodiments of the present disclosure operates in a CML mode. DETAILED DESCRIPTION

[0019] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings; however, they are not intended to limit the present disclosure to particular embodiments. Rather, the present disclosure will be described so that one of ordinary skill in the art can embody the present disclosure and with reference thereto, the scope of the present disclosure will be sufficiently conveyed. Throughout the disclosure, like reference numerals refer to like elements throughout the several drawings and embodiments of the present disclosure.

[0020] A display apparatus displays an image through a display panel, and includes a driver for driving the display panel and a timing controller for providing display data to the driver.

[0021] The driver and the timing controller can be respectively configured by separate chips. Among them, the timing controller corresponds to a data transmission circuit, and the driver corresponds to a data reception circuit.

[0022] ​​​​An interface scheme between the data transmission circuit and the data reception circuit can be limited to a specific scheme, such as a low voltage differential signaling (LVDS) scheme or a current mode logic (CML) scheme. Also, the data reception circuit can be configured to recover a signal in a specific scheme, such as an LVDS scheme or a CML scheme. The LVDS scheme or the CML scheme is an interface scheme that transmits a differential signal, and a signal output from the data transmission circuit through the LVDS scheme or the CML scheme can be defined as a differential transmission signal.

[0023] The data transmission circuit implemented through the present disclosure supports a plurality of data transmission schemes, is configured to be able to select a combination type of the data transmission schemes, and has compatibility with an interface scheme or an application.

[0024] Embodiments of the data transmission circuit of the present disclosure are configured to be able to select one of two data transmission modes through an option. The two data transmission modes can be exemplarily defined as modes requiring different current capacities. As the two data transmission modes, an LVDS mode and a CML mode can be exemplified. For convenience of explanation, the LVDS mode is defined as a first mode, and the CML mode is defined as a second mode.

[0025] Reference Figure 1 The data transmission circuit according to the embodiments of the present disclosure is shown to include a pre-driver 100, a main driver 200, and a pre-emphasis driver 300.

[0026] The pre-driver 100 is configured to receive first and second differential data signals DP and DN, and option signals DP_D and DN_D, and output first and second differential driving signals INP and INN, and pre-emphasis control signals INP_L, INN_L, INP_D_L, INN_D_L, INP_D_C, and INN_D_C.

[0027] The main driver 200 is configured to receive the first and second differential driving signals INP and INN, and output first and second differential transmission signals OUTP and OUTN.

[0028] The pre-emphasis driver 300 is configured to receive the pre-emphasis control signals INP_L, INN_L, INP_D_L, INN_D_L, INP_D_C, and INN_D_C, and perform pre-emphasis on the first and second differential transmission signals OUTP and OUTN.

[0029] The present disclosure can be configured to further include an external memory (not shown) that stores the option signals for selecting the options, and the external memory can be implemented by a memory such as an EEPROM configured separately from the data transmission circuit. The external memory can be configured to provide the option signals for selecting the modes according to the request of the data transmission circuit.

[0030] In Figure 1 and Figure 2 , DP_D and DN_D are shown as the option signals. However, the present disclosure is not limited thereto. The option signals can include an enable signal EN and ENB for identifying the first mode and the second mode, an enable signal PE_EN and PE_ENB for controlling the pre-emphasis, and a switching signal MS and MS_PE for switching the control according to the second mode or the pre-emphasis. Figure 1 and Figure 2 DP_D and DN_D representing the option signals are shown, and Figure 3 to Figure 7 various option signals in each component are shown.

[0031] Hereinafter, the configuration of each driver will be described in more detail.

[0032] Figure 2 and Figure 3 a detailed block diagram and a detailed circuit diagram of the pre-driver 100 of Figure 1 are shown, respectively.

[0033] The pre-driver 100 is configured to receive a first differential data signal DP, a second differential data signal DN, and option signals DP_D and DN_D.

[0034] Further, the pre-driver 100 is configured to output a first differential driving signal INP and a second differential driving signal INN by using the first differential data signal DP and the second differential data signal DN. Further, the pre-driver 100 is configured to output pre-emphasis control signals INP_L, INN_L, INP_D_L, INN_D_L, INP_D_C, and INN_D_C by using the first differential data signal DP, the second differential data signal DN, and the option signals DP_D and DN_D.

[0035] Among the pre-emphasis control signals INP_L, INN_L, INP_D_L, INN_D_L, INP_D_C, and INN_D_C, the pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L are used for the first mode in a manner of being activated in the first mode, and the pre-emphasis control signals INP_D_C and INN_D_C are used for the second mode in a manner of being activated in the second mode.

[0036] More specifically, the pre-driver 100 includes an LVDS pre-driver 10 and a CML pre-driver 12 as shown in Figure 2 The LVDS pre-driver 10 can be understood as a first mode pre-driver, and the CML pre-driver 12 can be understood as a second mode pre-driver.

[0037] The LVDS pre-driver 10 and the CML pre-driver 12 can determine whether to apply the first mode, the second mode, and pre-emphasis by the above option signal including the option signals DP_D and DN_D.

[0038] The LVDS pre-driver 10 is enabled corresponding to the first mode, amplifies the first and second differential data signals DP and DN to satisfy the first specification, and outputs the first and second differential drive signals INP and INN. The LVDS pre-driver 10 outputs pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L for pre-emphasis corresponding to the first and second differential data signals DP and DN and the option signals DP_D and DN_D.

[0039] The CML pre-driver 12 is enabled in response to the second mode, amplifies the first and second differential data signals DP and DN to satisfy the second specification, and outputs the first and second differential drive signals INP and INN. The CML pre-driver 12 outputs pre-emphasis control signals INP_D_C and INN_D_C for pre-emphasis corresponding to the option signals DP_D and DN_D.

[0040] In the above description, the first and second specifications mean restrictions on voltage characteristics and current characteristics defined in the respective modes. The amplification in the LVDS pre-driver 10 and the CML pre-driver 12 can include transferring a signal by maintaining a level of an original signal through buffering.

[0041] Reference Figure 3 Detailed configurations of the LVDS pre-driver 10 and the CML pre-driver 12 will be described.

[0042] The LVDS pre-driver 10 includes inverters A1 and A2 configured by amplifiers to output the first differential drive signal INP corresponding to the first differential data signal DP.

[0043] The inverter A1 is used to invert and amplify an input, and the inverter A2 is used to invert and amplify an input. The operation of the inverter A2 can be enabled or disabled according to the states of the enable signals EN and ENB. The inverter A2 can be understood as being enabled in the first mode. With the above configuration, the first differential data signal DP can be amplified by the inverters A1 and A2, and the first differential drive signal INP can be output from the inverter A2. In the second mode, the output of the first differential drive signal INP is disabled.

[0044] The LVDS pre-driver 10 includes inverters A3 and A4 configured by amplifiers to output a second differential drive signal INN corresponding to a second differential data signal DN.

[0045] The inverter A3 is used to invert and amplify an input, and the inverter A4 is used to invert and amplify an input. The operation of the inverter A4 can be enabled or disabled according to the states of the enable signals EN and ENB. The inverter A4 can be understood as being enabled in the first mode. With the above configuration, the second differential data signal DN can be amplified by the inverters A3 and A4, and the second differential drive signal INN can be output from the inverter A4. In the second mode, the output of the second differential drive signal INN is disabled.

[0046] The LVDS pre-driver 10 includes inverters P1 and P2 and an output circuit D1 to output a pre-emphasis control signal INP_L corresponding to the first differential data signal DP.

[0047] The inverter P1 is used to invert and amplify an input, and the inverter P2 is used to invert and amplify an input. The operation of the inverter P2 can be enabled or disabled according to the states of the pre-emphasis enable signals PE_EN and PE_ENB. The inverter P2 can be understood as being enabled in the case where pre-emphasis is applied to the first differential transmission signal OUTP and the second differential transmission signal OUTN.

[0048] The output circuit D1 includes a PMOS transistor T1 for high-level output and a PMOS transistor T2 for low-level output. The output circuit D1 drives the output of the inverter P2 applied to a node between the transistors T1 and T2 by a high-level output drive signal PE_EN_IN and a low-level output drive signal EVSS, and outputs the pre-emphasis control signal INP_L. With the above configuration, the first differential data signal DP can be amplified by the inverters P1 and P2 and driven by the output circuit D1, as a result, the pre-emphasis control signal INP_L can be output from the output circuit D1.

[0049] The LVDS pre-driver 10 includes inverters P3 and P4 and an output circuit D2 to output a pre-emphasis control signal INN_L corresponding to the second differential data signal DN. The LVDS pre-driver 10 includes inverters P5 and P6 and an output circuit D3 to output a pre-emphasis control signal INP_D_L corresponding to the option signal DP_D. The LVDS pre-driver 10 includes inverters P7 and P8 and an output circuit D4 to output a pre-emphasis control signal INN_D_L corresponding to the option signal DN_D.

[0050] In the above configuration, since the inverters P3 and P4; P5 and P6; P7 and P8 are configured in the same manner as the inverters P1 and P2, a repeated description thereof is omitted. The output circuits D2 and D4 differ from the output circuit D1 in that they output the pre-emphasis control signals INN_L and INN_D_L that swing between a high level and a low level by the drive signal EVDD and the pre-emphasis enable signal PE_ENB. The output circuit D3 differs from the output circuit D1 in that it outputs the pre-emphasis control signal INP_D_L.

[0051] The CML pre-driver 12 includes two-stage amplifiers 13 and 15. The two-stage amplifiers 13 and 15 are enabled corresponding to the second mode, and are configured to differentially amplify the first differential data signal DP and the second differential data signal DN, and output a first differential drive signal INP and a second differential drive signal INN. Further, the CML pre-driver 12 includes two-stage amplifiers 14 and 16. The two-stage amplifiers 14 and 16 are enabled corresponding to the second mode, and are configured to differentially amplify the option signals DP_D and DN_D, and output pre-emphasis control signals INP_D_C and INN_D_C for pre-emphasis.

[0052] The amplifier 13 includes a PMOS transistor Q1, a resistor R1, and an NMOS transistor Q2 connected in series. The amplifier 13 includes a PMOS transistor Q3, a resistor R2, and an NMOS transistor Q4 connected in series. The amplifier 13 includes a drive NMOS transistor Q5 connected to the NMOS transistors Q2 and Q4. Among them, the PMOS transistors Q1 and Q3 are configured to be controlled by the enable signal ENB to transfer the operating voltage AVDD to the respective resistors R1 and R2 in the second mode, and the NMOS transistor Q5 is configured to be controlled by the bias control signal IBIAS to apply the ground voltage AVSS to the NMOS transistors Q2 and Q4.

[0053] The amplifier 15 includes a PMOS transistor Q6, a resistor R3, and an NMOS transistor Q7 connected in series. The amplifier 15 includes a PMOS transistor Q8, a resistor R4, and an NMOS transistor Q9 connected in series. The amplifier 15 includes a driving NMOS transistor Q10 connected to the NMOS transistors Q7 and Q9. Since the structure of the amplifier 15 is the same as that of the amplifier 13, a repetitive description thereof is omitted.

[0054] The amplifier 13 configured as described above performs differential amplification by the first differential data signal DP and the second differential data signal DN applied to the NMOS transistors Q2 and Q4 in the second mode. The voltage of the node between the resistor R1 and the NMOS transistor Q2 is applied to the gate of the NMOS transistor Q7 of the amplifier 15, and the voltage of the node between the resistor R2 and the NMOS transistor Q4 is applied to the gate of the NMOS transistor Q9 of the amplifier 15. The amplifier 15 performs differential amplification in the same manner as the amplifier 13 in the second mode, thereby outputting the first differential driving signal INP through the node between the resistor R3 and the NMOS transistor Q7, and the second differential driving signal INN through the node between the resistor R4 and the NMOS transistor Q9.

[0055] The amplifier 14 includes a PMOS transistor Q11, a resistor R11, and an NMOS transistor Q12 connected in series. The amplifier 14 includes a PMOS transistor Q13, a resistor R12, and an NMOS transistor Q14 connected in series. The amplifier 14 includes a driving NMOS transistor Q15 connected to the NMOS transistors Q12 and Q14.

[0056] The amplifier 16 includes a PMOS transistor Q16, a resistor R13, and an NMOS transistor Q17 connected in series. The amplifier 16 includes a PMOS transistor Q18, a resistor R14, and an NMOS transistor Q19 connected in series. The amplifier 16 includes a driving NMOS transistor Q20 connected to the NMOS transistors Q17 and Q19. Since the structures of the amplifiers 14 and 16 are the same as those of the amplifiers 13 and 15, a repetitive description thereof is omitted.

[0057] The amplifiers 14 and 16 differentially amplify the option signals DP_D and DN_D in two stages corresponding to the second mode, and then output the option signals DP_D and DN_D as the pre-emphasis control signals INP_D_C and INN_D_C.

[0058] The main driver 200 will be described below with reference to Figure 4 FIG. 1.

[0059] The main driver 200 receives the first differential drive signal INP and the second differential drive signal INN supplied from the LVDS pre-driver 10 in the first mode, or receives the first differential drive signal INP and the second differential drive signal INN supplied from the CML pre-driver 12 in the second mode. The main driver 200 outputs the first differential transmission signal OUTP and the second differential transmission signal OUTN by using the first differential drive signal INP and the second differential drive signal INN.

[0060] More specifically, the main driver 200 performs high-level output and low-level output corresponding to the first mode by using the first high-level output circuit 30 and the low-level output circuit 32 operated by the first differential drive signal INP and the second differential drive signal INN. In addition, the main driver 200 performs high-level output and low-level output corresponding to the second mode by the second high-level output circuit 60 using the internal termination resistors R32 and R33 and the low-level output circuit 32 operated by the first differential drive signal INP and the second differential drive signal INN.

[0061] The main driver 200 can include a current source that provides a current path having a different current capacity to the low-level output circuit 32 according to the mode, the current path being shared by the first high-level output circuit 30 and the second high-level output circuit 60. The current source can be understood to include a first current source 40 and a second current source 70 connected to the low-level output circuit 32. The first current source 40 provides a first current path having a first current capacity to the low-level output circuit 32. The second current source 70 is enabled in the second mode and provides a second current path having a second current capacity to the low-level output circuit 32 in parallel with the first current source 40.

[0062] In the above-described configuration, the second high-level output circuit 60 has a fixed high-level output capacity determined by the internal termination resistors R32 and R33.

[0063] The configuration of the main driver 200 will be described in more detail below.

[0064] The main driver 200 includes the first high-level output circuit 30, the feedback circuit 20, the second high-level output circuit 60, the low-level output circuit 32, the current source including the first current source 40 and the second current source 70, and the bias signal providing unit 50.

[0065] In the main driver 200, the operating voltage AVDD is used as a high-level output voltage, and the ground voltage AVSS is used as a low-level output voltage. In the following description, the operating voltage AVDD is described as the high-level output voltage AVDD, and the ground voltage AVSS is described as the low-level output voltage AVSS.

[0066] In the first mode, the first high-level output circuit 30 receives the high-level output voltage AVDD through the feedback circuit 20 and performs a high-level output operation through the first differential driving signal INP and the second differential driving signal INN. To this end, the first high-level output circuit 30 includes a PMOS transistor Q33 and a PMOS transistor Q32, in which the PMOS transistor Q33 receives the high-level output voltage AVDD and is operated by the first differential driving signal INP, and the PMOS transistor Q32 receives the high-level output voltage AVDD in parallel with the PMOS transistor Q33 and is operated by the second differential driving signal INN.

[0067] The feedback circuit 20 feeds back the first differential transmission signal OUTP and the second differential transmission signal OUTN, and in the second mode in which the feedback voltage is higher than the reference voltage VCM, the high-level output voltage AVDD is prevented from being applied to the first high-level output circuit 30.

[0068] To this end, the feedback circuit 20 includes resistors R41 and R42, a comparator 22, and a PMOS transistor Q31. The resistor R41 is connected to a first node N1 formed at the drain of the PMOS transistor Q32, and is applied with the first differential transmission signal OUTP output from the first node N1. The resistor R42 is connected to a second node N2 formed at the drain of the PMOS transistor Q33, and is applied with the second differential transmission signal OUTN output from the second node N2. The comparator 22 is configured to have a positive input terminal (+), a negative input terminal (-), and an output terminal, the reference voltage VCM is applied to the positive input terminal (+), the feedback voltage fed back through the resistor R41 and the resistor R42 is applied to the negative input terminal (-), and the output terminal outputs a comparison signal PB to the gate of the PMOS transistor Q31.

[0069] The feedback voltage can be understood as a voltage applied through the resistors R41 and R42 connected in parallel. The switching of the PMOS transistor Q31 is controlled by the comparison signal PB, and switching of the transfer of the high-level output voltage AVDD to the first high-level output circuit 30 is performed.

[0070] Through the above configuration, in the case of the first mode in which the reference voltage VCM is higher than the feedback voltage, the feedback circuit 20 turns on the PMOS transistor Q31 and transfers the high-level output voltage AVDD to the first high-level output circuit 30, and in the case of the second mode in which the feedback voltage is higher than the reference voltage VCM, the PMOS transistor Q31 is turned off and the transfer of the high-level output voltage AVDD to the first high-level output circuit 30 is prevented.

[0071] The second high-level output circuit 60 includes PMOS transistors Q61 and internal termination resistors R32 and R33, and is configured to perform a high-level output operation using the internal termination resistors R32 and R33, and in the second mode, the PMOS transistor Q61 is turned on, so a high-level output voltage AVDD is applied to the internal termination resistors R32 and R33.

[0072] The operation of the PMOS transistor Q61 is controlled by a switching signal MS applied to its gate. In the case of the second mode, the switching signal MS is kept low and turns on the PMOS transistor Q61, while in the case of the first mode, it is kept high and turns off the PMOS transistor Q61.

[0073] The internal termination resistor R32 is connected to the first node N1, and the internal termination resistor R33 is connected to the second node N2. The second high-level output circuit 60 has a fixed output capacity determined by the internal termination resistors R32 and R33 having fixed resistance values, so it is advantageous for high-speed operation.

[0074] The low-level output circuit 32 is shared by the first high-level output circuit 30 and the second high-level output circuit 60 through the first node N1 and the second node N2. The low-level output circuit 32 performs a low-level output operation by a first differential drive signal INP and a second differential drive signal INN.

[0075] To this end, the low-level output circuit 32 includes NMOS transistors Q52 and Q53 configured in parallel. The NMOS transistor Q52 is configured to have a drain commonly connected with the drain of the PMOS transistor Q32 and the internal termination resistor R32 through the first node N1, and a gate to which the second differential drive signal INN is applied. The NMOS transistor Q53 is configured to have a drain commonly connected with the drain of the PMOS transistor Q33 and the internal termination resistor R33 through the second node N2, and a gate to which the first differential drive signal INP is applied.

[0076] The NMOS transistor Q52 and the NMOS transistor Q53 are configured such that they are driven by the first differential drive signal INP and the second differential drive signal INN to output a low level, and their sources are connected to the first current source 40 and the second current source 70.

[0077] The current source is configured to provide a current path having different current capacities corresponding to the first mode and the second mode to the low-level output circuit 32. To this end, the current source includes the first current source 40 and the second current source 70. In order to operate the first current source 40 and the second current source 70, a bias signal providing unit 50 that provides a bias signal NBIAS is configured.

[0078] The first current source 40 includes an NMOS transistor Q51 to which a bias signal NBIAS is applied to a gate thereof. The NMOS transistor Q51 is commonly connected to a source of the NMOS transistor Q52 and a source of the NMOS transistor Q53 of the low-level output circuit 32 and provides a current path to the low-level output circuit 32 by turning on. The first current source 40 provides the current path by remaining in an on state in both the first mode and the second mode.

[0079] The second current source 70 includes a PMOS transistor Q62 to which a switching signal MS is applied to a gate thereof and an NMOS transistor Q63 for providing a current path to the low-level output circuit 32. The switching signal MS turns on the PMOS transistor Q62 in the second mode. If the PMOS transistor Q62 is turned on, the NMOS transistor Q63 is turned on by a bias signal NBIAS applied to a gate thereof, thereby providing the current path. The second current source 70 is turned off in the first mode and turned on in the second mode, thereby providing the current path formed in parallel with the current path of the first current source 40.

[0080] The bias signal providing unit 50 is configured to include the NMOS transistor Q70. The NMOS transistor Q70 is configured such that a bias control signal IBIAS is provided to a drain thereof and the drain and a gate thereof are connected, and the bias signal NBIAS is provided to the first current source 40 and the second current source 70.

[0081] A pre-emphasis driver 300 according to an embodiment of the present disclosure will be described below with reference to Figure 5 Figure 1 The pre-emphasis driver 300 performs pre-emphasis of different amplification degrees on the first differential transmission signal OUTP and the second differential transmission signal OUTN in the first mode and the second mode by the pre-emphasis control signals INP_L, INN_L, INP_D_L, INN_D_L, INP_D_C, and INN_D_C.

[0082] The pre-emphasis driver 300 is configured to include a first bias circuit 80 for pre-emphasis, a second bias circuit 82, an amplification circuit 90, and a third current source 72.

[0083] The amplification circuit 90 includes a first amplification circuit for pre-emphasis in the first mode and a second amplification circuit for pre-emphasis in the second mode.

[0084] The pre-emphasis driver 300 is configured to include a first bias circuit 80 for pre-emphasis, a second bias circuit 82, an amplification circuit 90, and a third current source 72.

[0085] ​First, when pre-emphasis is enabled, the first bias circuit 80 transmits a high-level output voltage AVDD to the first amplification circuit of the amplification circuit 90.

[0086] To this end, the first bias circuit 80 includes an NMOS transistor Q72 and a PMOS transistor Q71, in which the NMOS transistor Q72 switches transmission of a bias signal PBIAS by an enable signal PE_EN for controlling pre-emphasis, and the PMOS transistor Q71 is turned on when the bias signal PBIAS is applied to the gate thereof, thereby transmitting a high-level output voltage AVDD to the amplification circuit 90. The PMOS transistor Q71 of the first bias circuit 80 is configured to be commonly connected with the PMOS transistor Q80 and the PMOS transistor Q90 of the amplification circuit 90, and to transmit the high-level output voltage AVDD. As the bias signal PBIAS is transmitted to the gate of the PMOS transistor Q71 by activation of the enable signal PE_EN, pre-emphasis in the first bias circuit 80 is enabled.

[0087] When pre-emphasis is enabled, the second bias circuit 82 transmits a low-level output voltage AVSS to the first amplification circuit and the second amplification circuit of the amplification circuit 90.

[0088] To this end, the second bias circuit 82 includes a PMOS transistor Q74 and an NMOS transistor Q73, in which the PMOS transistor Q74 switches transmission of a bias signal NBIAS by an enable signal PE_ENB for controlling pre-emphasis, and the NMOS transistor Q73 is turned on when the bias signal NBIAS is applied to the gate thereof, thereby transmitting a low-level output voltage AVSS to the amplification circuit 90. The NMOS transistor Q73 of the second bias circuit 82 is configured to be commonly connected with the NMOS transistor Q83 and the NMOS transistor Q93 of the amplification circuit 90, and to transmit the low-level output voltage AVSS. As the bias signal NBIAS is transmitted to the gate of the NMOS transistor Q73 by activation of the enable signal PE_ENB, pre-emphasis in the second bias circuit 82 is enabled.

[0089] The first amplification circuit of the amplification circuit 90 is configured by a differential amplification circuit in the first mode, and is configured to amplify a first differential transmission signal OUTP and a second differential transmission signal OUTN to a first amplification degree by first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L. The first amplification circuit includes transistors Q80 to Q85 and Q90 to Q95 therein, in which the gates of the transistors Q80 to Q85 and Q90 to Q95 are applied with the first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L.

[0090] More specifically, the PMOS transistor Q80 whose gate is applied with the first pre-emphasis control signal INN_L and the PMOS transistor Q81 whose gate is applied with the first pre-emphasis control signal INP_D_L are configured in series for high level output, and the NMOS transistor Q82 whose gate is applied with the first pre-emphasis control signal INP_D_L and the NMOS transistor Q83 whose gate is applied with the first pre-emphasis control signal INN_L are configured in series for low level output. Further, the PMOS transistor Q84 and the NMOS transistor Q85 connected in series are configured between the node between the PMOS transistor Q80 and the PMOS transistor Q81 and the node between the NMOS transistor Q82 and the NMOS transistor Q83, and the first pre-emphasis control signal INN_D_L is applied to the gate of the PMOS transistor Q84 and the gate of the NMOS transistor Q85.

[0091] The PMOS transistor Q90 whose gate is applied with the first pre-emphasis control signal INP_L and the PMOS transistor Q91 whose gate is applied with the first pre-emphasis control signal INN_D_L are configured in series for high level output, and the NMOS transistor Q92 whose gate is applied with the first pre-emphasis control signal INN_D_L and the NMOS transistor Q93 whose gate is applied with the first pre-emphasis control signal INP_L are configured in series for low level output. Further, the PMOS transistor Q94 and the NMOS transistor Q95 connected in series are configured between the node between the PMOS transistor Q90 and the PMOS transistor Q91 and the node between the NMOS transistor Q92 and the NMOS transistor Q93, and the first pre-emphasis control signal INP_D_L is applied to the gate of the PMOS transistor Q94 and the gate of the NMOS transistor Q95.

[0092] The PMOS transistor Q84, the NMOS transistor Q85, the PMOS transistor Q94, and the NMOS transistor Q95 should be cross-coupled for amplification. To this end, the node between the PMOS transistor Q84 and the NMOS transistor Q85 and the node between the PMOS transistor Q94 and the NMOS transistor Q95 are electrically connected.

[0093] In the above configuration, the node between the PMOS transistor Q81 and the NMOS transistor Q82 is connected to the first node N1, and the node between the PMOS transistor Q91 and the NMOS transistor Q92 is connected to the second node N2.

[0094] As a result, the first amplification circuit of the amplification circuit 90 performs pre-emphasis of the first mode by differentially amplifying the first differential transmission signal OUTP and the second differential transmission signal OUTN to the first amplification degree by the first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L.

[0095] The second amplification circuit of the amplification circuit 90 is configured to amplify the first differential transmission signal OUTP and the second differential transmission signal OUTN to the second amplification degree by the second pre-emphasis control signals INP_D_C and INN_D_C in the second mode.

[0096] The second amplification circuit includes an NMOS transistor Q88 connected to the first node N1 and an NMOS transistor Q98 connected to the second node N2.

[0097] In the above configuration, the NMOS transistor Q88 is connected to the first node N1, and the NMOS transistor Q98 is connected to the second node N2.

[0098] As a result, the second amplification circuit of the amplification circuit 90 performs pre-emphasis of the second mode by differentially amplifying the first differential transmission signal OUTP and the second differential transmission signal OUTN to the second amplification degree by the second pre-emphasis control signals INP_D_C and INN_D_C.

[0099] In the case where the pre-emphasis function is enabled in the second mode, the third current source 72 is connected to the low-level output circuit 32 to enhance the current capacity.

[0100] The third current source 72 is used to provide a third current path having a third current capacity to the low-level output circuit 32 in parallel with the first current source 40.

[0101] The third current source 72 includes a PMOS transistor Q76 whose gate is applied with a switching signal MS_PE, and an NMOS transistor Q75 for providing a current path to the low-level output circuit 32. In the case where the pre-emphasis function is performed in the second mode, the switching signal MS_PE turns on the PMOS transistor Q76. If the PMOS transistor Q76 is turned on, the NMOS transistor Q75 is turned on by a bias signal NBIAS applied to its gate, thereby providing a current path. The third current source 72 is turned on in the case where the pre-emphasis function is performed in the second mode, thereby providing a current path formed in parallel with the current path of the first current source 40.

[0102] By the above configuration, an embodiment according to the present disclosure can perform an operation of outputting the first differential transmission signal OUTP and the second differential transmission signal OUTN corresponding to the first differential data signal DP and the second differential data signal DN in the LVDS mode (first mode) or the CML mode (second mode).

[0103] The above-described modes can be selected by an option signal provided from a memory, and the data transmission circuit implemented by the present disclosure can perform the selected mode in a combination type by considering the option signal provided by the interface and the application.

[0104] First, the case where the data transmission circuit operates in an LVDS mode (first mode) will be described below. Figure 6

[0105] In the first mode, the NMOS transistor Q61 and the PMOS transistor Q62 of the second high-level output circuit 60 of the second current source 70 of the main driver 200 are cut off by the switching signal MS.

[0106] Therefore, in the first mode, the main driver 200 can then perform an operation of outputting the first differential transmission signal OUTP and the second differential transmission signal OUTN by the first high-level output circuit 30 and the low-level output circuit 32. The current path for the operation of the low-level output circuit 32 can be provided by the first current source 40 as a first current capacity. The first current capacity can be understood as a current capacity required in the first mode.

[0107] In the case where the pre-emphasis function is selected in the first mode, the pre-emphasis driver 300 performs pre-emphasis of amplifying the first differential transmission signal OUTP and the second differential transmission signal OUTN to a first amplification degree by the first amplification circuit of the amplification circuit 90 operated by the first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L. At this time, the transistors Q80 to Q85 and Q90 to Q95 included in the first amplification circuit are activated by the first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L, and the transistors Q88 and Q98 included in the second amplification circuit are in a cut-off state.

[0108] Second, the case where the data transmission circuit operates in a CML mode (second mode) will be described below. Figure 7

[0109] In the second mode, the NMOS transistor Q61 of the second high-level output circuit 60 and the PMOS transistor Q62 of the second current source 70 of the main driver 200 are turned on by the switching signal MS. That is, the second high-level output circuit 60 and the second current source 70 are activated.

[0110] ​​In the case of the CML mode, the voltages formed at the first node N1 and the second node N2 of the main driver 200 are higher than the reference voltage VCM. Accordingly, in the feedback circuit 20, the PMOS transistor Q31 is turned off by the comparison signal PB of the comparator 22. In other words, the high-level output current path of the first high-level output circuit 30 by the high-level output voltage AVDD is blocked.

[0111] Accordingly, in the second mode, the main driver 200 can perform an operation of outputting the first differential transmission signal OUTP and the second differential transmission signal OUTN by the second high-level output circuit 60 and the low-level output circuit 32.

[0112] The CML mode requires a current path having a greater current capacity than the LVDS mode. To this end, the current path for the operation of the low-level output circuit 32 is formed in parallel by the first current source 40 and the second current source 70. The first current source 40 has a first current capacity, and the second current source 70 has a second current capacity. As a result, since the current path in which the first current capacity and the second current capacity are added is provided to the low-level output circuit 32, a current path having a capacity required in the CML mode can be provided.

[0113] In the case where the pre-emphasis function is selected in the second mode, the pre-emphasis driver 300 performs pre-emphasis of amplifying the first differential transmission signal OUTP and the second differential transmission signal OUTN to a second amplification degree by the second amplification circuit of the amplification circuit 90 operated by the second pre-emphasis control signals INP_D_C and INN_D_C. At this time, the transistors Q80 to Q85 and Q90 to Q95 of the first amplification circuit of the amplification circuit 90 are deactivated by the first pre-emphasis control signals INP_L, INN_L, INP_D_L, and INN_D_L.

[0114] In the case where the pre-emphasis function is selected in the second mode, it is necessary to enhance the current capacity of the current path by pre-emphasis.

[0115] When the pre-emphasis function is enabled in the second mode, the third current source 72 is activated to enhance the current capacity, and thereby a third current path having a third current capacity is provided to the low-level output circuit 32 in parallel with the first current source 40. As a result, since the current path in which the first current capacity and the third current capacity are added is provided to the low-level output circuit 32, a current path having a capacity required in the CML mode can be provided in the case where pre-emphasis is performed in parallel.

[0116] Accordingly, embodiments of the disclosure can provide a combined function for outputting a differential transmission signal. Accordingly, an option can be selected in consideration of an interface or an application program, and embodiments of the disclosure can have compatibility with the interface or the application program.

[0117] Furthermore, embodiments of the present disclosure are designed to share some circuits, such as low-level output circuits, thereby providing the following advantages: it is possible to reduce the chip size, and it is possible to provide a current path with a variable current capacity according to a change in mode and application of pre-emphasis.

[0118] While various embodiments have been described above, it will be appreciated that those skilled in the art will understand that the described embodiments are merely exemplary. Accordingly, the disclosure described herein should not be limited based on the described embodiments.

Claims

1. A data transmission circuit comprising: a pre-driver configured to output first and second differential driving signals by using first and second differential data signals; and a main driver configured to output first and second differential transmission signals by using the first and second differential driving signals, wherein the main driver performs high and low level output operations corresponding to a first mode by using first and low level output circuits operated by the first and second differential driving signals, wherein the main driver performs high and low level output operations corresponding to a second mode by using a second high level output circuit using an internal termination resistor and the low level output circuit operated by the first and second differential driving signals, and wherein the main driver includes a current source providing current paths having different current capacities to the low level output circuit shared by the first and second high level output circuits according to modes. the first and second modes are defined as modes requiring different current capacities.

2. The data transmission circuit of claim 1, wherein, the first mode is a low voltage differential signaling (LVDS) mode and the second mode is a current mode logic (CML) mode.

3. The data transmission circuit of claim 2, wherein, the pre-driver includes:

4. The data transmission circuit of claim 1, wherein, a first mode pre-driver enabled corresponding to the first mode and configured to amplify the first and second differential data signals to satisfy a first specification; and a second mode pre-driver enabled corresponding to the second mode and configured to amplify the first and second differential data signals to satisfy a second specification. the second high level output circuit has a fixed output capacity determined by the internal termination resistor.

5. The data transmission circuit of claim 1, wherein, the current source includes:

6. The data transmission circuit of claim 1, wherein, a first current source configured to provide a first current path having a first current capacity to the low level output circuit; and a second current source enabled in the second mode and configured to provide a second current path having a second current capacity to the low level output circuit in parallel with the first current source, wherein the current paths having different current capacities are provided according to whether the second current source is enabled. the main driver includes:

7. The data transmission circuit of claim 1, wherein, the first high level output circuit to which a high level output voltage is applied in the first mode and configured to perform high level output operations by the first and second differential driving signals; a feedback circuit configured to feedback the first and second differential transmission signals and to prevent the high level output voltage from being applied to the first high level output circuit in the second mode in which a feedback voltage is higher than a reference voltage; the second high level output circuit having the internal termination resistor to which the high level output voltage is applied in the second mode and configured to perform high level output operations by using the internal termination resistor; and a low level output circuit operated by the first and second differential driving signals. the low-level output circuit is shared by the first high-level output circuit and the second high-level output circuit through a first node outputting the first differential transmission signal and a second node outputting the second differential transmission signal, and is configured to perform a low-level output operation through the first differential drive signal and the second differential drive signal; and a current source configured to provide a current path with different current capacities to the low-level output circuit corresponding to the first mode and the second mode.

8. The data transmission circuit of claim 7, wherein, the feedback circuit includes a first transistor that is turned on according to a result of comparing the feedback voltage and the reference voltage; wherein the first high-level output circuit includes a second transistor that receives the high-level output voltage through the first transistor and is operated by the first differential drive signal, and a third transistor that receives the high-level output voltage in parallel with the second transistor and is operated by the second differential drive signal; wherein the second high-level output circuit includes a first terminal resistor and a second terminal resistor that are applied with the high-level output voltage in the second mode, and are connected in parallel; and wherein the low-level output circuit includes a fourth transistor connected to the second transistor and the first terminal resistor through the first node and operated by the first differential drive signal, and a fifth transistor connected to the third transistor and the second terminal resistor through the second node and operated by the second differential drive signal.

9. A data transmission circuit, comprising: a pre-driver configured to output a first differential drive signal, a second differential drive signal, and a pre-emphasis control signal by using a first differential data signal, a second differential data signal, and an option signal; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential drive signal and the second differential drive signal; and a pre-emphasis driver configured to perform pre-emphasis of different amplification degrees on the first differential transmission signal and the second differential transmission signal in a first mode and a second mode through the pre-emphasis control signal; wherein the main driver performs high-level output and low-level output corresponding to the first mode by using a first high-level output circuit and a low-level output circuit operated by the first differential drive signal and the second differential drive signal, wherein the main driver performs high-level output and low-level output corresponding to the second mode by using a second high-level output circuit using an internal terminal resistor and the low-level output circuit operated by the first differential drive signal and the second differential drive signal, and The main driver includes a current source that provides current paths with different current capacities to the low-level output circuit shared by the first high-level output circuit and the second high-level output circuit according to modes.

10. The data transmission circuit of claim 9, wherein, The first mode and the second mode are defined as modes requiring different current capacities.

11. The data transmission circuit of claim 10, wherein, The first mode is a low-voltage differential signaling (LVDS) mode, and the second mode is a current-mode logic (CML) mode.

12. The data transmission circuit of claim 9, wherein, The pre-driver includes: a first mode pre-driver enabled corresponding to the first mode and configured to amplify the first differential data signal and the second differential data signal to meet a first specification and output a first pre-emphasis control signal corresponding to the first differential data signal, the second differential data signal, and the option signal for the first mode; and a second mode pre-driver enabled corresponding to the second mode and configured to amplify the first differential data signal and the second differential data signal to meet a second specification and output a second pre-emphasis control signal corresponding to the option signal for the second mode.

13. The data transmission circuit of claim 12, wherein, The pre-emphasis driver includes: a first amplification circuit configured to amplify the first differential transmission signal and the second differential transmission signal to a first amplification degree by the first pre-emphasis control signal in the first mode; and a second amplification circuit configured to amplify the first differential transmission signal and the second differential transmission signal to a second amplification degree by the second pre-emphasis control signal in the second mode; wherein the first amplification circuit and the second amplification circuit perform pre-emphasis on the first differential transmission signal and the second differential transmission signal by being commonly connected to a first node and a second node.

14. The data transmission circuit of claim 13, further comprising: a first biasing circuit configured to deliver a high-level output voltage to the first amplification circuit when the pre-emphasis is enabled; and a second biasing circuit configured to deliver a low-level output voltage to the first amplification circuit and the second amplification circuit when the pre-emphasis is enabled.

15. The data transmission circuit of claim 9, wherein, The second high-level output circuit has a fixed high-level output capacity determined by the internal termination resistor.

16. The data transmission circuit of claim 9, wherein, The current source includes: a first current source configured to provide a first current path with a first current capacity to the low-level output circuit; and a second current source enabled in the second mode and configured to provide a second current path with a second current capacity to the low-level output circuit in parallel with the first current source; and a third current source enabled when the pre-emphasis is enabled and configured to provide a third current path with a third current capacity to the low-level output circuit in parallel with the first current source, wherein the current paths with different current capacities are provided according to whether the second current source and the third current source are enabled.

17. The data transmission circuit of claim 9, wherein, The main driver includes: the first high-level output circuit applied with a high-level output voltage in the first mode and configured to perform a high-level output operation by the first differential drive signal and the second differential drive signal; a feedback circuit configured to feedback the first and second differential transmission signals and to block the high-level output voltage from being applied to the first high-level output circuit in the second mode in which a feedback voltage is higher than a reference voltage; the second high-level output circuit having the internal termination resistor to which the high-level output voltage is applied in the second mode and configured to perform a high-level output operation by using the internal termination resistor; the low-level output circuit shared by the first and second high-level output circuits through a first node at which the first differential transmission signal is output and a second node at which the second differential transmission signal is output, and configured to perform a low-level output operation by the first and second differential drive signals; and a current source configured to provide a current path having different current capacities to the low-level output circuit corresponding to the first and second modes.

18. The data transmission circuit of claim 17, wherein the feedback circuit including a first transistor turned on according to a result of comparing the feedback voltage and the reference voltage; wherein the first high-level output circuit includes a second transistor receiving the high-level output voltage through the first transistor and operated by the first differential drive signal and a third transistor receiving the high-level output voltage in parallel with the second transistor and operated by the second differential drive signal; wherein the second high-level output circuit includes a first termination resistor and a second termination resistor to which the high-level output voltage is applied in the second mode, and the first and second termination resistors are connected in parallel; and wherein the low-level output circuit includes a fourth transistor connected to the second transistor and the first termination resistor through the first node and operated by the first differential drive signal and a fifth transistor connected to the third transistor and the second termination resistor through the second node and operated by the second differential drive signal.

19. The data transmission circuit of claim 9, further comprising: an external memory configured to store the option signal, wherein the external memory provides the option signal corresponding to a mode selected between the first and second modes.

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