Systems and Methods for a Redundancy-Sensing Based Super-Resolution Digital-to-Analog Converter

Abstract

The present disclosure provides a digital-to-analog converter device. The digital-to-analog converter device includes: a set of components, each component included in the set of components includes a plurality of unit cells, and each unit cell is associated with a unit cell size representing the manufacturing specification of the unit cell; a plurality of switches, each switch included in the plurality of switches is coupled to the components included in the set of components; and an output electrode, the output electrode is coupled to the plurality of switches, and the converter device is configured to output an output signal on the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different from a second unit cell size associated with a second unit cell included in the set of components.

Description

[0001] Cross - reference to related applications

[0002] Not applicable. Technical Field

[0003] The field of the present invention is electrical converters including digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). More specifically, the present invention relates to super-resolution DACs using redundant sensing techniques. Background Art

[0004] The quantization process, i.e., analog-to-digital conversion (ADC), and the reverse operation of de-quantization, i.e., digital-to-analog conversion (DAC), are the basis of all modern sensing data acquisition systems. They allow "digital" artificial systems to sense and interact with the "analog" physical world. Quantization is essentially a lossy data compression process, in which information from a higher-resolution space is represented by a corresponding object at a lower resolution. In practical implementations, the accuracy of this process is always limited by system resources such as size, power, bandwidth, and memory. For example, in many ADC and DAC integrated circuit designs, increasing the resolution by 1 bit or doubling the accuracy typically requires a four-fold increase in chip area and power consumption. Although ultra-high-resolution ADCs / DACs up to 32 bits are possible, their large size and power consumption limit the use of these devices in many practical applications. Similarly, higher-resolution image sensors require more pixel counts and buffer memories, thus also resulting in larger devices and power consumption. Although pixel density can be increased, smaller pixel sizes are associated with increased noise that limits the dynamic range of the sensor.

[0005] Super-resolution (SR) is a technique aimed at achieving an effective resolution that exceeds the accuracy normally allowed by system resource limitations. They have a wide range of applications in various fields of engineering and science involving imaging and instrumentation, where higher-resolution data acquisition is always required. Previous SR techniques focused on recovering fine details of an object of interest by integrating information obtained from coarse observations. These techniques can generally be divided into two main categories: model-based and oversampling-based, which are also known as single-frame and multi-frame in image processing.

[0006] Modeling-based (single-frame) techniques focus on modeling the input source from available data points and reconstructing the lost information through approximation. In these techniques, SR is achieved by relying on known statistical properties of the input signal (such as the sparse property used in compressive sensing or the property extracted from a large amount of example data used in many machine learning-based methods). On the other hand, oversampling-based (multi-frame) techniques acquire and combine multiple samples of the input obtained at various spatial or temporal instants to extract sub-least significant change information. In these techniques, since the low-resolution data contains aliasing which embeds the high-resolution content, and this high-resolution content can be extracted with sufficient data volume through algorithm-based (e.g., noise reduction, deconvolution, etc.) or machine learning-based methods, SR is possible. For compressive sensing or other data-driven methods (including most existing machine learning-based techniques), after acquiring the low-resolution data, optimization or approximation is performed during reconstruction.

[0007] In addition, mismatch error is one of the main obstacles hindering the implementation of high-precision DAC / ADC in sub-micron CMOS processes. Mismatch error is a random deviation that occurs during the manufacturing of an integrated circuit (IC). Mismatch error may cause random variations in the inherent characteristics of IC components, including active electronic components (such as transistors) and / or passive electronic components (such as capacitors and / or resistors), which can lead to unpredictable circuit behavior and a reduction in the overall system accuracy. For example, due to mismatch error, a DAC / ADC actually designed with a 10-bit resolution may only have an effective resolution of about 8 - 9 bits.

[0008] Accordingly, it is desirable to provide systems and methods for designing a digital-to-analog converter that provide super-resolution without requiring post-processing and in the presence of mismatch error. SUMMARY OF THE INVENTION

[0009] In one aspect, the present disclosure provides a digital-to-analog converter device. The digital-to-analog converter device includes: a set of components, each component included in the set of components includes a plurality of unit cells, and at least one component includes a number of unit cells that is not a power of 2; a plurality of switches, each switch included in the plurality of switches is coupled to a component included in the set of components; an output electrode, coupled to the plurality of switches, and the converter device is configured to output an output signal at the output electrode; and a controller, coupled to the plurality of switches and configured to receive a desired output current; determine an anode component configuration including at least one component included in the set of components based on the desired output current; determine a cathode component configuration including at least one component included in the set of components based on the desired output current; and cause a current pulse to be output at the output electrode channel based on the anode component configuration and the cathode component configuration.

[0010] In a digital-to-analog converter device, the current pulses can include positive current pulses and negative current pulses.

[0011] In a digital-to-analog converter device, a controller includes a memory that includes a set of positive current values and a set of negative current values associated with a set of component configurations, the anode component configuration and the cathode component configuration being included in the set of component configurations.

[0012] In a digital-to-analog converter device, the anode component configuration includes at least one component not included in the cathode component configuration.

[0013] The effective resolution of a digital-to-analog converter device can be at least four times greater than the intrinsic resolution of the digital-to-analog converter device. The effective resolution of the device can be equal to the Shannon entropy of the digital-to-analog converter device, and the intrinsic resolution can be equal to the base-2 logarithm of the number of unit cells plus 1.

[0014] The digital-to-analog converter device can be included in a nerve stimulator device.

[0015] In a digital-to-analog converter device, a first unit cell size associated with a first unit cell included in a set of components can be different from a second unit cell size associated with a second unit cell included in the set of components, the first unit cell size including the length and width of the first unit cell.

[0016] In a digital-to-analog converter device, each unit cell can include at least one transistor.

[0017] In another aspect, the present disclosure provides a digital-to-analog converter device. The digital-to-analog converter device includes: a set of components, each component included in the set of components including a plurality of unit cells, each unit cell being associated with a unit cell size representing the manufacturing specifications of the unit cell; a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components; and an output electrode coupled to the plurality of switches, the converter device being configured to output an output signal on the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different from a second unit cell size associated with a second unit cell included in the set of components.

[0018] In a digital-to-analog converter device, the unit cell size can include a length value and a width value.

[0019] In a digital-to-analog converter device, the unit cell size can be associated with a transistor process size.

[0020] In a digital-to-analog converter device, at least one component included in the set of components includes a number of unit cells that is not a power of 2.

[0021] In another aspect, the present disclosure provides a method for determining manufacturing parameters of a digital-to-analog converter device including a set of components, each component included in the set of components including at least one unit cell, and each unit cell being associated with a unit cell size. The method includes: determining a required mismatch error for the unit cells included in the set of components based on a target effective resolution value; determining an initial unit cell size based on the required mismatch error; setting the unit cell size of each unit cell included in the set of components to be equal to the initial unit cell size; determining the effective resolution of the analog-to-digital converter device by performing a simulation; determining that the effective resolution is lower than the target effective resolution; adjusting the unit cell size of one or more unit cells included in the set of components in response to determining that the effective resolution is lower than the target effective resolution; and providing each unit cell size associated with each unit cell to a manufacturing facility.

[0022] In the method, the target effective resolution can be at least four times higher than the inherent resolution.

[0023] In the method, the unit cell size can include a length value and a width value, and each unit cell can include at least one transistor.

[0024] In the method, at least one component included in the set of components includes a number of unit cells that is not a power of 2.

[0025] In the method, the simulation can be a Monte Carlo simulation.

[0026] The foregoing and other aspects and advantages of the present invention will become apparent from the following description. In that description, reference is made to the accompanying drawings which form a part hereof and in which are shown, by way of illustration, preferred embodiments of the invention. However, such embodiments do not necessarily represent the full scope of the invention, and reference is therefore made to the claims and herein for interpreting the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is an exemplary 3-bit redundant sensing (RS) structure.

[0028] Figure 2 is a graph comparing the reference distributions between the "half-split" (HS) grouping method and the "uniform" (UN) grouping method on a shared sample space.

[0029] Figure 3A is the entropy average value of the inherent resolution N 0 = 10-bit device with respect to the respective target resolutions N k = N 0 + k mismatch rate graph.

[0030] Figure 3B is the inherent resolution N using the "uniform" (UN) binning method 0 = the average entropy of a 10-bit device relative to each target resolution N for k in the range [1,…,10] k = N 0 + the graph of the mismatch rate of k.

[0031] Figure 3C is the inherent resolution N using the HS binning method 0 = the standard deviation of the entropy of a 10-bit device relative to each target resolution N for k in the range [1,…,10] k = N 0 + the graph of the mismatch rate of k.

[0032] Figure 3D is the inherent resolution N using the UN binning method 0 = the standard deviation of the entropy of a 10-bit device relative to each target resolution N for k in the range [1,…,10] k = N 0 + the graph of the mismatch rate of k.

[0033] Figure 4A is the root mean square error (RMSE) calculated on the sample space for the target resolution N using the HS and UN binning methods k = 12

[0034] Figure 4B is the RMSE calculated on the sample space for the target resolution N using the HS and UN binning methods k = 18

[0035] Figure 5A is N using the (HS) binning method at a sampling space of δ = 95% 0 = the average entropy of a 10-bit device relative to each target resolution N for k in the range [1,…,10] k = N 0 + the graph of the mismatch rate of k.

[0036] Figure 5B is N using the UN binning method at a sampling space of δ = 95% 0 = the average entropy of a 10-bit device relative to each target resolution N for k in the range [1,…,10] k = N 0 + the graph of the mismatch rate of k.

[0037] Figure 5C is N using the HS binning method at a sampling space of δ = 95% 0= Standard deviation of the entropy of a 10-bit device relative to each target resolution N for k in the range [1, …, 10] k = N 0 + Curve of the mismatch rate of k.

[0038] Figure 5D is N under a sampling space of δ = 95% using the UN grouping method 0 = Standard deviation value of the entropy of a 10-bit device relative to each target resolution N for k in the range k = N 0 + Curve of the mismatch rate of k.

[0039] Figure 6A is an exemplary current digital-to-analog converter (DAC) circuit.

[0040] Figure 6B is a curve of the effective resolution relative to the target resolution from simulation results.

[0041] Figure 7A is an exemplary DAC channel.

[0042] Figure 7B is an exemplary output current waveform.

[0043] Figure 8A is an exemplary p-type operational amplifier.

[0044] Figure 8B is an exemplary n-type operational amplifier.

[0045] Figure 8C is an exemplary bias circuit.

[0046] Figure 9 is an exemplary voltage-to-current converter circuit.

[0047] Figure 10 is an exemplary voltage level converter circuit.

[0048] Figure 11 is an exemplary process for calibrating a DAC channel to achieve super-resolution (SR).

[0049] Figure 12 is an exemplary process for controlling a DAC channel to output a desired current.

[0050] Figure 13 is an exemplary process for determining the manufacturing parameters of a DAC with SR in the presence of mismatch errors.

[0051] Figure 14 is an exemplary analog-to-digital converter. Detailed Description

[0052] The present disclosure provides systems and methods for generating a super-resolution digital-to-analog converter (DAC) that provides super-resolution without post-processing and in the presence of mismatch errors.

[0053] In the present disclosure, a new approach to super-resolution (SR) based on redundant sensing (RS) is proposed that does not require either modeling or oversampling of the input signal. RS theory is a design framework that exploits redundancy to improve the performance of artificial systems. It can be applied to biomedical devices such as neural stimulators. An RS structure is inherently a redundant system of information representation where each outcome in the sample space can be generated by multiple different system configurations. In practice, these configurations are always affected by random mismatch errors, which are typically regarded as a "problem" that causes conversion errors and reduces the overall accuracy of the system. However, the present disclosure shows that mismatch errors allow the actual values of the redundant configurations of the system to "spread" into adjacent sample spaces such that, at a sufficient level, the RS structure has the ability to quantify data with an effective resolution that exceeds conventional resource limitations.

[0054] The UN-packet-based SR technique detailed herein is fundamentally different from some prior methods in that it does not involve reconstructing lost information and does not rely on any statistical properties of the input data. Due to its redundant architecture, the SR functionality is embedded in the internal structure of the sensor once manufactured. To realize SR data acquisition, this "hidden" potential must be revealed through optimization. The optimization process for each sensor needs to be performed only once and is independent of the input signal. Once optimized, the sensor can capture any type of signal at a super-resolved resolution regardless of its statistical distribution. For compressive sensing or other data-driven methods (including most existing machine learning-based techniques), optimization or approximation is performed during the reconstruction process after low-resolution data is acquired. In contrast, for the UN-packet method, the sensor is optimized before any data is acquired, and the fine-grained detailed information content of the input signal is not lost during quantization. This is achieved not only due to the RS architecture itself but also by cleverly controlling the mismatch errors - a factor that is not desired in traditional designs for accuracy limitations.

[0055] In the following "Super-Resolution" section, a mechanism for promoting SR in the RS architecture with a new theory is proposed. The Monte Carlo method is used to illustrate the advantages of the UN technology. The Monte Carlo analysis is an effective and widely used method when traditional proofs are too complex or infeasible, especially in this case where it can be shown to be an NP-hard optimization problem. This analysis is performed both at an abstract level assuming a simple probability distribution of components and at the circuit level considering all non-ideal factors due to process variations. A component is a combination of one or more unit cells, and this component behaves like a single entity. A component set (which can also be referred to as a component collection) is a collection of components used by a sensor to generate its internal reference. For example, a binary-weighted sensor has a component set of {1, 2, 4,..., 2 N-1}, which consists of 2 N - 1 identical unit cells, where the unit cell has a weight of 1 (unit). The unit cell can output an electrical signal (such as voltage or current). The results show that above a 10-bit quantizer in a 95% sampling space, an additional 8 - 9 bits of resolution or 256–512x precision can be achieved. In the "Practical Considerations and Applications" section, the potential applications and practical considerations of the proposed SR technology in fully integrated micro-bio-medical devices are described, where the complexity of the structure can be alleviated by approximation or conveniently circumvented. Example designs are shown where the UN grouping technology can be applied to improve the resolution of the current DAC in a neural stimulator, thereby giving more precise control over the output stimulation current.

[0056] Super - resolution

[0057] Quantization and mismatch error

[0058] Quantization is the process of mapping a continuous set (analog) to a finite set of discrete values (digital). Without loss of generality, it can be assumed that an N 0 quantizer divides the continuous interval [0, 1) into sub - intervals, which are defined by a set of reference such that each sub - interval is mapped to a digital code d in the range from 0 to :

[0059]

[0060] where x A is the analog input and x D is the digital output. The effective resolution of the quantizer can be quantified by the Shannon entropy as follows:

[0061]

[0062] where M is the normalized total mean squared error integrated over each digital code. It can be seen that for all values of the reference θ d , . Equality holds only when the references are equally spaced, i.e., This fundamental maximum of entropy is called the Shannon limit, where the effective resolution of the device is theoretically limited only by its inherent quantization error.

[0063] In practice, the accuracy of the quantizer is also affected by randomly occurring mismatch errors, leading to undesirable deviations of the references and degradation of the entropy. For example, some integrated ADC or DAC chips generate their references through an array of identical basic components simply regarded as unit cells. An N 0 -bit device typically has unit cells, which can be micro-capacitors, resistors, or transistors. Random mismatches of individual unit cells due to manufacturing process variations and other non-ideal factors are one of the main sources of mismatch errors, which may significantly reduce the accuracy of the device.

[0064] To effectively control the unit cells, the cells are typically grouped into bundles simply regarded as components. Grouping significantly reduces the number of control signals required. For example, using the conventional binary weighted method, unit cells are arranged into N components with nominal weights of 0 . Such a system is orthogonal because for N 0 binary control signals, i.e., 0 / 1 bits, corresponding to each digital code in the references can be uniquely created by selecting and combining components according to the binary number system.

[0065] Redundant sensing

[0066] RS is a design framework aimed at engineering redundancy to improve the performance of the system in terms of accuracy and precision, rather than reliability and fault tolerance as in other designs. Practical RS implementations must meet two criteria, namely representational redundancy (RPR) and entanglement redundancy (ETR).

[0067] RPR refers to a non-orthogonal information representation scheme in which each outcome in the sample space is encoded by numerous different system configurations. Each configuration responds differently to mismatch errors, so in any given situation, there is almost always one or more configurations with less error than the conventional representation.

[0068] TR refers to the implementation of the RS structure such that the statistical distributions of different system configurations are partially correlated (i.e., entangled), thereby allowing for large redundancy without incurring excessive resource overhead. ETR should be distinguished from traditional replication-based methods for achieving redundancy, where redundancy is linearly proportional to resource utilization.

[0069] Figure 1 An example of a 3-bit RS structure with RPR and ETR characteristics is shown, which can be implemented by using a non-orthogonal grouping method without the need for replication. While using the same amount of physical resources (i.e., 7 unit cells), in the RS structure, each digital code can be created by multiple different combinations of components, and each combination of components represents a different, partially correlated distribution with respect to random mismatch errors. This redundant system of information representation has been shown to suppress mismatch errors by allowing the search for the optimal component assembly with the minimum error with respect to each digital code. The redundancy mechanism can be well utilized to achieve an effective resolution beyond the conventional limit bounded by quantization error of N 0 of.

[0070] Code diffusion

[0071] The mismatch rate σ m is defined as the standard deviation of each unit cell, assuming it has a Gaussian distribution with a mean of 1. In the absence of mismatch errors or σ m = 0, regardless of how the unit cells are grouped and assembled, an array composed of the same units can only generate a limited number of references, which belong to the following discrete value set:

[0072]

[0073] is regarded as the inherent reference set corresponding to the inherent resolution N 0 of.

[0074] Due to σ m being assumed to be a non-zero value, as the actual values generated by different component assemblies start to "spread" into the adjacent sample spaces, the segments of the probability density function centered on each element of become wider. This feature is unique to the RS structure because (i) there are many different component assemblies that can generate references with the same nominal value, i.e., RPR, and (ii) the distributions of these assemblies are partially independent with respect to random mismatch errors, i.e., ETR. Subsequently, the expansion of the probability density function occurs in each mismatch error trial, rather than just being the result of Monte Carlo sampling.

[0075] Code diffusion is a characteristic of the RS structure, where due to random mismatch errors, the actual value of the internal reference of this RS structure extends into the adjacent sample space. In a non-SR quantizer, code diffusion is undesirable because it causes the reference to deviate which results in a degradation of the Shannon entropy, as shown in Equation (2). Some previous systems were designed to reverse the diffusion process by searching for the assembly closest to each element.

[0076] However, from another perspective, code diffusion means that the same system can generate references within a region of the sample space that belong to the inherent reference set of a higher resolution N k = N 0 + k:

[0077]

[0078] where at a sufficient level of the mismatch rate, the probability density function of the reference can almost cover almost all of the sample space with relatively uniform chances. Subsequently, there is a reasonable possibility that a set of assemblies very close to can be found, which will allow sampling at an effective resolution N 0 that exceeds the inherent resolution N k of the system. It is also interesting to note that mismatch errors are generally considered an undesirable non-ideal factor, but are a key element in achieving SR. Only when the mismatch rate reaches a certain level (e.g., ~10%), can the maximum SR efficiency be obtained, which is considered too large in many common applications.

[0079] Such a mechanism is only possible because due to redundancy, the number of different references that can be generated by the RS structure is significantly greater than and the cardinality of both. In an orthogonal structure such as binary, for all k, the number of different references is strictly which is less than Furthermore, not only the number of different component assemblies, but also their interrelationships play an important role. Ideally, the assemblies will be evenly spread over all of the sample space to maximize the approximation This characteristic is determined by the internal architecture of the device, i.e., how the components are designed.

[0080] Grouping method

[0081] The grouping method is the way of arranging unit cells into components. Almost all conventional designs can be classified as binary weighted (BW) structures, where the quantization partitions are uniquely encoded according to the binary number system. In contrast, the proposed RS architecture adopts a different strategy to achieve redundancy with RPR and ETR characteristics. There is no restriction on how to group the unit cells. Although the grouping method does not change the number of unit cells and thus has little impact on resource constraints, it determines the internal architecture of the system and greatly affects the number and distribution of references. The design of the grouping method differentiates one redundancy structure from another.

[0082] Suppose a given grouping method assembles unit cells into n components with nominal weights of and the actual weights with respect to the random mismatch error are C = {c 1 , c 2 , …, c n} for each subset encoded by the binary string , generating the normalized reference θ d as follows:

[0083]

[0084] Let Φ be the set of all references that the system can generate. To achieve effective resolution, N k is essentially searching for subsets that are closely close to . Obviously, SR can only be completed in redundancy structures such as or n > N k .

[0085] The previously proposed RS architecture adopted a class of grouping methods that were inspired by the binocular structure of the human visual system. They derived the nominal weights according to the following formula where the parameters (s, N 0 ') satisfy 1 ≤ N' 0 < N 0 , 1 ≤ s ≤ N 0 - N' 0 :

[0086]

[0087]

[0088] where, i ∈ [0, N 1 - 1], j ∈ [0, N 0 - 1]. In the special case of where N' 0= N 0 -1 and s = 1 is called a "half - split" (HS) array, and this "half - split" (HS) array has the following nominal weights Where:

[0089]

[0090]

[0091] In the RS structure, the HS design has the maximum number of components, so while having the maximum degree of redundancy, it contains a reasonable number of components as Moreover, the simplicity of the design allows it to be implemented in hardware with minimal complexity. Φ HS The distribution of Figure 2 is shown in

[0092] which will be described in more detail below. Although HS methods have a high degree of redundancy, their distribution may not be optimal for implementing SR. Most of these references focus on the middle region of the sample space, leaving the two ends under - covered and prone to errors. Where:

[0093]

[0094]

[0095] Where The intuition behind the UN design is to divide the components of a binary - weighted array into multiple sub - arrays with different resolutions (N 1 , N 2 , …), and these sub - arrays decrease by a factor of log₂ in the logarithmic base. This can maximize the distribution of the largest and smallest components in the digital code while keeping the total number of components at a reasonable value similar to the HS structure, 2N 0 . All the remaining components form the basic array

[0096] 0 = 10, the BW, HS, and UN methods yield the following nominal component sets:

[0097]

[0098] Figure 2 ​It is a graph showing the comparison of the reference distributions between the HS and UN grouping methods on a shared sample space. More specifically, the distribution of the HS method 200 and the distribution of the UN method 204 are shown. The UN method produces a more uniform (e.g., "flat") distribution in different regions of the sample space (especially at both ends), which will translate into better SR potential. The more flat distribution of the UN method will translate into a more uniform code diffusion over different regions of the sample space. The following sections will show that this property helps to suppress errors near both ends of the sample space and generally produces greater SR potential.

[0099] Beyond the Shannon limit

[0100] SR in the context of this disclosure should be understood as a resource-constrained problem. The accuracy of a sensor composed of unit cells was previously considered to be bounded by the Shannon limit determined by quantization error. By arranging these unit cells in a specific way to achieve a redundant structure and by adopting the statistical properties of random mismatch errors, an effective resolution beyond this conventional "limit" is achieved. 0 The Shannon limit exists because the ordinary expression of entropy as shown in Equation (2) is calculated for a reference set of only

[0101] values which is the maximum number of different reference numbers that a conventional binary weighted array can generate. This limit does not apply to redundant architectures. The reference set (Φ) is the set of all internal reference values that can be generated by the system. The reference set of a system with k components will be 2 k elements. The HS or UN structure has a reference set Φ HS / Φ UN which has as many different elements as . The key to achieving SR is to find a subset from Φ HS / Φ UN such that at resolution N it is very close to the inherent reference set k This can only be achieved in the presence of random mismatch errors that allow the elements of Φ / Φ HS to spread across the sample space. Thus, the concept of SR does not contradict the conventional Shannon limit, but rather represents a new interpretation of Shannon's theory beyond its usual understanding, which is only applicable in actual redundant architectures. UN / Φ 0 By making the substitution N

[0102] ←N k , the Shannon entropy in Equation (2) can be conveniently modified to target resolution N k dDenotes the effective resolution and extends the range to θ d to include all values in. Figure 3 shows the mean and standard deviation (STD) of the estimated entropy of an N 0 = 10-bit device using Monte Carlo simulation (n = 1000) at various target resolutions and mismatch ratios. More specifically, Figure 3A is the mean of the entropy of an N 0 = 10-bit device using the HS grouping method versus the mismatch ratio σ k = N 0 + k for each target resolution N m in the range [1,…,10]. Figure 3B is the mean of the entropy of an N 0 = 10-bit device using the UN grouping method versus the mismatch ratio σ k = N 0 + k for each target resolution N m in the range [1,…,10]. Figure 3C is the standard deviation of the entropy of an N 0 = 10-bit device using the HS grouping method versus the mismatch ratio σ k = N 0 + k for each target resolution N m in the range. Figure 3D is the standard deviation of the entropy of an N 0 = 10-bit device using the UN grouping method versus the mismatch ratio σ k = N 0 + k for each target resolution N m in the range. For both the HS and UN grouping methods, it is feasible to increase the effective resolution by 3 - 4 bits or enhance the precision by 8 - 16 times with a sufficient mismatch ratio. The optimal set is found using exhaustive search

[0103] As implied by the analysis of code diffusion, the best SR performance is obtained at mismatch ratios higher than ~10%. Both the HS and UN grouping methods provide an increase in effective resolution of 3 - 4 bits or an enhancement in precision of 8 - 16 times. Within the 10 - 50% mismatch ratio, the STD of the entropy is less than 0.2 bits, where the UN method has slightly better results. These results imply that the SR solution is consistent, which will translate to good device output under random errors in practical applications.

[0104] In addition, the consistency of the mechanism means that the mismatch error may not need to be truly "random". In a certain application, a 10% random deviation may seem unrealistic. Alternatively, the deviation can be deliberately added to the structure during the design process. Even if these artificial pseudo-random deviations may introduce a certain level of error, the consistency of the SR mechanism ensures that a solution can always be found.

[0105] Narrow - range sampling

[0106] Figure 4 shows the distribution of the root mean square error (RMSE) over the sample space or the value at each digital code d in formula (2) before summation. More specifically, Figure 4A is a graph of the root mean square error (RMSE) calculated using the HS and UN grouping methods for N k = 12 over the sample space (N 0 = 10, σ m = 10%). Figure 4B is a graph of the root mean square error (RMSE) calculated using the HS and UN grouping methods for N k = 18 over the sample space (N 0 = 10, σ m = 10%). Note that the x-axis shows only the first and last 5% of the sample space. At high resolution, the errors mostly occur at both ends where the redundancy level is low. This may lead to a significant degradation of the overall entropy. The UN method is designed to have a more flat code distribution, which helps to shape the error to the extreme.

[0107] Compared with the HS design, the UN method is designed to have better code expansion, so it can help to reduce part of the error by shaping the code to the extreme. However, due to the nature of grouping, it is mathematically impossible to cover the entire sample space equally. The UN method is superior to the HS structure because it is specifically designed to minimize the error at both ends. By sacrificing 5% of the sample space - a reasonable engineering trade-off, with the UN structure, an increase in the effective resolution of 8 - 9 bits or an improvement in precision of 256 - 512 times is feasible.

[0108] However, due to many practical reasons, many applications may not actually utilize the entire sample space equally. Many sensors are calibrated so that the signal to be captured falls into the middle of the sample space. This is because most signals are not evenly distributed across the samples, and "centering" the data can minimize the possibility that the signal exceeds the sampling range, resulting in distortion and information loss. If the two extremes are ignored, the proposed method allows for the implementation of a continuous sampling range centered on the middle of the sample space, where the overall effective resolution can be significantly enhanced.

[0109] Let δ ∈ [0, 1] be the length of a continuous region centered at the middle of the sample space, within which data is captured. This effectively reduces the full range and dynamic range of the device, resulting in a lower Shannon limit:

[0110]

[0111] Now, integrate the normalized total mean square error and entropy only over a smaller range of digital codes:

[0112]

[0113] Figure 5 shows the estimated entropy of the same system as in Figure 3 but at δ = 95% of the sample space. More specifically, Figure 5A is the average entropy of an N 0 = 10-bit device using the HS grouping method at δ = 95% sampling space versus the mismatch rate σ k = N 0 + k for each target resolution N in the range [1,…, 10] m of the graph. Figure 5B is the average entropy of an N 0 = 10-bit device using the UN grouping method at δ = 95% sampling space versus the mismatch rate σ k = N 0 + k for each target resolution N in the range [1,…, 10] m of the graph. Figure 5C is the standard deviation of the entropy of an N 0 = 10-bit device using the HS grouping method at δ = 95% sampling space versus the mismatch rate σ k = N 0 + k for each target resolution N in the range [1,…, 10] m of the graph. Figure 5D is the standard deviation of the entropy of an N 0 = 10-bit device using the UN grouping method at δ = 95% sampling space versus the mismatch rate σ k = N 0 + k for each target resolution N in the range of m of the graph.

[0114] Practical considerations and applications

[0115] In practice, the greatest challenge in utilizing the proposed SR and any RS architecture is to determine the correct configuration of the system among the numerous redundancy possibilities. In the context of the present disclosure, in N kImplementing SR under the following optimization problem needs to be solved: Problem: Find a subset of the set of components C = {c 1 , c 2 , … c n} such that this subset generates a reference that minimizes the error minimizes

[0116] This is essentially a version of the 0-1 knapsack problem, which has been shown to be NP-hard. Because Considering that the actual weights of all components are known, implementing SR at any target resolution N k is as difficult as the non-SR case with N 0 . However, this does not necessarily negate the practicality of the proposed method. The practical solutions to seemingly unsolvable problems may be specific to each application.

[0117] Implementing the proposed SR method (by the UN method) in ADC design will achieve a great improvement in the performance of various biomedical imaging and instrumentation systems (especially those that benefit from high precision and high dynamic range). For example, in a neuromodulation system, due to the large amplitude difference between the peripheral nerve signal (tens of μV) and the stimulation artifact (hundreds of mV), a high dynamic range implementation equivalent to a 14-18 bit ADC will be preferred for obtaining high-quality nerve data while minimizing circuit saturation. In a magnetic resonance imaging (MRI) system, it has been shown that replacing the default ADC (usually 16 bits) in commercial machines with an ultra-high dynamic range ADC of up to 20–24 bits as part of the RF receiver helps to improve the effective contrast and spatial resolution of the resulting images.

[0118] In addition, the proposed SR method can also be applied to enhance the performance of many biomedical devices that employ DACs. For example, an electrical nerve stimulator typically requires a DAC to generate an internal reference current. A higher resolution DAC is always desirable because it can provide more precise control of the stimulation current over a wider range, which may imply better modulation of different nerve circuits. In another example, many ultrasound imaging modalities employ DACs during their transmission phase to generate the necessary analog signals. High-precision commercial DACs of up to 12 bits and above have been utilized in various systems to facilitate their operation. Implementing such high-precision DACs (10-12 bits) on a chip is usually challenging and expensive because they occupy a large silicon area, especially in high-voltage processes (>30V). The proposed UN method can greatly benefit these designs by helping to achieve similar resolutions at a much lower cost.

[0119] Now refer to Figure 6A, an exemplary current DAC circuit 600 is shown. The current DAC circuit 600 can be included in a nerve stimulator device. In some embodiments, the current DAC circuit can be coupled to the nerve stimulator device. The current DAC circuit 600 can include unit cells grouped as components 604. Using the UN grouping described in Equation (8) above, based on the inherent resolution of the device (e.g., N 0 ), the current DAC circuit 600 can include any number of components and unit cells. For example, the current DAC circuit 600 can have an inherent resolution of N 0 = 8, which results in fifteen components {i 0 , i 1 , …, i n} having {1, 1, 1, 1, 2, 2, 2, 4, 4, 8, 8, 15, 30, 59, 117} unit cells respectively. The first component 604A can include one unit cell, and this component can include one transistor or a pair of transistors 608, each of which can be a MOS transistor. The second component 604B can include 117 transistors or transistor pairs, each of which can be a MOS transistor, and this second component can be the component with the largest number of unit cells and an eight-bit inherent resolution in the DAC circuit. Each component can be coupled to a switch such as a transistor for controlling the current output by each component. For example, the first component 604A can be coupled to the switch 612. Although transistor mismatch is mostly time-invariant, it is particularly complex because it depends not only on the physical dimensions (W / L) of the device but also on operating conditions such as bias voltage, load current, parasitic effects, etc. As a proof-of-concept demonstration, an SRDAC was designed and built in the GlobalFoundries BCDLite 0.18μm process using 30V transistors with a minimum feature size (W / L = 4.0 / 0.5μm). By selecting an appropriate set of components, the proposed SR method can be seamlessly embedded into a standard cascaded current DAC. The current DAC current 600 employs the UN grouping method at an inherent resolution of N 0 = 8 bits, which results in a set of components {1, 1, 1, 1, 2, 2, 2, 4, 4, 8, 8, 15, 30, 59, 117} (∑ = 2^8 - 1 = 255). Monte Carlo simulations (n = 16) were performed at the schematic level using the transistor statistical models provided by the foundry (both process and variants) without adding any pseudo-random mismatch. This model takes into account most of the mismatch except for the parasitic resistance of the metal connections in the layout. Figure 6BA graph of the effective resolution relative to the target resolution according to the simulation results is shown, where an average 12-bit effective resolution or a gain of 4-bit additional precision can be obtained at δ = 95% by only utilizing the natural mismatch of the transistors. As a result, the performance of high-precision devices can be greatly improved by utilizing the proposed SR mechanism by taking advantage of the natural mismatch of the transistors.

[0120] Moreover, unlike the ADC example, the neural stimulator operation is always controlled by an external controller during normal operation. The controller regularly communicates with the neural stimulator to update its parameters and trigger its functions when needed. Subsequently, the optimal system settings at each DAC output can be simply pre-determined through foreground calibration and stored on an external memory (i.e., a look-up table), which is accessible by the controller at any time. By transferring it to a memory difficult problem that may be easier to handle in some cases, this effectively circumvents the computationally difficult problem. For example, assuming that 20 components are to be used to achieve a 16-bit target SR, storing all the optimal configurations per DAC would require 2 16 ×20 = 1.3·10 6 bits or 163 KB of memory - which is negligible for off-chip flash.

[0121] Now referring to Figure 7A and Figure 6A , a DAC channel 700 is shown. The DAC channel 700 may include a current DAC circuit 704, which may include at least part of the electrical components of the current DAC circuit 600. The current DAC circuit 704 may include a set of components 706, which includes one or more components, including a first part 708A, a second component 708B, and a third component 708C. Each of these components may include one or more unit cells. The number of unit cells can be determined using the UN grouping method described in formula (8). For example, the current DAC circuit 704 may have an inherent resolution of N 0 = 8, which results in fifteen components {i 0 , i 1 , …, i n} having {1, 1, 1, 1, 2, 2, 2, 4, 4, 8, 8, 15, 30, 59, 117} unit cells respectively. Each unit cell may include a transistor or a pair of transistors. For example, the first component 708A may include a pair of transistors 712. Each component may be coupled to a switch such as a transistor for controlling the current output by each component. For example, the first component 708A may be coupled to a transistor 716. Each switch may receive a corresponding digital control signal at one of a set of digital control signal nets (D 0 , …, D n)。For example, transistor 716 can be coupled to a first digital control network included in digital control bus 720. When a digital control signal is activated (i.e., "high" for an NPN transistor), the corresponding component can provide an output current included in the output current I generated by current DAC circuit 704 DAC in the output current. An external controller (not shown) can be coupled to current DAC circuit 704 at digital control bus 720 to control the output of current DAC circuit 704 and / or DAC channel 700. The controller can be programmed with a predetermined component configuration to output a given digital value as an analog signal, which will be described in detail below. Each component configuration can be a grouping of several activated components, such as components coupled to a switch with an "activated" digital control signal. In some embodiments, a first controller programmed with a predetermined component configuration can be coupled to a second controller configured to generate digital control signals (D 0 , …, D n ) and an anode output switching signal SW A and a cathode output switching signal SW C . The first controller can provide the component configuration to the second controller. By activating the appropriate digital control signals for a given component configuration and by activating anode output switching signal SW A and cathode output switching signal SW C to modulate the final output current, the second controller can function as a timing controller, which will be described below. Current DAC circuit 704 can receive an internal reference current I ref at internal reference current network 728

[0122] DAC channel 700 can include a current mirror circuit 732. Current mirror circuit 732 can receive the output current I DAC from current DAC circuit 704. Current mirror circuit 732 generates a copy output current I DAC ' of output current I DAC and generates positive and negative bias voltages for output current driver circuit 760, which will be described below. Current mirror circuit 732 can receive a fixed positive bias voltage V DP , a fixed negative bias voltage V DN to bias the first n-type operational amplifier 736, the second n-type operational amplifier 740, and the first p-type operational amplifier 744. The fixed positive bias voltage V DP can be equal to V DD - 0.5, and the fixed negative bias voltage V DN can be equal to V SS+0.5. The current mirror circuit 732 can be constructed using a boost cascade architecture to achieve high-precision operation.

[0123] The current mirror circuit 732 can be coupled to the output current driver circuit 760 to provide a copy output current I DAC ' and the output current I DAC . The output current driver circuit 760 multiplies the output current I DAC by a fixed ratio and drives the electrode output 764 in the positive (anode) or negative (cathode) direction to generate the final stimulation pulse. Similar to the current mirror circuit 732, the output current driver circuit 760 also utilizes a boost cascade architecture for high precision and ultra-high output impedance. An anode output switching signal SW A and a cathode output switching signal SW C can be received from a controller such as a controller coupled to the current DAC circuit 704. The controller can include a timing controller to activate the anode signal transistor 765 or the cathode signal transistor 767 and thereby control the polarity and pulse width of the final stimulation. The electrode output 764 can be directly connected to the stimulation electrode included in the nerve stimulator. The output current driver circuit 760 can include a third n-type operational amplifier 768 and a second p-type operational amplifier 772.

[0124] The DAC converter device can include several DAC channels. In some embodiments, the DAC device can include sixteen channels. One or more controllers can be coupled to the channels included in the DAC device to control these channels as described above.

[0125] Now refer to Figure 7B and Figure 7A , an exemplary output current waveform 780 is shown. The output current pulse can be generated by the DAC channel 700 and output at the electrode output 764. The exemplary output current waveform 780 can include an anode or positive current pulse 784, a short delay period 788, and a cathode or negative current pulse 792.

[0126] Now refer to Figure 8A and Figure 7A , a p-type operational amplifier 800 is shown. The p-type operational amplifier 800 can be the first p-type operational amplifier 744 or the second p-type operational amplifier 772. The p-type operational amplifier 800 can receive a positive bias voltage V biasP from a bias circuit, which will be described below. The p-type operational amplifier 800 can be designed to operate when the input is close to the positive power supply voltage V DD .

[0127] Now refer to Figure 8B andFigure 7A , shows an n-type operational amplifier 804. The n-type operational amplifier 804 can be the first n-type operational amplifier 736, the second n-type operational amplifier 740, or the third n-type operational amplifier 768. The n-type operational amplifier 804 can receive a negative bias voltage V from a bias circuit biasN , which will be described below. The p-type operational amplifier 800 can be designed to operate when the input is close to the negative supply voltage V SS .

[0128] Now refer to Figure 8C and Figure 7A , Figure 8A and Figure 8B , shows a bias circuit 808. The bias circuit 808 can receive an internal reference current I OTA , and generate and output a positive bias voltage V biasP and a negative bias voltage V biasN .

[0129] Now refer to Figure 9 and Figure 7A and Figure 8C , shows a voltage-to-current converter circuit 900. The voltage-to-current converter circuit 900 can be used to generate an internal reference current I for the current DAC circuit 704 ref . The voltage-to-current converter circuit 900 can also be used to generate an internal reference current I for the bias circuit 808 OTA . The voltage-to-current converter circuit 900 can use a boost cascade architecture to generate a primary reference current I ref0 . The value of the primary reference current I ref0 can be determined by an external bias resistor as follows: where, V CM is the common voltage. The operational amplifier 904 included in the voltage-current converter circuit 900 can be designed to operate at a VCM of approximately (V DD +V SS ) / 2. The operational amplifier can be biased by a self-bias circuit independent of the power supply and may not require any other reference. The reference current (I ref0 ) is further divided by a factor of 10 and then copied to create I ref1 , I ref2 , …I refn , and each of these reference currents flows to the stimulation channel.

[0130] Now refer to Figure 10, shows a voltage level shifter circuit 1000. The analog front-end circuit requires a high-voltage power supply (+-10V) to fully drive the output electrodes, while the digital controller is designed with a low-voltage power supply (1.8V) to reduce chip area and power consumption. As a result, a voltage level shifter is required to convert the low-voltage control signal into a high-voltage corresponding signal. The voltage level shifter circuit 1000 may include a low-voltage section 1004 and a high-voltage section 1008. The low-voltage section 1004 may include transistors rated at 5V, for example, transistors 1012 and 1016, which are configured to boost the input signal from [0, 1.8V] to [-2.5V, +2.5V]. The high-voltage section 1012 may include transistors rated at 30V, for example, transistors 1020 and 1024, which are configured to further boost the signal from [-2.5V, +2.5V] to the required [-10V, +10V] level.

[0131] Reference Figure 11 And Figure 7A , shows an exemplary process 1100 for calibrating a DAC channel to obtain super-resolution (SR). The DAC channel may be the DAC channel 700 described above. The process may be implemented as instructions on one or more memories included in one or more controllers coupled to the DAC channel. Generally, the process 1100 may receive output current measurements configured for each component of the DAC channel. These measurements may then be used to select a component configuration that outputs a current closest to the input digital value. Compared to prior art such as binary-weighted component groupings (which may require additional unit cells to achieve a given effective resolution), selecting a specific component configuration may allow the output current to have an improved effective resolution and a reduced number of unit cells. The instructions may be executed by at least one processor included in at least one controller.

[0132] At 1104, the process 1100 may set the component configuration of the DAC channel. The process 1100 may select a component configuration that does not have an associated measured anode output current and measured cathode output current, and iterate through each component configuration until each component configuration has an associated measured anode and cathode output current. For example, the controller may provide appropriate digital control signals to output current or voltage from one or more components. For example, the first control switch coupled to the first component and the second control switch coupled to the second component may be turned on, and all control switches coupled to other components may be turned off. The process 1100 may then proceed to 1108.

[0133] At 1108, the process 1100 may activate the anode output switching signal (e.g., SW A) to activate an anode signal transistor (e.g., anode signal transistor 765) included in the DAC channel. The DAC channel can then provide a positive current at the output electrode of the DAC channel. The process can then proceed to 1112.

[0134] At 1112, process 1100 can receive an anode output current value. The anode output current value can be received from a benchtop measuring instrument operable by a person. The anode output current value can correspond to the output amperage that occurs when the selected component configuration is selected. Process 1100 can then proceed to 1116.

[0135] At 1116, process 1100 can save the anode output current value in a memory. The memory can be included in a controller that is coupled to the DAC channel and configured to control the DAC channel as described above. As described below, the controller can use this configuration when controlling the DAC channel to output a desired current. Process 1100 can then proceed to 1120.

[0136] At 1120, process 1100 can deactivate the anode output switching signal. Process 1100 can then proceed to 1124.

[0137] At 1124, process 1100 can activate a cathode output switching signal (e.g., SW C ) to activate a cathode signal transistor (e.g., cathode signal transistor 767) included in the DAC channel. Then, the DAC channel can provide a negative current on the output electrode of the DAC channel. The process can then advance to 1128.

[0138] At 1128, process 1100 can receive a cathode output current value. The cathode output current can be received from a benchtop measuring instrument operable by a person. The cathode output current value can correspond to the output amperage that occurs when the selected component configuration is selected. Process 1100 can then proceed to 1132.

[0139] At 1132, process 1100 can save the cathode output current value in a memory. The memory can be included in a controller that is coupled to the DAC channel and configured to control the DAC channel as described above. As described below, the controller can use this configuration when controlling the DAC channel to output a desired current. Process 1100 can then proceed to 1136.

[0140] At 1136, process 1100 can deactivate the cathode output switching signal. Process 1100 can then proceed to 1140.

[0141] At 1140, process 1100 may determine whether one or more component configurations need to have corresponding measured anode output current and cathode output current. Process 1100 may then proceed to 1144.

[0142] At 1144, if process 1100 determines that one or more component configurations still need to measure the output current (e.g., "yes" at 1144), then process 1100 may proceed to 1104. If process 1100 determines that one or more component configurations no longer need to measure the output current (e.g., "no" at 1144), then process 1100 may end.

[0143] Now refer to Figure 12 and Figure 7A and Figure 11 , an exemplary process 1200 for controlling a DAC channel to output a desired current is shown. The DAC channel may be the DAC channel 700 described above. The process may be implemented as instructions on one or more memories included in one or more controllers coupled to the DAC channel. The instructions may be executed by at least one processor included in at least one controller. For example, a portion of process 1200 may be executed on a first controller that includes a predetermined anode output current and cathode output current associated with a set of component configurations (i.e., the output current measured using the above process 1100), and another portion of process 1200 may be executed on a second controller (such as a timing controller) that is configured to generate digital control signals (D 0 , …, D n ) for a given component configuration, and generate an anode output switching signal SW A and a cathode output switching signal SW C , as described above. The DAC channel may be included in a medical device such as a nerve stimulator.

[0144] At 1204, process 1200 may receive the desired output current. The desired current may be received from an external process that implements the DAC channel as part of a medical device such as a nerve stimulator. The desired output current may correspond to the desired stimulation current. Process 1200 may then proceed to 1208.

[0145] At 1208, process 1200 may determine an anode component configuration for a desired output current based on the desired output current and a predetermined measurement of the output current for the set of component configurations. As described above, each component configuration may have an associated anode output current previously measured using, for example, a bench-top measuring instrument. Process 1200 may determine which component configuration has an associated anode output current closest in value to the desired output current from among the possible component configurations of all the DAC channels. For example, for a desired output current of 1.305 mA, process 1200 may determine an anode output current of 1.304 mA associated with a target component configuration that is closest to the desired output current compared to all other anode output currents, and select the target component configuration as the anode component configuration. Process 1200 may then proceed to 1212.

[0146] At 1212, process 1200 may determine a cathode component configuration for the desired output current based on the desired output current and a predetermined measurement of the output current for the set of component configurations. As described above, each component configuration may have an associated cathode output current previously measured using, for example, a bench-top measuring instrument. Process 1200 may determine which component configuration has an associated cathode output current magnitude closest in value to the desired output current from among the possible component configurations of all the DAC channels. For example, for a desired output current of 1.305 mA, process 1200 may determine a cathode output current of 1.304 mA associated with a target component configuration that is closest to the desired output current compared to all other cathode output currents, and select the target component configuration as the cathode component configuration. Process 1200 may then proceed to 1216.

[0147] At 1216, process 1200 may output a current pulse from the DAC channel based on the anode component configuration and / or the cathode component configuration. In some embodiments, process 1200 may activate appropriate digital control signals (D 0 , …, D n ) for the anode component configuration. For example, if the anode component configuration includes a first component and a third component, digital control signals D 0 and D 2 may be activated. Then, process 1200 may activate the anode output switching signal SW A , thereby causing the anode output current to be output at the output electrode of the DAC channel. Process 1200 may continuously provide the anode output current for a predetermined pulse width period, which may be predetermined or adjusted by an external process to tune process 1200 for a particular application (i.e., nerve stimulation). Then, process 1200 may deactivate the digital control signals (D 0 , …, D n ) and the anode output switching signal SWA 。After a short delay (such as 1 - 2 μs, which depends on the structure of the DAC channel (ideally as close to zero as possible)), process 1200 can activate the appropriate digital control signals (D 0 , …, D n ) for the cathode component configuration. Then, process 1200 can activate the cathode output switching signal SW C , so that the cathode output current is output at the output electrode of the DAC channel. Process 1200 can continuously provide the cathode output current within a predetermined pulse width period. Then, process 1200 can deactivate the digital control signals (D 0 , …, D n ) and the cathode output switching signal SW C . Process 1200 can then proceed to 1204. In some embodiments, process 1200 can only output positive or negative current from the DAC channel. In some embodiments, process 1200 can end.

[0148] Now refer to Figure 13 and Figure 7A , an exemplary process 1300 is provided for determining the manufacturing parameters of a DAC with SR in the presence of mismatch errors. Generally, compared with a typical DAC having the same number of components and another grouping (such as binary technology), process 1300 can be used to improve the actual resolution of the DAC.

[0149] At 1304, process 1300 can determine at least one of the intrinsic resolution N 0 or the number of unit cells. For example, process 1300 can receive an intrinsic resolution N of eight specified by a person such as an engineer 0 . As another example, process 1300 can receive the number of unit cells, such as 255. The number of components can be equal to where N 0 is the intrinsic resolution. The process can normalize the number of unit cells to the intrinsic resolution by setting the intrinsic resolution . Process 1300 can then proceed to 1308.

[0150] At 1308, process 1300 can determine the intrinsic resolution N 0and / or the number of unit cells to determine a set of components. The set of components may include a plurality of components, each component including at least one unit cell as described above. Each unit cell may include one transistor or a pair of transistors. In each component, the (one or more) unit cells may be coupled to a single switch (such as a transistor) to control the current output by the transistor as described above. Process 1300 may use the UN grouping method to determine the grouping of unit cells into components. The unit cells may be grouped according to equation (8) above. Process 1300 may group the unit cells into a base array and a plurality of sub-arrays. Each of the sub-arrays may have a different resolution, and the different resolutions decrease in a logarithmic scale across the number of sub-arrays. Each component included in the sub-array has a number of unit cells equal to a power of 2 (e.g., 2 j , where j is zero or a positive integer). The components of the base array may be determined using the bottom part of equation (8). Generally, for each component l included in the base array (e.g., for all l ∈ [0, N 0 - 1]), process 1300 may determine the number of unit cells to be included in the corresponding component. For a lower component l with a relatively low value (e.g., l < N 0 - N 1 ), process 1300 may set the number of unit cells to be equal to 2 l . For a component l with a relatively high value, process 1300 may determine the number of unit cells by subtracting the sum of l for all from 2 . Thus, the base array may include one or more components that include a number of unit cells not equal to a power of 2. As will be explained below, each unit cell may be associated with a unit cell size. Process 1300 may then proceed to 1312.

[0151] At 1312, process 1300 may determine a target effective resolution value. The target effective resolution value may be used to determine a mismatch error value as will be explained below. The target effective resolution may be specified by an engineer. The target effective resolution value may be greater than the inherent resolution. For example, if the inherent resolution is 10 (e.g., 10 bits), the value of the target effective resolution may be 14, 18, or greater. The target effective resolution value may represent an improvement in accuracy that is 256 times - 512 times greater than the inherent value over 95% of the sampling space of the DAC. Process 1300 may then proceed to 1316.

[0152] At 1316, method 1300 may determine a required mismatch error value for a unit cell based on a target effective resolution value. To achieve an effective resolution of at least the target effective resolution, the required mismatch error value may be the minimum mismatch error ratio (e.g., 10%) required for each unit cell. Process 1300 may estimate the entropy and the number of various mismatch ratios using Monte Carlo simulation at the target resolution, as described above. Then, process 1300 may use an exhaustive search technique to find the optimal set The optimal set may be associated with the mismatch error. Process 1300 may determine the optimal set is the set that achieves the target effective resolution with the lowest mismatch ratio. Then, process 1300 may set the required mismatch error value equal to the mismatch error associated with the optimal set and then the process may proceed to 1320.

[0153] At 1320, process 1300 may determine an initial unit cell size based on the required mismatch error value. Each unit cell included in the component set may initially be set to the initial unit cell size. Process 1300 may set the associated unit cell size associated with each unit cell included in the component set to be equal to the initial unit cell size. The unit cell size and the initial unit cell size may each include a length value and a width value. For example, if the DAC has ten (e.g., N 0The intrinsic resolution of = 10), including the sizes of all one thousand and twenty-four unit cells in the component set, can be set to match the initial unit cell size. The format of the unit cell size can vary depending on the cell type. For example, the size of a transistor can be determined by dividing the width by the length, which can be referred to as W / L. As another example, the size of a capacitor can be determined by multiplying the width by the length, which can be referred to as W*L. A manufacturer such as a foundry can provide measurement results that can be used to determine the initial unit cell size. For example, the measurement results can include the estimated mismatch error ratio of the saturation drain current for different transistor sizes (e.g., length and width). For some unit cell types, smaller unit cell sizes may have a higher mismatch error ratio. Process 1300 can determine the unit cell size that has an estimated mismatch error ratio of the saturation drain current above or closest to the desired mismatch error value. The foundry may not be able to produce a unit cell with the desired mismatch error value (e.g., fabricate a small enough unit cell), and process 1300 can determine that the initial unit cell size is the smallest unit cell size that the foundry can manufacture. The unit cell size can indicate that the unit cell is expected to be the nominal size or the expected size. The manufacturing process may introduce defects that cause differences in the sizes of each unit cell (even between unit cells with the same unit cell size). It should be understood that the unit cell size represents the expected size of a unit cell such as a transistor, and due to the differences introduced by the manufacturing process, the actual sizes of unit cells with the same unit cell size may vary slightly. The unit cell size can be associated with a specific process size (such as 10nm, 14nm, etc.) of the unit cell type (e.g., transistor process size). Although the impact of mismatch error on a transistor may involve factors other than mismatch in the saturation drain current, the measurement results provided by the foundry can provide a starting point for determining the overall mismatch error of a unit cell (e.g., a transistor). In a unit cell including a pair of transistors, the size of each transistor can be determined based on the size of the unit cell. Process 1300 can then proceed to 1324.

[0154] At 1324, process 1300 can determine the effective resolution of the DAC by performing a Monte Carlo simulation. The Monte Carlo simulation can be performed using a statistical model provided by the foundry based on the current unit cell size associated with each unit cell. In an embodiment where the unit cell includes a transistor, the Monte Carlo simulation can be performed at the schematic level using the transistor statistical model (both process and variations) provided by the foundry. The statistical model can take into account most of the mismatch errors except for the parasitic resistance of the metal connections in the schematic layout. Process 1300 can then proceed to 1328.

[0155] At 1328, process 1300 can determine whether the effective resolution determined at 1324 is lower than a target effective resolution. Process 1300 can then proceed to 1332.

[0156] At 1332, if process 1300 determines that the effective resolution is lower than the target effective resolution (e.g., “yes” at 1332), process 1300 can proceed to 1336. If process 1300 determines that the effective resolution is not lower than the target effective resolution (e.g., “no” at 1332), process 1300 can proceed to 1340.

[0157] At 1336, the process can adjust the unit cell size of one or more unit cells included in the component set. For example, process 1300 can increase the length of the transistors included in the component set. In some embodiments, process 1300 can adjust the widths of multiple transistors included in the component set. Process 1300 can adjust the unit cell size of one or more unit cells by randomly selecting one or more unit cells and adjusting the length and / or width of the selected unit cells by a random or predetermined amount. The process dimensions can be fixed for each unit cell (e.g., 10 nm, 14 nm, etc.). In some embodiments, the adjustment amount for each unit cell can be determined by using a random number generator (RNG). For example, a DAC can include an array of 10 unit transistors having a unit cell size of W / L = 100 / 10 nm, which is the minimum size for the process dimensions associated with the unit cell. It may be necessary to include additional mismatch to achieve a mismatch ratio of approximately 10%. An RNG with a normal distribution can be used, having a mean of 100 and a standard deviation of 10 (10% of the mean). The width of each of the 10 unit transistors can be adjusted according to the value generated by the RNG. For example, one unit transistor can be adjusted to 101 / 10 nm by process 1300, another unit transistor can be adjusted to 105 / 10 nm, and another unit transistor can be adjusted to 103 / 10 nm. The width value may not be adjusted to be less than 100 nm because 100 nm is already the minimum size of the transistors in the process. Adjusting the size of one or more unit cells may increase the mismatch of the DAC. Additionally, adjusting the size of one or more randomly selected unit cells can artificially increase the mismatch error of the DAC, which can result in an increase in the effective resolution of the DAC. The process can then proceed to 1324.

[0158] At 1340, process 1300 may determine manufacturing parameters for manufacturing a DAC having an SR based on the component set and the unit cell size of each unit cell included in the component set. Process 1300 may determine a circuit layout that includes a set of manufacturing parameters, such as electrical component values ​​and / or models (resistor values, specific models of capacitors, electrical trace materials, etc.) and electrical connections between components. The circuit layout may include a component set and a unit cell sized according to the unit cell size associated with the component set. The circuit layout may then be used to manufacture a DAC having an SR. The process may then proceed to 1344.

[0159] At 1344, process 1300 may provide manufacturing parameters to a manufacturing facility. For example, process 1344 may provide a circuit layout to a foundry. The foundry may then manufacture a DAC with an SR based on the component set and the unit cell size of each unit cell included in the component set. The foundry may manufacture a DAC with an SR to include the grouping indicated by the component set and the unit cells sized according to the unit cell size associated with the component set. Process 1300 may then end.

[0160] In some embodiments, any suitable computer-readable medium may be used to store instructions for performing the functions and / or processes described herein. For example, in some embodiments, the computer-readable medium may be transient or non-transient. For example, non-transient computer-readable media may include media such as magnetic media (such as hard disks, floppy disks, etc.), optical media (such as compressed disks, digital video disks, Blu-ray disks, etc.), semiconductor media (such as RAM, flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.), any suitable media that is not transient or permanent during transmission, and / or any suitable tangible media. As another example, transient computer-readable media may include signals, wires, conductors, optical fibers, circuits on a network, or any suitable media that is transient during transmission and does not have any permanent state, and / or any suitable intangible media.

[0161] It should be noted that as used herein, the term "mechanism" may encompass hardware, software, firmware, or any suitable combination thereof.

[0162] It should be understood that the above-described processes may be performed or carried out in other orders or sequences not limited to the order and sequence shown and described in the drawings. Figure 11 , Figure 12 and / or Figure 13 Likewise, the steps of the process may be performed or carried out substantially simultaneously. Figure 11 , Figure 12 and / or Figure 13 Some of the above steps of the process may also be performed to reduce waiting time and processing time.

[0163] Referring now to Figure 14 , an exemplary analog-to-digital converter 1400 is shown. The analog-to-digital converter 1400 may receive an analog electrical signal and output a fourteen-bit digital electrical signal. The analog-to-digital converter 1400 may include components grouped using the UN grouping technique. More specifically, the analog-to-digital converter 1400 may include a component set 1404 that includes a plurality of capacitors. Each component included in the component set from C 0 to C n may include one or more capacitors selected according to the above equation (8) based on the inherent resolution of the analog-to-digital converter 1400 and / or the number of capacitors included in the analog of the digital converter 1400. The effective resolution of the device may be four to six bits higher than the inherent resolution of the device. Each component may be coupled to a switch included in the switch group 1408. For example, the first component 1404A may be coupled to the first switch 1408A. The analog-to-digital converter 1400 may further include a digital circuit 1412 configured to selectively activate the switch group 1408 to determine a digital value. The digital circuit 1412 may include a controller. The digital circuit 1416 may be coupled to a memory 1416 on which a set of component configurations is stored, each component configuration being associated with a specific digital value. A digital signal indicative of the digital value may be output at the digital output network 1420. The analog-to-digital converter 1400 may include various subcircuits (not shown), a clock subcircuit, a level shifter subcircuit, etc., as is known in the art.

[0164] The present disclosure presents a new interpretation of the RS architecture that allows a quantization or dequantization process to obtain an effective resolution that exceeds the limits normally allowed by its resource constraints. Using Monte Carlo simulations, it can be shown that SR is feasible by cleverly exploiting a statistical property called "code spreading" (a property unique to redundant structures in the presence of random mismatch errors). By applying the UN method to a 10-bit device, a significant theoretical increase in 8-9 bit effective resolution, or a 256-512-fold increase in precision, was confirmed over 95% of the sample space. The UN grouping method can be applied to various fields of biomedical imaging and data acquisition instruments, especially low-power fully integrated sensors and devices that always require higher resolution, as well as other applications such as audio and video processing, including wired / wireless data transmission and / or data storage, remote sensing technologies such as radar, sonar, ultrasound, and / or infrared sensing, sensors and actuators used in robotics, etc.

[0165] Accordingly, the present disclosure provides systems and methods for generating a super-resolution analog-to-digital converter that provides super-resolution without post-processing and in the presence of mismatch errors.

[0166] The present invention has been described in terms of one or more preferred embodiments, and it should be understood that many equivalents, alternatives, variations, and modifications other than those clearly stated are possible and within the scope of the present invention.

Claims

1. A digital-to-analog converter device, comprising: a set of components, each component included in the set of components comprising a plurality of unit cells, and at least one component including a number of unit cells that is not a power of 2; a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components; an output electrode, coupled to the plurality of switches, the converter device being configured to output an output signal at the output electrode; and a controller, coupled to the plurality of switches and configured to: receive a desired output current; determine an anode component configuration based on the desired output current, the anode component configuration including at least one component included in the set of components; determine a cathode component configuration based on the desired output current, the cathode component configuration including at least one component included in the set of components; output a current pulse at the output electrode channel based on the anode component configuration and the cathode component configuration.

2. The digital-to-analog converter device according to claim 1, wherein, the current pulse includes a positive current pulse and a negative current pulse.

3. The digital-to-analog converter device according to claim 1, wherein, the controller includes a memory, the memory including a set of positive current values and negative current values associated with a set of component configurations, the anode component configuration and the cathode component configuration being included in the set of component configurations.

4. The digital-to-analog converter device according to claim 1, wherein, the anode component configuration includes at least one component not included in the cathode component configuration.

5. The digital-to-analog converter device according to claim 1, wherein, the effective resolution of the device is at least four times greater than the inherent resolution of the device.

6. The digital-to-analog converter device according to claim 5, wherein, the effective resolution of the device is equal to the Shannon entropy of the digital-to-analog converter device, and the inherent resolution is equal to the base-2 logarithm of the number of unit cells plus 1.

7. The digital-to-analog converter device according to claim 1, wherein, the digital-to-analog converter device is included in a nerve stimulator device.

8. The digital-to-analog converter device according to claim 1, wherein, a first unit cell size associated with a first unit cell included in the set of components is different from a second unit cell size associated with a second unit cell included in the set of components, the first unit cell size including the length and width of the first unit cell.

9. The digital-to-analog converter device according to claim 1, wherein, each unit cell includes at least one transistor.

10. A digital-to-analog converter device, comprising: a set of components, each component included in the set of components comprising a plurality of unit cells, each unit cell being associated with a unit cell size indicating the manufacturing specification of the unit cell; a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components; and an output electrode, coupled to the plurality of switches, the converter device being configured to output an output signal at the output electrode; Among them, a first unit cell size associated with a first unit cell included in the component set is different from a second unit cell size associated with a second unit cell included in the component set. The unit cell size of each unit cell is adjusted based on a mismatch error to achieve a target effective resolution.

11. The digital-to-analog converter device according to claim 10, wherein, the unit cell size includes a length value and a width value.

12. The digital-to-analog converter device according to claim 10, wherein, the unit cell size is associated with a transistor process size.

13. The digital-to-analog converter device according to claim 10, wherein, at least one component included in the component set includes a number of unit cells that is not a power of 2.

14. A method for determining manufacturing parameters of a digital-to-analog converter device including a component set, each component included in the component set including at least one unit cell, and each unit cell being associated with a unit cell size, the method comprising: determining a required mismatch error for the unit cells included in the component set based on a target effective resolution value; determining an initial unit cell size based on the required mismatch error; setting the unit cell size of each unit cell included in the component set to be equal to the initial unit cell size; determining the effective resolution of the digital-to-analog converter device by performing a simulation; determining that the effective resolution is lower than the target effective resolution; adjusting the unit cell size of one or more unit cells included in the component set in response to determining that the effective resolution is lower than the target effective resolution; and providing each unit cell size associated with each unit cell to a manufacturing facility.

15. The method according to claim 14, wherein, the target effective resolution is at least four times higher than the inherent resolution.

16. The method according to claim 14, wherein, the unit cell size includes a length value and a width value, and wherein each unit cell includes at least one transistor.

17. The method according to claim 14, wherein, at least one component included in the component set includes a number of unit cells that is not a power of 2.

18. The method according to claim 14, wherein, the simulation is a Monte Carlo simulation.

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