Gate voltage bootstrap switch circuit for ultra-low power analog-to-digital converter

Abstract

The present invention discloses a gate voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter. The single-phase clock SP is adopted. During sampling, the gate voltage of a sampling MOS tube MS is set to Vin+2VDD through a first-stage bootstrap circuit and an auxiliary-stage bootstrap circuit, so that the gate-source voltage difference of the sampling MOS tube MS is constant to 2VDD during the sampling stage, the on-resistance of the sampling tube is further reduced, the linearity is improved, and the accuracy of the sampling switch circuit is also improved. Based on the proposed two-stage bootstrap circuit, a sixth NMOS tube M6 and a seventh NMOS tube M7 are connected in series as a substrate switch of the sampling MOS tube MS. When in a sampling mode, the gate potential of the sampling MOS tube MS is kept consistent with the substrate potential, the liner bias effect of the sampling MOS tube MS is reduced, and the harmonic distortion is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a gate voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter. Background Art

[0002] The sampling switch is the front-end circuit of the ultra-low power analog-to-digital converter, which has the function of sampling and holding. The accuracy and linearity it can achieve will affect the system performance of the entire analog-to-digital converter, so the design of the sampling switch circuit is particularly important. There are three types of sampling switches in the sampling and holding circuit: a single NMOS tube or PMOS tube, a CMOS transmission gate, and a gate voltage bootstrap switch circuit. These three switches have their own advantages. Among them, the gate voltage bootstrap switch circuit has the advantages of minimum on-resistance, large input range, and high linearity, although the structure is complex. Therefore, it is suitable for ultra-low power analog-to-digital converters (Ultra Low Power Analog to Digital Converter) to achieve the sampling and holding function of the input analog signal.

[0003] The traditional gate voltage bootstrap switch circuit structure is as follows Figure 1 As shown in the figure, it consists of a sampling switch tube and a gate voltage bootstrap circuit, where MS is the sampling tube, and C1 and M1~MT constitute the gate voltage bootstrap circuit. As we all know, the on-resistance of the switching transistor is inversely proportional to the gate-source overdrive voltage, and depends to a large extent on the input signal level and the power supply voltage, which will reduce the linearity of the circuit (especially when working at ultra-low voltage). In the traditional gate voltage bootstrap switching circuit, since the gate-source overdrive voltage is still very low, the 1x VDD bootstrap is not enough to reduce the on-resistance and body effect of the switching transistor, and will bring nonlinear problems. Summary of the invention

[0004] The present invention aims to solve the problem that the linearity of the existing gate voltage bootstrap switch circuit is low, and provides a gate voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] The gate voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter is composed of an input inverter, a first-stage bootstrap circuit, an auxiliary-stage bootstrap circuit, a substrate switch and a sampling circuit; the input inverter includes a MOS tube M1 and a MOS tube M2; the first-stage bootstrap circuit includes a MOS tube M3a, a MOS tube M3b, a MOS tube M3c, a MOS tube M3d and a capacitor C1; the auxiliary-stage bootstrap circuit includes a MOS tube M4a, a MOS tube M4b, a MOS tube M4c, a MOS tube M4d, a MOS tube M5 and a capacitor C2; the substrate switch includes a MOS tube M6 and a MOS tube M7; and the sampling circuit includes a sampling MOS tube MS.

[0007] The source of MOS tube M1, the source of MOS tube M3a and the source of MOS tube M4a are connected to the working voltage VDD; the source of MOS tube M2, the source of MOS tube M3c, the source of MOS tube M4c, the source of MOS tube M4d and the source of MOS tube M7 are grounded; the gate of MOS tube M1 and the gate of MOS tube M2 are simultaneously connected to the single-phase clock SP; the upper plate of capacitor C1 is connected to the drain of MOS tube M3a and the source of MOS tube M3b; capacitor The lower plate of C1 is connected to the drain of MOS tube M3c and the source of MOS tube M3d; the gate of MOS tube M3a, the drain of MOS tube M3b and the gate of MOS tube M3d are connected; the gate of MOS tube M3b, the drain of MOS tube M3d and the gate of MOS tube M3c are connected to the drain of MOS tube M2; the upper plate of capacitor C2 is connected to the drain of MOS tube M4a and the source of MOS tube M4b; the lower plate of capacitor C2 is connected to the drain of MOS tube M4c The gate of MOS tube M3d; the gate of MOS tube M4a, the drain of MOS tube M4b, the drain of MOS tube M4d and the gate of MOS tube M5 are connected; the gate of MOS tube M4b is connected to the gate of MOS tube M3b; the gate of MOS tube M4c and the gate of MOS tube M4d are connected to the gate of MOS tube M3c; the source of MOS tube M5 is connected to the source of MOS tube M3d; the drain of MOS tube M5 is connected to the drain of MOS tube M6; the gate of MOS tube M6 is connected to the drain of MOS tube M4b; the source of MOS tube M6 is connected to the drain of MOS tube M7; the gate of MOS tube M7 is connected to the gate of MOS tube M4d; the gate of sampling MOS tube MS is connected to the gate of MOS tube M5, the source of sampling MOS tube MS and the drain of MOS tube M6 are connected to the input signal Vin, the drain of sampling MOS tube MS is connected to the output signal Vout, and the substrate of sampling MOS tube MS is connected to the drain of MOS tube M7.

[0008] As an improvement, the sampling circuit further includes a sampling capacitor CS; the upper plate of the sampling capacitor CS is connected to the drain of the sampling MOS tube MS; and the lower plate of the sampling capacitor CS is grounded.

[0009] In the above solution, MOS tube M1, MOS tube M3a, MOS tube M3b, MOS tube M4a and MOS tube M4b are PMOS tubes; MOS tube M2, MOS tube M3c, MOS tube M3d, MOS tube M4c, MOS tube M4d, MOS tube M5, MOS tube M6 and MOS tube M7 and sampling MOS tube MS are NMOS tubes.

[0010] As an improvement, the substrate of the MOS tube M3a is connected to the drain of the MOS tube M3a; the substrate of the MOS tube M4a is connected to the drain of the MOS tube M4a; and the substrate of the MOS tube M3b is connected to the source of the MOS tube M3b.

[0011] Compared with the prior art, the present invention has the following characteristics:

[0012] 1. The present invention adopts a single-phase clock SP. During sampling, the gate voltage of the sampling MOS tube MS is set to Vin+2VDD through the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit, so that the gate-source voltage difference of the sampling MOS tube MS is constant at 2VDD during the sampling stage. Compared with the traditional structure, the on-resistance of the sampling tube becomes smaller, the linearity is improved, and the accuracy of the sampling switch circuit is also improved;

[0013] 2. Based on the proposed bootstrap circuit structure, NMOS tube M6 and NMOS tube M7 are connected in series as the substrate switch of the sampling MOS tube MS. When in the sampling mode, the gate potential of the sampling MOS tube MS is consistent with the substrate potential, which reduces the substrate bias effect of the sampling MOS tube MS and reduces harmonic distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the schematic diagram of the traditional gate voltage bootstrap switching circuit.

[0015] Figure 2 It is a schematic diagram of the gate voltage bootstrap switch circuit of the present invention.

[0016] Figure 3 1 is a comparison waveform diagram of a single-phase clock signal, an input signal and an output signal in a gate voltage bootstrap switch according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0018] A gate voltage bootstrap switch circuit for ultra-low power analog-to-digital converters, such as Figure 2As shown, it is composed of an input inverter, a first-stage bootstrap circuit, an auxiliary-stage bootstrap circuit, a substrate switch and a sampling circuit. The input inverter includes MOS tubes M1 and M2. The first-stage bootstrap circuit includes MOS tubes M3a, M3b, M3c, M3d and capacitor C1. The auxiliary-stage bootstrap circuit includes MOS tubes M4a, M4b, M4c, M4d, M5 and capacitor C2. The substrate switch includes MOS tubes M6 and M7. The sampling circuit includes a sampling MOS tube MS and a sampling capacitor CS.

[0019] The source of MOS tube M1, the source of MOS tube M3a and the source of MOS tube M4a are connected to the working voltage VDD; the source of MOS tube M2, the source of MOS tube M3c, the source of MOS tube M4c, the source of MOS tube M4d and the source of MOS tube M7 are grounded; the gate of MOS tube M1 and the gate of MOS tube M2 are simultaneously connected to the single-phase clock SP; the upper plate of capacitor C1 is connected to the drain of MOS tube M3a and the source of MOS tube M3b; the lower plate of capacitor C1 is connected to The drain of MOS tube M3c and the source of MOS tube M3d are connected; the gate of MOS tube M3a, the drain of MOS tube M3b and the gate of MOS tube M3d are connected; the gate of MOS tube M3b, the drain of MOS tube M3d and the gate of MOS tube M3c are connected to the drain of MOS tube M2; the upper plate of capacitor C2 is connected to the drain of MOS tube M4a and the source of MOS tube M4b; the lower plate of capacitor C2 and the drain of MOS tube M4c are connected to the gate of MOS tube M3d; The gate of the MOS tube M4a, the drain of the MOS tube M4b, the drain of the MOS tube M4d and the gate of the MOS tube M5 are connected; the gate of the MOS tube M4b is connected to the gate of the MOS tube M3b; the gate of the MOS tube M4c and the gate of the MOS tube M4d are connected to the gate of the MOS tube M3c; the source of the MOS tube M5 is connected to the source of the MOS tube M3d; the drain of the MOS tube M5 is connected to the drain of the MOS tube M6; the gate of the MOS tube M6 is connected to the drain of the MOS tube M4b; the source of the MOS tube M6 is connected to the drain of the MOS tube M7; the gate of the MOS tube M7 is connected to the gate of the MOS tube M4d; the gate of the sampling MOS tube MS is connected to the gate of the MOS tube M5, the source of the sampling MOS tube MS and the drain of the MOS tube M6 are connected to the input signal Vin, the drain of the sampling MOS tube MS and the upper plate of the sampling capacitor CS are connected to the output signal Vout, the substrate of the sampling MOS tube MS is connected to the drain of the MOS tube M7, and the lower plate of the sampling capacitor CS is grounded.

[0020] MOS tube M1, MOS tube M3a, MOS tube M3b, MOS tube M4a and MOS tube M4b are PMOS tubes, and the substrates of all PMOS tubes are connected to the working voltage VDD. MOS tube M2, MOS tube M3c, MOS tube M3d, MOS tube M4c, MOS tube M4d, MOS tube M5, MOS tube M6 and MOS tube M7 and sampling MOS tube MS are NMOS tubes, and the substrates of all NMOS tubes are grounded. In order to improve the stability of the circuit, in the preferred embodiment of the present invention, the substrate of MOS tube M3a is connected to the drain of MOS tube M3a; the substrate of MOS tube M4a is connected to the drain of MOS tube M4a; the substrate of MOS tube M3b is connected to the source of MOS tube M3b, the substrates of the remaining PMOS tubes are connected to the working voltage VDD in a conventional manner, and the substrates of the remaining NMOS tubes are grounded in a conventional manner.

[0021] The working process of the present invention is as follows:

[0022] 1) When the single-phase clock SP is at a low level, the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit are both in the holding mode, the PMOS tube M1 is turned on, so that the drain level of the PMOS tube M1 is set to a high level, thereby turning on the NMOS tubes M3c, M4c, M4d and M7, the lower plate of the capacitor C1 is connected to the ground through the NMOS tube M3c, the lower plate of the capacitor C2 is connected to the ground through the NMOS tube M4c, the gate of the PMOS tube M3a is connected to the ground through the NMOS tube M4c, thereby turning on the PMOS tube M3a, setting the upper plate of the capacitor C1 to VDD, the gate of the PMOS tube M4a is connected to the ground through the NMOS tube M4d, thereby turning on the PMOS tube M4a, setting the upper plate of the capacitor C2 to VDD. Since the PMOS tube M4b is turned off, the capacitor C2 is separated from the sampling MOS tube MS, the gate of the sampling MOS tube MS is connected to the ground through the NMOS tube M4d, thereby turning off the sampling MOS tube MS, and the substrate of the sampling MOS tube MS is grounded through the NMOS tube M7.

[0023] 2) When the single-phase clock SP is at a high level, the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit both work in the sampling mode, and the NMOS tube M2 is turned on, so that the drain of the NMOS tube M2 is connected to a low level, thereby the NMOS tubes M3c, M4c, M4d and M7 are turned off, and the gate of the PMOS tube M4b is connected to the ground through the NMOS tube M2, thereby turning on the PMOS tube M4b, raising the gate voltages of the NMOS tube M5, the sampling MOS tube MS and the NMOS tube M6. Since the NMOS tube M5 is turned on, The lower plate of capacitor C1 is connected to the input signal Vin, that is, the level of the lower plate of capacitor C1 is Vin, the gate of PMOS tube M3b is connected to the ground through NMOS tube M2, so that PMOS tube M3b is turned on, so that capacitor C1 and capacitor C2 (capacitor C1 and capacitor C2 are both precharged to VDD in the holding mode) are connected in series, the gate voltage of sampling MOS tube MS is set to Vin+2VDD, and NMOS tube M6 is turned on, so that the substrate of sampling MOS tube MS is connected to the input signal Vin, so that the gate potential of the sampling tube is consistent with the substrate potential.

[0024] Figure 3 The single-phase clock signal, input signal and output signal comparison waveform diagram in the gate voltage bootstrap switch of the embodiment of the present invention are shown in the figure. The present invention adopts a single-phase clock SP, and sets the gate voltage of the sampling MOS tube MS to Vin+2VDD through the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit during sampling, so that the gate-source voltage difference of the sampling MOS tube MS is constant at 2VDD during the sampling stage, and the on-resistance of the sampling tube is further reduced, so that the linearity is improved, and the accuracy of the sampling switch circuit is also improved; based on the proposed two-stage bootstrap circuit, NMOS tube M6 and NMOS tube M7 are connected in series as the substrate switch of the sampling MOS tube MS. When in the sampling mode, the gate potential of the sampling MOS tube MS is consistent with the substrate potential, reducing the liner bias effect of the sampling MOS tube MS and reducing harmonic distortion.

[0025] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A gate voltage bootstrap switch circuit for an ultra-low power analog-to-digital converter, characterized in that: The invention is composed of an input inverter, a first-stage bootstrap circuit, an auxiliary-stage bootstrap circuit, a substrate switch and a sampling circuit; the input inverter includes a MOS tube M1 and a MOS tube M2; the first-stage bootstrap circuit includes a MOS tube M3a, a MOS tube M3b, a MOS tube M3c, a MOS tube M3d and a capacitor C1; the auxiliary-stage bootstrap circuit includes a MOS tube M4a, a MOS tube M4b, a MOS tube M4c, a MOS tube M4d, a MOS tube M5 and a capacitor C2; the substrate switch includes a MOS tube M6 and a MOS tube M7; the sampling circuit includes a sampling MOS tube MS; The source of the MOS tube M1, the source of the MOS tube M3a and the source of the MOS tube M4a are connected to the working voltage VDD; the source of the MOS tube M2, the source of the MOS tube M3c, the source of the MOS tube M4c, the source of the MOS tube M4d and the source of the MOS tube M7 are grounded; the gate of the MOS tube M1 and the gate of the MOS tube M2 are simultaneously connected to the single-phase clock SP; The upper plate of the capacitor C1 is connected to the drain of the MOS tube M3a and the source of the MOS tube M3b; The lower plate of capacitor C1 is connected to the drain of MOS tube M3c and the source of MOS tube M3d; the gate of MOS tube M3a, the drain of MOS tube M3b and the gate of MOS tube M3d are connected; the gate of MOS tube M3b, the drain of MOS tube M3d and the gate of MOS tube M3c are connected to the drain of MOS tube M2; the upper plate of capacitor C2 is connected to the drain of MOS tube M4a and the source of MOS tube M4b; the lower plate of capacitor C2 and the drain of MOS tube M4c are connected to the gate of MOS tube M3d; the gate of MOS tube M4a, the drain of MOS tube M4b, the drain of MOS tube M4d and the gate of MOS tube M5 are connected; the gate of MOS tube M4b is connected to the gate of MOS tube M3b; The gate of MOS tube M4c and the gate of MOS tube M4d are connected to the gate of MOS tube M3c; the source of MOS tube M5 is connected to the source of MOS tube M3d; the drain of MOS tube M5 is connected to the drain of MOS tube M6; the gate of MOS tube M6 is connected to the drain of MOS tube M4b; the source of MOS tube M6 is connected to the drain of MOS tube M7; the gate of MOS tube M7 is connected to the gate of MOS tube M4d; the gate of sampling MOS tube MS is connected to the gate of MOS tube M5, the source of sampling MOS tube MS and the drain of MOS tube M6 are connected to the input signal Vin, the drain of sampling MOS tube MS is connected to the output signal Vout, and the substrate of sampling MOS tube MS is connected to the drain of MOS tube M7.

2. The gate voltage bootstrap switch circuit for an ultra-low power consumption analog-to-digital converter according to claim 1, characterized in that: The sampling circuit further includes a sampling capacitor CS; the upper plate of the sampling capacitor CS is connected to the drain of the sampling MOS tube MS; and the lower plate of the sampling capacitor CS is grounded.

3. The gate voltage bootstrap switch circuit for ultra-low power consumption analog-to-digital converter according to claim 1, characterized in that: MOS tube M1, MOS tube M3a, MOS tube M3b, MOS tube M4a and MOS tube M4b are PMOS tubes; MOS tube M2, MOS tube M3c, MOS tube M3d, MOS tube M4c, MOS tube M4d, MOS tube M5, MOS tube M6, MOS tube M7 and sampling MOS tube MS are NMOS tubes.

4. The gate voltage bootstrap switch circuit for ultra-low power consumption analog-to-digital converter according to claim 1, characterized in that: The substrate of the MOS tube M3a is connected to the drain of the MOS tube M3a; the substrate of the MOS tube M4a is connected to the drain of the MOS tube M4a; and the substrate of the MOS tube M3b is connected to the source of the MOS tube M3b.

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