Semiconductor arrangement and method of forming the same

Abstract

A semiconductor arrangement and a method for forming the same, the semiconductor arrangement comprising a first dielectric feature passing through a semiconducting layer and a first dielectric layer on a substrate. The semiconductor arrangement comprises a conductive feature passing through the semiconducting layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent to the first dielectric feature and is electrically isolated from the semiconducting layer by the first dielectric feature.

Description

Technical Field

[0001] The present disclosure relates to semiconductor arrangements and methods of forming the same. Background Art

[0002] During semiconductor fabrication, various layers are formed and processed, such as by etching, to create a semiconductor arrangement having one or more features. Summary of the invention

[0003] According to some embodiments, a semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer above a substrate, and a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate, the conductive feature being adjacent to the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

[0004] According to some embodiments, a method of forming a semiconductor arrangement includes forming a dielectric material layer in a first opening in a stack and forming a conductive material layer in a second opening in the dielectric material layer, wherein the conductive material layer establishes a conductive path through the stack to a substrate underlying the stack.

[0005] According to some embodiments, a method of forming a semiconductor arrangement includes forming a first opening in a first dielectric layer above a substrate and in a semiconductive layer above the first dielectric layer; forming a first dielectric feature in the first opening adjacent to a sidewall of the first dielectric layer and a sidewall of the semiconductive layer; and forming a conductive feature in the first opening adjacent to the sidewall of the first dielectric feature, the conductive feature being electrically coupled to the substrate and electrically isolated from the semiconductive layer by the first dielectric feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 12 A semiconductor arrangement is illustrated at various stages of fabrication in accordance with some embodiments.

[0008]

Explanation of symbols

[0009] 100:Semiconductor Layout

[0010] 102:Substrate

[0011] 104: first dielectric layer

[0012] 106: Semiconducting layer

[0013] 108: Shallow trench isolation area

[0014] 108a: shallow trench isolation part

[0015] 108b: shallow trench isolation part

[0016] 110: shallow trench isolation extension layer

[0017] 112: Second dielectric layer

[0018] 114: third dielectric layer

[0019] 116: fourth dielectric layer

[0020] 120: Photoresist

[0021] 121: Opening

[0022] 124: Opening

[0023] 126: Dielectric material layer

[0024] 127: Part 1

[0025] 128: Part 2

[0026] 129: Part 3

[0027] 129a: First dielectric characteristic

[0028] 130: Part 4

[0029] 130a: Second dielectric feature

[0030] 131: Distance

[0031] 132: Doping area

[0032] 133: Conductive material layer

[0033] 134: Part 1

[0034] 135: Part 2

[0035] 136: Part 3

[0036] 137: Part 4

[0037] 138: Gap

[0038] 139: Groove

[0039] 140: Conductive contact

[0040] 141: Conductive characteristics

[0041] 142:Semiconductor Layout

[0042] 143: Doping area

[0043] 144:Semiconductor Layout

[0044] 146: Doping area

[0045] 148: Semiconducting area

[0046] 150:Semiconductor Layout

[0047] 160: Distance

[0048] 162: Width

[0049] 164: Width

[0050] 166:Thickness

[0051] 168: Width DETAILED DESCRIPTION

[0052] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the first feature in the following description is formed on or above the second feature and may include an embodiment in which the first feature and the second feature are formed as direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself represent the relationship between the various embodiments or configurations discussed.

[0053] Additionally, for simplicity of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as depicted in the figures. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0054] Some embodiments relate to a semiconductor arrangement including a first dielectric feature passing through a semiconducting layer and a first dielectric layer below the semiconducting layer. In some embodiments, the semiconductor arrangement includes a conductive feature passing through the semiconducting layer and the first dielectric layer and electrically coupled to a substrate below the first dielectric layer. In some embodiments, the conductive feature is adjacent to the first dielectric feature and is electrically isolated from the semiconducting layer by the first dielectric feature.

[0055] According to some embodiments, the semiconductor arrangement includes a second dielectric feature passing through the semiconductive layer and the first dielectric layer. In some embodiments, the conductive feature is adjacent to the second dielectric feature and is electrically isolated from the semiconductive layer by the second dielectric feature. In some embodiments, the conductive feature is between the first dielectric feature and the second dielectric feature.

[0056] According to some embodiments, one or more semiconductor arrangements are used for conduction through various layers (such as for electrical coupling to a substrate), while at the same time one or more semiconductor arrangements are used for isolation, separation, spacing, etc. According to some embodiments, a first semiconductor arrangement is between an active region and a second semiconductor arrangement. According to some embodiments, the active region is part of a transistor. According to some embodiments, the first semiconductor arrangement between the active region and the second semiconductor arrangement is used to isolate, separate, space, etc. the second semiconductor arrangement from the active region. According to some embodiments, this isolation, separation, spacing, etc. suppresses unintended effects of the second semiconductor arrangement on the active region and vice versa.

[0057] Figure 1 A semiconductor arrangement 100 is shown according to some embodiments. In some embodiments, the semiconductor arrangement 100 includes a substrate 102, a first dielectric layer 104, a semiconducting layer 106, a shallow trench isolation (STI) region 108, a shallow trench isolation extension layer 110, a second dielectric layer 112, a third dielectric layer 114, and a fourth dielectric layer 116. In some embodiments, the substrate 102 acts as a base, a foundation, or a pedestal to hold the various layers during manufacturing. According to some embodiments, the substrate 102 is made of glass. In some embodiments, the substrate 102 is transparent to light. In some embodiments, the substrate 102 is transparent to light of ultraviolet (UV) wavelengths. In some embodiments, the substrate 102 is a p-type semiconductor substrate (P-substrate). In some embodiments, the substrate 102 is an n-type semiconductor substrate (N-substrate). In some embodiments, the substrate 102 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenic phosphide, or other suitable materials. In some embodiments, the substrate 102 includes at least one doped region. According to some embodiments, the substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer.

[0058] According to some embodiments, the first dielectric layer 104 is formed on the substrate 102. In some embodiments, the first dielectric layer 104 contacts the top surface of the substrate 102. In some embodiments, the first dielectric layer 104 is a bottom oxide (BOX). In some embodiments, the first dielectric layer 104 includes at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, the first dielectric layer 104 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques. In some embodiments, the first dielectric layer 104 is at least 0.3 microns thick.

[0059] According to some embodiments, the semiconductive layer 106 is formed on the first dielectric layer 104. In some embodiments, the semiconductive layer 106 contacts the top surface of the first dielectric layer 104. In some embodiments, the semiconductive layer 106 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or other suitable materials. In some embodiments, the semiconductive layer 106 is a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductive layer 106 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the semiconductive layer 106 is at least 5 microns thick.

[0060] According to some embodiments, shallow trench isolation region 108 is formed over semiconductive layer 106. In some embodiments, shallow trench isolation region 108 contacts a top surface of semiconductive layer 106. In some embodiments, shallow trench isolation region 108 comprises at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, shallow trench isolation region 108 is at least partially formed within semiconductive layer 106. In some embodiments, a recess (such as etched) is formed in semiconductive layer 106, and shallow trench isolation region 108 is formed in this recess. In some embodiments, shallow trench isolation region 108 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, shallow trench isolation region 108 is at least 0.2 microns thick.

[0061] According to some embodiments, a shallow trench isolation extension layer 110 is formed over the semiconductive layer 106. In some embodiments, the shallow trench isolation extension layer 110 contacts a top surface of the semiconductive layer 106. In some embodiments, the shallow trench isolation extension layer 110 comprises at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, the shallow trench isolation extension layer 110 is formed simultaneously with the formation of the shallow trench isolation region 108. In some embodiments, the shallow trench isolation extension layer 110 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the shallow trench isolation extension layer 110 is at least 0.01 microns thick.

[0062] According to some embodiments, the second dielectric layer 112 is formed over the shallow trench isolation extension layer 110. In some embodiments, the second dielectric layer 112 contacts the top surface of the shallow trench isolation extension layer 110. In some embodiments, the second dielectric layer 112 includes at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, the second dielectric layer 112 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the second dielectric layer 112 is at least 0.06 microns thick. In some embodiments, the shallow trench isolation region 108 extends over the semiconductive layer 106 so that a portion of the sidewall of the STI region abuts the sidewall of the second dielectric layer 112. In some embodiments, the second dielectric layer 112 has the same composition as the first dielectric layer 104. In some embodiments, the second dielectric layer 112 does not have the same composition as the first dielectric layer 104. In some embodiments, the second dielectric layer 112 is formed in the same manner as the first dielectric layer 104. In some embodiments, the second dielectric layer 112 is not formed in the same manner as the first dielectric layer 104.

[0063] According to some embodiments, the third dielectric layer 114 is formed on at least one of the second dielectric layer 112 or the shallow trench isolation region 108. In some embodiments, the third dielectric layer 114 contacts at least one of the top surface of the second dielectric layer 112 or the top surface of the shallow trench isolation region 108. In some embodiments, the third dielectric layer 114 includes at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, the third dielectric layer 114 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the third dielectric layer 114 is at least 0.12 microns thick. In some embodiments, the third dielectric layer 114 has the same composition as at least one of the first dielectric layer 104 or the second dielectric layer 112. In some embodiments, the third dielectric layer 114 does not have the same composition as at least one of the first dielectric layer 104 or the second dielectric layer 112. In some embodiments, the third dielectric layer 114 is formed in the same manner as at least one of the first dielectric layer 104 or the second dielectric layer 112. In some embodiments, the third dielectric layer 114 is not formed in the same manner as at least one of the first dielectric layer 104 or the second dielectric layer 112.

[0064] According to some embodiments, the fourth dielectric layer 116 is formed on the third dielectric layer 114. In some embodiments, the fourth dielectric layer 116 contacts the top surface of the third dielectric layer 114. In some embodiments, the fourth dielectric layer 116 includes at least one of silicon, oxide, nitride (such as SiN), or other suitable materials. In some embodiments, the fourth dielectric layer 116 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the fourth dielectric layer 116 is at least 0.7 microns thick. In some embodiments, the fourth dielectric layer 116 has the same composition as at least one of the first dielectric layer 104, the second dielectric layer 112, or the third dielectric layer 114. In some embodiments, the fourth dielectric layer 116 does not have the same composition as at least one of the first dielectric layer 104, the second dielectric layer 112, or the third dielectric layer 114. In some embodiments, the fourth dielectric layer 116 is formed in the same manner as at least one of the first dielectric layer 104, the second dielectric layer 112, or the third dielectric layer 114. In some embodiments, the fourth dielectric layer 116 is not formed in the same manner as at least one of the first dielectric layer 104, the second dielectric layer 112, or the third dielectric layer 114.

[0065] Figure 2According to some embodiments, a photoresist 120 formed on the fourth dielectric layer 116 and patterned to have an opening 121 is depicted. In some embodiments, the photoresist 120 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the photoresist 120 includes a photosensitive material, wherein the properties (such as solubility) of the photoresist 120 are affected by light. The photoresist 120 is a negative photoresist or a positive photoresist. With respect to negative photoresists, regions of the negative photoresist become insoluble when illuminated by a light source, so that applying a solvent to the negative photoresist during a subsequent development stage removes the un-irradiated regions of the negative photoresist. The pattern formed in the negative photoresist is thus a negative of the pattern defined by the opaque regions of a template (such as a mask) between the light source and the negative photoresist. In positive photoresist, the irradiated area of ​​positive photoresist becomes soluble and is removed via a coating solvent during development. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque area of ​​a template (such as a mask) between the light source and the positive photoresist. According to some embodiments, one or more etchants are selective so that one or more etchants remove or etch away one or more layers exposed to or not covered by the photoresist at a rate greater than that of the one or more etchants. Therefore, the opening in the photoresist allows one or more etchants to form corresponding openings in one or more layers below the photoresist, and thereby transfer the pattern in the photoresist to one or more layers below the photoresist. After the pattern transfer, the photoresist is stripped or washed away. In some embodiments, the photoresist 120 is at least 0.01 microns thick.

[0066] Figure 3The patterned photoresist 120 is used to remove portions of the fourth dielectric layer 116, the third dielectric layer 114, the shallow trench isolation region 108, the semiconductive layer 106, and the first dielectric layer 104 to form an opening 124 and expose the substrate according to some embodiments. In some embodiments, an etching process is performed to form the opening 124, wherein the opening 121 in the photoresist 120 allows one or more etchants to be applied during the etching process to remove the aforementioned portions of the various layers or stacks down to the substrate 102, while the remaining portions of the photoresist 120 protect or shield the portions of the various layers or stacks covered by the photoresist 120. According to some embodiments, the etching process is a dry etching process. According to some embodiments, the etching process uses at least one of hydrogen chloride (HCl2), hydrogen sulfide (H2S), or other suitable materials. According to some embodiments, the patterned photoresist 120 is removed after the opening 124 is formed. According to some embodiments, the patterned photoresist 120 is removed after one or more layers, elements, features, etc. are formed in the opening 124. In some embodiments, when the opening 124 is formed, the thickness of the fourth dielectric layer 116 decreases, such as from about 0.9 microns to about 0.54 microns. According to some embodiments, when the patterned photoresist 120 is removed, the thickness of the fourth dielectric layer 116 decreases. According to some embodiments, the patterned photoresist 120 is removed after the fourth dielectric layer 116 is patterned but before the third dielectric layer 114, the shallow trench isolation region 108, the semiconductive layer 106, and the first dielectric layer 104 are all removed, so that when at least one of the third dielectric layer 114, the shallow trench isolation region 108, the semiconductive layer 106, or the first dielectric layer 104 is removed, the thickness of the fourth dielectric layer 116 decreases. According to some embodiments, a single template (such as a mask) is used to form the opening 124.

[0067] Figure 4A dielectric material layer 126 is shown formed in the opening 124 according to some embodiments. In some embodiments, the dielectric material layer 126 is formed over (such as in contact with) the sidewalls of the fourth dielectric layer 116, the substrate 102, and one or more layers, regions, etc. that define the opening 124. In some embodiments, a first portion 127 of the dielectric material layer 126 is formed over the fourth dielectric layer 116. In some embodiments, a second portion 128 of the dielectric material layer 126 is formed over the substrate 102. In some embodiments, a third portion 129 of the dielectric material layer 126 is formed on the left side of the opening 124, over the sidewalls of the one or more layers, regions, etc. that define the opening 124. In some embodiments, a fourth portion 130 of the dielectric material layer 126 is formed on the right side of the opening 124, over the sidewalls of the one or more layers, regions, etc. that define the opening 124. In some embodiments, the dielectric material layer 126 includes at least one of HARP, TEOS, HDP, HTO, SiN, USG, liner OX, or other suitable materials. In some embodiments, the dielectric material layer 126 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the dielectric material layer 126 is at least 0.5 microns thick. According to some embodiments, the dielectric material layer 126 includes one or more layers. According to some embodiments, at least some of the one or more layers are formed simultaneously. According to some embodiments, at least some of the one or more layers are not formed simultaneously. According to some embodiments, at least some of the one or more layers are formed in the same manner. According to some embodiments, at least some of the one or more layers are not formed in the same manner. In some embodiments, such layers of dielectric material layer 126 include at least one of HTO / SiN / HTO, TEOS / SiN / HTO, HARP / SiN / TEOS, liner OX / SiN, liner OX / SiN / HARP, liner OX / SiN / HTO, liner OX / HDP, liner OX / USG, liner OX / SiN / USG, USG / SiN, USG / SiN / USG, or other suitable layer combinations. According to some embodiments, a distance 131 between third portion 129 of dielectric material layer 126 and fourth portion 130 of dielectric material layer 126 is about 0.4 microns.

[0068] Figure 5The removal of the first portion 127 of the dielectric material layer 126 and the second portion 128 of the dielectric material layer 126 is illustrated according to some embodiments. In some embodiments, at least one of the first portion 127 of the dielectric material layer 126 or the second portion 128 of the dielectric material layer 126 is removed by at least one of etching, chemical mechanical polishing (CMP), or other suitable techniques. In some embodiments, the first portion 127 of the dielectric material layer 126 and the second portion 128 of the dielectric material layer 126 are removed simultaneously. In some embodiments, the first portion 127 of the dielectric material layer 126 and the second portion 128 of the dielectric material layer 126 are not removed simultaneously. In some embodiments, the first portion 127 of the dielectric material layer 126 and the second portion 128 of the dielectric material layer 126 are removed in the same manner. In some embodiments, the first portion 127 of the dielectric material layer 126 and the second portion 128 of the dielectric material layer 126 are not removed in the same manner. In some embodiments, a portion of fourth dielectric layer 116 is removed when at least one of first portion 127 of dielectric material layer 126 or second portion 128 of dielectric material layer 126 is removed, such that a thickness of fourth dielectric layer 116 is reduced, such as from about 0.54 microns to about 0.4 microns. According to some embodiments, when at least one of first portion 127 of dielectric material layer 126 or second portion 128 of dielectric material layer 126 is removed, a thickness of at least one of third portion 129 of dielectric material layer 126 or fourth portion 130 of dielectric material layer 126 is reduced, such that a distance 131 between third portion 129 of dielectric material layer 126 and fourth portion 130 of dielectric material layer 126 is increased, such as from about 0.4 microns to about 0.46 microns.

[0069] Figure 6 A doped region 132 is shown formed in substrate 102 according to some embodiments. In some embodiments, doped region 132 is aligned between third portion 129 of dielectric material layer 126 and fourth portion 130 of dielectric material layer 126. In some embodiments, doped region 132 is formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, the depth of the dopant in the substrate is controlled by increasing or decreasing the voltage used to direct the dopant into substrate 102. In some embodiments, doped region 132 has a gradient so that the concentration of the dopant changes, such as increases or decreases, as doped region 132 extends into substrate 102. In some embodiments, doped region 132 includes p-type dopant. In some embodiments, doped region 132 includes n-type dopant.

[0070] Figure 7A conductive material layer 133 is shown formed in the opening 124 according to some embodiments. In some embodiments, the conductive material layer 133 is formed over (such as in contact with) the fourth dielectric layer 116, the third portion 129 of the dielectric material layer 126, the fourth portion 130 of the dielectric material layer 126, and the doped region 132 of the substrate 102. In some embodiments, a first portion 134 of the conductive material layer 133 is formed over the fourth dielectric layer 116. In some embodiments, a second portion 135 of the conductive material layer 133 is formed over the doped region 132. In some embodiments, a third portion 136 of the conductive material layer 133 is formed on the left side of the opening 124, over the third portion 129 of the dielectric material layer 126. In some embodiments, a fourth portion 137 of the conductive material layer 133 is formed on the right side of the opening 124, over the fourth portion 130 of the dielectric material layer 126. According to some embodiments, the conductive material layer 133 includes at least one of silicon, cobalt, tungsten, titanium, tantalum (such as tantalum nitride (TaN)), or other suitable materials. In some embodiments, the conductive material layer 133 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the conductive material layer 133 is formed on at least one of the fourth dielectric layer 116, the third portion 129 of the dielectric material layer 126, the fourth portion 130 of the dielectric material layer 126, and the doped region 132 of the substrate 102 using a seed layer. In some embodiments, the seed layer includes at least one of copper, titanium, or other suitable materials. In some embodiments, the seed layer promotes the growth of the conductive material layer 133. In some embodiments, the conductive material layer 133 is at least 0.2 microns thick. In some embodiments, a gap 138 (e.g., including air) is between or defined by the third portion 136 of the conductive material layer 133 and the fourth portion 137 of the conductive material layer 133. In some embodiments, the gap 138 is caused by the relatively high aspect ratio of the opening 124, such that the conductive material layer 133 sandwiches or blocks the opening 124 closer to the fourth dielectric layer 116 before filling the opening 124 closer to the doped region 132.

[0071] Figure 8The removal of the first portion 134 of the conductive material layer 133 and the fourth dielectric layer 116 is shown according to some embodiments. In some embodiments, at least one of the first portion 134 of the conductive material layer 133 or the fourth dielectric layer 116 is removed by at least one of etching, chemical mechanical polishing (CMP), or other suitable techniques. In some embodiments, the first portion 134 of the conductive material layer 133 and the fourth dielectric layer 116 are removed simultaneously. In some embodiments, the first portion 134 of the conductive material layer 133 and the fourth dielectric layer 116 are not removed simultaneously. In some embodiments, the first portion 134 of the conductive material layer 133 and the fourth dielectric layer 116 are removed in the same manner. In some embodiments, the first portion 134 of the conductive material layer 133 and the fourth dielectric layer 116 are not removed in the same manner. In some embodiments, a portion of the third dielectric layer 114 is removed when removing at least one of the first portion 134 of the conductive material layer 133 or the fourth dielectric layer 116, so that the thickness of the third dielectric layer 114 is reduced, such as from about 0.16 microns to about 0.14 microns. According to some embodiments, when at least one of first portion 134 of conductive material layer 133 or fourth dielectric layer 116 is removed, at least one of a portion of third portion 129 of dielectric material layer 126, a portion of fourth portion 130 of dielectric material layer 126, a portion of third portion 136 of conductive material layer 133, or a portion of fourth portion 137 of conductive material layer 133 is removed. According to some embodiments, when at least one of first portion 134 of conductive material layer 133 or fourth dielectric layer 116 is removed, at least one of an uppermost surface of third portion 129 of dielectric material layer 126, an uppermost surface of fourth portion 130 of dielectric material layer 126, an uppermost surface of third portion 136 of conductive material layer 133, or an uppermost surface of fourth portion 137 of conductive material layer 133 is made substantially planar. According to some embodiments, when at least one of the first portion 134 of the conductive material layer 133 or the fourth dielectric layer 116 is removed, at least two of the uppermost surface of the third portion 129 of the dielectric material layer 126, the uppermost surface of the fourth portion 130 of the dielectric material layer 126, the uppermost surface of the third portion 136 of the conductive material layer 133, or the uppermost surface of the fourth portion 137 of the conductive material layer 133 are substantially coplanar.

[0072] According to some embodiments, the third portion 136 of the conductive material layer 133 and the fourth portion 137 of the conductive material layer 133 constitute a conductive feature 141 that establishes a conductive path to the substrate 102 (such as to the doped region 132 of the substrate 102). According to some embodiments, the third portion 129 of the dielectric material layer 126 constitutes a first dielectric feature 129a that electrically isolates the conductive feature 141 from the semiconductive layer 106. According to some embodiments, the fourth portion 137 of the dielectric material layer 126 constitutes a second dielectric feature 130a that electrically isolates the conductive feature 141 from the semiconductive layer 106. According to some embodiments, at least one of the first dielectric feature 129a or the second dielectric feature 130a is adjacent to (such as in contact with) at least one of the conductive feature 141 or the semiconductive layer 106.

[0073] Fig. 9 The diagram shows that a portion of the conductive feature 141 is removed to form a recess 139 between the first dielectric feature 129a and the second dielectric feature 130a according to some embodiments. In some embodiments, an etching process is performed to form the recess 139. According to some embodiments, the etching process is a wet etching process. According to some embodiments, the etching process is a dry etching process. According to some embodiments, the etching process uses at least one of hydrogen chloride (HCl2), hydrogen sulfide (H2S), or other suitable materials. According to some embodiments, the recess 139 is formed so that the uppermost surface of the conductive feature 141 is above the uppermost surface of the semiconductive layer 106. According to some embodiments, the recess 139 is formed so that the uppermost surface of the conductive feature 141 is below the uppermost surface of the semiconductive layer 106. According to some embodiments, the recess 139 is formed so that the uppermost surface of the conductive feature 141 is substantially coplanar with the uppermost surface of the semiconductive layer 106.

[0074] Fig.10A doped region 143 formed in a conductive feature 141 according to some embodiments is illustrated. In some embodiments, the doped region 143 is aligned between the first dielectric feature 129a and the second dielectric feature 130a. In some embodiments, the doped region 143 is formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, the depth of the dopant in the conductive feature 141 is controlled by increasing or decreasing the voltage used to direct the dopant into the conductive feature 141. In some embodiments, the doped region 143 is above the gap 138. In some embodiments, the doped region 143 extends below the gap 138. In some embodiments, the doped region 143 has a gradient so that the concentration of the dopant changes, such as increases or decreases, as the doped region 143 extends into the conductive feature 141. In some embodiments, the doped region 143 includes a p-type dopant. In some embodiments, the doped region 143 includes an n-type dopant.

[0075] Fig.11 A conductive contact 140 is shown formed in the recess 139 according to some embodiments. In some embodiments, the conductive contact 140 includes at least one of copper, tungsten, or other suitable materials. In some embodiments, the conductive contact 140 provides a mechanism to access the conductive path provided by the conductive feature 141. In some embodiments, the conductive contact 140 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. According to some embodiments, the ratio of the distance 160 between the shallow trench isolation portions 108a, 108b to the width 162 of one of the shallow trench isolation portions 108a or 108b (such as, divided by the width 162) is about 7 to 14. According to some embodiments, the ratio of the width 164 of one of the first and second dielectric features 129a or 130a to the thickness 166 of the first dielectric layer 104 (such as, divided by the thickness 166) is about 1.5 to 3. According to some embodiments, a ratio of a width 164 of one of the first and second dielectric features 129a or 130a to a distance 160 between shallow trench isolation portions 108a, 108b (e.g., divided by the distance 160) is about 0.4 to 0.8. According to some embodiments, the distance 160 between shallow trench isolation portions 108a, 108b is equal to twice the width 164 of one of the first and second dielectric features 129a or 130a plus twice the width 168 of one of the third portion 136 of the conductive material layer 133 or the fourth portion 137 of the conductive material layer 133.

[0076] Fig.12A semiconductor arrangement 150 is shown including a plurality of semiconductor arrangements, such as semiconductor arrangement 142 and semiconductor arrangement 144, according to some embodiments. In some embodiments, semiconductor arrangement 144 is similar to Fig. 9 In some embodiments, the semiconductor arrangement 142 is similar to Fig.11 100. According to some embodiments, any number of semiconductor arrangements are contemplated. According to some embodiments, one or more semiconductor arrangements (such as semiconductor arrangement 142) are used for conduction (such as electrically coupling to substrate 102) through various layers, while one or more semiconductor arrangements (such as semiconductor arrangement 144) are used for isolation, separation, spacing, etc. According to some embodiments, semiconductor arrangement 144 isolates, separates, spaces, etc. semiconductor arrangement 142 from an active region. According to some embodiments, the active region includes at least one of doped region 146 or semiconductive region 148. According to some embodiments, semiconductive region 148 is a doped well region, such as a 5 volt n-well (5VNW). According to some embodiments, the active region is part of a transistor. In some embodiments, doped region 146 is N+ doped. In some embodiments, doped region 146 is P+ doped. According to some embodiments, such isolation, separation, spacing, etc. suppresses unintended effects of semiconductor arrangement 142 on at least one of doped region 146 or semiconductive region 148, or vice versa. According to some embodiments, the unintended effect is due to a magnetic field generated when current flows through conductive feature 141 to substrate 102. According to some embodiments, the unintended effect corresponds to crosstalk between semiconductor arrangement 142 and at least one of doped region 146 or semiconductive region 148.

[0077] According to some embodiments, a semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer above a substrate, and a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate, the conductive feature being adjacent to the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

[0078] According to some embodiments, a semiconductor arrangement includes a second dielectric feature passing through the semiconducting layer and the first dielectric layer, the conductive feature being adjacent to the second dielectric feature and between the first dielectric feature and the second dielectric feature.

[0079] According to some embodiments, a semiconductor arrangement includes a shallow trench isolation region in a semiconductive layer, wherein a first dielectric feature and a conductive feature pass through the shallow trench isolation region.

[0080] According to some embodiments, a semiconductor arrangement includes a doped region in a substrate, wherein the conductive feature is electrically coupled to the doped region.

[0081] According to some embodiments, an uppermost surface of the conductive feature is below an uppermost surface of the semiconductive layer.

[0082] According to some embodiments, a semiconductor arrangement includes a second dielectric layer over the semiconducting layer, wherein the first dielectric feature and the conductive feature pass through the second dielectric layer.

[0083] According to some embodiments, a semiconductor arrangement includes a third dielectric layer over the second dielectric layer, wherein the first dielectric feature and the conductive feature pass through the third dielectric layer.

[0084] According to some embodiments, the semiconductor arrangement includes a shallow trench isolation region in the semiconductive layer, wherein the first dielectric feature and the conductive feature pass through the shallow trench isolation region. A third dielectric layer is above the shallow trench isolation region.

[0085] According to some embodiments, a first portion of a sidewall of the shallow trench isolation region abuts a sidewall of the second dielectric layer.

[0086] In accordance with some embodiments, a second portion of the sidewall of the shallow trench isolation region abuts a sidewall of the semiconductive layer.

[0087] According to some embodiments, a first portion of the conductive feature is separated from a second portion of the conductive feature to define an aperture in the conductive feature.

[0088] According to some embodiments, a semiconductor arrangement includes a doped region in a conductive feature.

[0089] According to some embodiments, a method of forming a semiconductor arrangement includes forming a dielectric material layer in a first opening in a stack and forming a conductive material layer in a second opening in the dielectric material layer, wherein the conductive material layer establishes a conductive path through the stack to a substrate underlying the stack.

[0090] According to some embodiments, a method includes forming a first opening, wherein forming the first opening includes removing a portion of a first dielectric layer over a substrate and removing a portion of a semiconductive layer over the portion of the first dielectric layer.

[0091] According to some embodiments, the method includes reducing a height of the conductive material layer such that an uppermost surface of the conductive material layer in the second opening is below an uppermost surface of the semiconductive layer.

[0092] According to some embodiments, a method includes, before forming the conductive material layer, removing a first portion of the dielectric material layer to expose a portion of the substrate, wherein the conductive via passes through the portion of the substrate.

[0093] According to some embodiments, a method includes doping a portion of the substrate after removing a first portion of the dielectric material layer but before forming the conductive material layer.

[0094] According to some embodiments, forming the conductive material layer in the first opening includes forming the conductive material layer to have a pore, such that a first portion of the conductive material layer is separated from a second portion of the conductive material layer by the pore.

[0095] According to some embodiments, a method of forming a semiconductor arrangement includes forming a first opening in a first dielectric layer above a substrate and in a semiconductive layer above the first dielectric layer; forming a first dielectric feature in the first opening adjacent to a sidewall of the first dielectric layer and a sidewall of the semiconductive layer; and forming a conductive feature in the first opening adjacent to the sidewall of the first dielectric feature, the conductive feature being electrically coupled to the substrate and electrically isolated from the semiconductive layer by the first dielectric feature.

[0096] According to some embodiments, a method includes doping a portion of a conductive feature above an aperture in the conductive feature.

[0097] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art may better understand the various aspects of the present disclosure. Those of ordinary skill in the art should understand that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the various embodiments described herein. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0098] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least a portion of the claims.

[0099] Various operations of the embodiments are provided herein. The order in which some or all of these operations are described should not be interpreted as implying that these operations are necessarily related to order. With the benefit of this description, alternative sequencing will be understood. In addition, it will be understood that in each embodiment provided herein, not all operations are necessarily present. In addition, it will be understood that in some embodiments, not all operations are necessary.

[0100] It will be appreciated that in some embodiments, for the purpose of simplicity and ease of understanding, the layers, features, elements, etc. depicted herein are depicted with specific dimensions (such as structural dimensions or orientations) relative to each other, and their actual dimensions are substantially different from the dimensions depicted herein. In addition, there are a variety of techniques for forming the layers, regions, features, elements, etc. described herein, such as at least one of an etching technique, a planarization technique, a implantation technique, a doping technique, a spin coating technique, a sputtering technique, a growth technique, or a deposition technique (such as chemical vapor deposition (CVD)).

[0101] In addition, "exemplary" is used herein to mean serving as an example, an illustration, an illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, as used in this application and the appended claims, "a" and "an" are generally interpreted to mean "one or more", unless otherwise specified or the context clearly points to a singular form. Again, at least one of A and B and / or the like generally means A or B or both A and B. In addition, with respect to the use of "including", "having", "has", "with" or variations thereof, these terms are intended to be inclusive in a manner similar to the term "comprising". Again, unless otherwise specified, "first", "second" or the like are not intended to imply a temporal aspect, a spatial aspect, an order, etc. In fact, these terms are used only as identifiers, names, etc. of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.

[0102] Again, although the disclosure has been shown and described with respect to one or more implementations, other persons generally familiar with the art will think of equivalent changes and modifications based on the reading and understanding of this specification and the accompanying drawings. The disclosure includes all such modifications and changes and is limited only by the scope of the above claims. In particular, with respect to the various functions performed by the above elements, unless otherwise indicated, the terms used to describe these elements are intended to correspond to any element (e.g., functionally equivalent) that performs the specified function of the element, even if the structure is not identical to the disclosed structure. In addition, although specific features of the disclosure may have been disclosed with respect to only one of several implementations, these features may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or specific application.

Claims

1. A semiconductor arrangement, characterized in that include: a first dielectric feature extending through a semi-conductive layer and a first dielectric layer on a substrate; a shallow trench isolation region in the semiconductive layer, wherein the first dielectric feature passes through the shallow trench isolation region; a second dielectric layer on the semiconductive layer, wherein a first portion of a sidewall of the shallow trench isolation region is adjacent to a sidewall of the second dielectric layer; as well as A conductive feature passes through the shallow trench isolation region, the semiconductive layer and the first dielectric layer and is electrically coupled to the substrate. The conductive feature is adjacent to the first dielectric feature and is electrically isolated from the semiconductive layer by the first dielectric feature.

2. The semiconductor arrangement according to claim 1, characterized in that include: A second dielectric feature passes through the semiconductive layer and the first dielectric layer, the conductive feature is adjacent to the second dielectric feature and is located between the first dielectric feature and the second dielectric feature.

3. The semiconductor arrangement according to claim 1, characterized in that include: A doped region in the substrate, wherein the conductive feature is electrically coupled to the doped region.

4. The semiconductor arrangement according to claim 1, characterized in that Wherein an uppermost surface of the conductive feature is below an uppermost surface of the semiconductive layer.

5. The semiconductor arrangement according to claim 1, characterized in that The first dielectric feature and the conductive feature pass through the second dielectric layer.

6. The semiconductor arrangement according to claim 5, characterized in that include: A third dielectric layer is formed on the second dielectric layer, wherein the first dielectric feature and the conductive feature pass through the third dielectric layer.

7. The semiconductor arrangement according to claim 6, characterized in that in The third dielectric layer is above the shallow trench isolation region.

8. The semiconductor arrangement according to claim 1, characterized in that A second portion of the sidewall of the shallow trench isolation region is adjacent to a sidewall of the semiconductive layer.

9. The semiconductor arrangement according to claim 1, characterized in that A first portion of the conductive feature is separated from a second portion of the conductive feature to define a void in the conductive feature.

10. The semiconductor arrangement according to claim 1, characterized in that include: A doped region in the conductive feature.

11. A method of forming a semiconductor arrangement, characterized in that include: forming a dielectric material layer in a first opening in a stack; forming a layer of conductive material in a second opening in the layer of dielectric material, wherein the layer of conductive material establishes a conductive path through the stack to a substrate underlying the stack, and wherein forming the first opening comprises: removing a portion of a first dielectric layer overlying the substrate; and removing a portion of the semi-conductive layer over the portion of the first dielectric layer; and A height of the conductive material layer is reduced so that an uppermost surface of the conductive material layer in the second opening is below an uppermost surface of the semiconductive layer.

12. The method according to claim 11, characterized in that include: Before forming the conductive material layer, a first portion of the dielectric material layer is removed to expose a portion of the substrate, wherein the conductive path passes through the portion of the substrate.

13. The method according to claim 12, characterized in that include: After removing the first portion of the dielectric material layer but before forming the conductive material layer, the portion of the substrate is doped.

14. The method according to claim 11, characterized in that The forming of the conductive material layer in the first opening includes forming the conductive material layer to have a pore, so that a first portion of the conductive material layer is separated from a second portion of the conductive material layer through the pore.

15. A method of forming a semiconductor arrangement, characterized in that include: forming a first opening in a first dielectric layer on a substrate and in a semi-conductive layer on the first dielectric layer; forming a first dielectric feature in the first opening adjacent to a sidewall of the first dielectric layer and a sidewall of the semiconductive layer; forming a conductive feature in the first opening adjacent to a sidewall of the first dielectric feature, the conductive feature electrically coupled to the substrate and electrically isolated from the semiconductive layer by the first dielectric feature; and A portion of the conductive feature is doped above an aperture in the conductive feature.

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