A method for controlling the height of semiconductor dummy components

By cutting grooves and depositing stress relief layers on semiconductor dummy components, the shadowing problem caused by changes in semiconductor dummy components is solved, and high effective control and cost savings are achieved.

CN112735951BActive Publication Date: 2025-04-04SAE TECH DELEVOPMENT DONGGUAN
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Patent Information

Application Number
CN201911028693.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2019-10-28
Publication Date
2025-04-04
Estimated Expiration
2039-10-28

AI Technical Summary

Technical Problem

During the protection process of semiconductor components, the height changes of semiconductor dummy components cause shadows on normal components, and their height needs to be controlled to avoid this.

Method used

The height is controlled by cutting the grooves parallel to each other on the front and back of the semiconductor dummy components, and depositing the stress relief layer of borosilicate glass or borophosphosilicate glass on the bottom and sides of the grooves.

Benefits of technology

This method effectively reduces the height of semiconductor dummy components, reduces the impact on normal components, and reduces costs and energy consumption.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention provides a method for controlling the height of a semiconductor dummy component, comprising the following steps: (1) cutting 2 to 5 mutually parallel grooves on the front side of the semiconductor dummy component and cutting 2 to 5 mutually parallel grooves on the back side of the semiconductor dummy component, the difference between the number of grooves on the front side and the back side is 1, the grooves on the front side and the grooves on the back side are parallel to each other, and the distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap; (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, the material of the stress release layer is borosilicate glass or borophosphosilicate glass; (3) performing annealing at 60 to 120° C. The method of the present invention greatly reduces the height of the semiconductor dummy component by limiting the number of grooves and the cutting position, and reduces the shadow caused to the normal component by the semiconductor dummy component during the process of laying the semiconductor component.
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Description

Technical Field

[0001] The invention relates to the field of semiconductor preparation, and in particular to a method for controlling the height of a semiconductor dummy component. Background Art

[0002] In order to avoid damage to semiconductor components caused by etching during DLC ​​or ion etching, semiconductor dummy components need to be laid on the semiconductor components to protect the semiconductor components. Semiconductor dummy components usually need to be recycled to reduce costs. During this process, the semiconductor dummy components will produce changes in surface curvature, which will increase the height of the semiconductor dummy components, which will cause shadows on normal components when the semiconductor dummy components are laid on the semiconductor components. Therefore, it is necessary to control the height of the semiconductor dummy components to avoid shadows on normal components when the semiconductor dummy components are laid on the semiconductor components. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for controlling the height of a semiconductor dummy component.

[0004] To achieve the above object, the technical solution adopted by the present invention is: a method for controlling the height of a semiconductor dummy component, the method comprising the following steps:

[0005] (1) 2 to 5 mutually parallel grooves are cut on the front side of the semiconductor dummy component and 2 to 5 mutually parallel grooves are cut on the back side of the semiconductor dummy component, the difference in the number of grooves on the front side of the semiconductor dummy component and the back side of the semiconductor dummy component is 1, the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other, and the distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on a plane are equal and do not overlap;

[0006] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass (BSG) or borophosphosilicate glass (BSG);

[0007] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 60 to 120°C.

[0008] The above-mentioned method for controlling the height of semiconductor dummy components cuts grooves on the front and back sides of the semiconductor dummy components and deposits a stress release layer made of borosilicate glass or borophosphosilicate glass on the bottom and sides of the grooves, followed by annealing. By limiting the number of grooves and the cutting positions, the height of the semiconductor dummy components is greatly reduced, and the shadows cast on normal components by the semiconductor dummy components during the process of laying them on semiconductor components are reduced.

[0009] Preferably, the thickness of the stress release layer is 5-10 nm.

[0010] The inventors have found through research that in the above-mentioned method for controlling the height of semiconductor dummy components, a stress release layer having a thickness of 5 to 10 nm can better reduce the height of the semiconductor dummy components.

[0011] Preferably, the thickness of the stress release layer is 6-8 nm.

[0012] Preferably, in step (1), 2 to 4 mutually parallel grooves are cut on the front side of the semiconductor dummy component and 2 to 4 mutually parallel grooves are cut on the back side of the semiconductor dummy component.

[0013] Preferably, in step (1), two mutually parallel grooves are cut on the front side of the semiconductor dummy component and three mutually parallel grooves are cut on the back side of the semiconductor dummy component, or three mutually parallel grooves are cut on the front side of the semiconductor dummy component and two mutually parallel grooves are cut on the back side of the semiconductor dummy component.

[0014] The above-mentioned method for controlling the height of semiconductor dummy components controls the number of cutting grooves, and it is found that the above-mentioned method can reduce the height of semiconductor dummy components to the greatest extent with the minimum number of cutting grooves, and the cost is relatively low.

[0015] Preferably, in step (3), the annealing temperature is 70-80°C.

[0016] The inventors have found through research that the height control method of the semiconductor dummy component can better reduce the height of the semiconductor dummy component at a lower temperature when the annealing temperature in step (3) is 70-80°C, thereby saving energy.

[0017] Preferably, in step (1), the width of the groove is 1.9 to 2.1 mm, and the depth of the groove is 0.7 to 0.9 μm.

[0018] Preferably, in step (1), the width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0019] The beneficial effects of the present invention are as follows: the present invention provides a method for controlling the height of semiconductor dummy components. The method for controlling the height of semiconductor dummy components of the present invention cuts grooves on the front and back sides of the semiconductor dummy components and deposits a stress release layer made of borosilicate glass or borophosphosilicate glass on the bottom and sides of the grooves, followed by annealing. By limiting the number of grooves and the cutting positions, the height of the semiconductor dummy components is greatly reduced, and the shadows cast on normal components by the semiconductor dummy components during the process of laying them on semiconductor components are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram showing the effect of the method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention.

[0021] Among them, (a) is a top view of the semiconductor dummy component, and (b) is a main view. DETAILED DESCRIPTION

[0022] In order to better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below in conjunction with specific embodiments.

[0023] Example 1

[0024] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0025] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0026] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 5 nm;

[0027] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 70°C.

[0028] Example 2

[0029] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0030] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0031] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 6 nm;

[0032] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 70°C.

[0033] Example 3

[0034] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0035] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0036] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 8 nm;

[0037] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 70°C.

[0038] Example 4

[0039] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0040] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0041] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 10 nm;

[0042] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 70°C.

[0043] Example 5

[0044] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0045] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0046] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 5 nm;

[0047] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 80°C.

[0048] Example 6

[0049] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0050] (1) Cut three parallel grooves on the front side of the semiconductor dummy component and cut four parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0051] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass and the thickness of the stress release layer is 5 nm;

[0052] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 80°C.

[0053] Example 7

[0054] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0055] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0056] (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borophosphosilicate glass, and the thickness of the stress release layer is 5 nm;

[0057] (3) Annealing the semiconductor dummy component after the treatment in step (2) at 70°C.

[0058] Comparative Example 1

[0059] As a method for controlling the height of a semiconductor dummy component according to an embodiment of the present invention, the method comprises the following steps:

[0060] (1) Cut two parallel grooves on the front side of the semiconductor dummy component and cut three parallel grooves on the back side of the semiconductor dummy component. The grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other. The distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap. The width of the groove is 2.0 mm and the depth of the groove is 0.8 μm.

[0061] (2) Annealing the semiconductor dummy component after the treatment in step (1) at 70°C.

[0062] Effect Example 1

[0063] The methods of Example 1 and Comparative Example 1 were applied to process 5 semiconductor dummy component samples of the same specifications, respectively, and the thickness of the processed samples was measured. The average thickness of the 5 samples processed by the method of Example 1 and the average thickness of the 5 samples processed by the method of Comparative Example 1 were taken, and it was found that the thickness of the samples processed by Example 1 was 3 nm smaller than the thickness of the samples processed by the comparative example. This shows that the method of Example 1 can reduce the height of the semiconductor dummy components by forming a stress release layer on the bottom and side surfaces of the groove, thereby reducing the shadowing of normal components by the semiconductor dummy components during the process of laying them on semiconductor components.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for controlling the height of a semiconductor dummy component, characterized in that: The method comprises the following steps: (1) 2 to 5 mutually parallel grooves are cut on the front side of the semiconductor dummy component and 2 to 5 mutually parallel grooves are cut on the back side of the semiconductor dummy component, the difference in the number of grooves on the front side of the semiconductor dummy component and the back side of the semiconductor dummy component is 1, the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component are parallel to each other, and the distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap; (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, wherein the material of the stress release layer is borosilicate glass or borophosphosilicate glass; (3) annealing the semiconductor dummy component after the treatment in step (2) at 60 to 120° C.; The thickness of the stress release layer is 5 to 10 nm; In the step (1), the width of the groove is 1.9 to 2.1 mm, and the depth of the groove is 0.7 to 0.9 μm.

2. The method according to claim 1, characterized in that The thickness of the stress release layer is 6-8 nm.

3. The method according to claim 1, characterized in that In the step (1), 2 to 4 mutually parallel grooves are cut on the front side of the semiconductor dummy component and 2 to 4 mutually parallel grooves are cut on the back side of the semiconductor dummy component.

4. The method according to claim 3, characterized in that In the step (1), two mutually parallel grooves are cut on the front side of the semiconductor dummy component and three mutually parallel grooves are cut on the back side of the semiconductor dummy component, or three mutually parallel grooves are cut on the front side of the semiconductor dummy component and two mutually parallel grooves are cut on the back side of the semiconductor dummy component.

5. The method according to claim 1, characterized in that In the step (3), the annealing temperature is 70-80°C.

6. The method according to claim 1, characterized in that In the step (1), the width of the groove is 2.0 mm, and the depth of the groove is 0.8 μm.

Citation Information

Patent Citations

  • Semiconductor device and manufacturing method thereof

    CN103367395A