Integrated chip structure, method for forming the same, and method for forming a multi-dimensional integrated chip

Abstract

In some embodiments, the present disclosure relates to a method of forming an integrated chip structure. The method can be performed by forming a plurality of interconnect layers within a first interconnect structure disposed above an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove portions of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by an inner sidewall disposed directly above the first semiconductor substrate. After performing the edge trimming process, a dielectric protection layer is formed on sidewalls of the first interconnect structure. The present disclosure also relates to a method of forming a multi-dimensional integrated chip and an integrated chip structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated chip structures and methods of forming the same, as well as methods of forming multi-dimensional integrated chips. Background Art

[0002] A multi-dimensional integrated chip is an integrated chip with multiple semiconductor dies that are stacked vertically on each other and electrically connected by through-substrate vias (TSVs) extending through one or more semiconductor dies. As photolithography scaling becomes increasingly difficult, multi-dimensional integrated chips have become an attractive alternative to single-die integrated chips (ICs). Compared to single-die ICs, multi-dimensional integrated chips offer many advantages, such as small footprint, shorter interconnections between adjacent dies, higher device density, and the ability to integrate different types of semiconductor dies (e.g., memory, logic, MEMS, etc.) into a single integrated chip structure. Summary of the invention

[0003] According to one aspect of the present invention, a method for forming an integrated chip structure is provided, comprising: forming a plurality of interconnect layers within a first interconnect structure disposed above an upper surface of a first semiconductor substrate; performing an edge trimming process to remove portions of the first interconnect structure and the first semiconductor substrate along a periphery of the first semiconductor substrate, wherein the edge trimming process causes the first semiconductor substrate to have a recessed surface coupled to the upper surface via an inner sidewall disposed directly above the first semiconductor substrate; and forming a dielectric protection layer on sidewalls of the first interconnect structure after performing the edge trimming process.

[0004] According to another aspect of the present invention, a method for forming a multi-dimensional integrated chip is provided, comprising: forming a plurality of interconnection layers within a dielectric structure above an upper surface of a first substrate; bonding the first substrate to a second substrate, wherein the dielectric structure is located between the first substrate and the second substrate after bonding; performing an edge trimming process to remove portions of the dielectric structure and the first substrate along a periphery of the first substrate; and forming a dielectric protection layer along side walls of the dielectric structure and the first substrate after performing the edge trimming process.

[0005] According to another aspect of the present invention, an integrated chip structure is provided, comprising: a first substrate having an upper surface within a central region and a recessed surface within a recessed region surrounding the central region, wherein the recessed surface extends laterally from the central region to the outermost surface of the first substrate and is vertically located between a lower surface of the first substrate relative to the upper surface; a first plurality of interconnect layers arranged in a first dielectric structure on the upper surface; and a dielectric protection layer located above the recessed surface and along the sidewalls of the first dielectric structure and along the sidewalls of the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1B Some embodiments of an integrated chip structure having a dielectric protection layer configured to mitigate damage caused by an edge trimming process are shown.

[0008] FIG. 2A to FIG. 2D Cross-sectional views of some embodiments of multi-dimensional integrated chip structures with dielectric protection layers are shown.

[0009] FIG. 3A to FIG. 3B Some additional embodiments of multi-dimensional integrated chip structures with dielectric protection layers are shown in cross-sectional views.

[0010] FIG. 4A to FIG. 4D Cross-sectional views of some embodiments of multi-dimensional integrated chip structures with hybrid bonding regions and dielectric capping layers are shown.

[0011] Figure 5 Cross-sectional views of some embodiments of a multi-dimensional integrated chip structure with a dielectric bonding region and a dielectric protection layer are shown.

[0012] Figure 6 to Figure 7 Cross-sectional views of some embodiments of a singulated integrated chip structure with a dielectric cap layer are shown.

[0013] Figures 8 to 12B Cross-sectional views of some embodiments of methods of forming an integrated chip structure having a dielectric cap layer configured to mitigate damage caused by an edge trimming process are shown.

[0014] Fig.13 A flow chart illustrating some embodiments of a method of forming an integrated chip structure having a dielectric protection layer.

[0015] Figures 14 to 17DCross-sectional views of some embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown.

[0016] Fig.18 A flow chart illustrating some embodiments of a method of forming a multi-dimensional integrated chip structure with a dielectric protection layer.

[0017] Figures 19 to 22H Cross-sectional views of some additional embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown.

[0018] Fig.23 Flowcharts illustrating some additional embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer.

[0019] Figures 24 to 27H Cross-sectional views of some additional embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown.

[0020] Fig.28 Flowcharts illustrating some additional embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer. Specific embodiments

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0023] A multi-dimensional integrated chip is typically formed by stacking a plurality of semiconductor substrates (e.g., semiconductor wafers) on top of one another. For example, during a multi-dimensional integrated chip manufacturing process, a first wafer may be bonded to an overlying second wafer. After the bonding process is completed, the second wafer may then be thinned to reduce the thickness of the second wafer. By thinning the second wafer, through-substrate vias (TSVs) can extend through the second wafer to an overlying wafer or bonding structure (e.g., bonding pads).

[0024] The outer surface of a semiconductor wafer generally has a rounded shape, as viewed from a cross-sectional view of the semiconductor wafer. Due to the rounded shape, the thinning process will cause the semiconductor wafer to be thinned along the outer edge, resulting in a sharp outer edge with low mechanical strength. The sharp outer edge may cause the wafer to break and / or peel during subsequent processes. In order to prevent breakage or peeling, an edge trimming process may be performed on the wafer. The edge trimming process is a process in which a mechanical dicing tool removes material along the outer edge of the wafer using a saw blade. By removing material along the outer edge of the wafer, sharp edges with low mechanical strength may be eliminated, and breakage and / or peeling may be mitigated.

[0025] However, it has been recognized that the saw blades used during the edge trimming process can cause damage to the interlayer dielectric (ILD) layer overlying the wafer. For example, the edge trimming process can impose stress on the ILD layer, causing cracks to propagate within the low-k and / or ultra-low-k dielectric material. During subsequent manufacturing processes (e.g., wafer thinning processes, wafer bonding processes, etc.), thermal mechanical forces can exacerbate the damage caused by the edge trimming process, resulting in die failure and / or reduced yield.

[0026] The present disclosure relates to a method for reducing damage to one or more interlayer dielectric (ILD) layers of an overlying semiconductor substrate due to an edge trimming process. In some embodiments, the method includes forming one or more ILD layers above a semiconductor substrate. An edge trimming process is performed to remove portions of the ILD layer and the semiconductor substrate along the periphery of the semiconductor substrate. A dielectric protection layer is then formed above the sidewalls of the one or more ILD layers. The dielectric protection layer protects damaged areas within the one or more ILD layers that may be formed in the edge trimming process, thereby preventing increased damage to the one or more ILD layers during subsequent manufacturing processes.

[0027] Figure 1A to Figure 1B Some embodiments of an integrated chip structure having a dielectric protection layer configured to prevent damage caused by an edge trimming process are shown.

[0028] like Figure 1AAs shown in the cross-sectional view 100 of FIG. 1 , the integrated chip structure includes an interconnect structure 104, which is arranged above the upper surface 102u of the semiconductor substrate 102. The semiconductor substrate 102 includes an inner sidewall 102s that couples the upper surface 102u of the semiconductor substrate 102 to a recessed surface 102r of the semiconductor substrate 102. The recessed surface 102r defines a recessed area 112 surrounding a central area 110 of the semiconductor substrate 102. In the recessed area 112, the semiconductor substrate 102 has a first thickness, which is less than the thickness of the semiconductor substrate 102 in the central area 110. As shown in FIG. Figure 1B As shown in the top view 120 of FIG. 1 , the recessed region 112 extends around the periphery of the semiconductor substrate 102 and extends from the central region 110 of the semiconductor substrate 102 to the outermost surface.

[0029] Reference again Figure 1A In the cross-sectional view 100, a plurality of transistor devices 103 are arranged within an upper surface 102u of a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may include a semiconductor wafer, and the plurality of transistor devices 103 may be arranged within a plurality of separate die regions, the die regions corresponding to the integrated chip dies within the semiconductor wafer, respectively. An interconnect structure 104 is above the upper surface 102u of the semiconductor substrate 102. The interconnect structure 104 includes a plurality of interconnect layers 108, and the plurality of interconnect layers 108 are arranged within a dielectric structure 106 comprising one or more dielectric materials. The plurality of interconnect layers 108 are electrically coupled to the plurality of transistor devices 103. In some embodiments, the plurality of interconnect layers 108 may include conductive contacts 108a, interconnect lines 108b, and / or interconnect vias 108c. In some embodiments, the plurality of interconnect layers 108 may include copper, tungsten, aluminum, and / or the like.

[0030] The dielectric structure 106 includes a plurality of stacked interlayer dielectric (ILD) layers 106a-106e surrounding a plurality of interconnect layers 108. In some embodiments (not shown), the plurality of stacked ILD layers 106a-106e may be vertically separated from each other by an etch stop layer. One or more of the plurality of stacked ILD layers 106a-106e may include a low-k dielectric layer (i.e., a dielectric layer having a dielectric constant less than that of silicon dioxide), an ultra-low-k dielectric material, an extremely low-k dielectric material, etc. In some embodiments, one or more of the plurality of stacked ILD layers 106a-106e may have a damaged region 114 arranged along the outermost sidewall 104s of the interconnect structure 104. The damaged region 114 may be a result of stress from an edge trimming process performed on the interconnect structure 104, and may define a recess in one or more of the plurality of stacked ILD layers 106a-106e. In some embodiments, the damaged region 114 may be within an ILD layer including a low-k dielectric material or an extremely low-k dielectric material.

[0031] The dielectric protection layer 118 is disposed over the semiconductor substrate 102 and along the outermost sidewall 104s of the interconnect structure 104. In some embodiments, the dielectric protection layer 118 may also line the recessed surface 102r, the inner sidewall 102s of the semiconductor substrate 102, and / or be disposed over the interconnect structure 104. In some embodiments, the dielectric protection layer 118 may further extend into the recess 116 within the damaged region 114. Because the dielectric protection layer 118 lines the outermost sidewall 104s of the interconnect structure 104, the dielectric protection layer 118 covers and / or seals the damaged region 114. By covering and / or sealing the damaged region 114 of the interconnect structure 104, the interconnect structure 104 is protected from further damage caused by stress (e.g., thermal stress, mechanical stress, thermomechanical stress, etc.) of subsequent manufacturing processes (e.g., bonding process, grinding process, etc.), thereby improving the yield of the integrated chip.

[0032] It should be understood that in various embodiments, the disclosed dielectric protection layer may be located at different positions along the multi-dimensional integrated chip structure. FIG. 2A to FIG. 2D Cross-sectional views of various embodiments of a dielectric capping layer on a multi-dimensional integrated chip structure having multiple tiers are shown.

[0033] Figure 2A Cross-sectional views of some embodiments of a multi-dimensional integrated chip structure 200 with a dielectric protection layer are shown.

[0034] The multi-dimensional integrated chip structure 200 includes a first level 202a and a second level 202b disposed above the first level 202a. The first level 202a and the second level 202b include semiconductor substrates (e.g., silicon substrates, germanium substrates, etc.), respectively. In some embodiments, the first level 202a and / or the second level 202b may further include an interconnect structure arranged on the semiconductor substrate. In various embodiments, the first level 202a may include an insertion substrate, one or more TSVs, and / or one or more logic devices. In various embodiments, the second level 202b may include one or more logic devices, MEMS (micro-electromechanical systems) devices, memory devices, image sensor devices (e.g., photodiodes), etc.

[0035] The first level 202a has a lower surface 202L and an upper surface 202U. The upper surface 202U is coupled to an inner sidewall 202S of the first level 202a directly above the lower surface 202L. 1 . Inner wall 202S 1 The first level 202a is also coupled to a recessed surface 202R defining the recessed area 112. The recessed surface 202R extends from the inner sidewall 202S of the first level 202a. 1 Extending to the outermost side wall 202S of the first level 202a2 The second level 202b is disposed above the upper surface 202U of the first level 202a and extends from the outermost side wall 202S of the first level 202a. 2 Retract to a non-zero distance.

[0036] The dielectric protection layer 118 is disposed on the inner sidewall 202S of the first level 202a. 1 The outermost wall 202S of the upper and second levels 202b 3 The dielectric protection layer 118 further lines the recessed surface 202R. In some embodiments, the dielectric protection layer 118 may include silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, hafnium dioxide, tantalum pentoxide, aluminum oxide, zinc peroxide, etc. In some embodiments, the dielectric protection layer 118 may have a first thickness t greater than or equal to about 200 angstroms. 1 In some embodiments, the dielectric cap layer 118 may have a first thickness t between about 200 angstroms and about 2000 angstroms. 1 .

[0037] In some embodiments, the dielectric cap layer 118 may extend continuously over the top surface 202T of the second level 202b such that the top surface 202T is completely covered by the dielectric cap layer 118. In other embodiments (not shown), the top surface 202T of the second level 202b is free of the dielectric cap layer 118. In some such embodiments, the dielectric cap layer 118 may have a top surface that is substantially aligned with the top surface 202T of the second level 202b, or is below the top surface 202T of the second level 202b.

[0038] Figure 2B Some further embodiments of a multi-dimensional integrated chip structure with a dielectric cap layer are shown in cross-sectional view 204 .

[0039] like Figure 2B As shown in the cross-sectional view 204, the dielectric protection layer 118 is disposed on the inner sidewall 202S of the first level 202a. 1 The outermost wall 202S of the upper and second levels 202b 3 The recessed surface 202R continuously extends from directly below the dielectric protection layer 118 to laterally cross the outermost sidewall of the dielectric protection layer 118 .

[0040] Figure 2C Some further embodiments of a multi-dimensional integrated chip structure with a dielectric protection layer are shown in cross-sectional view 206 .

[0041] like Figure 2C As shown in the cross-sectional view 206, the dielectric protection layer 118 is disposed on the inner sidewall 202S of the first level 202a. 1 The outermost wall 202S of the upper and second levels 202b3 The dielectric protection layer 118 extends from the inner sidewall 202S of the first level 202a. 1 Continuously extending above the recessed surface 202R and extending to the outermost sidewall 202S of the first level 202a 2 .

[0042] Figure 2D Some further embodiments of a multi-dimensional integrated chip structure with a dielectric cap layer are shown in cross-sectional view 208 .

[0043] like Figure 2D As shown in the cross-sectional view 208, the dielectric protection layer 118 extends from the recessed surface 202R along the inner sidewall 202S of the first level 202a. 1 and the outermost wall 202S of the second level 202b 3 The dielectric cap layer 118 extends onto the top surface 202T of the second level 202b. The dielectric cap layer 118 includes one or more sidewalls 118s that define an opening 210 above the top surface 202T of the second level 202b. In some embodiments, the one or more sidewalls 118s are disposed directly above the top surface 202T of the second level 202b. In some such embodiments, the dielectric cap layer 118 extends beyond the outermost sidewall 202S of the second level 202 by a non-zero distance 212. 3 In some embodiments, non-zero distance 212 is greater than about 500 angstroms. In some such embodiments, non-zero distance is in a range between about 500 angstroms and about 2 mm. In other embodiments, non-zero distance 212 may be greater than about 100 angstroms, greater than about 250 angstroms, greater than about 350 angstroms, or greater than about 400 angstroms.

[0044] Figure 3A Cross-sectional views of some further embodiments of a multi-dimensional integrated chip structure 300 with a dielectric protection layer are shown.

[0045] The multi-dimensional integrated chip structure 300 includes a first level 202a and a second level 202b. The first level 202a includes a first semiconductor substrate 102a. The second level 202b includes an interconnect structure 104, and the interconnect structure 104 includes a plurality of interconnect layers in a dielectric structure disposed on a front side of the second semiconductor substrate 102b. In some embodiments, an upper surface 102u of the first semiconductor substrate 102a extends laterally beyond an opposite side of the second level 202b. A plurality of through-substrate vias (TSVs) 302 extend from the front side of the second semiconductor substrate 102b to the back side of the second semiconductor substrate 102b. In some embodiments, the first semiconductor substrate 102a may have a first thickness that is greater than a second thickness of the second semiconductor substrate 102b.

[0046] The dielectric protection layer 118 is disposed on the sidewalls of the second semiconductor substrate 102b and the interconnect structure 104. The dielectric protection layer 118 separates the first semiconductor substrate 102a from the interconnect structure 104. In some embodiments, the dielectric protection layer 118 may have a top surface 118t that is substantially aligned with a back side of the second semiconductor substrate 102b that faces away from the first semiconductor substrate 102a.

[0047] Figure 3B Cross-sectional views of some further embodiments of a multi-dimensional integrated chip structure 304 with a dielectric protection layer are shown.

[0048] The multi-dimensional integrated chip structure 304 includes a first level 202a and a second level 202b. The first level 202a includes a first semiconductor substrate 102a having a central region 110 surrounded by a recessed region 112. The central region 110 is defined by an upper surface 102u of the first semiconductor substrate 102a. The recessed region 112 is defined by an inner sidewall 102s of the first semiconductor substrate 102a and a recessed surface 102r of the first semiconductor substrate 102a. The second level 202b includes an interconnect structure 104 on the front side of the second semiconductor substrate 102b. In some embodiments, the interconnect structure 104 is bonded to the upper surface 102u by a bonding region 308.

[0049] In some embodiments, the recessed surface 102r of the first semiconductor substrate 102a may have a first width 310. In some embodiments, the first width 310 may be less than or equal to about 2 microns. In other embodiments, the first width 310 may be in a range between about 5 millimeters (mm) and about 20 mm. In other embodiments, the first width 310 may be in a range between about 10 mm and about 30 mm. In some embodiments, the inner sidewall 102s of the first semiconductor substrate 102a may have a first depth 312. In some embodiments, the first depth 312 may be greater than or equal to about 20 microns.

[0050] The dielectric capping layer 118 is disposed on the recessed surface 102r of the first semiconductor substrate 102a and arranged along the inner sidewalls 102s of the first semiconductor substrate 102a, the interconnect structure 104 and the second semiconductor substrate 102b. In some embodiments, the dielectric capping layer 118 may extend over the back side of the second semiconductor substrate 102b.

[0051] FIG. 4A to FIG. 4D Some embodiments of multi-dimensional integrated chip structures including dielectric protection layers and hybrid bonding interfaces are shown.

[0052] Figure 4AA cross-sectional view of some embodiments of a multi-dimensional integrated chip structure 400 having a dielectric cap layer bonded in a face-to-face configuration is shown.

[0053] The multi-dimensional integrated chip structure 400 includes a first level 202a and a second level 202b. The first level 202a includes a first semiconductor substrate 102a having a central region 110 surrounded by a recessed region 112. A first interconnect structure 104a is disposed on the central region 110 of the first semiconductor substrate 102a. The second level 202b includes a second interconnect structure 104b disposed on the front side of the second semiconductor substrate 102b. In some embodiments, the first semiconductor substrate 102a may have a first thickness that is less than a second thickness of the second semiconductor substrate 102b.

[0054] The first interconnect structure 104a is bonded to the second interconnect structure 104b along the hybrid bonding region 402. The hybrid bonding region 402 includes a first plurality of conductive bonding components 404a disposed within a first dielectric layer 406a and a second plurality of conductive bonding components 404b disposed within a second dielectric layer 406b. In some embodiments, the first plurality of conductive bonding components 404a and the second plurality of conductive bonding components 404b may include copper, aluminum, etc. In some embodiments, the first dielectric layer 406a and the second dielectric layer 406b may include oxides, nitrides, etc. Along the hybrid interface 408, the first plurality of conductive bonding components 404a contact the second plurality of conductive bonding components 404b along the first interface, and the first dielectric layer 406a contacts the second dielectric layer 406b along the second interface.

[0055] The dielectric capping layer 118 is disposed on the sidewalls of the first semiconductor substrate 102 a , the first interconnect structure 104 a , the second semiconductor substrate 102 b , the second interconnect structure 104 b , and the hybrid bonding region 402 .

[0056] Figure 4B Cross-sectional views of some further embodiments of a multi-dimensional integrated chip structure 410 having a dielectric cap layer bonded in a face-to-face configuration are shown.

[0057] The multi-dimensional integrated chip structure 410 includes a first dielectric protection layer 118a and a first interconnect structure 104a disposed on the sidewalls of the first semiconductor substrate 102a. The first dielectric protection layer 118a may further extend over the top of the first interconnect structure 104a. The second dielectric protection layer 118b is disposed on the sidewalls of the second semiconductor substrate 102b and the second interconnect structure 104b. The second dielectric protection layer 118b may further extend over the top of the second interconnect structure 104b.

[0058] The first interconnect structure 104a is bonded to the second interconnect structure 104b along a hybrid bonding region 402 disposed between the first dielectric protection layer 118a and the second dielectric protection layer 118b. The hybrid bonding region 402 includes a first plurality of conductive bonding components 404a disposed within the first dielectric layer 406a and a second plurality of conductive bonding components 404b disposed within the second dielectric layer 406b. The first plurality of conductive bonding components 404a are coupled to the first interconnect structure 104a via a first conductive component 405a extending through the first dielectric protection layer 118a. The second plurality of conductive bonding components 404b are coupled to the second interconnect structure 104b via a second conductive component 405b extending through the second dielectric protection layer 118b.

[0059] In some embodiments, the first dielectric layer 406a and the second dielectric layer 406b may extend to the outer sidewalls of the first dielectric protection layer 118a and / or the second dielectric protection layer 118b. In some such embodiments, the first dielectric protection layer 118a or the second dielectric protection layer 118b does not cover the outermost sidewalls of the first dielectric layer 406a and the second dielectric layer 406b.

[0060] Figure 4C Cross-sectional views of some additional embodiments of bonding a multi-dimensional integrated chip structure 412 with a dielectric cap layer in face-to-face and face-to-back configurations are shown.

[0061] The multi-dimensional integrated chip structure 412 includes: a first level 202a, the first level 202a includes a first interconnect structure 104a arranged on a first semiconductor substrate 102a; a second level 202b, the second level 202b includes a second interconnect structure 104b arranged on a second semiconductor substrate 102b; and a third level 202c, the third level 202c includes a third interconnect structure 104c arranged on a third semiconductor substrate 102c.

[0062] The first level 202a is bonded to the second level 202b in a face-to-face configuration such that the first interconnect structure 104a and the second interconnect structure 104b are disposed between the front side of the first semiconductor substrate 102a and the front side of the second semiconductor structure 102b. In some embodiments, the first interconnect structure 104a and the second interconnect structure 104b are bonded together by a first hybrid bonding region 402a.

[0063] The second level 202b is bonded to the third level 202c in a back-to-face configuration such that the third interconnect structure 104c is disposed between the back side of the second semiconductor substrate 102b and the front side of the third semiconductor substrate 102c. In some embodiments, the second semiconductor substrate 102b and the third interconnect structure 104c are bonded together by a second hybrid bonding region 402b.

[0064] The first dielectric protection layer 118a covers the sidewalls of the first semiconductor substrate 102a, the first interconnect structure 104a, the first hybrid bonding region 402a, the second interconnect structure 104b, and the second semiconductor substrate 102b. The first dielectric protection layer 118a further covers the back side of the second semiconductor substrate 102b. The second dielectric protection layer 118b covers the sidewalls of the first dielectric protection layer 118a, the second hybrid bonding region 402b, the third interconnect structure 104c, and the third semiconductor substrate 102c. The second dielectric protection layer 118b further covers the back side of the third semiconductor substrate 102c.

[0065] A first BTSV (back-side through substrate via) 414a extends through the second semiconductor substrate 102b and the first dielectric protection layer 118a to electrically couple the second interconnect structure 104b to the third interconnect structure 104c. A second BTSV 414b extends through the third semiconductor substrate 102c and the second dielectric protection layer 118b.

[0066] Figure 4D Cross-sectional views of some additional embodiments of bonding a multi-dimensional integrated chip structure 416 with a dielectric cap layer in face-to-face and face-to-back configurations are shown.

[0067] The multi-dimensional integrated chip structure 416 includes a first level 202a, a second level 202b, and a third level 202c. The first level 202a is coupled to the second level 202b in a face-to-face configuration through the first hybrid bonding region 402a. The second level 202b is coupled to the third level 202c in a face-to-face configuration through the second hybrid bonding region 402b. The first dielectric protection layer 118a covers the sidewalls and horizontally extending surface of the first level 202a. The second dielectric protection layer 118b covers the sidewalls and horizontally extending surface of the second level 202b. The third dielectric protection layer 118c covers the first dielectric protection layer 118a, the second dielectric protection layer 118b, the first hybrid bonding region 402a, the second hybrid bonding region 402b, and the sidewalls of the third level 202c.

[0068] Figure 5 Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 500 including a dielectric cap layer and a dielectric bonding interface are shown.

[0069] The multi-dimensional integrated chip structure 500 includes a first level 202a, a second level 202b, and a third level 202c. The first level 202a is coupled to the second level 202b in a face-to-face configuration through a first dielectric bonding region 502a, and the first dielectric bonding region 502a has two different dielectric bonding structures 504a-504b that meet along a first dielectric interface 506a. The second level 202b is coupled to the third level 202c in a face-to-face configuration through a second dielectric bonding region 502b, and the second dielectric bonding region 502b has two different dielectric bonding structures 504c-504d that meet along a second dielectric interface 506b. In some embodiments, the third dielectric bonding structure 504c can surround one or more redistribution layers 507 including a conductive material. The first dielectric protection layer 118a covers the sidewalls of the first level 202a, the second level 202b, and the first dielectric bonding region 502a. The second dielectric protection layer 118 b covers the first dielectric protection layer 118 a , the second dielectric bonding region 502 b , and the sidewalls of the third level 202 c .

[0070] The first BTSV 508a extends through the first dielectric protection layer 118a of the first dielectric bonding region 502a, the second level 202b, and the first dielectric interface 506a. The first BTSV 508a electrically contacts the interconnection layer within the first level 202a and the second level 202b. The second BTSV 508b extends through the second dielectric protection layer 118b of the second dielectric bonding region 502b, the third level 202c, and the second dielectric interface 506b. The second BTSV 508b electrically contacts the interconnection layer within the second level 202b and the third level 202c.

[0071] Figure 6 to Figure 7 Cross-sectional views of some embodiments of a singulated (eg, diced) integrated chip structure with a dielectric protection layer are shown.

[0072] Figure 6 A cross-sectional view of some embodiments of a single integrated chip structure 600 is shown.

[0073] The single integrated chip structure 600 includes a plurality of integrated chip (IC) dies 602a-602c stacked on each other. In some embodiments, the plurality of IC dies 602a-602c may include a first IC die 602a, a second IC die 602b, and a third IC die 602c. The first IC die 602a, the second IC die 602b, and the third IC die 602c respectively include an interconnect structure 104 disposed on a semiconductor substrate 102. The first IC die 602a is bonded to the second IC die 602b through a first hybrid bonding region 402a, and the second IC die 602b is bonded to the third IC die 602c through a second hybrid bonding region 402b. The sidewalls of the first IC die 602a, the second IC die 602b, and the third IC die 602c are substantially aligned along a line perpendicular to the top surface of the first IC die 602a.

[0074] The first dielectric protection layer 118a is disposed between two IC dies. For example, in some embodiments, the first dielectric protection layer 118a can be disposed between the second IC die 602b and the third IC die 602c. In some embodiments, the second dielectric protection layer 118b is disposed above the third IC die 602c. The first dielectric protection layer 118a and the second dielectric protection layer 118b have a top surface and a bottom surface extending between the opposite outermost walls of the first dielectric protection layer 118a and the second dielectric protection layer 118b, respectively. In some embodiments, the outermost walls of the first dielectric protection layer 118a and the second dielectric protection layer 118b are substantially aligned with the outermost walls of the first IC die 602a, the second IC die 602b, and the third IC die 602c. In some such embodiments, the first dielectric protection layer 118a and the second dielectric protection layer 118b are not disposed along the sidewalls of one or more of the plurality of IC dies 602a-602c.

[0075] In some embodiments, the first IC die 602a, the second IC die 602b, and / or the third IC die 602c may include damaged regions 114 arranged along a first side of the single integrated chip structure 600. The damaged regions 114 may define one or more recesses 116 within the dielectric material. In some such embodiments, an opposite second side of the single integrated chip structure 600 may be free of damaged regions.

[0076] In some embodiments, a passivation structure 604 including one or more passivation layers 604a-604b is disposed over the second dielectric cap layer 118b. In some embodiments, one or more redistribution layers 606 may be disposed within the passivation structure 604. The one or more redistribution layers 606 may be configured to electrically couple the plurality of IC dies 602a-602c to a bonding pad 608 disposed on or over the passivation structure 604. In some embodiments, a conductive solder bump 610 is disposed on the bonding pad 608.

[0077] Figure 7 Cross-sectional views of some additional embodiments of a single integrated chip structure 700 are shown.

[0078] The single integrated chip structure 700 includes a plurality of integrated chip (IC) dies 602a-602b stacked on each other. In some embodiments, the plurality of IC dies 602a-602b may include a first IC die 602a and a second IC die 602b. The first IC die 602a is bonded to the second IC die 602b via a hybrid bonding region 402. A first dielectric protection layer 118a and a second dielectric protection layer 118b are disposed on opposite sides of the hybrid bonding region 402. The first dielectric protection layer 118a separates the hybrid bonding region 402 from the first interconnect structure 104a. The second dielectric protection layer 118b separates the hybrid bonding region 402 from the second interconnect structure 104b.

[0079] Figures 8 to 12B Cross-sectional views 800-1202 of some embodiments of methods for forming an integrated chip structure with a dielectric protection layer are shown. Although. With respect to the method described Figures 8 to 12B , it should be understood that Figures 8 to 12B It is not limited to this method, but can exist independently as a structure independent of this method.

[0080] like Figure 8 As shown in the cross-sectional view 800 of , one or more transistor devices 103 are formed in the first semiconductor substrate 102a. In various embodiments, the first semiconductor substrate 102a can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments, the transistor device 103 may include a transistor formed by depositing a gate dielectric film and a gate electrode film on the first semiconductor substrate 102a. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric and a gate electrode. The first semiconductor substrate 102a may then be implanted to form a source region and a drain region in the first semiconductor substrate 102a on opposite sides of the gate electrode.

[0081] After forming the transistor device 103, a first interconnect structure 104a is formed over the upper surface 102u of the first semiconductor substrate 102a. The first interconnect structure 104a includes a dielectric structure 106 having one or more stacked ILD layers 106a-106d respectively surrounding one or more interconnect layers 108. In some embodiments, the first interconnect structure 104a may be formed by forming an ILD layer over the first semiconductor substrate 102a, selectively etching the ILD layer (e.g., oxide, low-k dielectric, or ultra-low-k dielectric) to define vias and / or trenches within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the vias and / or trenches to fill the openings, and performing a planarization process (e.g., a chemical mechanical planarization process). In some embodiments, the ILD layer may include one or more of silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), and the like.

[0082] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , an edge trimming process is performed. The edge trimming process removes portions of the first semiconductor substrate 102a and the first interconnect structure 104a along the perimeter of the first semiconductor substrate 102a. By removing portions of the first semiconductor substrate 102a, the edge trimming process defines a central region 110 and a recessed region 112 of the first semiconductor substrate 102a. In some embodiments, the recessed region 112 is defined by a recessed surface coupled to the upper surface 102u through the inner sidewall 102s of the first semiconductor substrate 102a.

[0083] In some embodiments, an edge trimming process can be performed by contacting a blade 902 along a closed loop extending along the periphery of the first semiconductor substrate 102a with the first semiconductor substrate 102a and the first interconnect structure 104a. The blade 902 has a grinding element 904 (e.g., diamond particles) bonded to a core 906 having a circular cross-section. When the grinding element 904 contacts the first semiconductor substrate 102a and the first interconnect structure 104a, the core 906 is configured to rotate around an axis 908. During the edge trimming process, the blade 902 applies stress to the first interconnect structure 104a. The stress damages the first interconnect structure 104a and forms a damaged area 114, which defines one or more recesses 116 within the first interconnect structure 104a.

[0084] like Fig.10As shown in the cross-sectional view 1000 of , a cleaning process may be performed after the edge trimming process is completed. In some embodiments, the cleaning process may include a wet cleaning process. In such an embodiment, the wet cleaning process may expose the first semiconductor substrate 102a and the first interconnect structure 104a to one or more liquids 1002 (e.g., acetone, deionized water, etc.) to remove debris from the edge trimming process. In other embodiments, the cleaning process may include a dry cleaning process.

[0085] like Fig.11 As shown in the cross-sectional view 1100 of , an annealing process 1102 may be performed after the cleaning process is completed. The annealing process 1102 is performed to remove unwanted moisture (e.g., moisture from a wet cleaning process) from the first semiconductor substrate 102a and the first interconnect structure 104a. The annealing process may be performed by exposing the first semiconductor substrate 102a and the first interconnect structure 104a to an elevated temperature. In some embodiments, the elevated temperature may be greater than about 100°C. In some other embodiments, the elevated temperature may be greater than about 200°C, greater than about 300°C, greater than about 400°C, or greater than about 500°C. In some embodiments, the elevated temperature may be in a range between about 100°C and about 300°C.

[0086] like Fig. 12A As shown in the cross-sectional view 1200 of FIG. 1 , a dielectric protection layer 118 is formed along the outermost sidewall 104s of the first interconnect structure 104a defined by the edge trimming process. In some embodiments, the dielectric protection layer 118 may also be formed on the sidewall of the first semiconductor substrate 102a along the recessed surface 102r of the first semiconductor substrate 102a and / or within the recess 116 of the damaged region 114.

[0087] In some embodiments, the dielectric capping layer 118 includes silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, hafnium dioxide, tantalum pentoxide, aluminum oxide, zinc oxide, etc. The dielectric capping layer 118 has a first thickness t along the sidewall of the first interconnect structure 104a. 1 and a second thickness t directly above the first interconnect structure 104a 2 In some embodiments, the first thickness t 1 Greater than or equal to the second thickness t 2 In some embodiments, the first thickness t 1 Greater than or equal to the second thickness t 2 In some embodiments, the first thickness t 1 At the second thickness t 2 between about 80% and about 100%.

[0088] In some embodiments, the dielectric protection layer 118 may be exposed to one or more etchants (e.g., wet etchants used to remove photoresist used in patterning BTSV) during subsequent manufacturing processes. Therefore, the dielectric protection layer 118 must have a thickness and / or density that provides sufficient etching resistance to protect the first interconnect structure 104a from further damage. In some embodiments, the first thickness t of the dielectric protection layer 118 is t 1 A first thickness t greater than or equal to about 200 angstroms. A first thickness t greater than or equal to about 200 angstroms 1 The first interconnect structure 104 can be protected from the subsequent etching process. In some such embodiments, the first thickness t 1 In other embodiments, the first thickness t of the dielectric cap layer 118 is in the range of about 200 angstroms to about 2000 angstroms. 1 The thickness of the second layer may be greater than or equal to about 500 angstroms, greater than or equal to about 750 angstroms, or greater than or equal to about 1000 angstroms. 2 80% of the first thickness t 1 Allows the dielectric cap layer 118 to be efficiently and cost effectively deposited to a first thickness t 1 , the first thickness t 1 The first interconnect structure 104a can be protected from further damage (eg, the first thickness t 1 greater than 200 angstroms).

[0089] In some embodiments, the dielectric protection layer 118 may have a relatively low wet etching rate to protect the first interconnect structure 104a during a subsequent wet etching process. For example, in some embodiments, the dielectric protection layer 118 may have a wet etching rate of less than about 500 angstroms / minute. In some embodiments, when exposed to a wet etchant containing dilute hydrofluoric acid, the wet etching rate of the dielectric protection layer 118 may be less than about 100 angstroms / minute. min (e.g., at room temperature H 2 O to HF ratio is 100:1).

[0090] In some embodiments (in Fig. 12A 1200), the dielectric cap layer 118 may be deposited by a plasma enhanced atomic layer deposition (PEALD) process, an atomic layer deposition (ALD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an integrated profile modulation (IPM) deposition process, or a metal organic chemical vapor deposition (MOCVD) process. In some such embodiments, the dielectric cap layer 118 may completely cover the first semiconductor substrate 102a and the first interconnect structure 104a.

[0091] In other embodiments (in Fig. 12B1202), the dielectric protection layer 118 may be formed by an oblique angle deposition process. In such an embodiment, the dielectric protection layer 118 is formed over the outer region of the first semiconductor substrate 102a, but not over the center of the first semiconductor substrate 102a. The resulting dielectric protection layer 118 includes one or more sidewalls 118s, which define an opening 210 over the first interconnect structure 104a.

[0092] Fig.13 A flow chart of some embodiments of a method 1300 of forming an integrated chip structure with a dielectric protection layer is shown.

[0093] Although the methods disclosed herein (e.g., methods 1300, 1800, 2300, and 2800) are illustrated and described as a series of actions or events, it should be understood that the order of description of such actions or events is not to be construed as limiting. For example, in addition to those actions or events illustrated and / or described herein, certain actions may occur in different orders and / or simultaneously with other actions or events. In addition, all the actions shown may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0094] At 1302, a first interconnect structure is formed over a first semiconductor substrate. Figure 8 A cross-sectional view 800 corresponding to some embodiments of act 1302 is shown.

[0095] At 1304 , an edge trimming process is performed to remove portions of the first semiconductor substrate and the first interconnect structure along a perimeter of the first semiconductor substrate. Fig. 9 Cross-sectional view 900 is shown corresponding to some embodiments of act 1304 .

[0096] At 1306 , a wet cleaning process is performed on the first semiconductor substrate and the first interconnect structure. Fig.10 Cross-sectional view 1000 is shown corresponding to some embodiments of act 1306 .

[0097] At 1308, an annealing process is performed on the first semiconductor substrate and the first interconnect structure. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 1308 .

[0098] At 1310 , a dielectric capping layer is formed along sidewalls of a first interconnect structure defined by the edge trimming process. Fig. 12A Cross-sectional view 1200 is shown corresponding to some embodiments of act 1310 . Fig. 12BCross-sectional view 1202 corresponding to some alternative embodiments of act 1310 is shown.

[0099] Figures 14 to 17D Cross-sectional views 1400-1706 of some embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown. Figures 14 to 17D , it will be understood that Figures 14 to 17D The structure disclosed in is not limited to this method, but can be independently used as a structure independent of this method. In addition, although Figures 14 to 17D The method is illustrated as a wafer-to-wafer (W2W) bonding process, but it should be understood that the method can be applied to a chip-to-wafer (C2W) bonding process.

[0100] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , one or more transistor devices 103 are formed within the first semiconductor substrate 102a. A conductive contact 108a is formed within the first ILD layer 106a, which is formed above the first semiconductor substrate 102a. The conductive contact 108a is coupled to the one or more transistor devices 103. In some embodiments, the first semiconductor substrate 102a and the first ILD layer 106a may be etched to define a TSV opening 1402 extending into the first semiconductor substrate 102a. In such an embodiment, a conductive material may be formed within the TSV opening 1402, and then a planarization process may be performed to define the TSV 302.

[0101] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15, one or more additional ILD layers 106b-106d are formed over the first ILD layer 106a to define the dielectric structure 106 on the first semiconductor substrate 102a. One or more interconnect layers 108 are formed within the one or more additional ILD layers 106b-106d to define the first interconnect structure 104a.

[0102] FIG. 16A to FIG. 16D Some embodiments of edge trimming processes and bonding processes for forming a multi-level semiconductor structure are shown.

[0103] like Fig.16A As shown in the cross-sectional view 1600 of FIG. 16 , an edge trimming process is performed to remove portions of the first semiconductor substrate 102a and the first interconnect structure 104a along the perimeter of the first semiconductor substrate 102a. In some embodiments, the edge trimming process can be performed by contacting the blade 902 with the first semiconductor substrate 102a and the first interconnect structure 104a along a closed loop path.

[0104] like Fig. 16BAs shown in the cross-sectional view 1602 of FIG. 16 , a dielectric protection layer 118 is formed along the sidewalls of the first interconnect structure 104a defined by the edge trimming process. In some embodiments, the dielectric protection layer 118 may also be formed on the sidewalls of the first semiconductor substrate 102a and / or along the recessed surface of the first semiconductor substrate 102a defined by the edge trimming process.

[0105] like Fig. 16C As shown in the cross-sectional view 1604 of FIG. 1 , the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b to form a multi-level semiconductor structure having a first level 202a and a second level 202b. In some embodiments, the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b through the dielectric protection layer 118. In other embodiments (not shown), the first semiconductor substrate 102a may be bonded to the second semiconductor substrate 102b through an additional bonding region layer.

[0106] like Fig.16D As shown in the cross-sectional view 1606 of , the first semiconductor substrate 102a is thinned. In various embodiments, the first semiconductor substrate 102a can be thinned by etching and / or mechanically grinding the back side of the first semiconductor substrate 102a along line 1608. In some embodiments, the first semiconductor substrate 102a can be thinned by a first grinding process, a subsequent second grinding process, and a chemical mechanical polishing (CMP) process. In some embodiments, the first grinding process can achieve a first surface roughness, the second grinding process can achieve a second surface roughness less than the first surface roughness, and the CMP process can achieve a third surface roughness less than the second surface roughness.

[0107] 17A to 17D Some alternative embodiments of edge trimming processes and bonding processes for forming multi-level semiconductor structures are shown.

[0108] like Fig.17A As shown in the cross-sectional view 1700 of FIG. 17 , an edge trimming process is performed to remove portions of the first semiconductor substrate 102 a and the first interconnect structure 104 a along a perimeter of the first semiconductor substrate 102 a .

[0109] like Fig. 17B As shown in the cross-sectional view 1702 of FIG. 17 , a first dielectric protection layer 118 a is formed along the sidewalls of the first interconnect structure 104 a defined by the edge trimming process. In some embodiments, the first dielectric protection layer 118 a may also be formed on the sidewalls of the first semiconductor substrate 102 a and / or along the recessed surface of the first semiconductor substrate 102 a defined by the edge trimming process.

[0110] like Fig. 17CAs shown in the cross-sectional view 1704 of FIG. 1 , the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b to form a multi-level semiconductor structure having a first level 202a and a second level 202b. In some embodiments, a second edge trimming process may be performed on the second semiconductor substrate 102b before bonding. In such an embodiment, a second dielectric protection layer 118b may be formed over the second semiconductor substrate 102b before bonding.

[0111] In some embodiments, prior to bonding, one or more conductive features 405 may be formed to extend through the first dielectric protection layer 118a and the second dielectric protection layer 118b. In some such embodiments, the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b through the first dielectric protection layer 118a and the second dielectric protection layer 118b. In other embodiments (not shown), the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b through a bonding region (e.g., a hybrid bonding region or a dielectric bonding region).

[0112] like Fig.17D As shown in the cross-sectional view 1706 , the first semiconductor substrate 102 a is thinned along line 1708 .

[0113] Fig.18 A flow chart illustrating some embodiments of a method 1800 of forming a multi-layer semiconductor structure with a dielectric cap layer.

[0114] At 1802, one or more transistor devices are formed within a first semiconductor substrate. Fig.14 Cross-sectional view 1400 is shown corresponding to some embodiments of act 1802 .

[0115] At 1804 , a through substrate via (TSV) is formed in a first semiconductor substrate. Fig.14 Cross-sectional view 1400 is shown corresponding to some embodiments of act 1804 .

[0116] At 1806 , a first interconnect structure is formed over a first semiconductor substrate. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 1806 .

[0117] At 1808 , an edge trimming process is performed on the first interconnect structure and the first semiconductor substrate. Fig.16A Cross-sectional view 1600 is shown corresponding to some embodiments of act 1808 . Fig.17A Cross-sectional view 1700 is shown corresponding to some alternative embodiments of act 1808 .

[0118] At 1810, a dielectric capping layer is formed along sidewalls of the first interconnect structure. Fig. 16BCross-sectional view 1602 corresponding to some embodiments of act 1810 is shown. Fig. 17B Cross-sectional view 1702 corresponding to some alternative embodiments of act 1810 is shown.

[0119] At 1812 , the first semiconductor substrate is bonded to the second semiconductor substrate to form a multi-level semiconductor structure. Fig. 16C Cross-sectional view 1604 is shown corresponding to some embodiments of act 1812 . Fig. 17C Cross-sectional view 1704 is shown corresponding to some alternative embodiments of act 1812 .

[0120] At 1814, the first semiconductor substrate is thinned. Fig.16D Cross-sectional view 1606 is shown corresponding to some embodiments of act 1814 . Fig.17D Cross-sectional view 1706 is shown corresponding to some alternative embodiments of act 1814 .

[0121] At 1816, the multilayer semiconductor structure is diced to form a plurality of multi-dimensional integrated chips.

[0122] Figures 19 to 22H Cross-sectional views 1900-2216 of some other embodiments of methods for forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown. Although. With respect to the method described Figure 19-22H , it should be understood that Figures 19 to 22H The structure disclosed in the method may not be limited to this method, but may exist independently as a structure independent of this method. Figures 19 to 22H The method is illustrated as a wafer-to-wafer (W2W) bonding process, but it should be understood that the method can be applied to a chip-to-wafer (C2W) bonding process.

[0123] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 19 , one or more transistor devices 103 are formed in the first semiconductor substrate 102a. A conductive contact 108a is formed in the first ILD layer 106a formed above the first semiconductor substrate 102a. In some embodiments, TSVs 302 may be subsequently formed in the first semiconductor substrate 102a.

[0124] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2 , one or more additional ILD layers 106b-106d are formed on the first ILD layer 106a to define the dielectric structure 106 on the first semiconductor substrate 102a. One or more interconnect layers 108 are formed within the one or more additional ILD layers 106b-106d to define the first interconnect structure 104a.

[0125] FIG. 21A to FIG. 21DCross-sectional views of some embodiments of edge trimming processes and bonding processes for forming a multi-level semiconductor structure are shown.

[0126] like Fig.21A As shown in the cross-sectional view 2100 of FIG. 21 , the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b to form a multi-level semiconductor structure having a first level 202a and a second level 202b. In some embodiments, the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b via a bonding region 308 .

[0127] like Fig. 21B As shown in the cross-sectional view 2102 of FIG. 2104 , the first semiconductor substrate 102a is thinned. In various embodiments, the first semiconductor substrate 102a may be thinned by etching along line 2104 and / or mechanically grinding the back side of the first semiconductor substrate 102a.

[0128] like Fig. 21C As shown in the cross-sectional view 2106 of FIG. 21 , an edge trimming process is performed to remove portions of the first semiconductor substrate 102 a , the second semiconductor substrate 102 b , and the first interconnect structure 104 a along a perimeter of the second semiconductor substrate 102 a .

[0129] like Fig.21D As shown in the cross-sectional view 2108 of FIG. 21 , a dielectric protection layer 118 is formed along the sidewalls of the first interconnect structure 104a defined by the edge trimming process. In some embodiments, the dielectric protection layer 118 may also be formed on the sidewalls of the first semiconductor substrate 102a, the sidewalls of the second semiconductor substrate 102b, and / or along the recessed surface of the second semiconductor substrate 102b.

[0130] FIG. 22A to FIG. 22H Some additional embodiments of edge trimming processes and bonding processes for forming a multi-level semiconductor structure are shown.

[0131] like Fig.22A As shown in the cross-sectional view 2200 of , a first plurality of conductive bonding features 404a are formed in the first dielectric layer 406a formed above the first interconnect structure 104a.

[0132] like Fig. 22B As shown in the cross-sectional view 2202 of FIG. 2 , the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b to define a multi-level semiconductor structure including the first level 202a and the second level 202b. In some embodiments, the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b by a first hybrid bonding region 402a formed by contacting a first plurality of conductive bonding features 404a in the first dielectric layer 406a with a second plurality of conductive bonding features 404b in the second dielectric layer 406b.

[0133] like Fig. 22C As shown in the cross-sectional view 2204 of FIG. 1 , a first edge trimming process is performed to remove a portion of the multi-level semiconductor structure along a periphery of the second semiconductor substrate 102 b .

[0134] like Fig.22D As shown in the cross-sectional view 2206 of FIG. 2207 , a first dielectric protection layer 118a is formed along the sidewalls of the first level 202a and the second level 202b defined by the first edge trimming process. In some embodiments, the first dielectric protection layer 118a may also be formed on the recessed surface of the second semiconductor substrate 102b.

[0135] like Fig.22E As shown in the cross-sectional view 2208 , the first semiconductor substrate 102 a may be thinned along line 2210 .

[0136] like Fig.22F As shown in the cross-sectional view 2212 of FIG. 22 , the third semiconductor substrate 102c and the third interconnect structure 104c are bonded to the second semiconductor substrate 102b through the second hybrid bonding region 402b to form a third level 202c of the multi-level semiconductor structure.

[0137] like Figure 22G As shown in the cross-sectional view 2214 of FIG. 2214 , a second edge trimming process is performed to remove portions of the third semiconductor substrate 102 c and the third interconnect structure 104 c. In some embodiments, the second edge trimming process may also remove portions of the first dielectric protection layer 118 a.

[0138] like Fig.22H As shown in the cross-sectional view 2214 of FIG. 2215 , a second dielectric protection layer 118b is formed along the sidewalls of the first level 202a, the second level 202b, and the third level 202c defined by the second edge trimming process. After forming the second dielectric protection layer 118b, a second thinning process may be performed along line 2218 to reduce the thickness of the third semiconductor substrate 102c.

[0139] Fig.23 A flow chart illustrating some other embodiments of a method 2300 of forming a multi-level semiconductor structure having a dielectric cap layer.

[0140] At 2302, one or more transistor devices are formed within a first semiconductor substrate. Fig.19 Cross-sectional view 1900 corresponding to some embodiments of act 2302 is shown.

[0141] At 2304 , a through substrate via (TSV) is formed in the first semiconductor substrate. Fig.19 Cross-sectional view 1900 corresponding to some embodiments of act 2304 is shown.

[0142] At 2306 , a first interconnect structure is formed over the first semiconductor substrate. Fig. 20 Cross-sectional view 2000 is shown corresponding to some embodiments of act 2306 .

[0143] At 2308 , the first semiconductor substrate is bonded to the second semiconductor substrate to define a multi-level semiconductor structure. Fig.21A Cross-sectional view 2100 corresponding to some embodiments of act 2308 is shown. FIG. 22A to FIG. 22B Cross-sectional views 2200 - 2202 corresponding to some alternative embodiments of act 2308 are shown.

[0144] At 2310, a thinning process is performed on the multi-level semiconductor structure. In some embodiments, the thinning process can be performed before actions 2312-2314. Fig. 21B Some such embodiments are shown in cross-sectional view 2102. In some embodiments, a thinning process may be performed after steps 2312-2314. Fig.22E A cross-sectional view 2208 of some such embodiments is shown.

[0145] At 2312, an edge trimming process is performed on the multi-level semiconductor structure. Fig. 21C Cross-sectional view 2106 corresponding to some embodiments of act 2312 is shown. Fig. 22C Cross-sectional view 2204 corresponding to some alternative embodiments of act 2312 is shown.

[0146] At 2314 , a dielectric capping layer is formed along sidewalls of the multi-level semiconductor structure. Fig.21D Cross-sectional view 2108 is shown corresponding to some embodiments of act 2314 . Fig.22D Cross-sectional view 2206 corresponding to some alternative embodiments of act 2314 is shown.

[0147] In some embodiments, actions 2308 - 2314 may be repeated (along line 2316 ) to form a multi-dimensional semiconductor structure having more than two levels. FIG. 22F to FIG. 22H Cross-sectional views 2212 - 2216 of some embodiments corresponding to repetitions of acts 2308 - 2314 are shown.

[0148] At 2318, the multi-level semiconductor structure is diced to form a plurality of multi-dimensional integrated chips.

[0149] Figures 24 to 27H Cross-sectional views 2400-2720 of some additional embodiments of methods of forming a multi-dimensional integrated chip structure with a dielectric protection layer are shown. Figures 24 to 27H , will understand that in Figures 24 to 27HThe structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0150] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , one or more transistor devices 103 are formed in a first semiconductor substrate 102a. A conductive contact 108a is formed in a first ILD layer 106a formed above the first semiconductor substrate 102a.

[0151] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, one or more additional ILD layers 106b-106d are formed over the first ILD layer 106a to define the dielectric structure 106 on the first semiconductor substrate 102a. One or more interconnect layers 108 are formed within the one or more additional ILD layers 106b-106d to define the first interconnect structure 104a.

[0152] FIG. 26A to FIG. 26H Cross-sectional views of some embodiments of edge trimming processes and bonding processes for forming a multi-level semiconductor structure are shown.

[0153] like Fig.26A As shown in the cross-sectional view 2600 of , a first plurality of conductive bonding features 404a are formed in the first dielectric layer 406a formed above the first interconnect structure 104a.

[0154] like Fig.26B As shown in the cross-sectional view 2602 of FIG. 26 , the first semiconductor substrate 102 a is bonded to the second semiconductor substrate 102 b to define a multi-level semiconductor structure including a first level 202 a and a second level 202 b .

[0155] like Fig.26C As shown in the cross-sectional view 2604 of FIG. 26 , a first edge trimming process is performed to remove portions of the first semiconductor substrate 102a and the first interconnect structure 104a along the perimeter of the second semiconductor substrate 102b. In some embodiments, a first thinning process may also be performed to thin the first semiconductor substrate 102a along line 2606.

[0156] like Fig.26D As shown in the cross-sectional view 2608 of FIG. 2608 , a first dielectric protection layer 118a is formed along the sidewalls of the first level 202a and the second level 202b defined by the first edge trimming process. In some embodiments, the first dielectric protection layer 118a may also be formed on the recessed surface of the second semiconductor substrate 102b.

[0157] After forming the first dielectric capping layer 118a, a first backside through substrate via (BTSV) opening 2610 is formed. The first BTSV opening 2610 extends through the first dielectric capping layer 118a and the first semiconductor substrate 102a to the interconnect layer within the first interconnect structure 104a. Subsequently, the first BTSV opening 2610 is filled with a conductive material to define a first backside through substrate via (BTSV) 414a.

[0158] like Fig.26E As shown in the cross-sectional view 2612 of FIG. 26A , the third semiconductor substrate 102c and the third interconnect structure 104c are bonded to the second semiconductor substrate 102b through the second hybrid bonding region 402b to form the third level 202c of the multi-level semiconductor structure.

[0159] like Fig.26F As shown in the cross-sectional view 2614 of FIG. 26A , a second edge trimming process is performed to remove portions of the third semiconductor substrate 102c and the third interconnect structure 104c. In some embodiments, the second edge trimming process may also remove portions of the first dielectric capping layer 118a.

[0160] like Figure 26G As shown in the cross-sectional view 2616 of , a second thinning process may be performed to thin the third semiconductor substrate 102 c along line 2618 .

[0161] like Fig.26H As shown in the cross-sectional view 2620 of FIG. 26 , a second dielectric protection layer 118b is formed along the sidewalls of the first level 202a, the second level 202b, and the third level 202c defined by the edge trimming process. After the second dielectric protection layer 118b is formed, a second BTSV opening 2622 is formed. The second BTSV opening 2622 extends through the second dielectric protection layer 118b and the third semiconductor substrate 102c to the interconnect layer within the third interconnect structure 104c. Subsequently, the second BTSV opening 2622 is filled with a conductive material to define a second BTSV 414b.

[0162] FIG. 27A to FIG. 27H Some other embodiments of edge trimming processes and bonding processes for forming a multi-level semiconductor structure are shown.

[0163] like Fig.27A As shown in the cross-sectional view 2700 of , a first dielectric bonding structure 504a is formed over the first interconnect structure 104a.

[0164] like Fig.27BAs shown in the cross-sectional view 2702 of FIG. 27 , the first semiconductor substrate 102a is bonded to the second semiconductor substrate 102b through the first dielectric bonding region 502a to define a multi-level semiconductor structure including the first level 202a and the second level 202b. In some embodiments, the first dielectric bonding structure 504a can contact the second dielectric bonding structure 504b along the first dielectric interface 506a within the first dielectric bonding region 502a.

[0165] like Fig.27C As shown in the cross-sectional view 2704 of FIG. 27 , a first edge trimming process is performed to remove a portion of the multi-level semiconductor structure along the periphery of the multi-level semiconductor structure. In some embodiments, a first thinning process may also be performed to thin the first semiconductor substrate 102 a along line 2706 .

[0166] like Fig.27D As shown in the cross-sectional view 2708 of FIG. 27 , a first dielectric protection layer 118a is formed along the sidewalls of the first level 202a and the second level 202b defined by the first edge trimming process. In some embodiments, the first dielectric protection layer 118a may also be formed on the recessed surface of the second semiconductor substrate 102b.

[0167] After forming the first dielectric capping layer 118a, a first BTSV opening 2710 is formed. The first BTSV opening 2710 extends through the first dielectric capping layer 118a, the first semiconductor substrate 102a, and the first dielectric bonding region 502a to the interconnect layer within the second interconnect structure 104b. Subsequently, the first BTSV opening 2710 is filled with a conductive material to define a first BTSV 508a.

[0168] like Fig.27E As shown in the cross-sectional view 2712 , the third semiconductor substrate 102 c and the third interconnect structure 104 c are bonded to the second semiconductor substrate 102 b through the second dielectric bonding region 502 b to form a third level 202 c of the multi-level semiconductor structure.

[0169] like Fig.27F As shown in the cross-sectional view 2714 of FIG. 27 , a second edge trimming process is performed to remove portions of the third semiconductor substrate 102c and the third interconnect structure 104c. In some embodiments, the second edge trimming process may also remove portions of the first dielectric protection layer 118a.

[0170] like Figure 27G As shown in the cross-sectional view 2716 of FIG. 2717 , a second thinning process may be performed to thin the third semiconductor substrate 102 c along line 2718 .

[0171] like Fig.27HAs shown in the cross-sectional view 2720 of FIG. 27 , a second dielectric protection layer 118b is formed along the sidewalls of the first level 202a, the second level 202b, and the third level 202c defined by the edge trimming process. After the second dielectric protection layer 118b is formed, a second BTSV opening 2722 is formed. The second BTSV opening 2722 extends through the second dielectric protection layer 118b and the third semiconductor substrate 102c to the interconnect layer within the third interconnect structure 104c. The second BTSV opening 2722 is then filled with a conductive material to define a second BTSV 508b.

[0172] Fig.28 A flow chart illustrating some other embodiments of a method 2800 of forming a multi-dimensional integrated chip structure with a dielectric protection layer.

[0173] At 2802, one or more transistor devices are formed within a first semiconductor substrate. Fig.24 Cross-sectional view 2400 is shown corresponding to some embodiments of act 2802 .

[0174] At 2804 , a first interconnect structure is formed over a first semiconductor substrate. Fig.25 Cross-sectional view 2500 is shown corresponding to some embodiments of act 2804 .

[0175] At 2806 , the first semiconductor substrate is bonded to an additional semiconductor substrate to define a multi-level semiconductor structure. FIG. 26A to FIG. 26B A cross-sectional view corresponding to some embodiments of act 2806 is shown. FIG. 27A to FIG. 27B Cross-sectional views corresponding to some alternative embodiments of act 2806 are shown.

[0176] At 2808, a thinning process is performed on the multi-level semiconductor structure. Fig.26C Cross-sectional view 2604 is shown corresponding to some embodiments of act 2808 . Fig.27C Cross-sectional view 2704 is shown corresponding to some embodiments of act 2808 .

[0177] At 2810, an edge trimming process is performed on the multi-level semiconductor structure. Fig.26C Cross-sectional view 2604 corresponding to some embodiments of act 2810 is shown. Fig.27C Cross-sectional view 2704 corresponding to some embodiments of act 2810 is shown.

[0178] At 2812 , a dielectric capping layer is formed along sidewalls of the multi-level semiconductor structure. Fig.26D Cross-sectional view 2608 is shown corresponding to some embodiments of act 2812 . Fig.27D Cross-sectional view 2708 is shown corresponding to some embodiments of act 2812 .

[0179] At 2814 , a BTSV is formed through the dielectric cap layer. Fig.26D Cross-sectional view 2608 is shown corresponding to some embodiments of act 2814 . Fig.27D Cross-sectional view 2708 is shown corresponding to some embodiments of act 2814 .

[0180] In some embodiments, acts 2806 - 2814 may be repeated (along line 2816 ) to form a multi-dimensional chip having more than two stacked wafers. FIG. 26E to FIG. 26H Cross-sectional views of some embodiments corresponding to repetitions of acts 2806 - 2814 are shown. FIG. 27E to FIG. 27H Cross-sectional views of some embodiments corresponding to repetitions of acts 2806 - 2814 are shown.

[0181] At 2818, the multi-level semiconductor structure is diced to form a plurality of multi-dimensional integrated chips.

[0182] Thus, in some embodiments, the present disclosure is directed to a method for reducing damage to one or more interlayer dielectric (ILD) layers overlying a substrate after an edge trimming process by forming a dielectric protection layer along sidewalls of the one or more ILD layers during the edge trimming process.

[0183] In some embodiments, the present disclosure relates to a method for forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a first interconnect structure disposed above an upper surface of a first semiconductor substrate; performing an edge trimming process to remove portions of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate, wherein the edge trimming process causes the first semiconductor substrate to have a recessed surface coupled to the upper surface through an inner sidewall disposed directly above the first semiconductor substrate; and after performing the edge trimming process, forming a dielectric protection layer on the sidewalls of the first interconnect structure. In some embodiments, the method may further include bonding the first semiconductor substrate to a second semiconductor substrate; and after bonding the first semiconductor substrate to the second semiconductor substrate, reducing the thickness of the first semiconductor substrate. In some embodiments, before reducing the thickness of the first semiconductor substrate, the dielectric protection layer is formed on the sidewalls of the first interconnect structure. In some embodiments, after reducing the thickness of the first semiconductor substrate, the dielectric protection layer is formed on the sidewalls of the first interconnect structure. In some embodiments, the method may further include performing a second edge trimming process on the second semiconductor substrate before bonding the first semiconductor substrate to the second semiconductor substrate. In some embodiments, the method may further include bonding a third semiconductor substrate to a second semiconductor substrate after the dielectric protection layer is formed on the sidewalls of the first interconnect structure; performing a second edge trimming process on the third semiconductor substrate; and forming a second dielectric protection layer on the dielectric protection layer and on the sidewalls of the third semiconductor substrate. In some embodiments, the dielectric protection layer is directly between the first semiconductor substrate and the second semiconductor substrate. In some embodiments, the dielectric protection layer includes silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, hafnium dioxide, tantalum pentoxide, aluminum oxide, or zinc peroxide. In some embodiments, the thickness of the dielectric protection layer is greater than or equal to 200 angstroms. In some embodiments, the edge trimming process damages one or more dielectric materials within the first interconnect structure, thereby causing a recess to be formed in the side of the one or more dielectric materials; the dielectric protection layer is formed in the recess. In some embodiments, the dielectric protection layer is deposited by an oblique angle deposition process. In some embodiments, the dielectric protection layer has a first thickness along the sidewalls of the first interconnect structure, and the first thickness is between 80% and 100% of the second thickness of the dielectric protection layer directly above the first interconnect structure.

[0184] In other embodiments, the present disclosure relates to a method for forming a multi-dimensional integrated chip. The method includes forming a plurality of interconnect layers within a dielectric structure above an upper surface of a first substrate; bonding the first substrate to a second substrate, wherein the dielectric structure is located between the first substrate and the second substrate after bonding; performing an edge trimming process to remove portions of the dielectric structure and the first substrate along a periphery of the first substrate; and forming a dielectric protection layer along the dielectric structure and the sidewalls of the first substrate after performing the edge trimming process. In some embodiments, the method may further include reducing the thickness of the first substrate, wherein the dielectric protection layer is formed on the sidewalls of the dielectric structure before reducing the thickness of the first substrate. In some embodiments, the method may further include performing a wet cleaning process after performing the edge trimming process; and performing an annealing process after performing the wet cleaning process and before forming the dielectric protection layer. In some embodiments, the method may further include reducing the thickness of the first substrate, wherein the dielectric protection layer is formed on the sidewalls of the dielectric structure after reducing the thickness of the first substrate. In some embodiments, the method may further include bonding a third substrate to the first substrate, wherein the dielectric protection layer is directly disposed between the first substrate and the third substrate.

[0185] In other embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface within a central region and a recessed surface within a recessed region surrounding the central region, wherein the recessed surface extends laterally from the central region to the outermost surface of the first substrate and is vertically located between the lower surface of the first substrate relative to the upper surface; a first plurality of interconnect layers disposed within a first dielectric structure on the upper surface; and a dielectric protection layer located above the recessed surface and along the sidewalls of the first dielectric structure and along the sidewalls of the first substrate. In some embodiments, the dielectric protection layer has a first thickness along the sidewalls of the first dielectric structure, the first thickness being greater than or equal to approximately 80% of the second thickness of the dielectric protection layer on the top surface of the first dielectric structure. In some embodiments, the recessed surface extends laterally beyond the outermost sidewalls of the dielectric protection layer.

[0186] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that these equivalent structures do not deviate from the spirit and scope of the present invention, and can be subjected to various changes, substitutions and changes without departing from the spirit and scope of the present invention.

Claims

1. A method of forming an integrated chip structure, comprising: forming a plurality of interconnect layers within a first interconnect structure disposed above an upper surface of a first semiconductor substrate; performing an edge trim process to remove portions of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate, wherein the edge trim process causes the first semiconductor substrate to have a recessed surface coupled to the upper surface through an inner sidewall directly disposed above the first semiconductor substrate; forming a dielectric protection layer on sidewalls of the first interconnect structure after performing the edge trim process; bonding the first semiconductor substrate to a second semiconductor substrate; and reducing a thickness of the first semiconductor substrate after bonding the first semiconductor substrate to the second semiconductor substrate.

2. The method according to claim 1, wherein: after reducing the thickness of the first semiconductor substrate, the thickness of the first semiconductor substrate is less than the thickness of the second semiconductor substrate.

3. The method according to claim 1, wherein, before reducing the thickness of the first semiconductor substrate, the dielectric protection layer is formed on the sidewalls of the first interconnect structure.

4. The method according to claim 1, wherein, after reducing the thickness of the first semiconductor substrate, the dielectric protection layer is formed on the sidewalls of the first interconnect structure.

5. The method according to claim 1, further comprising: performing a second edge trim process on the second semiconductor substrate before bonding the first semiconductor substrate to the second semiconductor substrate.

6. The method according to claim 1, further comprising: bonding a third semiconductor substrate to the second semiconductor substrate after the dielectric protection layer is formed on the sidewalls of the first interconnect structure; performing a second edge trim process on the third semiconductor substrate; and forming a second dielectric protection layer on the dielectric protection layer and on sidewalls of the third semiconductor substrate.

7. The method according to claim 1, wherein, the dielectric protection layer is directly located between the first semiconductor substrate and the second semiconductor substrate.

8. The method according to claim 1, wherein, the dielectric protection layer comprises silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, hafnium dioxide, tantalum pentoxide, aluminum oxide, or zinc peroxide.

9. The method according to claim 1, wherein, the thickness of the dielectric protection layer is greater than or equal to 200 angstroms.

10. The method according to claim 1, wherein, the edge trim process damages one or more dielectric materials within the first interconnect structure, thereby forming recesses within sides of the one or more dielectric materials; and wherein the dielectric protection layer is formed within the recesses.

11. The method according to claim 1, wherein, the dielectric protection layer is deposited by an angled deposition process.

12. The method according to claim 1, wherein, The dielectric protection layer has a first thickness along the sidewall of the first interconnect structure, and the first thickness is between 80% and 100% of the second thickness of the dielectric protection layer directly above the first interconnect structure.

13. A method for forming a multi-dimensional integrated chip, comprising: forming a plurality of interconnect layers in a dielectric structure above the upper surface of a first substrate; performing an edge trimming process to remove portions of the dielectric structure and the first substrate along the periphery of the first substrate; after performing the edge trimming process, forming a dielectric protection layer along the sidewalls of the dielectric structure and the first substrate; and bonding the first substrate to a second substrate, wherein after bonding, the dielectric structure is located between the first substrate and the second substrate, and a portion of the dielectric protection layer directly above the upper surface of the first substrate is in contact with the second substrate.

14. The method according to claim 13, further comprising: reducing the thickness of the first substrate, wherein the dielectric protection layer is formed on the sidewall of the dielectric structure before reducing the thickness of the first substrate.

15. The method according to claim 13, further comprising: performing a wet cleaning process after performing the edge trimming process; and performing an annealing process after performing the wet cleaning process and before forming the dielectric protection layer.

16. The method according to claim 14, wherein reducing the thickness of the first substrate includes performing a first grinding process, a second grinding process, and a chemical mechanical polishing (CMP) process to thin the first substrate.

17. The method according to claim 13, wherein the first substrate is bonded to the second substrate through the dielectric protection layer.

18. An integrated chip structure, comprising: a first substrate having an upper surface in a central region and a recessed surface in a recessed region surrounding the central region, wherein the recessed surface extends laterally from the central region to the outermost surface of the first substrate and is vertically between the lower surfaces of the first substrate relative to the upper surface; a first plurality of interconnect layers disposed in a first dielectric structure on the upper surface; and a dielectric protection layer located above the recessed surface and along the sidewalls of the first dielectric structure and along the sidewalls of the first substrate, wherein the recessed surface extends laterally beyond the sidewall of the dielectric protection layer facing away from the first dielectric structure.

19. The integrated chip structure according to claim 18, wherein the dielectric protection layer has a first thickness along the sidewall of the first dielectric structure, and the first thickness is greater than or equal to 80% of the second thickness of the dielectric protection layer on the top surface of the first dielectric structure.

20. The integrated chip structure according to claim 18, wherein the recessed surface extends laterally beyond the outermost sidewall of the dielectric protection layer.

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