A semiconductor device and a half-bridge circuit module using a power half-bridge stacking solution

Abstract

Disclosed is a semiconductor device and a half-bridge circuit module using a power half-bridge stacking scheme, wherein the semiconductor device includes a packaging frame and at least two transistors stacked on a base of the packaging frame, wherein the upper transistor of two adjacent transistors is arranged in a first window area on the upper surface of the lower transistor, and a series or parallel connection is achieved in the first window area. The semiconductor device of the present invention stacks at least two transistors on the base of the packaging frame, which reduces the demand for the number of base islands of the base, facilitates compatibility with ordinary packaging frames, and reduces packaging costs. The half-bridge circuit module of the present invention stacks the first transistor and the second transistor on the base of the packaging frame, and the first transistor and the second transistor are electrically connected in series through a conductive layer, which reduces the demand for the base island of the base of the packaging frame, facilitates compatibility with ordinary packaging frames, and reduces packaging costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a half-bridge circuit module using a power half-bridge stacking solution. Background Art

[0002] In the field of high-voltage and high-power power supply applications, it is a common method to use a high-voltage MOS (metal-oxide semiconductor) half-bridge and its driving technology to realize various power supply topologies.

[0003] The high-voltage MOS half-bridge is composed of an upper tube and a lower tube. For example, both the upper tube and the lower tube are NMOS (N-Metal-Oxide-Semiconductor) tubes. Figure 1 , the drain end of the upper tube M1 is connected to the bus potential V1, the source end of the lower tube M2 is connected to the reference potential V2, and the source end of the upper tube M1 and the drain end of the lower tube M2 are connected.

[0004] Reference Figure 2 In the TO252 package structure, most NMOS tubes are three-terminal components, and the pins include the source terminal S, the gate terminal G and the drain terminal D. In the high-voltage (withstand voltage above 500V) MOS half-bridge structure, the two high-voltage NMOS tubes required are mostly a combination structure of two discrete independently packaged NMOS tubes, with low integration, or the integration of two independent NMOS tubes requires a specially designed packaging architecture, which is costly. Summary of the invention

[0005] In view of the above problems, the object of the present invention is to provide a semiconductor device and a half-bridge circuit module using a power half-bridge stacking solution, so as to achieve integrated packaging of at least two transistors with a conventional packaging architecture and reduce the integrated packaging cost of multiple transistors.

[0006] According to one aspect of the present invention, there is provided a semiconductor device using a power half-bridge stacking solution, characterized in that it comprises:

[0007] A packaging frame, including a base;

[0008] At least two transistors are stacked on the base, wherein:

[0009] An upper surface of a lower transistor in an adjacent transistor among the at least two transistors includes a first window region, and the first window region includes at least one of a source electrode and a drain electrode of the lower transistor;

[0010] An upper transistor among adjacent transistors among the at least two transistors is arranged in the first window area of ​​the lower transistor, and the lower surface of the upper transistor includes at least one of the source electrode and the drain electrode of the upper transistor, and is connected in series or in parallel with at least one of the source electrode and the drain electrode of the lower transistor.

[0011] Optionally, the transistor of the at least two transistors comprises a vertical double diffused metal oxide semiconductor.

[0012] Optionally, the at least two transistors include:

[0013] A first transistor is disposed on the base, wherein the upper surface of the first transistor includes a first window region and a second window region isolated by an insulating layer, and the lower surface includes a drain electrode, the first window region of the first transistor includes a source electrode of the first transistor, and the second window region of the first transistor includes a gate electrode of the first transistor;

[0014] a second transistor, arranged on the first window region of the first transistor, wherein the upper surface of the second transistor includes the first window region and the second window region isolated by the insulating layer, and the lower surface includes a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor includes the source electrode of the second transistor, and the second window region of the second transistor includes the gate electrode of the second transistor,

[0015] The first transistor and the second transistor are both vertical double diffused metal oxide field effect transistors.

[0016] Optionally, a conductive layer is provided between the first window region of the first transistor and the lower surface of the second transistor, and the conductive layer includes conductive glue.

[0017] Optionally, the first transistor and the second transistor are high-voltage transistors.

[0018] Optionally, the first transistor and the second transistor are NMOS transistors.

[0019] Optionally, an area of ​​the first window region of the first transistor is larger than an area of ​​the lower surface of the second transistor.

[0020] Optionally, the packaging frame includes:

[0021] a first pin electrically connected to a drain electrode on a lower surface of the first transistor;

[0022] The second pin is electrically connected to the source electrode of the first window region of the second transistor.

[0023] Optionally, the gate electrode of the first transistor and the gate electrode of the second transistor are respectively electrically connected to two pins of the package frame or to the same pin of the package frame.

[0024] According to another aspect of the present invention, a half-bridge circuit module is provided, characterized in that it comprises:

[0025] A packaging frame, including a base;

[0026] A first transistor is disposed on the base, wherein an upper surface of the first transistor includes a first window area, and the first window area includes a first electrode of the first transistor;

[0027] a second transistor disposed above the first transistor, wherein a lower surface of the second transistor includes a second electrode of the second transistor; and

[0028] A conductive layer having an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled to the first window area, and the upper surface of the conductive layer is coupled to the lower surface of the second transistor, for electrically connecting the first electrode of the first transistor and the second electrode of the second transistor.

[0029] The semiconductor device provided by the present invention stacks at least two transistors on a base of a packaging frame, which reduces the demand for the number of base islands of the base, facilitates compatibility with common packaging frames, and reduces packaging costs.

[0030] The half-bridge circuit module provided by the present invention stacks the first transistor and the second transistor on the base of the packaging frame, and electrically connects the first electrode of the first transistor and the second electrode of the second transistor through a conductive layer, thereby reducing the demand for the number of base islands of the base, facilitating compatibility with ordinary packaging frames, and reducing packaging costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 A schematic diagram of the structure of a half-bridge structure unit according to the prior art is shown;

[0033] Figure 2 A schematic diagram of a packaging structure according to the prior art is shown;

[0034] Figure 3 A schematic diagram of a cross-sectional structure of a transistor according to the prior art is shown;

[0035] Figure 4 A schematic diagram of the upper surface structure of a transistor of a semiconductor device according to an embodiment of the present invention is shown;

[0036] Figure 5 A schematic cross-sectional structure diagram of a transistor of a semiconductor device according to an embodiment of the present invention is shown;

[0037] Figure 6 A partial structural schematic diagram of a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0038] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0039] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0040] Figure 3 A schematic diagram of a cross-sectional structure of a transistor according to the prior art is shown.

[0041] like Figure 3 As shown, the transistor 100 is a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), and in this embodiment, it is an N-type VDMOS, which is provided with an epitaxial layer 120 on a substrate 110, and the two ends of the upper surface of the epitaxial layer 120 include two spaced-apart well regions 130, and the upper surfaces of the two well regions 130 both include doped regions 131, and a gate structure is provided on the epitaxial layer 120, and the gate structure includes a gate oxide layer 141 and a polysilicon gate 142, and the projection of the polysilicon gate 142 on the upper surfaces of the two well regions 130 is located between the two doped regions 131. The two ends of the transistor 100 are respectively extended to the two doping regions 131 to form a channel region between the two doping regions 131. The gate oxide layer 141 surrounds the polysilicon gate 142 to isolate the direct electrical connection between the polysilicon gate 142 and other structures. The source metal layer 101 covers the upper surface of the transistor 100 and is in electrical contact with the well region 130 and the doping region 131 to lead out the source electrode through the source metal layer 101 to form a source S. The lower surface of the substrate 110 is covered with a drain metal layer 102 to lead out the drain electrode to form a drain D, and the polysilicon gate 142 leads out the gate G.

[0042] Taking N-type VDMOS as an example, the substrate 110 is an N-type doped substrate, such as a silicon substrate, the drift region 120 is an N-type doped region, the well region 130 is a P-type doped region, and the transistor 100 forms a structure with a source S on top and a drain D on the bottom.

[0043] Figure 4FIG. 4 is a schematic diagram showing the upper surface structure of a transistor of a semiconductor device according to an embodiment of the present invention, Figure 5 FIG. 4 is a schematic diagram showing a cross-sectional structure of a transistor of a semiconductor device according to an embodiment of the present invention, wherein: Figure 5 correspond Figure 4 Schematic diagram of the cross-sectional structure of transistor 200 along line AA.

[0044] Reference Figure 4 and Figure 5 The upper surface of the transistor 200 of the semiconductor device of the embodiment of the present invention includes a first window area 201 and a gate structure 220 isolated by an insulating layer 210. The upper surface of the first window area 201 corresponds to the source electrode. The gate structure 220 includes a second window area 221 for the gate electrode (polysilicon gate). The lower surface of the transistor 200 corresponds to the drain electrode. Taking N-type VDMOS as an example, the structure of the transistor 200 is the same as that of the transistor 100, except that the source electrode and the gate electrode are clearly separated. The electrode material is generally copper, that is, the surfaces of the first window area 201 and the second window area 221 and the lower surface of the transistor 200 are covered with copper.

[0045] Among them, the thickness from the upper surface of the insulating layer 210 to the lower surface of the transistor 200 is greater than the thickness from the upper surface of the first window area 201 and the second window area 221 to the lower surface of the transistor 200, which can ensure the insulation performance and facilitate the positioning stability of the subsequent upper transistor set in the first window area of ​​the lower transistor.

[0046] Figure 6 A partial structural schematic diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0047] like Figure 6 As shown, the semiconductor device 300 of the embodiment of the present invention includes a packaging frame and a first transistor 2001 and a second transistor 2002 arranged in the packaging frame, and the packaging frame includes a base 310 and a pin 320 fixedly connected to the base 310. The structures of the first transistor 2001 and the second transistor 2002 are the same as the structure of the transistor 200, the difference is that the size of the second transistor 2002 is smaller than the size of the first transistor 2001, and mainly that the surface area of ​​the first window region of the first transistor 2001 is greater than or equal to the area of ​​the lower surface of the second transistor 2002, so that the second transistor 2002 can be placed in the first window region of the first transistor 2001, and it is convenient to lead out the gate electrode of the second window region of the first transistor 2001.

[0048] In an optional embodiment, the size of the second transistor 2002 is larger than the size of the first window area of ​​the first transistor 2001, and the corresponding electrodes of the first transistor 2001 and the second transistor 2002 (the source electrode (first electrode) of the first window area of ​​the first transistor 2001 and the drain electrode (second electrode) on the lower surface of the second transistor 2002 are connected) can be reliably electrically connected through the conductive layer 301, and the size design of the second transistor 2002 can be maintained to ensure the performance of the second transistor 2002 and the performance of the corresponding half-bridge circuit module.

[0049] The first transistor 2001 and the second transistor 2002 are stacked in sequence on the base 310. The first transistor 2001 is a lower transistor and is directly arranged on the upper surface of the base 310. The drain electrode on the lower surface of the first transistor 2001 is electrically connected to one of the pins 320 through the circuit arrangement on the base 310, and the corresponding drain end of the semiconductor device 300 is led out.

[0050] The second transistor 2002 corresponds to the upper transistor and is arranged in the first window area of ​​the first transistor 2001. The drain electrode on the lower surface of the second transistor 2002 is electrically connected to the source electrode on the upper surface of the first window area of ​​the first transistor 2001, forming a series structure of the first transistor 2001 and the second transistor 2002. The source electrode of the first window area of ​​the second transistor 2002, the gate electrode of the second window area and the gate electrode of the second window area of ​​the first transistor 2001 are connected to the corresponding pins 320 through wire wiring 304 to lead out the source electrode of the second transistor 2002 as the source of the semiconductor device 300, and to lead out the gates of the first transistor 2001 and the second transistor 2002.

[0051] Among them, the gate electrodes of the second window areas of the first transistor 2001 and the second transistor 2002 can be respectively led out to two pins 320 or to the same pin 320, and are uniformly controlled, which can be applicable to TO252 packaging and only lead out three pins.

[0052] In this embodiment, the conductive layer 301 is a conductive adhesive, and the electrical connection between the lower surface of the second transistor 2002 and the upper surface of the first window area of ​​the first transistor 2001 is connected through the conductive adhesive, which can ensure the reliability of the electrical connection, and the conductive adhesive can be sintered at a low temperature, which is convenient to operate. In an optional embodiment, the electrical connection between the lower surface of the second transistor 2002 and the upper surface of the first window area of ​​the first transistor 2001 is patch welding, and correspondingly, the conductive layer 301 is other conductive materials such as solder.

[0053] In this embodiment, the source electrode is arranged on the upper surface of the first transistor 2001 and the drain electrode is arranged on the lower surface, and they are stacked to form a series connection, which is a small improvement on the structure of the ordinary VDMOS transistor 100 and is easy to implement. In an optional embodiment, the source electrode and the drain electrode can be arranged on the upper surface of the first transistor 2001 at the same time, and the electrode can be led out to the pin 320 by a wire. The source electrode and the drain electrode of the second transistor 2002 can be arranged on the same surface, and are connected in series or in parallel with the source electrode and the drain electrode on the upper surface of the first transistor 2001, which can also reduce the demand for the number of base islands of the base 310.

[0054] The semiconductor device 300 of the embodiment of the present invention has a first transistor 2001 and a second transistor 2002 stacked, and the second transistor 2002 is arranged on the first window area of ​​the first transistor 2001. The requirements for the base 310 of the packaging frame are limited to the placement of the first transistor 2001. A conventional packaging frame can be used, and there is no need to design a packaging frame separately. The packaging of the dual transistors of the half-bridge structure is achieved without increasing the design cost of the packaging frame. In addition, the stacking of the first transistor 2001 and the second transistor 2002 makes their connection distance close, reducing the resistance on the series connection path.

[0055] In this embodiment, two transistor stacking arrangements are taken as an example. In an optional embodiment, multiple transistor stacking arrangements are provided, which can also reduce the demand for the number of base islands of the packaging frame and reduce the packaging cost.

[0056] The semiconductor device adopting the power half-bridge stacking scheme of the present invention stacks at least two transistors on the base of the packaging frame, which reduces the demand for the number of base islands of the base, facilitates compatibility with ordinary packaging frames, and reduces packaging costs. The packaging of the power half-bridge stacking scheme can be selected in the form of TO252, TO247 and TO263.

[0057] In some embodiments, the bonding position, direction, thickness, etc. may be different from the embodiments shown in the figures or described above.

[0058] It should be understood that situations where the positional relationship of "upper" and "lower" is swapped, or the positional relationship after the overall angle is uniformly adjusted, etc. are all within the protection scope of the present invention.

[0059] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device using a power half-bridge stacking solution, characterized in that: include: A packaging frame, including a base; At least two transistors are stacked on the base, wherein: An upper surface of a lower transistor in an adjacent transistor among the at least two transistors includes a first window region, and the first window region includes at least one of a source electrode and a drain electrode of the lower transistor; An upper transistor in the adjacent transistors of the at least two transistors is arranged in the first window region of the lower transistor, and a lower surface of the upper transistor includes at least one of a source electrode and a drain electrode of the upper transistor, and is connected in series or in parallel with at least one of a source electrode and a drain electrode of the lower transistor; A transistor of the at least two transistors comprises a vertical double diffused metal oxide semiconductor; The at least two transistors include: A first transistor is disposed on the base, wherein the upper surface of the first transistor includes a first window region and a second window region isolated by an insulating layer, and the lower surface includes a drain electrode, the first window region of the first transistor includes a source electrode of the first transistor, and the second window region of the first transistor includes a gate electrode of the first transistor; a second transistor, arranged on the first window region of the first transistor, wherein the upper surface of the second transistor includes the first window region and the second window region isolated by the insulating layer, and the lower surface includes a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor includes the source electrode of the second transistor, and the second window region of the second transistor includes the gate electrode of the second transistor, The first transistor and the second transistor are both vertical double diffused metal oxide field effect transistors.

2. The semiconductor device according to claim 1, wherein: A conductive layer is arranged between the first window region of the first transistor and the lower surface of the second transistor, and the conductive layer includes conductive glue.

3. The semiconductor device according to claim 1, wherein: The first transistor and the second transistor are high voltage transistors.

4. The semiconductor device according to claim 3, characterized in that The first transistor and the second transistor are NMOS transistors.

5. The semiconductor device according to claim 1, wherein: An area of ​​a first window region of the first transistor is larger than an area of ​​a lower surface of the second transistor.

6. The semiconductor device according to claim 1, wherein: The packaging frame comprises: a first pin electrically connected to a drain electrode on a lower surface of the first transistor; The second pin is electrically connected to the source electrode of the first window region of the second transistor.

7. The semiconductor device according to claim 1 or 6, characterized in that: The gate electrode of the first transistor and the gate electrode of the second transistor are respectively electrically connected to two pins of the package frame or to the same pin of the package frame.

8. A half-bridge circuit module, characterized in that: include: A packaging frame, including a base; A first transistor is disposed on the base, wherein an upper surface of the first transistor includes a first window area, and the first window area includes a first electrode of the first transistor; A second transistor is disposed above the first transistor, wherein a lower surface of the second transistor includes a second electrode of the second transistor; as well as A conductive layer having an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled to the first window region, and the upper surface of the conductive layer is coupled to the lower surface of the second transistor, for electrically connecting the first electrode of the first transistor and the second electrode of the second transistor; The transistor comprises a vertical double diffused metal oxide semiconductor tube; The transistor comprises: A first transistor is disposed on the base, wherein the upper surface of the first transistor includes a first window region and a second window region isolated by an insulating layer, and the lower surface includes a drain electrode, the first window region of the first transistor includes a source electrode of the first transistor, and the second window region of the first transistor includes a gate electrode of the first transistor; a second transistor, arranged on the first window region of the first transistor, wherein the upper surface of the second transistor includes the first window region and the second window region isolated by the insulating layer, and the lower surface includes a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor includes the source electrode of the second transistor, and the second window region of the second transistor includes the gate electrode of the second transistor, The first transistor and the second transistor are both vertical double diffused metal oxide field effect transistors.

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